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ibm powerpc 750gl risc microprocessor revision level dd1.x datasheet version: 1.2 preliminary march 13, 2006
? copyright and disclaimer ? copyright international business machines corporation 2005, 2006 all rights reserved printed in the united states of america march 2006. the following are trademarks of international business machin es corporation in the united states, or other countries, or both. ibm ibm logo powerpc powerpc logo powerpc 750 powerpc architecture ieee is a registered trademark in the united states, owned by the institute of electrical and electronics engineers. other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. the information contained in this document does not affect or change ibm product specifications or warranties. noth ing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ib m or third parties. all information contained in this docu- ment was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. some of the information provided herein pertains to third pa rty vendors and their products and services. you are directed to contact such vendors with all questions pertaining to their respective products or services, as well as any requests for product or service updates. you are solely responsible for the selection of any vendors, including their products and services. the vendors identified herein are not agents or representatives of ibm and are not authorized to make commit- ments, warranties or representations on behalf of ibm. ibm makes no commitments, warranties or representations with regard to the vendors, their respective product or services, or the compatibility of such products or services with any of ibm's product or services. the information contained in this document is provided on an ?as is? basis and no warranties of any kind, including but not limited to the implied warranties of merchantability and fitness for a particular purpose, are provided. in no event will ibm be liable to you or to any third parties for any damages ar ising directly or indirectly from any use of the information contained in this document. ibm microelectronics systems and technology group 2070 route 52, bldg. 330 hopewell junction, ny 12533-6351 the ibm home page can be found at ibm.com the ibm microelectronics home page can be found at ibm.com /chips 750gl_ds_title.fm 1.2 march 13, 2006 note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change with out notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design. w hile the information contained herein is believed to be accurate, such information is preliminary, and should not be r elied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made .
datasheet dd 1.x preliminary powerpc 750gl risc microprocessor 750gl_dstoc.fm.1.2 march 13, 2006 page 3 of 74 1. general information .................................................................................................... 9 1.1 features .................................................................................................................. .......................... 9 1.3 processor version register ................................................................................................ ............ 11 1.4 part number information ................................................................................................... .............. 12 2. overview ................................................................................................................... . 13 2.1 block diagram ............................................................................................................. .................... 13 2.2 general parameters ........................................................................................................ ................ 14 3. electrical and thermal characteristics ................................................................... 15 3.1 dc electrical characteristics ............................................................................................. .............. 15 3.2 ac electrical characteristics ............................................................................................. .............. 19 3.3 clock ac specifications ................................................................................................... ............... 19 3.4 spread spectrum clock generator ........................................................................................... ...... 20 3.4.1 design considerations ................................................................................................... ....... 20 3.5.1 input setup timing ...................................................................................................... .......... 21 3.6 60x bus output ac specifications .......................................................................................... ........ 24 3.6.1 ieee 1149.1 ac timing specifications ................................................................................. 27 4. dimensions and signal assignments ..................................................................... 30 4.1 package ................................................................................................................... ....................... 30 4.2 module substrate decoupling voltage assignments ...................................................................... 35 4.3 microprocessor ball placement ............................................................................................. .......... 36 5. system design information ..................................................................................... 46 5.1 pll operation ............................................................................................................. .................... 46 5.1.1 overview ................................................................................................................ ................ 46 5.1.2 restrictions and considerations for pll configuration ......................................................... 47 5.1.2.1 configuration restriction on frequency transitions ...................................................... 47 5.1.3 pll_rng[0:1] definitions for dual pll operation ................................................................ 47 5.1.4 pll configuration ....................................................................................................... ........... 48 5.2 pll power supply filtering ................................................................................................ ............. 50 5.3 decoupling recommendations ................................................................................................ ....... 54 5.4 connection recommendations ................................................................................................ ....... 56 5.5 output buffer dc impedance ................................................................................................ .......... 57 5.5.1 input/output usage ...................................................................................................... ......... 58 5.6 thermal management information ............................................................................................ ...... 62 5.6.1 thermal assist unit ..................................................................................................... .......... 64 5.6.2 minimum heat sink requirements ........................................................................................ 6 4 5.6.3 internal package conduction resistance .............................................................................. 65 5.6.4 adhesives and thermal interface materials .......................................................................... 66 5.7 heat-sink selection example ............................................................................................... ........... 68 5.8 operational and design considerations ..................................................................................... .... 70 5.8.1 level protection ........................................................................................................ ............. 70 5.8.2 64-bit or 32-bit data bus mode .......................................................................................... ... 70 5.8.4 q ack signal implementation for selected features ............................................................ 71 5.8.4.1 precharge duration selection and application ............................................................... 71
datasheet dd 1.x powerpc 750gl risc microprocessor preliminary page 4 of 74 750gl_dstoc.fm.1.2 march 13, 2006 5.8.4.2 processor debug system enablement when implementing precharge selection ......... 72 revision log ................................................................................................................. 73
datasheet dd 1.x preliminary powerpc 750gl risc microprocessor 750gl_dslot.fm.1.2 march 13, 2006 page 5 of 74 table 1-1. 750gl processor version register (pvr) ............................................................................. 11 table 2-1. 750gl general parameters ............................................................................................. ...... 14 table 3-1. absolute maximum ratings ............................................................................................. ...... 15 table 3-2. recommended operating conditions .................................................................................... 1 5 table 3-3. package thermal characteristics ...................................................................................... .... 16 table 3-4. dc electrical specifications ......................................................................................... .......... 16 table 3-5. power consumption (low power) ........................................................................................ .. 17 table 3-6. power consumption (standard power) .................................................................................. 1 7 table 3-7. clock ac timing specifications ....................................................................................... ...... 19 table 3-8. 60x bus input ac timing specifications ............................................................................... .21 table 3-9. 60x bus output ac timing specifications ............................................................................. 2 4 table 3-10. jtag ac timing specifications (independent of sysclk) .................................................. 27 table 4-1. pinout listing for the cbga package .................................................................................. ... 37 table 4-2. signal listing for the cbga package .................................................................................. .. 40 table 4-3. signal locations ..................................................................................................... ................ 43 table 4-4. voltage and ground assignments ....................................................................................... .. 45 table 5-1. pll_rng[0:1] definitions for dual pll operation ................................................................ 47 table 5-2. 750gl microprocessor pll configuration ............................................................................. 48 table 5-3. sample pll power supply filtering circuits .......................................................................... 5 0 table 5-4. recommended decoupling capacitor specifications ............................................................ 54 table 5-5. driver impedance characteristics ..................................................................................... ..... 58 table 5-6. input/output usage ................................................................................................... ............. 59 table 5-7. maximum heat-sink weight limit for the cbga .................................................................... 63 table 5-8. 750gl heat-sink vendors .............................................................................................. ....... 64 table 5-9. 750gl thermal interface and adhesive materials vendors .................................................. 68 table 5-10. summary of mode select .............................................................................................. ......... 71
datasheet dd 1.x powerpc 750gl risc microprocessor preliminary page 6 of 74 750gl_dslot.fm.1.2 march 13, 2006
datasheet dd 1.x preliminary powerpc 750gl risc microprocessor 750gl_dslof.fm.1.2 march 13, 2006 page 7 of 74 figure 2-1. ibm powerpc 750gl risc microprocessor block diagram ................................................. 13 figure 3-1. sysclk input timing diagram ......................................................................................... ..... 19 figure 3-2. linear sweep modulation profile ..................................................................................... ...... 20 figure 3-3. input timing definition ............................................................................................. .............. 22 figure 3-4. input timing diagram ................................................................................................ ............. 22 figure 3-5. mode select input timing diagram .................................................................................... .... 23 figure 3-6. output valid timing definition ...................................................................................... .......... 25 figure 3-7. output timing diagram for ibm powerpc 750gl risc microprocessor .............................. 26 figure 3-8. jtag clock input timing diagram ..................................................................................... .... 28 figure 3-9. trst timing diagram ................................................................................................. .......... 28 figure 3-10. boundary-scan timing diagram ....................................................................................... ..... 28 figure 3-11. test access port timing diagram .................................................................................... ...... 29 figure 4-1. mechanical dimensions, standard (leaded) package .......................................................... 31 figure 4-2. mechanical dimensions, rohs-compatible package .......................................................... 33 figure 4-3. module substrate decoupling voltage assignments ............................................................. 35 figure 4-4. powerpc 750gl microprocessor ball placement .................................................................. 36 figure 5-1. single pll power supply filter circuit with a1vdd pin and a2vdd pin tied to gnd ......... 51 figure 5-2. pll power supply filter circuit with two avdd pins and one ferrite bead ........................ 51 figure 5-3. dual pll power supply filter circuits ............................................................................... .... 53 figure 5-4. orientation and layout of the 750gl decoupling capacitors ................................................ 56 figure 5-5. driver impedance measurement ........................................................................................ .... 57 figure 5-6. ibm riscwatch jtag to hreset, trst, and sreset signal connector ........................ 62 figure 5-7. package exploded cross-sectional view with several heat-sink options ........................... 63 figure 5-8. c4 package with heat sink mounted to a printed-circuit board ........................................... 66 figure 5-9. thermal performance of select thermal interface material .................................................. 67 figure 5-10. example of a pin-fin heat-sink-to-ambient thermal resistance versus airflow velocity .... 69
datasheet dd 1.x powerpc 750gl risc microprocessor preliminary page 8 of 74 750gl_dslof.fm.1.2 march 13, 2006
datasheet ibm powerpc 750gl risc microprocessor dd1.x 750gl_ds_body.fm.1.2 march 13, 2006 general information page 9 of 74 1. general information the ibm powerpc ? 750gl risc 1 microprocessor is a 32-bit implementation of the ibm powerpc family. this document contains pertinent physical and electrical characteristics of the ibm powerpc 750gl risc microprocessor revision dd1.x single chip module (scm). the ibm powerpc 750gl risc microprocessor is also referred to as the 750gl throughout this document. 1.1 features this section summarizes the features of the 750gl implementation of the powerpc architecture?. major features of the 750gl include the following: branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving two speculations) ? up to one speculative stream in execution, one additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots decode ? register file access ? forwarding control ? partial instruction decode load/store unit ? one cycle load or store cache access (byte, half-word, word, double-word) ? effective address generation ? hits under miss (four outstanding misses) ? single-cycle misaligned access within double-word boundary ? alignment, zero padding, sign extend for integer register file ? floating-point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering ? cache and translation lookaside buffer (tlb) instructions ? big-endian and little-endian byte addressing supported ? misaligned little-endian support in hardware dispatch unit ? full hardware detection of dependencies (resolved in the execution units) ? dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, or floating-point) ? 4-stage pipeline: fetch, dispatch, execute, and complete ? serialization control (predispatch, postdispatch, execution, serialization) fixed-point units ? fixed-point unit 1 (fxu1): multiply, divide, shift, rotate, arithmetic, logical ? fixed-point unit 2 (fxu2): shift, rotate, arithmetic, logical ? single-cycle arithmetic: shift, rotate, logical ? multiply and divide support (multi-cycle) ? early out multiply ? thirty-two 32-bit general purpose registers floating-point unit ? support for ieee ? -754 standard single-pre- cision and double-precision floating-point arithmetic ? optimized for single-precision multiply/add ? thirty-two 64-bit floating-point registers ? enhanced reciprocal estimates ? 3-cycle latency, 1-cycle throughput, single-precision multiply-add ? 3-cycle latency, 1-cycle throughput, double-precision add ? 4-cycle latency, 2-cycle throughput, double-precision multiply-add ? hardware support for divide ? hardware support for denormalized numbers ? time deterministic non-ieee mode 1. reduced instruction set computer .
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary general information page 10 of 74 750gl_ds_body.fm 1.2 march 13, 2006 system unit ? executes condition register (cr) logical instructions and miscellaneous system instructions ? special register transfer instructions level 1 (l1) cache structure ? 32-kb, 8-way set associative instruction and data caches ? single-cycle cache access ? pseudo-least-recently-used (plru) replacement ? cache write-back or write-through opera- tions programmable on a virtual-page or bat-block basis ? parity on l1 tags and caches ? 3-state modified/exclusive/invalid (mei) memory coherency ? hardware support for data coherency ? non-blocking instruction cache (one out- standing miss) ? non-blocking data cache (four outstanding misses) ? no snooping of instruction cache memory management unit ? 64-entry, 2-way set associative instruction tlb (total 128) ? 64-entry, 2-way set associative data tlb (total 128) ? hardware reload for tlbs ? eight instruction block address translation (bat) arrays and eight data bat arrays ? virtual memory support for up to 4 exabytes (2 52 ) virtual memory ? real memory support for up to 4 gigabytes (2 32 ) of physical memory ? support for big-endian/little-endian address- ing dual phase-locked loops (plls) ? allow seamless frequency switching level 2 (l2) cache ? integrated 1-mb l2 cache with on-chip con- troller and 8-kb entry tags ? 4-way set-associative; supports locking by way ? ability to restrict the cache for instruction- only or data-only operation ? copy-back or write-through data cache on a page basis, or for entire l2 cache ? 64-byte sectored line size ? l2 frequency at core speed ? error checking and correction (ecc) protec- tion on sram array ? parity on l2 tags ? supports up to four outstanding misses (four data or three data and one instruction) power ? low power consumption with low voltage application at lower frequency ? dynamic power management ? three static power save modes: doze, nap, and sleep ? thermal assist unit (tau) bus interface ? 32-bit address bus ? 64-bit data bus (also supports 32-bit mode) ? up to 200-mhz 60x bus frequency ? four load/store requests, plus one snoop are supported for a total of five outstanding bus requests. load/store requests can be a combination of three data and one instruc- tion, or four data requests ? core-to-bus multipliers are supported in half-step integer increments from 2 through 10, and in full-step increments from 10 through 20. ratios of 3.5x and lower are not supported with miss-under-miss enabled ? supports 1.8-v, 2.5-v, or 3.3-v i/o modes reliability and serviceability ? parity checking on 60 bus interface ? ecc detection and correction on l2 cache ? parity on the l1 caches ? parity on the l1 and l2 tags testability ? level-sensitive scan design (lssd) testing ? powerful diagnostic and test interface through common on-chip processor (cop) and ieee 1149.1 (jtag) interface
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 general information page 11 of 74 1.2 design highlights the 750gl supports several unique features including: pin compatible with the powerpc 750fx risc microprocessor 1-mb l2 cache, 4-way set associative, operating at core frequency independent l2 cache locking of all four ways l2 cache may be configured to contain instructions only or data only enhanced 60 bus to support up to five pipelined transactions 1.3 processor version register the ibm powerpc 750gl risc microprocessor has the following processor version register (pvr) values for the respective design revision levels. table 1-1. 750gl processor version register (pvr) 750gl design revision level 750gl pvr dd1.2 0x700201r2 note: r = reserved nibble; reserved bits can be either '0' or '1', and should be masked in application software.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary general information page 12 of 74 750gl_ds_body.fm 1.2 march 13, 2006 1.4 part number information ibm25ppc750glecr powerpc 750 family member process technology test conditions shipping container reliability grade performance sort package type design revision level process technology e = 9s2, 0.13 m design revision level c = dd1.2 package type b = ceramic ball grid array r = reduced lead ceramic ball grid array performance sort 2h = 800mhz, half-mode good (see errata #9) 5h = 933mhz, half-mode good (see errata #9) test conditions 3 = 1.40 v - 1.50 v, -40 c - 105 c, low power 4 = 1.45 v - 1.55 v, -40 c - 105 c, low power a = 1.40 v - 1.50 v, -40 c - 105 c, standard power b = 1.45 v - 1.55 v, -40 c - 105 c, standard power reliability grade 3 = grade 3, <100 failures in time (fit) average failure rate (afr) 4 = grade 4, commercial shipping container t = tray yy x x t example part numbers (dd1.2, reduced-lead, half-mode good, commercial grade, tray) ppc750glecr2h34t = 800mhz, 1.45v 50mv ppc750glecr5h44t = 933mhz, 1.50v 50mv
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 overview page 13 of 74 2. overview the ibm powerpc 750gl risc microprocessor, also called the 750gl, is targeted for high-performance, low-power systems using a 60 bus. the 750gl also includes an internal 1-mb l2 cache with on-board error correction circuitry (ecc). 2.1 block diagram figure 2-1. ibm powerpc 750gl risc microprocessor block diagram load/store floating- instruction fetch system completion 32-kb instruction cache bht/ enhanced l2 cache fxu2 dispatch branch unit control unit (fprs) 1-mb 32-kb data cache l2 tags fxu1 with ecc with parity with parity with parity unit btic 60x bus and rename buffers unit (lsu) floating- point registers point unit (fpu) interface unit (biu) (gprs) and rename buffers general- purpose registers
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary overview page 14 of 74 750gl_ds_body.fm 1.2 march 13, 2006 2.2 general parameters table 2-1. 750gl general parameters item description notes technology 0.13- m copper silicon-on-insulator (csoi) technology 6-layer metallization plus one level of local interconnect die size 52.5 sq. mm (diced 7.6 mm 6.9 mm) logic design fully static package reduced lead 292-pin ceramic ball grid array (cbga) 21 21 mm (1.0-mm pitch) 0.8-mm ball size core power supply 1.45 v 50 mv for 800 mhz, 1.50 v 50 mv for 933 mhz i/o power supply 3.3 v 165 mv (bvsel = 1, l1_tstclk = 0) or 2.5 v 125 mv (bvsel = 1, l1_tstclk = 1) or 1.8 v 100 mv (bvsel = 0, l1_tstclk = 1) 1 notes: 1. bvsel = 0, l1_tstclk = 0 is an invalid setting.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 15 of 74 3. electrical and thermal characteristics this section provides ac and dc electrical specifications and thermal characteristics for the 750gl. 3.1 dc electrical characteristics the tables in this section describe the dc electrical characteristics for the 750gl. table 3-1. absolute maximum ratings 1 characteristic symbol 1.8 v 2.5 v 3.3 v unit notes core supply voltage v dd -0.3 to 1.6 -0.3 to 1.6 -0.3 to 1.6 v 3, 4 pll supply voltage a1v dd , a2v dd -0.3 to 1.6 -0.3 to 1.6 -0.3 to 1.6 v 3, 4, 5 60x bus supply voltage ov dd -0.3 to 2.0 -0.3 to 2.75 -0.3 to 3.7 v 3, 4 input voltage v in -0.3 to 2.0 -0.3 to 2.75 -0.3 to 3.7 v 2 storage temperature range t stg -55 to 150 -55 to 150 -55 to 150 c notes: 1. functional and tested operating conditions are given in table 3-2 recommended operating conditions . absolute maximum rat- ings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed above ma y affect device reliability or caus e permanent damage to the device. 2. caution: transient v in overshoots of up to ov dd + 0.8 v, with a maximum of 4.0 v for 3.3 v operation, and undershoots down to gnd - 0.8 v, are allowed for up to 5 ns. 3. caution: ov dd must not exceed v dd /av dd by more than 2.5 v continuously. ov dd may exceed v dd /av dd by up to 2.65 v for up to 20 ms during power-on or power-off. ov dd must not exceed v dd /av dd by more than 2.65 v for any amount of time. 4. caution: v dd /av dd must not exceed ov dd by more than 1.0 v continuously. v dd /av dd may exceed ov dd by up to 1.6 v for up to 20 ms during power-on or power-off. v dd /av dd must not exceed ov dd by more than 1.6 v for any amount of time. 5. caution: av dd must not exceed v dd by more than 0.5 v at any time. table 3-2. recommended operating conditions characteristic symbol value unit notes core supply voltage v dd 1.2 to 1.55 v 1, 2 pll supply voltage av dd vdd (see section 5.3) v 1, 3 60 bus supply voltage (1.8 v) ov dd 1.7 to 1.9 v 2 60 bus supply voltage (2.5 v) ov dd 2.375 to 2.675 v 2 60 bus supply voltage (3.3 v) ov dd 3.135 to 3.465 v 2 input voltage v in gnd to ov dd v2 die-junction temperature t j -40 to 105 c notes: 1. lower core voltages are supported to allow slower operation at substantial power savings. see the application conditions for addi- tional information. 2. these are recommended and tested operating conditions. proper device operation outside of thes e conditions is not guaranteed. 3. av dd should be set to the same value as v dd for single pll operation.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 16 of 74 750gl_ds_body.fm 1.2 march 13, 2006 table 3-3. package thermal characteristics characteristic symbol value unit cbga package thermal resistance, juncti on-to-case thermal resistance (typical) jc 0.1 c/w cbga package thermal resistance, junction-to-lead thermal resistance (typical) jb 7.6 c/w note: jc is the internal resistance from the junction to the back of the die. a heat sink customized to the end user application and ambient operating environment is required to ensure the die junc tion temperature is maintained within the limits defined in table 3-2 on page 15. for more information about thermal management, see section 5.6 on page 63. table 3-4. dc electrical specifications see table 3-2 on page 15 for recommended operating conditions. characteristic symbol voltage unit notes min. max. input high voltage (all inputs except system clock [sysclk]) v ih (1.8 v) 1.20 ? v 2 v ih (2.5 v) 1.70 ? v 2 v ih (3.3 v) 2.4 ? v 2 input low voltage (all inputs except sysclk) v il (1.8 v) ?0.60v v il (2.5 v) ?0.70v v il (3.3 v) ?0.80v sysclk input high voltage cv ih (1.8 v) 1.20 ? v cv ih (2.5 v) 1.90 ? v cv ih (3.3 v) 2.1 ? v sysclk input low voltage cv il (1.8 v, 2.5 v, 3.3 v) ?0.40v input leakage current, v in = applies to all ov dd levels i in ? 300 a3 hi-z (off state) leakage current, v in = applies to all ov dd levels i tsi ?20 a3 output high voltage, i oh = -4 ma v oh (1.8 v) 1.30 ? v v oh (2.5 v) 2.00 ? v v oh (3.3 v) 2.40 ? v output low voltage, i ol = 4 ma v ol (1.8 v, 2.5 v, 3.3 v) ?0.4v capacitance, v in = 0 v, f = 1 mhz c in ?7pf1 notes: 1. capacitance values are guaranteed by desi gn and characterization, and are not tested. 2. maximum input high voltage for short duration (not continuous operation). 3. additional input current may be attributed to the lev el protection keeper lock circuitry. for details, see section 5.8, operational and design considerations, on page 71.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 17 of 74 table 3-5. power consumption (low power) see table 3-2 on page 15 for recommended operating conditions. mode t j unit notes 500 mhz 800 mhz 933 mhz recommended operating conditions 1.20 to 1.55 1.40 to 1.55 1.45 to 1.55 v 4 core voltage ? ? 1.45 1.5 v maximum power 105c ? 8.5 10.3 w 1, 2 typical power 65c ? 5.9 6.5 w 1, 3 nap power, maximum 50c ? 3.5 4.5 w 1 50c 1.8 @ 1.30 v ? ? w 1 50c 1.5 @ 1.25 v ? ? w 1 30c 1.2 @ 1.25 v ? ? w 1 sleep power, maximum 50c ? 3.5 4.3 w 1 50c 1.8 @ 1.30 v ? ? 1 50c 1.5 @ 1.25 v ? ? 1 30c 1.1 @ 1.25 v ? ? 1 notes: 1. these values apply for all valid 60 buses. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent, but is typically less than 2% of v dd power. 2. maximum power is measured at the indicated v dd and t j using parts with worst-case process parameters and running rc5-72. rc5-72 runs hotter than typical production c ode, but it is possible to design code t hat runs even hotter than rc5-72. see reduc- ing powerpc 750gx power dissipation application note for more information. 3. typical power is an estimate of the average value model ed in a system executing typical applications with v dd and typical process parameters. note that typical power cannot be used in the design of the power supply or cooling system. 4. timing and all ac/dc characteristics are guaranteed over the vdd range of 1.20v to 1.55v. the supported vdd operating range f or 800mhz and 933mhz operation are as shown. power is specified at the single core (vdd) voltage shown, not over the recom- mended operating conditions range. for example, the maximum power at 800mhz/105c/1.45v is 8.5w. maximum power at higher voltage or frequency will be higher. table 3-6. power consumption (standard power) see table 3-2 on page 15 for recommended operating conditions. mode t j unit notes 800 mhz standard 933 mhz standard core voltage ? 1.45 1.5 v maximum power 105c 11.5 13.75 w 1, 2 typical power 65c 6.5 8.0 w 1, 3 notes: 1. these values apply for all valid 60 buses. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent, but is typically less than 2% of v dd power. 2. maximum power is measured at the indicated v dd and t j using parts with worst-case process parameters and running rc5-72. rc5-72 runs hotter than typical production c ode, but it is possible to design code t hat runs even hotter than rc5-72. see reduc- ing powerpc 750gx power dissipation application note for more information. 3. typical power is an estimate of the average value modeled in a system executing typical applications with v dd and typical process parameters. note that typical power cannot be used in the design of the power supply or cooling system.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 18 of 74 750gl_ds_body.fm 1.2 march 13, 2006 nap power, maximum 50c 5.2 6.2 w 1 sleep power, maximum 50c 5.2 6.0 w 1 table 3-6. power consumption (standard power) (continued) see table 3-2 on page 15 for recommended operating conditions. mode t j unit notes 800 mhz standard 933 mhz standard notes: 1. these values apply for all valid 60 buses. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent, but is typically less than 2% of v dd power. 2. maximum power is measured at the indicated v dd and t j using parts with worst-case process parameters and running rc5-72. rc5-72 runs hotter than typical production c ode, but it is possible to design code t hat runs even hotter than rc5-72. see reduc- ing powerpc 750gx power dissipation application note for more information. 3. typical power is an estimate of the average value m odeled in a system executing typical applications with v dd and typical process parameters. note that typical power cannot be used in the design of the power supply or cooling system.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 19 of 74 3.2 ac electrical characteristics this section provides the ac electrical characteristics for the 750gl. after fabrication, parts are sorted by maximum processor core frequency as shown in section 3.3, clock ac specifications, on page 19, and tested for conformance to the ac specifications for that frequency. the processor core frequency is deter- mined by the bus (sysclk) frequency and the settings of the pll configuration (pll_cfg[0-4]) signals. 3.3 clock ac specifications table 3-7 provides the clock ac timing specifications as defined in figure 3-1 . table 3-7. clock ac timing specifications see table 3-2 on page 15 for recommended operating conditions. 1, 3 figure 3-1 timing reference characteristic value unit notes min. max. processor frequency 500 933 mhz sysclk frequency 25 200 mhz 1 sysclk cycle time 5.0 40 ns 2, 3 sysclk slew rate 1.0 4.0 v/ns 2 4 sysclk duty cycle measured at 0.65 v 25 75 % sysclk cycle-to-cycle jitter ? 150 ps 4 internal pll relock time ? 100 s5 notes: 1. caution: the sysclk frequency and the pll_cfg[0:4] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll frequency do not exceed t heir respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in table 5-2, 750gl microprocessor pll configuration, on page 48 for valid pll_cfg[0:4] settings. 2. slew rate for the sysclk inputs is measured from 0.4 to 1.0 v. 3. timing is guaranteed by design and c haracterization, and is not tested. 4. see section 3.4, spread spectrum clock generator, on page 20 for long-term jitter. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hard reset (hreset ) must be held asserted for a minimum of 255 bus clocks afte r the pll-relock time during the power-on reset sequence. figure 3-1. sysclk input timing diagram v m cv il cv ih 1 2 4 3 4 sysclk v m-sysclk : 0.65 v
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 20 of 74 750gl_ds_body.fm 1.2 march 13, 2006 3.4 spread spectrum clock generator 3.4.1 design considerations when designing with the spread spectrum clock generator (sscg), there are a number of design issues that must be taken into account. sscg creates a controlled amount of long-term jitter. in order for a receiving pll in the 750gl to operate in this environment, it must be able to accurately track the sscg clock jitter. the accuracy to which the 750gl pll can track the sscg clock is referred to as tracking skew. when performing system timing analysis, the tracking skew must be added or subtracted to the i/o timing specifica- tions because the tracking skew appears as a static phase error between the internal pll and the sscg clock. to minimize the impact on i/o timings, the following sscg configuration is recommended: down spread mode, less than or equal to 1% of the maximum frequency. a modulation frequency of 30 khz. linear sweep modulation or ?hershey?s kiss? (as in a lexmark 1 profile) modulation profile as shown in figure 3-2 . in this configuration, the tracking skew is less than 100 ps. 1. see patent 5,631,920. figure 3-2. linear sweep modulation profile down spread frequency change 0% -1% 0 s time increases percentage decreases 33.3 s
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 21 of 74 3.5 60x bus input ac specifications table 3-8 provides the 60x bus ac timing specifications defined in figure 3-4 and figure 3-5 on page 23. 3.5.1 input setup timing the information in this subsection is provided to clarify the criteria used to establish the timings in table 3-8 . the dc electrical specifications shown in table 3-4 on page 16 are not altered by this clarification. the valid input signal levels remain v ih and v il . the input setup times shown as 10a in table 3-8 specify the required time from the input signal crossing v m to the rising edge of sysclk crossing v m . for the timings in table 3-8 to be valid, the falling edge of the input signal shown in table 3-8 is assumed to transition through v m and cross v il-ac at the slew rate specified in table 3-8 . input signals that do not reach the v il-ac boundary, or slew from v m to v il-ac more slowly than specified, will result in longer input setup times. in the same way, on the rising edge, the input signal must continue past v m and cross the v ih-ac boundary within the specified minimum slew rate. input signals that do not reach the v ih-ac boundary within the slew rate specified will result in longer input setup times. figure 3-4 provides the input timing diagram for the 750gl. table 3-8. 60x bus input ac timing specifications see table 3-2 on page 15 for operating conditions. 1, 5, 6 figure 3-4 and 3-5 timing reference characteristic 1.8 v mode 2.5 v mode 3.3 v mode unit notes min. max. min. max. min. max. 10a input setup: sysclk to inputs valid. 1.0 ? 1.1 ? 1.6 ? ns 10c mode select input setup to hreset (tlbi- sync , drtry , l2_tstclk, dbdis , qack , and dbwo ) 8?8?8?t sysclk 2, 3, 4 11a input hold: sysclk to inputs invalid, smi , tben, drtry , int , mcp , and tlbisync 0.45 ? 0.3 ? 0.3 ? ns 11c hreset to mode select input hold (tlbi- sync , drtry , l2_tstclk, dbdis , qack , and dbwo ) 0?0?0?ns2, 4 v m measurement reference voltage for inputs ov dd /2 ? v il-ac ac timing reference levels ?0.2?0.2?0.2 v7 v ih-ac ov dd - 0.2 ?ov dd - 0.2 ?ov dd - 0.2 ? slew rate reference input slew rate 1.0 ? 1.5 ? 2.0 ? v/ns notes: 1. input specifications are meas ured from the midpoint voltage (v m ) of the signal in question to the v m of the rising edge of the input sysclk. timings are measured at the pin (see figure 3-4 on page 22). 2. the setup and hold time is with respect to the rising edge of hreset (see figure 3-5 on page 23). 3. t sysclk is the period of the external clock (sysclk) in nanoseconds (n s). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time during the power-on reset sequence. 5. all values are guaranteed by design, and are not tested. 6. refer to section 3.5.1 on page 21 and figure 3-3 on page 22 for input setup timing definitions. 7. input reference signal levels used to est ablish the timings defined in this table.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 22 of 74 750gl_ds_body.fm 1.2 march 13, 2006 figure 3-3. input timing definition figure 3-4. input timing diagram slew rate v ih-ac v il v il-ac ov dd-0.2 v v ih ov dd /2 0.2 v ov dd v m gnd v t v m-sysclk (0.65 v) sysclk all inputs v m = midpoint voltage (ov dd /2) 10b 10a 11a v m v m 11b ov dd - 0.2 v 0.2 v note: the minimum slew rate specified in table 3-8 on page 21 is required to achieve t he input timings specified. see section 3.5.1, input setup timing, on page 21 and figure 3-3 for additional information.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 23 of 74 figure 3-5 provides the mode select input timing diagram for the 750gl. figure 3-5. mode select input timing diagram v ih v ih = 1.20?1.90 v for 1.8 v ov dd mode pins 10c 11c hreset 10c 11c v ih = 1.70?2.625 v for 2.5 v ov dd v ih = 2.4?3.465 v for 3.3 v ov dd
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 24 of 74 750gl_ds_body.fm 1.2 march 13, 2006 3.6 60x bus output ac specifications table 3-9 provides the 60 bus output ac timing specifications for the 750gl as defined in figure 3-7 on page 26. table 3-9. 60x bus output ac timing specifications see table 3-2 on page 15 for operating conditions. 1, 4, 6 figure 3-7 timing reference characteristic 1.8 v 2.5 v 3.3 v unit notes min. max. min. max. min. max. 12 sysclk to output driven (output enable time) 0.3 ? 0.3 ? 0.3 ? ns 13 sysclk to output valid ? 2.4 ? 2.3 ? 2.4 ns 5 14 sysclk to output invalid (output hold) 1.0 ? 0.6 ? 0.6 ? ns 15 sysclk to output high impedance (all signals except address retry [artry ], address bus busy [abb ], and data bus busy [dbb ]) ?2.5?2.5?2.5ns 16 sysclk to abb and dbb high impedance after precharge ?1.0?1.0?1.0t sysclk 2 17 sysclk to artry high impedance before precharge ?3.0?3.0?3.0ns 18 sysclk to artry precharge enable 0.2 t sysclk + 1.0 0.2 t sysclk + 1.0 ? 0.2 t sysclk + 1.0 ?ns 3 19 maximum delay to artry precharge ? 1.0 ? 1.0 ? 1.0 t sysclk 2, 3 20 sysclk to artry high impedance after precharge ?2.0?2.0?2.0t sysclk 2, 3 notes: 1. all output specifications are measured from the v m of the rising edge of sysclk to the midpoint of the output signal in question using a test load as shown in figure 3-6 on page 25. both input and output timings ar e measured at the pin. timings are deter- mined by design. 2. t sysclk is the period of the external bus clock (sysclk) in nanos econds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 3. nominal precharge width for artry is 1.0 t sysclk . 4. guaranteed by design and characterization, and not tested. 5. output valid timing increases as the v dd is reduced. these values assume a v dd minimum of 1.4 v. 6. see figure 3-6 on page 25 and figure 3-7 on page 26 for output loading and timing definitions.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 25 of 74 figure 3-6. output valid timing definition note: the timing definition is valid using the termination model shown here with timings referenced to the respective pin of the spec i- fied output driver. output driver sysclk positive output transition negative output transition output transition defined between sysclk at v m and the respective transition level. v m = ov dd /2 12 pf v m-sysclk (0.65 v)
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 26 of 74 750gl_ds_body.fm 1.2 march 13, 2006 figure 3-7. output timing diagram for ibm powerpc 750gl risc microprocessor note: sysclk v m as defined in section 3.3, clock ac specifications, on page 19. output v m as defined in figure 3-6, output valid timing definition, on page 25. sysclk all outputs (except ts , artry ) ts artry 12 13 13 14 15 15 v m-sysclk v m-sysclk 14 v m-sysclk 13 19 17 20 18 v m v m v m low level hi-z high level 16 abb , dbb
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 27 of 74 3.6.1 ieee 1149.1 ac timing specifications table 3-10 provides the ieee 1149.1 (jtag) ac timing specifications as defined in the following figures: the five jtag signals are: test data input (tdi), test data output (tdo), test mode select (tms), test clock (tck), and test reset (trst ). to find out more about... see... jtag clock input timing diagram figure 3-8 on page 28. trst timing diagram figure 3-9 on page 28. boundary-scan timing diagram figure 3-10 on page 28. test access port timing diagram figure 3-11 on page 29. table 3-10. jtag ac timing specifications (independent of sysclk) see table 3-2 on page 15 for operating conditions. figures 3-8 through 3-11 timing reference characteristic min. max. unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ? ns 2 tck clock pulse width measured at 1.1 v 15 ? ns 3 tck rise and fall times 0 2 ns 4 4 specification obsolete, intentionally omitted ? ? ? 5trst assert time 25 ? ns 1 6 boundary-scan input data setup time 0 ? ns 2 7 boundary-scan input data hold time 13 ? ns 2 8 tck to output data valid ? 8 ns 3, 5 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ? ns 11 tms, tdi data hold time 15 ? ns 12 tck to tdo data valid 2.0 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 14 tck to output data invalid (output hold) 0 ? ns notes: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum specification guaranteed by characterization and not tested.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary electrical and thermal characteristics page 28 of 74 750gl_ds_body.fm 1.2 march 13, 2006 figure 3-8 provides the jtag clock input timing diagram. figure 3-9 provides the trst timing diagram. figure 3-10 provides the boundary-scan timing diagram. figure 3-8. jtag clock input timing diagram figure 3-9. trst timing diagram figure 3-10. boundary-scan timing diagram 1 2 2 3 3 v m tck v m v m v m = midpoint voltage (ov dd /2) 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 electrical and thermal characteristics page 29 of 74 figure 3-11 provides the test access port timing diagram. figure 3-11. test access port timing diagram 12 10 11 tck tdi, tms tdo tdo input data (valid) output data (valid) tdo 13 14 output data (invalid)
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 30 of 74 750gl_ds_body.fm 1.2 march 13, 2006 4. dimensions and signal assignments ibm offers a lead-reduced ceramic ball grid array (cbga) that supports 292 balls for the 750gl package. this is a signal and power compatible footprint to the powerpc 750fx risc microprocessor module. this section contains several views of the 750gl physical package and descriptions and listings of the signals and ball/pin locations. use a01 corner designation for correct placement. use the five plated dots that form a right angle (|_) to locate the a01 corner as shown in figure 4-1 . 4.1 package
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 31 of 74 figure 4-1. mechanical dimensions, standard (leaded) package (292x) ? 0.8 0.04 ? ? 0.3 m c c a s b s 0.1 m (solderball) a01 corner (chip carrier) (19x) (1) (19x) (1) 19 (21) 19 (21) 1 2 (0.91 max) (0.33 min) (0.91 max) (0.33 min) view a-a 1 c7 this side 2 b 96p3464 (21 0.2) 2 1 a (21 0.2) 1 2 b module sub-asm a01 corner (chip carrier) chip capacitor c4encapsulant fillet 45l5857 (292) solderball 5 3 a a j4 e d 0.81 0.1 (1.32 max) (1.08 min) (7x)(0.51 max) (7x)(1.83 max) (7x)(2.74 max) (0.907 max) (0.779 min) (2.227 max) (1.859 min) (3.137 max) (2.569 min) 0.15 c seating c plane m odule subassembly drawing 96p3537 this side
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 32 of 74 750gl_ds_body.fm 1.2 march 13, 2006 notes: 1. datum a is the center plane of feature labeled datum a. 2. datum b is the center plane of feature labeled datum b. 3. unless otherwise specified, part is symmetrical about centerlines defined by datums a and b. 4. where not otherwise defined, centerlines indicated are to be interpreted as a datum framework estab- lished by datums d, a, and b, respectively. 5. eutectic solder 63/37 sn/pn is used to join ball to chip carrier. figure 4-1. mechanical dimensions, standard (leaded) package(continued)
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 33 of 74 figure 4-2. mechanical dimensions, rohs-compatible package (292x) ? 0.7 0.1 ? ? 0.25 m c c a s b s 0.10 m (sac solderball) a01 corner (chip carrier) (19x) (1) (19x) (1) 19 (21) 19 (21) 1 2 (1.15 max) (0.45 min) (1.15 max) (0.45 min) view a-a 1 c7 this side 2 b 32r8168 (21 0.2) 2 1 a (21 0.2) 1 2 b module sub-asm a01 corner (chip carrier) chip capacitor c4 encapsulant fillet 99p0225 (292) sac solderball 5 3 a a j4 e d 0.5 0.1 (1.32 max) (1.08 min) (7x)(0.51 max) (7x)(1.83 max) (2.42 max) (0.908 max) (0.779 min) (2.228 max) (1.859 min) (2.828 max) (2.259 min) 0.2 c seating c plane m odule subassembly drawing 32r8317 this side
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 34 of 74 750gl_ds_body.fm 1.2 march 13, 2006 notes: 1. datum a is the center plane of feature labeled datum a. 2. datum b is the center plane of feature labeled datum b. 3. unless otherwise specified, part is symmetrical about centerlines defined by datums a and b. 4. where not otherwise defined, centerlines indicated are to be interpreted as a datum framework estab- lished by datums d, a, and b, respectively. 5. snagcu (sac) balls joined to the chip carrier. figure 4-2. mechanical dimensions, rohs-compatible package (continued)
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 35 of 74 4.2 module substrate decoupling voltage assignments the on-board substrate voltage-to-ground assignments for the capacitor locations are shown in figure 4-3 . figure 4-3. module substrate decoupling voltage assignments a01 corner b04 b03 c02 d02 e02 f04 f03 + = v dd ? = gnd 2 = ov dd ? ? 2 + + 2 + ? ? ? 2 ? + ?
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 36 of 74 750gl_ds_body.fm 1.2 march 13, 2006 4.3 microprocessor ball placement figure 4-4. powerpc 750gl microprocessor ball placement 20 a6 a8 a3 a2 a0 dh31 dh25 dh26 dp2 dh22 dh19 dh18 dh16 dh15 dh14 dp0 dh9 dh10 dh4 dh2 19 a13 gnd a5 a4 a1 dh29 dp3 dh28 dh23 dh24 dh21 dh20 dp1 dh17 dh11 dh8 dh6 dh5 gnd dh3 18 a11 a10 ovdd gnd ovdd gnd vdd vdd gnd ovdd gnd ovdd dh0 pll_cfg0 17 a12 tt1 ovdd a9 dh30 dh27 gnd gnd dh12 dh13 dh1 ovdd pll_cfg1 pll_cfg2 16 a14 a15 gnd ap0 a7 gnd ovdd ovdd ovdd ovdd gnd dh7 pll_cfg3 gnd sysclk a2vdd 15 tt3 ts vdd vdd pll_rng0 a1vdd 14 tsiz0 tt2 ovdd tt0 gnd ovdd gnd gnd ovdd gnd pll_rng1 ovdd pll_cfg4 agnd 13 ap2 tt4 gnd ap1 vdd gnd gnd vdd vdd vdd vdd gnd gnd vdd llsd_ mode gnd l2_tstclk l1_tstclk 12 ta tsiz1 vdd gnd gnd gnd gnd vdd mcp checkstop 11 tbst tsiz2 vdd gnd ovdd gnd vdd vdd gnd ovdd gnd vdd tlbisync hreset 10 dbdis a16 vdd gnd ovdd gnd gnd gnd gnd ovdd gnd vdd smi ckstp 9 a18 a17 vdd gnd vdd vdd gnd vdd bvsel int 8 aack ap3 gnd a21 vdd gnd gnd vdd vdd vdd vdd gnd gnd vdd qreq gnd tben qack 7 a20 a19 ovdd a24 gnd ovdd gnd gnd ovdd gnd dbb ovdd artry sreset 6 dbwo a23 vdd vdd tea abb 5 a22 a26 gnd a25 a31 gnd ovdd ovdd ovdd ovdd gnd clk_o ut wt gnd tdo dbg 4 a28 a27 ovdd dl3 dp5 dl13 gnd gnd dl23 dl26 ci ovdd bg rsrv 3 a29 a30 ovdd gnd ovdd gnd vdd vdd gnd ovdd gnd ovdd drtry br 2 dl0 gnd dl2 dl6 dl5 dl11 dl10 dl12 dl16 dl15 dl19 dl20 dl22 dl27 dl28 tck dl30 tdi gnd blank 1 dl1 dp4 dl4 dl8 dl7 dl9 dl14 dp6 dl18 dl17 dl21 dp7 dl24 dl25 dl29 dl31 trst tms gbl blank a b c d e f g h j k l m n p r t u v w y note: this view is looking down from above the 750gl placed and soldered on the system board.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 37 of 74 4.4 pinout listings table 4-1 contains the pinout listing for the 750gl cbga package. table 4-1. pinout listing for the cbga package signal name pin number active input/output notes a[0:31] e20, e19, d20, c20, d19, c19, a20, e16, b20, e17, b18, a18, a17, a19, a16, b16, b10, b9, a9, b7, a7, d8, a5, b6, d7, d5, b5, b4, a4, a3, b3, e5. high input/output a1v dd y15 ? ? a2v dd y16 ? ? aack a8 low input abb y6 low input/output agnd y14 ? ? ap[0:3] d16, d13, a13, b8 high input/output 6 artry w7 low input/output bg w4 low input blank y1, y2 ? ? 3 br y3 low output bvsel w9 ? input 4 checkstop (ckstp_out) y12 low output ci t4 low output ckstp_in y10 low input clk_out t5 high output dbb u7 low input/output dbdis a10 low input dbg y5 low input dbwo a6 low input dh[0:31] w18, t17, y20, y19, w20, v19, u19, t16, t19, u20, v20, r19, n17, p17, r20, p20, n20, p19, m20, l20, m19, l19, k20, j19, k19, g20, h20, h17, h19, f19, g17, f20 high input/output dl[0:31] a2, a1, c2, e4, c1, e2, d2, e1, d1, f1, g2, f2, h2, h4, g1, k2, j2, k1, j1, l2, m2, l1, n2, n4, n1, p1, p4, p2, r2, r1, u2, t1 high input/output dp[0:7] t20, n19, j20, g19, b1, g4, h1, m1 high input/output 6 drtry w3 low input gbl w1 low input/output notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus. 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left floating if unused in the design.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 38 of 74 750gl_ds_body.fm 1.2 march 13, 2006 gnd b2, b19, c5, c8, c13, c16, d10, d11, e3, e7, e14, e18, f10, f11, g5, g8, g13, g16, h3, h8, h9, h12, h13, h18, j12, k4, k7, k10, k14, k17, l4, l7, l10, l14, l17, m12, n3, n8, n9, n12, n13, n18, p5, p8. p13, p16, r10, r11, t3, t7, t14, t18, u10, u11, v5, v8, v13,v16, w2, w19, ?? hreset y11 low input int y9 low input l1_tstclk y13 high input 4 l2_tstclk w13 high input 1 lssd_mode u13 low input 1 mcp w12 low input ov dd c4, c7, c14, c17, d3, d18, e10, e11, g3, g7, g14, g18, h5, h16, k5, k16, l5, l16, n5, n16, p3, p7, p14, p18, t10, t11, u3, u18, v4, v7, v14, v17 ??2 pll_cfg[0:4] y18, w17, y17, u16, w14 high input pll_rng[0:1] w15, u14 high input qack y8 low input qreq u8 low output rsrv y4 low output smi w10 low input sreset y7 low input sysclk w16 high input ta a12 low input tben w8 high input tbst a11 low input/output tck t2 high input 5 tdi v2 high input tdo w5 high output tea w6 low input tlbisync w11 low input tms v1 high input trst u1 low input ts b15 low input/output tsiz[0:2] a14, b12, b11 high output table 4-1. pinout listing for the cbga package (continued) signal name pin number active input/output notes notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus. 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left floating if unused in the design.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 39 of 74 tt[0:4] d14, b17, b14, a15, b13 high input/output v dd c10, c11, e8, e13, f6, f9, f12, f15, j8, j9, j13, k3, k8, k11, k13, k18, l3, l8, l11, l13, l18, m8, m9, m13, r6, r9, r12, r15, t8, t13, v10, v11 ??2 wt u5 low output table 4-1. pinout listing for the cbga package (continued) signal name pin number active input/output notes notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus. 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left floating if unused in the design.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 40 of 74 750gl_ds_body.fm 1.2 march 13, 2006 table 4-2. signal listing for the cbga package signal name pin count active input/output notes a[0:31] 32 high input/output a1v dd 1 ? ? supply for pll0 a2v dd 1 ? ? supply for pll1 aack 1 low input abb 1 low input/output agnd 1 ? ? ground for pll ap[0:3] 4 high input/output artry 1 low input/output bg 1 low input br 1 low output bvsel 1 high input i/o voltage mode select for 60x bus. see section 5.8.3 on page 72 for setup conditions. ci 1 low output ckstp_in 1 low input ckstp_out 1 low output clk_out 1 high output dbb 1 low input/output dbdis 1 low input factory usage mode pin. pull inactive (high) when hreset transitions from low to high for normal machine operation. dbg 1 low input dbwo 1 low input factory usage mode pin. pull inactive (high) when hreset transitions from low to high for normal machine operation. dh[0:31] 32 high input/output dl[0:31] 32 high input/output dp[0:31] 8 high input/output drtry 1 low input optional data retry mode select. this function will be set when hreset transitions from low to high. drtry high indicates data-retry mode; drtry low indicates no data-retry mode. gbl 1 low input/output ground 60 ? ? common ground hreset 1 low input see note 1. notes: 1. qack in a logical high state at the transition of hreset from asserted to negated enables standard pre-charge mode in the 750gl. qack in a logical low state at the transition of hreset from asserted to negated enables extended pre-charge mode in the 750gl. 2. qack , in a logical low state at the transition of qreq from asserted to negated, enables the 750gl processor to enter the soft stop (nap) state for proper jtag emulator operation.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 41 of 74 int 1 low input l1_tstclk 1 high input i/o voltage mode select for 60x bus. see section 5.8.3 on page 72 for setup conditions. l2_tstclk 1 high input these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. lssd_mode 1 low input these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. mcp 1 low input ov dd 32 ? ? supply for receivers/drivers pll_cfg[0:4] 5 high input pll_rng[0:1] 2 high input qack 1 low input see notes 1 and 2. qreq 1 low output rsrv 1 low output smi 1 low input sreset 1 low input sysclk 1 high input ta 1 low input tben 1 high input tbst 1 low input/output tck 1 high input tdi 1 high input tdo 1 high output tea 1 low input tlbisync 1 low input optional : 64/32-bit data bus mode select. this function will be set when hreset transitions (low to high). tlbisync : high = 64-bit mode, low = 32-bit mode. tms 1 high input trst 1 low input ts 1 low input/output tsiz[0:2] 3 high output tt[0:4] 5 high input/output v dd 32 supply for core table 4-2. signal listing for the cbga package (continued) signal name pin count active input/output notes notes: 1. qack in a logical high state at the transition of hreset from asserted to negated enables standard pre-charge mode in the 750gl. qack in a logical low state at the transition of hreset from asserted to negated enables extended pre-charge mode in the 750gl. 2. qack , in a logical low state at the transition of qreq from asserted to negated, enables the 750gl processor to enter the soft stop (nap) state for proper jtag emulator operation.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 42 of 74 750gl_ds_body.fm 1.2 march 13, 2006 wt 1 low output table 4-2. signal listing for the cbga package (continued) signal name pin count active input/output notes notes: 1. qack in a logical high state at the transition of hreset from asserted to negated enables standard pre-charge mode in the 750gl. qack in a logical low state at the transition of hreset from asserted to negated enables extended pre-charge mode in the 750gl. 2. qack , in a logical low state at the transition of qreq from asserted to negated, enables the 750gl processor to enter the soft stop (nap) state for proper jtag emulator operation.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 43 of 74 . table 4-3. signal locations signal ball location signal ball location signal ball location signal ball location a0 e20 dh0 w18 dl0 a2 aack a8 a1 e19 dh1 t17 dl1 a1 abb y6 a2 d20 dh2 y20 dl2 c2 agnd y14 a3 c20 dh3 y19 dl3 e4 artry w7 a4 d19 dh4 w20 dl4 c1 bg w4 a5 c19 dh5 v19 dl5 e2 br y3 a6 a20 dh6 u19 dl6 d2 bvsel w9 a7 e16 dh7 t16 dl7 e1 checkstop (ckstp_out )y12 a8 b20 dh8 t19 dl8 d1 ci t4 a9 e17 dh9 u20 dl9 f1 clk_out t5 a10 b18 dh10 v20 dl10 g2 ckstp (ckstp_in )y10 a11 a18 dh11 r19 dl11 f2 dbb u7 a12 a17 dh12 n17 dl12 h2 dbdis a10 a13 a19 dh13 p17 dl13 h4 dbg y5 a14 a16 dh14 r20 dl14 g1 dbwo a6 a15 b16 dh15 p20 dl15 k2 drtry w3 a16 b10 dh16 n20 dl16 j2 gbl w1 a17 b9 dh17 p19 dl17 k1 hreset y11 a18 a9 dh18 m20 dl18 j1 int y9 a19 b7 dh19 l20 dl19 l2 l1_tstclk y13 a20 a7 dh20 m19 dl20 m2 l2_tstclk w13 a21 d8 dh21 l19 dl21 l1 lssd_mode u13 a22 a5 dh22 k20 dl22 n2 mcp w12 a23 b6 dh23 j19 dl23 n4 pll_cfg0 y18 a24 d7 dh24 k19 dl24 n1 pll_cfg1 w17 a25 d5 dh25 g20 dl25 p1 pll_cfg2 y17 a26 b5 dh26 h20 dl26 p4 pll_cfg3 u16 a27 b4 dh27 h17 dl27 p2 pll_cfg4 w14 a28 a4 dh28 h19 dl28 r2 pll_rng0 w15 a29 a3 dh29 f19 dl29 r1 pll_rng1 u14 a30 b3 dh30 g17 dl30 u2 qack y8 a31 e5 dh31 f20 dl31 t1 qreq u8 rsrv y4 smi w10 sreset y7 sysclk w16
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary dimensions and signal assignments page 44 of 74 750gl_ds_body.fm 1.2 march 13, 2006 ap0 d16 dp0 t20 ta a12 ap1 d13 dp1 n19 tben w8 ap2 a13 dp2 j20 tbst a11 ap3 b8 dp3 g19 tck t2 dp4 b1 tdi v2 dp5 g4 tdo w5 dp6 h1 tea w6 dp7 m1 tlbisync w11 tms v1 trst u1 ts b15 tsiz0 a14 tsiz1 b12 tsiz2 b11 tt0 d14 tt1 b17 tt2 b14 tt3 a15 tt4 b13 wt u5 table 4-3. signal locations (continued) signal ball location signal ball location signal ball location signal ball location
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 dimensions and signal assignments page 45 of 74 table 4-4. voltage and ground assignments a1v dd a2v dd ov dd ov dd v dd v dd gnd gnd y15 y16 c4 c7 c10 c11 b2 b19 c14 c17 e8 e13 c5 c8 d3 d18 f6 f9 c13 c16 e10 e11 f12 f15 d10 d11 g3 g7 j8 j9 e3 e7 g14 g18 j13 k3 e14 e18 h5 h16 k8 k11 f10 f11 k5 k16 k13 k18 g5 g8 l5 l16 l3 l8 g13 g16 n5 n16 l11 l13 h3 h8 p3 p7 l18 m8 h9 h12 p14 p18 m9 m13 h13 h18 t10 t11 r6 r9 j12 k4 u3 u18 r12 r15 k7 k10 v4 v7 t8 t13 k14 k17 v14 v17 v10 v11 l4 l7 l10 l14 l17 m12 n3 n8 n9 n12 n13 n18 p5 p8 p13 p16 r10 r11 t3 t7 t14 t18 u10 u11 v5 v8 v13 v16 w2 w19
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 46 of 74 750gl_ds_body.fm 1.2 march 13, 2006 5. system design information this section provides electrical and thermal design recommendations for successful applications on the 750gl. 5.1 pll operation after the 750gl application condition, within the supported limits, has been selected, the 750gl?s dual pll feature can also be used to provide additional power savings. 5.1.1 overview the 750gl design includes two plls (pll0 and pll1), allowing the processor clock frequency to dynami- cally change between the pll frequencies via software control. use the bits in hardware implementation dependent register 1 (hid1) to specify: the frequency range of each pll the clock multiplier for each pll external or internal control of pll0 which pll is selected (which is the source of the processor clock at any given time) at power-on reset, the hid1 register contains zeros for all the non-read-only bits (bits 7 to 31). this configura- tion corresponds to the selection of pll0 as the source of the processor clocks and selects the external configuration and range pins to control pll0. the external configuration and range pin values are accessible to software using hid1 read-only bits 0-6. pll1 is always controlled by its internal configuration and range bits. the hid1 setting associated with hard reset corresponds to a pll1 configuration of clock off, and selec- tion of the medium frequency range. as stated in the hardware specification, hreset must be asserted during power up long enough for the pll(s) to lock, and for the internal hardware to be reset. once this timing is satisfied, hreset can be negated. the processor now will proceed to execute instructions, clocked by pll0 as configured via the external pins. the processor clock frequency can be modified from this initial setting in one of two ways. first, as with earlier designs, hreset can be asserted, and the external configuration pins can be set to a new value. the machine state is lost in this process, and, as always, hreset must be held asserted while the pll relocks, and the internal state is reset. second, the introduction of another pll provides an alternative means of changing the processor clock frequency, which does not involve the loss of machine state nor a delay for pll relock. the following sequence can be used to change processor clock frequency. note: assume pll0 is currently the source for the processor clock. 1. configure pll1 to produce the desired clock frequency by setting hid1[pr1] and hid1[pc1] to the appropriate values. 2. wait for pll1 to lock. the lock time is the same for both plls (see table 3-7, clock ac timing specifica- tions, on page 19). 3. set hid1[ps] to '1' to initiate the transition from pll0 to pll1 as the source of the processor clocks. from the time the hid1 register is updated to select the new pll, the transition to the new clock fre- quency will complete within three bus cycles. after the transition, the hid(pss) bit indicates which pll is in use.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 47 of 74 after both plls are running and locked, the processor frequency can be toggled with very low latency. for example, when it is time to change back to the pll0 frequency, there is no need to wait for pll lock. hid1[ps] can be reset to '0', causing the processor clock source to transition from pll1 back to pll0. if pll0 will not be needed for some time, it can be configured to be off while not in use. this is done by resetting the hid1[pc0] field to '0', and setting hid1[pi0] to '1'. turning the non-selected pll off results in a modest power savings, but introduces added latency when changing frequency. if pll0 is configured to be off, the procedure for switching to pll0 as the selected pll involves changing the configuration and range bits, waiting for lock, and then selecting pll0, as described in the previous paragraph. 5.1.2 restrictions and considerations for pll configuration consider the following when reconfiguring the plls: the configuration and range bits in hid1 should only be modified for the non-selected pll, since it will require time to lock before it can be used as the source for the processor clock. the hid1[pi0] bit should only be modified when pll0 is not selected. whenever one of the plls is reconfigured, it must not be selected as the active pll until enough time has elapsed for the pll to lock. at all times, the frequency of the processor clock, as determined by the various configuration settings, must be within the specification range for the current operating conditions. never select a pll that is in the off configuration. 5.1.2.1 configuration restriction on frequency transitions it is considered a programming error to switch from one pll to the other when both are configured in a half-cycle multiplier mode. for example, with pll0 configured in 9:2 mode (pc0) and pll1 configured in 13:2 mode (pc1), changing the select bit (hid1[ps]) is not allowed. in cases where such a pairing of configu- rations is desired, an intermediate full-cycle configuration must be used between the two half-cycle modes. for example, with pll0 at 9:2, pll1, configured at 6:1, is selected. then pll0 is re configured at 13:2, locked, and selected. 5.1.3 pll_rng[0:1] definitions for dual pll operation the dual plls on the 750gl are configured by the pll_cfg[0:4] and pll_rng[0:1] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and voltage controlled oscillator (vco) frequency of operation. the 750gl pll range configuration for dual pll operation is shown in the following table. table 5-1. pll_rng[0:1] definitions for dual pll operation pll_rng[0:1] pll frequency range 00 (default) 600 mhz?900 mhz 01 (fast) 900 mhz?1.0 ghz 10 (slow) 500 mhz?600 mhz 11 (reserved) reserved note: pll_rng bit settings are valid for a v dd range of 1.4 v?1.55 v and a temperature range of -40 c?105 c.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 48 of 74 750gl_ds_body.fm 1.2 march 13, 2006 5.1.4 pll configuration table 5-2 shows the pll configuration for the 750gl for nominal frequencies. table 5-2. 750gl microprocessor pll configuration pll_cfg [0:4] processor to bus frequency ratio (ptbfr) frequency range supported by vco having an example range of... sysclk 1 (mhz) core (mhz) binary decimal minimum (sysclk min ) maximum (sysclk max ) minimum (core frequency min ) maximum (core frequency max ) 00000 0 off 2 n/a n/a off off 00001 1 off 2 n/a n/a off off 00010 2 pll bypass 3 n/a n/a n/a n/a 00011 3 pll bypass 3 n/a n/a n/a n/a 00100 4 2 4 n/a n/a n/a n/a 00101 5 2.5 4 200 200 500 500 00110 6 3 4 167 200 500 600 00111 7 3.5 4 143 200 500 700 01000 8 4 125 200 500 800 01001 9 4.5 111 200 500 900 01010 10 5 100 200 500 1000 01011 11 5.5 91 182 500 1000 01100 12 6 83 166 500 1000 01101 13 6.5 77 154 500 1000 01110 14 7 71 143 500 1000 01111 15 7.5 67 133 500 1000 10000 16 8 62 125 500 1000 10001 17 8.5 59 118 500 1000 10010 18 9 55 111 500 1000 10011 19 9.5 51 105 500 1000 10100 20 10 50 100 500 1000 10101 21 11 45 91 500 1000 10110 22 12 42 83 500 1000 10111 23 13 38 77 500 1000 11000 24 14 36 71 500 1000 11001 25 15 33 66 500 1000 notes: 1. the sysclk frequency equals the core frequency divided by the processor-to-bus frequency ratio (ptbfr). 2. in clock-off mode, no clocking occurs inside the 750gl regardless of the sysclk input. 3. in pll-bypass mode, the sysclk input signal clocks the inte rnal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. the ac timing specifications given in the document do not apply in pll-bypass mode. 4. the 2?3.5 processor-to-bus ratios are currently not supported when miss- under-miss is enabled (hid0(14) = '1').
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 49 of 74 11010 26 16 31 63 500 1000 11011 27 17 29 59 500 1000 11100 28 18 28 56 500 1000 11101 29 19 26 53 500 1000 11110 30 20 25 50 500 1000 11111 31 off 2 n/a n/a n/a n/a table 5-2. 750gl microprocessor pll configuration (continued) pll_cfg [0:4] processor to bus frequency ratio (ptbfr) frequency range supported by vco having an example range of... sysclk 1 (mhz) core (mhz) binary decimal minimum (sysclk min ) maximum (sysclk max ) minimum (core frequency min ) maximum (core frequency max ) notes: 1. the sysclk frequency equals the core frequency divided by the processor-to-bus frequency ratio (ptbfr). 2. in clock-off mode, no clocking occurs inside the 750gl regardless of the sysclk input. 3. in pll-bypass mode, the sysclk input signal clocks the inte rnal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. the ac timing specifications given in the document do not apply in pll-bypass mode. 4. the 2?3.5 processor-to-bus ratios are currently not supported when miss- under-miss is enabled (hid0(14) = '1').
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 50 of 74 750gl_ds_body.fm 1.2 march 13, 2006 5.2 pll power supply filtering the 750gl microprocessor has two separate av dd signals (a1v dd and a2v dd ), which provide power to the clock generation pll. most designs are expected to use a single pll configuration mode throughout the application. these types of designs should use the default pll (pll0), filtering its respective supply, a1v dd . the a2v dd supply signal should be grounded through a 100 ? resistor, as shown in figure 5-1 on page 51. for designs planning to optimize power savings through dynamic switching between dual pll circuits, it is recommended, though not required, that each av dd have a separate voltage input and filter circuit. this optional circuit is also shown. to ensure stability of the internal clock, the power supplied to the av dd input signals should be filtered using a circuit similar to the one shown in figure 5-1 on page 51. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. for descriptions of the sample pll power supply filtering circuits, see table 5-3 . table 5-3. sample pll power supply filtering circuits circuit description number of filtering circuits ferrite beads circuit figure recommended circuit design notes single pll circuit configuration that uses the a1v dd and ties the a2v dd pin to gnd. 11 figure 5-1 on page 51 yes 1, 2 single pll circuit configuration that uses both the a1v dd and the a2v dd pins and a single ferrite bead. 11 figure 5-2 on page 51 optional 1, 2 dual pll configuration that uses a separate circuit for the a1v dd pin and for the a2v dd pin. 22 figure 5-3 on page 53 yes 2, 3 notes: 1. optional configurations are supported, though not recommended. 2. this circuit design can be used with the dual pll feature enabled, though optimum power savings may not be realized. for additional information, see figure 5-3, dual pll power supply filter circuits, on page 53. 3. this circuit design can be used with the dual pll feature enabled to optimize power savings.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 51 of 74 figure 5-1. single pll power supply filter circuit with a1v dd pin and a2v dd pin tied to gnd (recommended) figure 5-2. pll power supply filter circuit with two av dd pins and one ferrite bead (optional) discrete resistor 2 ? ferrite bead1 av dd c2 c1 agnd pin 1 a1v dd pin item description/value resistor 2 ? , 100 ? c1 0.1 f ceramic c2 10.0 f ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar notes: 1. connected to ground without a filter. 2. single pll0 only. a2v dd 2 pin discrete resistor 100 ? discrete resistor 2 ? ferrite bead1 av dd c2 c1 agnd pin 1 a1v dd pin item description/value resistor 2 ? c1 0.1 f ceramic c2 10.0 f ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar note: 1. connected to ground without a filter. a2v dd pin
datasheet dd1.x preliminary ibm powerpc 750gl risc microprocessor 750gl_ds_body.fm.1.2 march 13, 2006 system design information page 52 of 74
datasheet dd1.x ibm powerpc 750gl risc microprocessor preliminary system design information page 53 of 74 750gl_ds_body.fm.1.2 march 13, 2006 figure 5-3. dual pll power supply filter circuits (recommended if dual-pll is enabled) 1 discrete resistor 2 ? ferrite bead av dd 2 c2 c1 agnd pin a1v dd pin item description/value resistor 2 ? c1 0.1 f ceramic c2 10.0 f ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar notes: 1. the dual pll power supply circuits shown in this figure are recommended for a desi gn that uses the dual pll feature. for more information about the dual pll feature, see section 5.2, low voltage operation at lower frequency, on page 43. 2. connected to ground without a filter. discrete resistor 2 ? ferrite bead av dd 2 c2 c1 agnd pin a2v dd pin
datasheet dd1.x ibm powerpc 750gl risc microprocessor preliminary system design information page 54 of 74 750gl_ds_body.fm.1.2 march 13, 2006 5.3 decoupling recommendations capacitor decoupling is required for the 750gl. decoupling capacitors act to reduce high-frequency chip switching noise and pro vide localized bulk charge storage to reduce major power-surge effects. guidelines for high-frequency noise decoupling will be provided in a s eparate appli- cation note. bulk decoupling requires a more complete understanding of the system and system power architecture, which is beyon d the scope of this document. high-frequency decoupling capacitors should be located as close as possible to the processor with low lead inductance to the gr ound and voltage planes. decoupling capacitors are recommended on the back of the card, directly opposite the module. the recommended placement and numb er of decoupling capacitors, 34 v dd -gnd capacitors and 44 ov dd -gnd capacitors, are described in figure 5-4 on page 56. the recommended decoupling capacitor specifications are provided in table 5-4 . the placement and usage described here are guidelines for decoupling capaci- tors and should be applied for system designs. note: the decoupling capacitor electrodes are located directly opposite their corresponding bga pins where possible. also, each elect rode for each decoupling capacitor needs to be connected to one or more bga pins (balls) with a short electrical path. thus, through -vias adjacent to the decoupling capacitors are recommended. the card designer can expand on the decoupling capacitor recommendations by doing the following: adding additional decoupling capacitors. if using additional decoupling capacitors, verify that these additional capacitors do not reduce the number of card vias or cau se the vias to lose proximity to each capacitor electrode. adding additional through-vias or blind-vias. card technologies are available that will reduce the inductance between the decoupling capacitor and the bga pin (ball). replac ing single vias with multiple vias is certainly approved. place gnd vias close to v dd or ov dd vias to reduce loop inductance. table 5-4. recommended decoupling capacitor specifications item description decoupling capacitor specifications: type x5r or y5v 10 v minimum 0402 size 40 20 mils, nominally 1.0 mm 0.5 mm 0.1 mm on both dimensions 100 nf recommended minimum number of decou- pling capacitors on the back of the card: 34 v dd -gnd capacitors 44 ov dd -gnd capacitors
datasheet dd1.x preliminary ibm powerpc 750gl risc microprocessor 750gl_ds_body.fm.1.2 march 13, 2006 system design information page 55 of 74 figure 5-4 on page 56 shows the mapping of power, ground, and signal pin assignments, and recommended layout of decoupling capacitors under application conditions. in test mode, pins c11 and g8 can be used as kelvin probes, in which case the pins should be disc onnected from card gnd and v dd . capacitors should not be connected to the kelvin pins during kelvin probe voltage measurements.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 56 of 74 750gl_ds_body.fm 1.2 march 13, 2006 5.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all no-connect (nc) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , av dd , and gnd pins of the 750gl. figure 5-4. orientation and layout of the 750gl decoupling capacitors vd v v o g g g g g g g g g g g g g g g g g g g g g g g g g g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g g g g g o v v v g v v g g v g g v g v g v g v g g g v g v g v v o g o g o g o g o g o g g v g v g v g v g v g v g v v o g o g g g g g v g v v = av dd pin = agnd pin = ov dd gnd capacitor = v dd gnd capacitor = gnd via = v dd via = ov dd via = gnd pin = v dd pin = ov dd pin = signal pin g v o v g ov vd vg vg vg ov ov ov vg vd vd ov vg ov vg v v ov vg vg ov vg vg ov ov ov vg vg ov vd vg vd vg vd vg vg vd vd vd vd vg vg ov ov vg ov vg ov vg vg vg vg vd vd vd vd vg ov vg vg vg vg ov ov vg ov vd v vg vg ov vg ov vd vg ov v v g o vd vg vg vd ov vg vg vd vg vd vd vg vg vg ov ov ov vg vg vg ov ov vg vd ov v v bottom view ov vg vd y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 1011 12131415 1617181920
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 57 of 74 5.5 output buffer dc impedance the 750gl 60x drivers were characterized over various process, voltage, and temperature conditions. to measure driver impedance, an external resistor is connected to the chip pad, either to ov dd or gnd. then the value of such resistor is varied until the pad voltage is ov dd /2 (see figure 5-5 ). the output impedance is actually the average of two resistances: the resistance of the pull-up and the resis- tance of pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r n is trimmed until pad = ov dd /2; r n then becomes the resistance of the pull-up devices. when data is held low, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2; r p then becomes the resistance of the pull-down devices. with a properly designed driver, r p and r n are close to each other in value; then driver impedance equals (r p + r n )/2. figure 5-5. driver impedance measurement data ov dd r p sw2 sw1 pad r n gnd
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 58 of 74 750gl_ds_body.fm 1.2 march 13, 2006 table 5-5 summarizes the driver impedance characteristics a designer uses to design a typical process. 5.5.1 input/output usage table 5-6, input/output usage, on page 59 provides details on the input/output usage of the ibm powerpc 750gl risc microprocessor signals. the usage group column refers to the general functional category of the signal. in the ibm powerpc 750gl risc microprocessor, certain input/output signals have pullups and pulldowns, which may or may not be enabled. in table 5-6, the ?input/output with internal pullup resistors? column defines which signals have these pullups or pulldowns and their active or inactive state. the ?level protect? column defines which signals have the designated function added to their input/output cell. for more about level protection, see section 5.8.1 on page 71. caution: this section is based on preliminary information and is subject to change. table 5-5. driver impedance characteristics process 60 impedance ( ? ) ov dd (v) temperature ( c) worst 49 1.8 105 typical 47 1.8 105 best 43 1.8 85 worst 47 2.5 105 typical 45 2.5 105 best 43 2.5 85 worst 51 3.3 105 typical 49 3.3 105 best 45 3.3 85
datasheet dd1.x preliminary ibm powerpc 750gl risc microprocessor 750gl_ds_body.fm.1.2 march 13, 2006 system design information page 59 of 74 table 5-6. input/output usage 750gl signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes a1v dd ? ? power supply a2v dd ? ? power supply a[0:31] high input/output address bus keeper 1, 3, 4 aack low input address termination keeper must be actively driven 3, 4, 5 abb low input/output ? keeper 5 k ? pullup required to ov dd 3, 4, 5 agnd ? ? power supply ap[0:3] high input/output ? keeper 3, 4 artry low input/output address termination keeper 5 k ? pullup required to ov dd 3, 4, 5 bg low input address arbitration keeper active driver or pulldown 3, 4, 5 br low output address arbitration keeper chip actively drives 3, 4, 5 bvsel n/a input mode select/control 5 k ? pullup/pulldown, as required 5 checkstop low output interrupt/resets keeper 5 k ? pullup required to ov dd 3, 4, 5 ci low output transfer attributes keeper 1, 3, 4 ckstp_in low input interrupt/resets keeper must be actively driven 3, 4, 5 clk_out high output ? keeper 3, 4 dbb low input/output ? keeper 5 k ? pullup required to ov dd 3, 4, 5 dbdis low input mode select/control keeper 3, 4, 6 dbg low input data arbitration keeper active driver or tie low 3, 4, 5 notes: 1. depends on the system design. the electrical characteristic s of the 750gl do not add additional constraints to the system des ign, so whatever is done with the net will depend on the system requirements. 2. hreset , sreset , and trst are signals used for riscwatch to enable proper operation of the debuggers. logical and gates should be placed between these s ignals and the ibm powerpc 750gl risc microprocessor (see figure 5-6 on page 63). 3. the 750gl provides protection from meta-stability on input s through the use of a ?keeper? circuit on specific inputs (see section 5.8 on page 71 for a more detailed descrip- tion). 4. if a system design requires a signal level to be maintained while not being actively driven, an ex ternal resistor or device m ust be used (keepers assure no meta-stability of inputs but do not guarantee a level). 5. the 750gl does not require external pullups on address and data lines. control lines must be treated individually. 6. mode select/control pins require the proper state at hreset to configure the operating mode of the processor (see table 5-10, summary of mode select, on page 72).
datasheet dd1.x ibm powerpc 750gl risc microprocessor preliminary system design information page 60 of 74 750gl_ds_body.fm.1.2 march 13, 2006 dbwo low input mode select/control keeper 3, 4, 6 dh[0:31] high input/output data bus keeper 1, 3, 4 dl[0:31] high input/output data bus keeper 1, 3, 4 dp[0:7] high input/output ? drtry low input ? keeper 3, 4, 6 gbl low input/output transfer attributes keeper 1, 3, 4 gnd ? ? power supply hreset low input interrupt/resets keeper active driver 2, 3, 4, 5 int low input interrupt/resets keeper active driver or pullup 3, 4, 5 l1_tstclk high input mode select/control not enabled 5 k ? pullup/pulldown, as required 5 l2_tstclk high input lssd not enabled 5 k ? pullup required to ov dd 5, 6 lssd_mode low input lssd not enabled 5 k ? pullup required to ov dd 5 mcp low input interrupt/resets keeper active driver or pullup 3, 4, 5 ov dd ? ? power supply pll_cfg[0:4] high input clock control keeper as required pullup/pulldown, as required 3, 4, 5 pll_rng[0:1] high input ? keeper as required pullup/pulldown, as required 3, 4, 5 qack low input mode select/control keeper must be actively driven 3, 4, 5, 6 qreq low output status/control keeper chip actively drives 3, 4, 5 rsrv low output ? keeper no connect 3, 4, 5 table 5-6. input/output usage (continued) 750gl signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristic s of the 750gl do not add additional constraints to the system des ign, so whatever is done with the net will depend on the system requirements. 2. hreset , sreset , and trst are signals used for riscwatch to enable proper operation of the debuggers. logical and gates should be placed between these s ignals and the ibm powerpc 750gl risc microprocessor (see figure 5-6 on page 63). 3. the 750gl provides protection from meta-stability on input s through the use of a ?keeper? circuit on specific inputs (see section 5.8 on page 71 for a more detailed descrip- tion). 4. if a system design requires a signal level to be maintained while not being actively driven, an ex ternal resistor or device m ust be used (keepers assure no meta-stability of inputs but do not guarantee a level). 5. the 750gl does not require external pullups on address and data lines. control lines must be treated individually. 6. mode select/control pins require the proper state at hreset to configure the operating mode of the processor (see table 5-10, summary of mode select, on page 72).
datasheet dd1.x preliminary ibm powerpc 750gl risc microprocessor 750gl_ds_body.fm.1.2 march 13, 2006 system design information page 61 of 74 smi low input ? keeper 3, 4 sreset low input interrupt/resets keeper active driver or pullup 2, 3, 4, 5 sysclk high input clock control keeper no resistor by design active driver 3, 4, 5 ta low input data termination keeper active driver 3, 4, 5 tben high input ? tbst low input/output transfer attributes keeper 1, 3, 4 tck high input jtag not enabled external pulldown 5 k ? to gnd 5 tdi high input jtag enabled high internal enabled 50 a @ 2.5 v 25 a @ 1.8 v (the pullup current for the inter- nal resistor) 5 tdo high output jtag keeper 3, 4 tea low input data termination keeper active driver or pullup 3, 4, 5 tlbisync low input mode select/control keeper must be actively driven 3, 4, 6 tms high input jtag enabled high internal enabled 50 a @ 2.5 v 25 a @ 1.8 v (the pullup current for the inter- nal resistor) 5 table 5-6. input/output usage (continued) 750gl signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristic s of the 750gl do not add additional constraints to the system des ign, so whatever is done with the net will depend on the system requirements. 2. hreset , sreset , and trst are signals used for riscwatch to enable proper operation of the debuggers. logical and gates should be placed between these s ignals and the ibm powerpc 750gl risc microprocessor (see figure 5-6 on page 63). 3. the 750gl provides protection from meta-stability on input s through the use of a ?keeper? circuit on specific inputs (see section 5.8 on page 71 for a more detailed descrip- tion). 4. if a system design requires a signal level to be maintained while not being actively driven, an ex ternal resistor or device m ust be used (keepers assure no meta-stability of inputs but do not guarantee a level). 5. the 750gl does not require external pullups on address and data lines. control lines must be treated individually. 6. mode select/control pins require the proper state at hreset to configure the operating mode of the processor (see table 5-10, summary of mode select, on page 72).
datasheet dd1.x ibm powerpc 750gl risc microprocessor preliminary system design information page 62 of 74 750gl_ds_body.fm.1.2 march 13, 2006 trst low input jtag enabled high internal enabled 50 a @ 2.5 v 25 a @ 1.8 v (the pullup current for the inter- nal resistor) 2, 5 ts low input/output address start keeper 5 k ? pullup required to ov dd 3, 4, 5 tsiz[0:2] high output transfer attributes keeper 1, 3, 4 tt[0:4] high input/output transfer attributes keeper 1, 3, 4 v dd ? ? power supply wt low output transfer attributes keeper 1, 3, 4 table 5-6. input/output usage (continued) 750gl signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristic s of the 750gl do not add additional constraints to the system des ign, so whatever is done with the net will depend on the system requirements. 2. hreset , sreset , and trst are signals used for riscwatch to enable proper operation of the debuggers. logical and gates should be placed between these s ignals and the ibm powerpc 750gl risc microprocessor (see figure 5-6 on page 63). 3. the 750gl provides protection from meta-stability on input s through the use of a ?keeper? circuit on specific inputs (see section 5.8 on page 71 for a more detailed descrip- tion). 4. if a system design requires a signal level to be maintained while not being actively driven, an ex ternal resistor or device m ust be used (keepers assure no meta-stability of inputs but do not guarantee a level). 5. the 750gl does not require external pullups on address and data lines. control lines must be treated individually. 6. mode select/control pins require the proper state at hreset to configure the operating mode of the processor (see table 5-10, summary of mode select, on page 72).
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 63 of 74 5.6 thermal manage ment information this section provides thermal management information for the cbga package for air cooled applications. proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air flow, and the thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, mounting clip, or a screw assembly (see figure 5-7, package exploded cross-sectional view with several heat-sink options, on page 64). note: this section is based on preliminary information and is subject to change. figure 5-6. ibm riscwatch jtag to hreset , trst , and sreset signal connector note: see notes for table 5-6, input/output usage, on page 59. hreset from riscwatch system hreset hreset to powerpc 750gl trst to powerpc 750gl sreset to powerpc 750gl sreset from riscwatch system sreset trst from riscwatch
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 64 of 74 750gl_ds_body.fm 1.2 march 13, 2006 the board designer can choose between several types of heat sinks to place on the 750gl. there are several commercially-available heat sinks for the 750gl provided by the vendors listed in table 5-8, 750gl heat-sink vendors, on page 65. figure 5-7. package exploded cross-sectional view with several heat-sink options table 5-7. maximum heat-sink weight limit for the cbga force maximum notes maximum dynamic compressive force allowed on the bga balls 42.9 n 1 maximum dynamic tensile force allowed on the bga balls 9.05 n 2 maximum dynamic compressive force allowed on the chip 22.4 n 3 maximum mass of module + heat sink when heat sink is not bolted to card 39 g 4 maximum torque on die (or substrate) 28in-lbs 1. the maximum instantaneous compressive force distributed across the module surface, and perpendicular to the surface of the board on which it is mounted. 2. the maximum instantaneous tensile force exerted across the modu le surface, and perpendicular to the surface of the board on which it is mounted. 3. the maximum instantaneous compressive force distributed across the die surface, and perpendicular to the surface of the board on which it is mounted. 4. the maximum combined mass of the module, attached heat sink or spreader, and adhesive material used to secure or support the heat sink or spreader to the module?s ceramic surface. cbga package heat sink heat sink clip adhesive printed option circuit board or thermal interface material
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 65 of 74 5.6.1 thermal assist unit ibm recommends that the thermal assist unit (tau) in these devices be calibrated before use. calibration methods are discussed in the ibm application note, calibrating the thermal assist unit in the ibm25ppc750l processors . although this note was written for the 750l, the calibration methods discussed in this document also apply to the 750gl. 5.6.2 minimum heat sink requirements the worst-case power dissipation (p d ) for the 750gl is shown in table 3-5, power consumption (low power), on page 17. a conservative thermal management design will provide sufficient cooling to maintain the junction temperature (t j ) of the 750gl below 105 c at maximum p d and worst-case ambient tempera- ture and airflow conditions. many factors affect the 750gl power dissipation, including v dd , t j , core frequency, process factors, and the code that is running on the processor. in general, p d increases with increases in t j , v dd , core frequency, process variables, and the number of instructions executed per second. for various reasons, a designer may determine that the power dissipation of the 750gl in their application will be less than the maximum value shown in this datasheet. assuming a lower p d will result in a thermal management system with less cooling capacity than would be required for the maximum p d shown in the datasheet. in this case, the designer may decide to determine the actual maximum 750gl p d in the particular application. contact your ibm powerpc field applications engineer for more information. in addition to the system factors that must be considered in a cooling system analysis, three things should be noted. table 5-8. 750gl heat-sink vendors company names and addresses for heat-sink vendors chip coolers, inc. 333 strawberry field rd. warwick, ri 02886 (800) 227-0254 http://www.chipcoolers.com international electronic re search corporation (ierc) 413 north moss street burbank, ca 91502 (818) 842-7277 http://www.ctscorp.com/ aavid thermalloy 80 commercial street concord, nh 03301 (603) 224-9888 http://www.aavid.com http://www.aavidthermalloy.com wakefield thermal solutions inc. 33 bridge street pellham, nh 03076 (603) 635-2800 http://www.wakefield.com
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 66 of 74 750gl_ds_body.fm 1.2 march 13, 2006 first, 750gl p d rises as t j increases, so it is most useful to measure p d while the 750gl junction tempera- ture is at maximum. while not specified or guaranteed, this rise in p d with t j is typically less than 1 w per 10 c. so regardless of other factors, the minimum cooling solution must have a maximum temperature rise of no more than 10 c/w. this minimum cooling solution is not generally achievable without a heat sink. a heat sink or heat spreader of some sort must always be used in 750gl applications. second, due to process variations, there can be a significant variation in the p d of individual 750gl devices. finally, regardless of methodology, ibm only supports system designs that successfully maintain the maximum junction temperature within the datasheet limits. ibm also supports designs that rely on the maximum p d values given in this datasheet and supply a cooling solution sufficient to dissipate that amount of power while keeping the maximum junction temperature below the maximum t j . 5.6.3 internal package conduction resistance for the exposed-die packaging technology, shown in table 3-3, package thermal characteristics, on page 16, the intrinsic conduction thermal resistance paths illustrated in figure 5-8 on page 67 are as follows: die junction-to-case thermal resistance (primary thermal path), defined as the thermal resistance from the die junctions to the back (exposed) surface of the die. die junction-to-lead thermal resistance (not normally a significant thermal path), defined as the thermal resistance from the die junctions to the circuit board interface. die junction-to-ambient thermal resistance (largely dependent on customer-supplied heat sink), defined as the sum total of all the thermally conductive components that comprise the end user's application. ambient is further defined as the air temperature in the immediate vicinity of the thermally conductive components, including the pre-heat contributions of surrounding heat sources. figure 5-8 on page 67 is a thermal model, in schematic form, of the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 67 of 74 heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat- sink attach material (or thermal interface material), and finally to the heat sink; where it is removed by forced- air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat-sink conduc- tion/convective thermal resistances are the dominant terms. 5.6.4 adhesives and thermal interface materials a thermal interface material is required at the package die-surface-to-heat-sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by a spring clip mecha- nism, figure 5-9 on page 68 shows an example of the thermal performance of three thin-sheet thermal-inter- face materials (silicon, graphite/oil, floroether oil), a bare joint, and a joint with synthetic grease, as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of synthetic grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the synthetic grease joint. customers are advised to investigate alternative thermal interface materials to ensure the most reliable, efficient, and cost-effective thermal design. an example of heat-sink attachment to the package by means of a spring clip to holes in the printed-circuit board is illustrated in figure 5-7, package exploded cross-sectional view with several heat-sink options, on page 64. therefore the synthetic grease offers the best thermal performance, considering the low inter- face pressure. of course, the selection of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so forth. figure 5-8. c4 package with heat sink mounted to a printed-circuit board external resistance components external resistance components internal resistance components (note the internal versus external package resistance.) radiation convection radiation convection custom/application specific die junction to case printed-circuit board thermal interface material die junction to lead chip junction (package and die) (defined by customer application) heat sink (die surface) resistance (package and leads) (defined by board design and layout) r jc r jb
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 68 of 74 750gl_ds_body.fm 1.2 march 13, 2006 figure 5-9. thermal performance of select thermal interface material specific thermal resistance (kin 2 /w) 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 contact pressure (psi) + + + silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease +
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 69 of 74 the board designer can choose between several types of thermal interfaces. heat-sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: section 5.7 provides a heat-sink selection example using one of the commercially available heat sinks. 5.7 heat-sink selection example for preliminary heat-sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) p d where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the system cabinet jc is the junction-to-case thermal resistance int is the thermal resistance of the thermal interface material sa is the heat-sink-to-ambient thermal resistance p d is the power dissipated by the device table 5-9. 750gl thermal interface and adhesive materials vendors company names and addresses for thermal interfaces and adhesive materials vendors dow-corning corporation dow-corning electronic materials p.o. box 0997 midland, mi 48686-0997 (989) 496-4000 http://www.dowcorning.com/content/etronics chomerics, inc. 77 dragon court woburn, ma 01888-4850 (781) 935-4850 http://www.chomerics.com thermagon, inc. 4797 detroit avenue cleveland, oh 44102-2216 (216) 939-2300 / (888) 246-9050 http://www.thermagon.com loctite corporation 1001 trout brook crossing rocky hill, ct 06067 (860) 571-5100 / (800) 562-8483 http://www.loctite.com ai technology 70 washington road princeton, nj 08550-1097 (609) 799-9388 http://www.aitechnology.com
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 70 of 74 750gl_ds_body.fm 1.2 march 13, 2006 typical die-junction temperatures (t j ) should be maintained less than the value specified in table 3-3, package thermal characteristics, on page 16. the temperature of the air cooling component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 c to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 cto10 c. the thermal resistance of the interface material ( int ) is typi- cally about 1 c/w. assuming a t a of 30 c, a t r of 5 c, a cbga package jc = 0.1, and a power dissipation (p d ) of 10 watts, the following expression for t j is obtained. die-junction temperature: t j = 30 c + 5 c + (0.1 c/w +1.0 c/w + sa ) 10 w as an example heat sink, the heat-sink-to-ambient thermal resistance ( sa ) versus air flow velocity is shown in figure 5-10 . assuming an air velocity of 1.0 m/s, we have an effective sa of 5.8 c/w, thus t j = 30 c + 5 c + (0.1 c/w +1.0 c/w + 5.8 c/w) 10 w, resulting in a junction temperature of approximately 104 c, which is within the maximum operating temperature of the component in this example. heat sinks offered by companies such as chip coolers, ierc, aavid thermalloy, and wakefield engineering offer different heat-sink-to-ambient thermal resistances, and may or may not need air flow. figure 5-10. example of a pin-fin heat-sink-to-ambient thermal resistance versus airflow velocity approach air velocity (m/s) heat-sink thermal resistance ( c/w) 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 example pin-fin heat sink (25 28 15 mm)
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 71 of 74 though the junction-to-ambient and the heat-sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technolo- gies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. these factors might include air flow, board population (local heat flux of adjacent components), heat-sink efficiency, heat-sink attach, next-level interconnect technology, system air temperature rise, and so forth. 5.8 operational and design considerations 5.8.1 level protection a level protection feature is included in the ibm powerpc 750gl risc microprocessor. the level protection feature is available in the 1.8 v, 2.5 v, and 3.3 v bus modes. this feature prevents ambiguous floating refer- ence voltages by pulling the respective signal line to the last valid or nearest valid state. for example, if the input/output voltage level is closer to ov dd , the circuit pulls the i/o level to ov dd. if the i/o level is closer to gnd, the i/o level is pulled low. this self-latching circuitry keeps the floating inputs defined and avoids meta-stability. in table 5-6, input/output usage, on page 59, these signals are defined as ?keeper? in the ?level protect? column. the level protect circuitry provides no additional leakage current to the signal i/o; however, some amount of current must be applied to the keeper node to overcome the level protection latch. this current is process dependent, but in no case is the current required over 100 a. this feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce costs. note: having a keeper on the associated signal i/o does not replace a pull-up or pull-down resistor that is needed by a separate device located on the 60x bus. the designer must supply any termination requirements for these separate devices, as defined in their specifications. 5.8.2 64-bit or 32-bit data bus mode the typical operation for the 750gl dd1.x revision level is considered to be in 64-bit data bus mode. mode setting is determined by the state of the mode signal, tlbisync , at the transition of hreset from its active to inactive state (low to high). if tlbisync is high when hreset transitions from active to inactive, 64-bit mode is selected. if tlbisync is low when hreset transitions from active to inactive, 32-bit mode is selected. special note: (reduced pin out mode) to transition from a previous processor with reduced pin out mode, the customer will need to drive tlbisync appropriately, leave the dp(0..7) and ap(0..3) pins floating, and disable parity checking with the hid0 bits. the 750gl, like the 750fx, 750cxe, and 750, does not have ape and dpe pins.
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 72 of 74 750gl_ds_body.fm 1.2 march 13, 2006 5.8.3 i / o voltage mode selection selection between 1.8 v, 2.5 v, or 3.3 v i/o modes is accomplished by using the bvsel and l1_tstclk pins: if bvsel = 1 and l1_tstclk = 0, then the 3.3 v mode is enabled. if bvsel = 1 and l1_tstclk = 1, then the 2.5 v mode is enabled. if bvsel = 0 and l1_tstclk = 1, then the 1.8 v mode is enabled. note: do not set bvsel = 0 and l1_tstclk = 0 since it yields an invalid mode . 5.8.4 q ack signal implementation for selected features 5.8.4.1 precharge duration selection and application an extended precharge feature is available for the signals abb , dbb , and artry in situations where the loading and net topology of these signals requires a longer precharge duration for the signals to attain a valid level. this feature has not been fully tested and should not be necessary in a properly designed system, even at 200 mhz. system designers should assume standard precharge as the default selection, with an option to use extended precharge. the bus signals, abb , dbb , and artry , require a precharge to the inactive state (bus high) before going to tristate. the precharge duration in standard precharge mode is approximately one half cycle, and should be used for systems with point-to-point topologies. extended precharge mode increases the precharge duration to one cycle. this increase may be required for bus speeds approaching 200 mhz when bus loading is high. qack in a logical high state at the transition of hreset from asserted to negated enables standard pre- charge mode in the 750gl. qack in a logical low state at the transition of hreset from asserted to negated enables extended pre-charge mode in the 750gl. table 5-10. summary of mode select mode 750gl 32-bit mode sample tlbisync to select high = 64-bit mode low = 32-bit mode data retry mode selects drtry mode. 0 at hreset transition no drtry mode 1 at hreset transition drtry mode factory usage modes factory usage modes are selected by sensing the data bus disable (dbdis ), data bus write-only (dbwo ), and l2_tstclk pins at the transition of hreset from low to high. these pins should be held inactive (high) at the hreset transition for normal machine operation. i/o mode selection 3.3 v 165 mv (bvsel = 1, l1_tstclk = 0) or 2.5 v 125 mv (bvsel = 1, l1_tstclk = 1) or 1.8 v 100 mv (bvsel = 0, l1_tstclk = 1) standard/extended precharge mode qack in a logical high state at the transition of hreset from asserted to negated enables standard precharge mode, the recommended default. see section 5.8.4.1 for details.
datasheet ibm powerpc 750gl risc microprocessor preliminary dd1.x 750gl_ds_body.fm 1.2 march 13, 2006 system design information page 73 of 74 5.8.4.2 processor debug system enablement when implementing precharge selection system designers who want to use a processor debug system attached to the 750gl ieee 1149.1 test access port (tap) interface (such as the ibm riscwatch debug system) should provide a method to assert qack after the transition of hreset . debug systems use a ?soft stop? feature to stop the processor, allow processor internal states to be read, and then restart of the processor. a soft stop requires the system to be in a quiescent state before the processor can be queried for internal state values. this is accomplished by the assertion of a quiescent request (that is, qreq is asserted) and subsequent acknowledgement (that is, qack is asserted). systems that do not use the power management features; doze, nap, and sleep; and do not require the extended pre-charge feature can drive the qack pin with an inverted version of hreset .
datasheet ibm powerpc 750gl risc microprocessor dd1.x preliminary system design information page 74 of 74 750gl_ds_body.fm 1.2 march 13, 2006
datasheet ibm powerpc 750gl risc microprocessor dd1.x 750gl_ds_revlog.fm 1.2 march 13, 2006 revision log page 74 of 74 revision log date description 5-27-05 initial release. 6-1-05 revised document number to version 1.0. 2-24-06 revised document number to version 1.1. changed section 1.4 part number information. changed table 3-5 power consumption (low power). added new table 3-6 power consumption (standard power). changed table 3-6 clock ac timing specifications (now table 3-7, etc.). changed figure 4-1 mechanical dim ensions, standard (leaded) package. added figure 4-2 mechanical dimensions, rohs-compatible package. 3-13-06 revised document number to version 1.2. changed section 1.4 part number information.

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