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note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: two-wire chopper-stabilized hall effect latch a1242 for existing customer transition, and for new customers or new appli- cations, contact allegro sales. date of status change: january 31, 2011 these parts are in production but have been determined to be not for new design. this classification indicates that sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. not for new design
description the a1242 hall effect latch is a two-wire latch especially suited for operation over extended temperature ranges, from ?40 to +150c. superior high-temperature performance is made possible through the allegro ? patented dynamic offset cancellation technique, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. the current-switching output technique allows for the reduction in cost in the wiring harness because only two connections to the device are required. the current-switching output structure also inherently provides more immunity against emc/esd transients. these devices have low magnetic thresholds, thereby enabling more flexibility in the magnetic circuit design. the hall effect latch will be in the high output current state in the presence of a magnetic south pole field of sufficient magnitude and will remain in this state until a sufficient north pole field is present. the a1242 includes the following on a single silicon chip: a voltage regulator, hall-voltage generator, small-signal amplifier, chopper stabilization, schmitt trigger, and a current source output. advanced bicmos wafer fabrication processing takes advantage of low-voltage requirements, component 1242-ds, rev. 6 features and benefits ? chopper stabilization ? superior temperature stability ? extremely low switchpoint drift ? insensitive to physical stress ? reverse battery protection ? solid-state reliability ? small size ? robust emc capability ? high esd ratings (hbm) two-wire chopper-stabilized hall effect latch continued on the next page? functional block diagram not to scale a1242 packages: 3 pin sot23w (suffix lh), and 3 pin sip (suffix ua) not to scale amp regulator low-pass filter gnd vcc gnd package ua only clock/logic dynamic offset cancellation sample and hold to all subcircuits
two-wire chopper-stabilized hall effect latch a1242 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com description (continued) pin-out diagrams absolute maximum ratings characteristic symbol notes rating unit* supply voltage v cc 28 v reverse supply voltage v rcc ?18 v magnetic flux density b unlimited g operating ambient temperature t a range e ?40 to 85 oc range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc *1 g (gauss) = 0.1 mt (millitesla) matching, very low input-offset errors and small component geometries. suffix ?l-? devices are rated for operation over a temperature range of ?40c to +150c; suffix ?e-? devices are rated for operation over a temperature range of ?40c to +85c. two a1242 package styles provide magnetically optimized solutions for most applications. package lh is a sot23w, a miniature low-profile surface-mount package, while package ua is a three-pin ultramini sip for through- hole mounting. each package is available lead (pb) free, with 100% matte tin plated leadframes. 1 2 3 nc 1 2 3 selection guide part number packaging* mounting low current, i cc(l) (ma) ambient, t a (c) b rp(min) (g) b op(max) (g) a1242elhlt-i1-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount 5.0 to 6.9 ?40 to 85 ?80 80 a1242elhlt-i2-t 2.0 to 5.0 a1242eua-i1-t bulk, 500 pieces/bag 3-pin sip through hole 5.0 to 6.9 A1242LLHLT-I1-T 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount 5.0 to 6.9 ?40 to 150 a1242llhlt-i2-t 2.0 to 5.0 a1242lua-i1-t bulk, 500 pieces/bag 3-pin sip through hole 5.0 to 6.9 a1242lua-i2-t 2.0 to 5.0 *contact allegro for additional packing options. terminal list name number function package lh package ua vcc 1 1 connects power supply to chip gnd 3 2,3 ground nc 2 ? no internal connection lh package ua package
two-wire chopper-stabilized hall effect latch a1242 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com device qualification program contact allegro for information. emc (electromagnetic compatibility) performance contact allegro for information. electrical characteristics over full operating voltage and temperature ranges, unless otherwise specified characteristic symbol test conditions min. typ. 1 max. units electrical characteristics supply voltage 2 3 v cc operating, t j < 165c 3.5 ? 24 v supply current i cc(l) -i1, b < b rp 5 ? 6.9 ma -i2, b < b rp 2?5ma i cc(h) -i1 and -i2, b > b op 12 ? 17 ma output slew rate 4 di/dt r s = 100 , c s = 20 pf, no bypass capacitor ? 36 ? ma/ s chopping frequency f c ? 200 ? khz power-on time t po v cc > v cc(min) ??25 s power-on state 5 pos t po < t po(max) , dv cc / dt > 25 mv / s?i cc(h) ?? supply zener clamp voltage v z(supply) i cc = 20 ma; t a = 25c 28 ? ? v supply zener current 6 i z(supply) v s = 28 v ? ? 20 ma reverse battery current i rcc v rcc = ?18 v ? ? 2.5 ma magnetic characteristics 7 operate point b op south pole adjacent to branded face of device 5 32 80 g release point b rp north pole adjacent to branded face of device ?80 ?32 ?5 g hysteresis b hys b op ? b rp 40 64 110 g 1 typical values are at t a = 25c and v cc = 12 v. performance may vary for individual units, within the specified maximum and mini- mum limits. 2 maximum voltage must be adjusted for power dissipation and junction temperature; see power derating section. 3 v cc represents the generated voltage between the v cc pin and the gnd pin. 4 the value of di is the difference between 90% of i cc(h) and 10% of i cc(l) , and the value of dt is time period between those two points. the value of di/dt depends on the value of the bypass capacitor, if one is used, with greater capacitances resulting in lower rates of change. 5 for t > t po(max) , and b rp < b < b op , pos is undefined. 6 maximum current limit is equal to the maximum i ccl(max) + 3 ma. 7 magnetic flux density, b, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for sou th-polarity magnetic fields. this so-called algebraic convention supports arithmetic comparison of north and south polarity values, where t he rela- tive strength of the field is indicated by the absolute value of b, and the sign indicates the polarity of the field (for examp le, a ?100 g field and a 100 g field have equivalent strength, but opposite polarity).
two-wire chopper-stabilized hall effect latch a1242 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja package lh, minimum-k pcb (single layer, single-sided with copper limited to solder pads) 228 oc/w package lh, low-k pcb (single layer, double-sided with 0.926 in 2 copper area) 110 oc/w package ua, minimum-k pcb (single layer, single-sided with copper limited to solder pads) 165 oc/w *additional information available on the allegro web site. power derating curve t j(max) = 165c; i cc = i cc(max) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 temperature (c) maximum allowable v cc (v) minimum-k pcb, package ua (r ja = 165 c/w) minimum-k pcb, package lh (r ja = 228 c/w) v cc(max) v cc(min) low-k pcb, package lh (r ja = 110 c/w) power dissipation versus ambient temperature 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (mw) low-k pcb, package lh (r ja = 110 c/w) min-k pcb, package lh (r ja = 228 c/w) min-k pcb, package ua (r ja = 165 c/w)
two-wire chopper-stabilized hall effect latch a1242 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic data supply current (low) versus ambient temperature (1242- i1) 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 -50 0 50 100 150 t a (c) i cc(l) (ma) vcc (v) 24 12 3.75 supply current (low) versus ambient temperature (1242- i2) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 0 50 100 150 t a (c) i cc(l) (ma) vcc (v) 24 12 3.75 supply current (high) versus ambient temperature 12 13 14 15 16 17 -50 0 50 100 150 t a (c) i cc(h) (ma) vcc (v) 24 12 3.75 supply current (low) versus supply voltage (a1242-i1) 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 0 5 10 15 20 25 v cc (v) i cc(l) (ma) t a (c) -40 25 85 150 supply current (low) versus supply voltage (a1242-i2) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 v cc (v) i cc(l) (ma) t a (c) -40 25 150 supply current (high) versus supply voltage 12 13 14 15 16 17 0 5 10 15 20 25 v cc (v) i cc(h) (ma) t a (c) -40 25 85 150
two-wire chopper-stabilized hall effect latch a1242 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operate point versus ambient temperature 5 20 35 50 65 80 -50 0 50 100 150 t a (c) b op (g) vcc (v) 24 12 3.5 release point versus ambient temperature -80 -65 -50 -35 -20 -5 -50 0 50 100 150 t a (c) b rp (g) vcc (v) 24 12 3.5 hysteresis versus ambient temperature 40 50 60 70 80 90 100 110 -50 0 50 100 150 t a (c) b hys (g) vcc (v) 24 12 3.5 operate point versus supply voltage 5 20 35 50 65 80 0 5 10 15 20 25 v cc (v) b op (g) t a (c) -40 25 150 release point versus supply voltage -80 -65 -50 -35 -20 -5 0 5 10 15 20 25 v cc (v) b rp (g) t a (c) 150 25 -40 hysteresis versus supply voltage 40 50 60 70 80 90 100 110 0 5 10 15 20 25 v cc (v) b hys (g) t a (c) -40 25 150
two-wire chopper-stabilized hall effect latch a1242 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description operation the output, i cc , of the a1242 switches to the high current state when a magnetic field perpendicular to the hall element exceeds the operate point threshold, b op . note that the device latches, that is, a south pole of sufficient strength towards the branded surface of the device switches the device output to i cc(h) . the device retains its output state if the south pole is removed. when the magnetic field is reduced to below the release point thresh- old, b rp , the device output goes to the low current state. the dif- ference between the magnetic operate and release points is called the hysteresis of the device, b hys . this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. . typical application circuit the a1242 should be protected by an external bypass capaci- tor, c byp , connected between the supply, v cc , and the ground, gnd, of the device. c byp reduces both external noise and the noise generated by the chopper-stabilization function. as shown in figure 2, a 0.01 f capacitor is typical. installation of c byp must ensure that the traces that connect it to the a1242 pins are no greater than 5 mm in length. all high-frequency interferences conducted along the supply lines are passed directly to the load through c byp , and it serves only to protect the a1242 internal circuitry. as a result, the load ecu (electronic control unit) must have sufficient protection, other than c byp , installed in parallel with the a1242. a series resistor on the supply side, r s (not shown), in combina- tion with c byp , creates a filter for emi pulses. when determining the minimum v cc requirement of the a1242 device, the voltage drops across r s and the ecu sense resistor, r sense , must be taken into consideration. the typical value for r sense is approximately 100 . extensive applications information on magnets and hall-effect devices is available in: ? hall-effect ic applications guide, an27701, ? guidelines for designing subassemblies using hall-effect devices, an27703.1 ? soldering methods for allegro products ? smd and through- hole, an26009 all are provided in allegro electronic data book, ams-702 and the allegro web site: www.allegromicro.com. figure 1. switching behavior of the a1242. on the horizontal axis, the b+ direction indicates increasing south polarity magnetic field strength, and the b? direction indicates decreasing south polarity field strength (including the case of increasing north polarity). b op b rp b hys i cc(h) i cc i cc(l) switch to high switch to low b+ i+ b? 0 0 gnd a1242 vcc v+ 0.01 uf a b b gnd ecu package ua only a b maximum separation 5 mm r sense c byp figure 2. typical application circuit
two-wire chopper-stabilized hall effect latch a1242 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 3. chopper stabilization circuit (dynamic quadrature offset cancellation) amp regulator clock/logic hall element sample and hold low-pass filter chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall element. this makes it difficult to process the signal while maintaining an accurate, reliable output over the specified oper- ating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. the patented allegro technique, namely dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation- demodulation process. the undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field induced signal to recover its original spectrum at baseband, while the dc offset becomes a high-frequency signal. the magnetic sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. this configuration is illustrated in figure 3. the chopper stabilization technique uses a 200 khz high frequency clock. for demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency (400 khz). this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensi- tizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. the repeatability of magnetic field-induced switching is affected slightly by a chopper technique. however, the allegro high frequency chopping approach minimizes the affect of jitter and makes it imperceptible in most applications. applications that are more likely to be sensitive to such degradation are those requiring precise sensing of alternating magnetic fields; for example, speed sensing of ring-magnet targets. for such applica- tions, allegro recommends its digital device families with lower sen- sitivity to jitter. for more information on those devices, contact your allegro sales representative.
two-wire chopper-stabilized hall effect latch a1242 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power derating power derating the device must be operated below the maximum junction temperature of the device, t j(max) . under certain combinations of peak conditions, reliable operation may require derating sup- plied power or improving the heat dissipation properties of the application. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ? ja , is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r ? jc , is relatively small component of r ? ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ? ???????????????????????? t = p d r ? ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 6 ma, and r ? ja = 165 c/w, then: p d = v cc i cc = 12 v 6 ma = 72 mw ?? t = p d r ? ja = 72 mw 165 c/w = 12c t j = t a + ? t = 25c + 12c = 37c a worst-case estimate, p d(max) , represents the maximum allow- able power level (v cc(max) , i cc(max) ), without exceeding t j(max) , at a selected r ? ja and t a . example : reliability for v cc at t a = 150c, package lh, using minimum-k pcb. observe the worst-case ratings for the device, specifically: r ? ja = 228c/w, t j(max) = 165c, v cc(max) = 24 v, and i cc(max) = 17 ma. calculate the maximum allowable power level, p d(max) . first, invert equation 3: ? t max = t j(max) ? t a = 165 c ? 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: ???? p d(max) = ? t max r ? ja = 15c 228 c/w = 66 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d(max) i cc(max) = 66 mw 17 ma = 3.9 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc(max) . if v cc(est) v cc(max) , then reli- able operation between v cc(est) and v cc(max) requires enhanced r ? ja . if v cc(est) v cc(max) , then operation between v cc(est) and v cc(max) is reliable under these conditions.
two-wire chopper-stabilized hall effect latch a1242 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lh, 3-pin (sot-23w) 0.55 ref gauge plane seating plane 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 a active area depth, 0.28 mm ref b c c b reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion a pcb layout reference view standard branding reference view 1 branded face n = last two digits of device part number t = temperature code nnt 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 for reference only; not for tooling use (reference dwg. 802840) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown d hall element, not to scale d d d 1.49 0.96 3
two-wire chopper-stabilized hall effect latch a1242 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua, 3-pin sip 23 1 0.79 ref 1.27 nom 2.16 max 0.51 ref 45 c 45 b e e e 2.04 1.44 gate burr area a b c dambar removal protrusion (6x) a d e d branding scale and appearance at supplier discretion hall element, not to scale active area depth, 0.50 mm ref for reference only; not for tooling use (reference dwg-9049) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown standard branding reference view = supplier emblem n = last two digits of device part number t = temperature code nnt 1 mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 15.75 0.51 1.52 0.05 copyright ?2005-2010, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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