datel, inc., mans eld, ma 02048 (usa) ? tel: (508)339-3000, (800)233-2765 fax: (508)339-6356 ? e?ail: sales@datel.com ? internet: www.datel.com adc-208a 8-bit, 20msps cmos flash a/d (adc-208 compatible) figure 1. adc-208a block diagram ?? features ? 8-bit ash a/d converter ? 20mhz sampling rate ? 10mhz full-power bandwidth ? sample-hold not required ? low power cmos ? +5vdc operation ? 1.2 micron cmos ? 8-bit latched outputs ? surface-mount version ? no missing codes general description the adc-208a utilizes an advanced vlsi 1.2 micron cmos in providing 20mhz sampling rates at 8-bits. the exibility of the design architecture and process delivers latch-up free operation without external components and operation over the full military range. the adc-208a is mechanically and electrically equivalent to the adc-208 series, with the exception of the overflow (pin 13) and enable (pins 11 and 12) functions. these functions are not offered on the adc-208a. 1 vdd 24 bit 8 (lsb) 2 clock input 23 bit 7 3 ?eference 22 bit 6 4 ana/dig gnd (vss) 21 bit 5 5 analog input 20 ref 1/4 fs 6 ref midpoint 19 vdd 7 analog input 18 ref 3/4 fs 8 ana/dig gnd (vss) 17 bit 4 9 +reference 16 bit 3 10 vdd 15 bit 2 11 n.c. 14 bit 1 (msb) 12 n.c. 13 n.c. pin function pin function analog input r2 1 ? 1 ? 1 ? r r r r2 r2 r2 r2 +reference ? reference ? reference ? reference midpoint reference clock clock generator bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (lsb) 256 to 7 encoder 5,7 pins 1, 10, 19 +5v pins 4-8 digital gnd analog gnd +v dd 9 18 6 20 3 2 14 02 02 01 01 15 16 17 21 22 23 24 d g q d g q d g q d g q d g q d g q d g q d g q d g q d g q d g q d g q input/output connections
2 datel, inc., mans? eld, ma 02048 (usa) ? tel: (508)339-3000, (800)233-2765 fax: (508)339-6356 ? eCmail: sales@datel.com ? internet: www.datel.com adc-208a performance min. typ. max. units int. linearity over temp. (ref. unadjusted) end-point ? 2.3 2.6 lsb best-? t line ? 1.8 2.0 lsb zero-scale offset ? 1 2 lsb (code "0" to "1" transition) gain error ? 1.5 3 lsb differential gain ? ? 2 ? % differential phase ? ? 1.1 ? degrees aperture delay ? 8 ? ns aperture jitter ? 50 ? ps harmonic distortion (8mhz second order harm.) ?40 ?46 ? db ref. bandwidth (see tech note 5) ? 10 ? mhz power supply rejection ? 0.02 0.05 %fsr/%vs no missing codes over the operating temperature range power requirements power supply range (+v dd ) +3.0 +5.0 +5.5 volts power supply current +25c ? +45 +65 ma +125c ? +40 +60 ma ?55c ? +50 +70 ma power dissipation +25c ? 225 325 mw +125c ? 200 300 mw ?55c ? 250 350 mw physical environmental operating temp. range, case: mc/lm versions 0 ? +70 c mm/lm/ql versions ?55 ? +125 c storage temp. range ?65 ? +150 c package type dip 24-pin ceramic dip lcc 24-pin ceramic lcc parameters limits units power supply voltage ( v dd pin 1, 10, 19 ) ?0.5 to +7 volts digital inputs ?0.5 to +5.5 volts analog input ?0.5 to (+v dd +0.5) volts reference inputs ?0.5 to (+v dd +0.5) volts digital outputs ?0.5 to +5.5 volts (short circuit protected to ground) lead temperature (10 sec. max.) +300 max. c storage temperature ?65 to +150 c functional specifications (typical at +5v power, +25c, 20mhz clock, +reference = +5v, ?reference = ground, unless noted) absolute maximum ratings analog input min. typ. max. units single-ended, non-isolated input range dc - 20mhz 0 ? +5.0 volts analog input capacitance (static - pin 5 to 7) ? 20 ? pf (dynamic - pin 5 to 7) ? 64 ? pf reference ladder resistance ? 500 ? ohms reference input (note 5) ?0.5 ? v dd +0.5 volts digital inputs logic levels logic "1" 3.2 ? ? volts logic "0" ? ? 0.8 volts logic loading logic loading "1" ? +1 +5 a logic loading "0" ? +1 +5 a clock low pulse width 15 25 ? nsec digital outputs logic levels logic "1" 2.4 4.5 5.0 volts logic "0" ? ? 0.4 volts logic loading logic loading "1" 4 ? ? ma logic loading "0" 4 ? ? ma output data valid delay from rising clock edge 99% probability 5 10 15 nsec 100% probability +25c 5 10 25 nsec ?55c to +125c ? ? 40 nsec data output resolution 8 ? ? bits data coding straight binary performance sampling rate ? 15 20 ? msps full power bandwidth 10 ? ? mhz diff. linearity @ +25c (see tech note 7) code transitions ? 0.5 1.0 lsb center of codes ? 0.25 ? lsb diff. linearity over temp. code transitions ? 0.5 1.0 lsb center of codes ? 0.25 ? lsb int. linearity @ +25c (see tech note 4)(ref. adjusted) end-point ? ? 1/2 lsb best-? t line ? ? 1/2 lsb int. linearity over temp. (ref. adjusted) best-? t line ? 1/2 1 lsb int. linearity @ +25c (ref. unadjusted) end-point ? 2 2.6 lsb best-? t line ? 1.6 1.9 lsb footnotes: ? maximum input impedance is a function of clock frequency. ? at full-power input. ? for 10-step, 40 ire ntsc ramp test. technical notes 1. the reference ladder is ? oating with respect to vdd and may be referenced anywhere within the speci? ed limits. ac modulation of the reference voltage may also be utilized; contact datel for further information. 2. clock pulse width C to improve performance when input signals may exceed nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of the clock pulse is 15nsec wide. reducing the sampling time period minimizes the amount the input voltage slews and prevents the comparators from saturating. 3. a full-scale input produces all "1" on the data outputs. 4. datel uses the conservative de? nitions when specifying intergal linearity (end-point) and differential linearity (code transition). the speci? cations using the less conservative de? nition have also been provided as a comparative speci? cation for products speci? ed this way.
3 datel, inc., mans? eld, ma 02048 (usa) ? tel: (508)339-3000, (800)233-2765 fax: (508)339-6356 ? eCmail: sales@datel.com ? internet: www.datel.com adc-208a 5. the process that is used to fabricate the adc-208a eliminates the latchup phenomena that has plagued cmos devices in the past. these converters do not require external protection diodes. 6. for clock rates less than 100khz, there may be some degradation in offset and differential nonlinearity. performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). 7. connect the converter appropriately; a typical connection circuit is shown in figure 2. then apply an appropriate clock input.the reference input should be held to 0.1% accuracy or better. do not use the +5v power supply as a reference without precision regulation and high-frequency decoupling capacitors. 8. zero adjustment - adjusting the voltage at Creference (pin 3) adjusts the offset or zero of the device. pin 3 can be tied to ground for operation without adjustments 9. full scale adjustment - adjusting the voltage at +reference (pin 9) adjusts the gain of the device. pin 9 can be tied directly to a +5v reference for operation without adjustment. table 1. adc-208a output code note: values shown here are for a +5.12vdc reference. scale other refereces proportionally. (+ref=+5.12v, ?ref=gnd, ?, ?, and ? references fs=no connection) 10. integral nonlinearity adjustments - provision is made for optional adjustment of integral nonlinearity through access of the reference's ?, ?, and ? full scale points. for example, the ref. midpoint (pin 6) can be tied to a precision voltage halfway between +reference and Creference. pins 6, 18 and 20 should be bypassed to ground through 0.1f capacitors for operation without inl adjustments figure 2. adc-208a typical connection diagram analog data data input code 1234 5678 decimal hex 0.00v zero 0000 0000 0000 0 00 +0.02v +1 lsb 0000 0001 1 01 +1.28v +? fs 0100 0000 64 40 +2.54v +? fs-ilsb 0111 1111 127 7f +2.56v +? fs 1000 0000 128 80 +2.58v +? fs+ilsb 1000 0001 129 81 +3.84v +? fs 1100 0000 192 c0 +5.10v +fs 1111 1111 255 ff ref. d2 20mhz clock vin 5,7 r? clock 2 d gnd 4 ref-3 ref mid 6 ref+9 a gnd 8 vdd 1,10,19 hp2811 +5v +5v +15 +15v +15v ?15 11 20 18 12 + + + + + + + 5 5 6 4 2 2 9 6 7 5 12 13 14 10 8 1 3 10 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0 .1f 10 ? 10k ? 2k ? 1k ? 1k ? 1k ? 1.5k ? 1.5k ? 2k ? 0.1f 0.01f 4.7f 4.7f 4.7f 4.7f 4.7f 4.7f 4.7f ha-5033 lm324 1+n 1-n lm324 1+n 1-n lm324 1+n 1-n lm324 1+n 1-n 24 (lsb) 23 22 21 17 16 15 14 (msb) b8 b7 b6 b5 b4 b3 b2 b1 r?
4 adc-208a datel, inc. 11 cabot boulevard, mans? eld, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 internet: www.datel.com email: sales@datel.com datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 01-34-60-01-01 datel gmbh mnchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subj ect to change without notice. the datel logo is a registered datel, inc. trademark. ds-0500c 01/03 ?? adc-208a lcc adc-208a dip ? ? 0.250 0.005 (6.35) 0.050 (1.27) 0.090 max. (2.28) 0.400 sq. +0.010, ?0.005 (10.16) 0.020 0.005 (0.50) pin 1 pin 9 pin 21 1.250 (31.7) pin 1 identifier 0.500 (12.7) datel adc-208a 0.020 (0.5) 0.100 (2.5) 0 .050 (1.3) 0.610 (15.5) 0.190 (4.9) 0.190 (4.9) 0.38 (9.7) 01 02 01 02 01 02 auto zero sample n n data n+1 data auto zero sample n+1 auto zero sample n+2 40nsec max. 40nsec max. model temp. range package adc-208amc 0c to +70c 24-pin dip adc-208amm C55c to +125c 24-pin dip adc-208alc 0c to +70c 24-pin lcc adc-208alm C55c to +125c 24-pin lcc figure 3 timing diagram ? ? -ql. ordering information mechnical dimensions
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