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1 pcm1702 bicmos advanced sign magnitude 20-bit digital-to-analog converter description features l ultra low C96db max thd+n (no external adjustment required) l near-ideal low level operation l glitch-free output l 120db snr typ (a-weight method) l industry std serial input format l fast (200ns) current output ( 1.2ma) l capable of 16x oversampling l complete with reference l low power (150mw typ) 49% fpo the pcm1702 is a precision 20-bit digital-to-analog converter with ultra-low distortion (C96db typ with a full scale output). incorporated into the pcm1702 is an advanced sign magnitude architecture that elimi- nates unwanted glitches and other nonlinearities around bipolar zero. the pcm1702 also features a very low noise (120db typ snr: a-weighted method) and fast settling current output (200ns typ, 1.2ma step) which is capable of 16 x oversampling rates. applications include very low distortion frequency synthesis and high-end consumer and professional digital audio applications. international airport industrial park ? mailing address: po box 11400 ? tucson, az 85734 ? street address: 6730 s. tucson blvd. ? tucson, az 85706 tel: (520) 746-1111 ? twx: 910-952-1111 ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 reference and servo i out dcom le data clock bpo dc bipolar offset balanced current segment dac a input shift register and control logic balanced current segment dac b serv dc rf dc acom +v cc ? cc pcm1702p pcm1702u ? 1993 burr-brown corporation pds-1175b printed in u.s.a. june, 1995 sbas026
2 pcm1702 specifications all specifications at 25 c, v cc and +v dd = 5v unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pcm1702p/u, -j, -k parameter conditions min typ max units resolution 20 bits dynamic range, thd + n at C60db referred to full scale, with a-weight 110 db digital input logic family ttl/cmos compatible logic level: v ih +2.4 +v dd v v il 0 0.8 v i ih v ih = +v dd 10 m a i il v il = 0v 10 m a data format serial, msb first, btc (1) input clock frequency 12.5 20.0 mhz total harmonic distortion + n (2) p/u v o = 0db f s = 352.8khz (3) , f = 1002hz (4) C92 C88 db v o = C20db f s = 352.8khz (3) , f = 1002hz (4) C82 C74 db v o = C60db f s = 352.8khz (3) , f = 1002hz (4) C46 C40 db p/u, -j v o = 0db f s = 352.8khz (3) , f = 1002hz (4) C96 C92 db v o = C20db f s = 352.8khz (3) , f = 1002hz (4) C83 C76 db v o = C60db f s = 352.8khz (3) , f = 1002hz (4) C48 C42 db p/u, -k v o = 0db f s = 352.8khz (3) , f = 1002hz (4) C100 C96 db v o = C20db f s = 352.8khz (3) , f = 1002hz (4) C84 C80 db v o = C60db f s = 352.8khz (3) , f = 1002hz (4) C50 C44 db accuracy level linearity at C90db signal level 0.5 db gain error 0.5 3% bipolar zero error (5) 0.25 % gain drift 0 c to 70 c 25 ppm of fsr/ c bipolar zero drift 0 c to 70 c 5 ppm of fsr/ c warm-up time 1 minute idle channel snr (6) bipolar zero, a-weighted filter 110 120 db analog output output range 1.2 ma output impedance 1.0 k w settling time ( 0.003% of fsr, 1.2ma step) 200 ns glitch energy no glitch around zero power supply requirements supply voltage range: +v cc = +v dd +4.75 +5.00 +5.25 v Cv cc = Cv dd C4.75 C5.00 C5.25 v combined supply current: +i cc +v cc = +v dd = +5v +5.00 +9.0 ma combined supply current: Ci cc Cv cc = Cv dd = C5v C25.00 C41.0 ma power dissipation v cc = v dd = 5v 150 250 mw temperature range operating C25 +85 c storage C55 +125 c notes: (1) binary twos complement coding. (2) ratio of (distortion rms + noise rms ) / signal rms . (3) d/a converter sample frequency (8 x 44.1khz; 8 x oversampling). (4) d/a converter output frequency (signal level). (5) offset error at bipolar zero. (6) measured using an opa627 and 5k w feedback and an a-weighted filter.
3 pcm1702 power supply voltage .................................................................. 6.5vdc input logic voltage ........................................... dgnd0.3v~+v dd +0.3v operating temperature ..................................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c power dissipation .......................................................................... 300mw lead temperature (soldering, 5s) .................................................... 260 c absolute maximum ratings (sop package) absolute maximum ratings (dip package) power supply voltage .................................................................. 6.5vdc input logic voltage ........................................... dgnd0.3v~+v dd +0.3v operating temperature ..................................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c power dissipation .......................................................................... 500mw lead temperature (soldering, 10s) .................................................. 260 c pin mnemonic pin mnemonic 1 data 9 +v cc 2 clock 10 bpo dc 3+v dd 11 i out 4 dcom 12 acom 5Cv dd 13 acom 6 le 14 serv dc 7 nc 15 ref dc 8nc16Cv cc pin assignments (dip package) package information (1) package drawing model package number pcm1702p 16-pin plastic dip 180 pcm1702u 20-pin plastic sop 248 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix d of burr-brown ic data book. pin mnemonic pin mnemonic 1 data 11 +v cc 2 clock 12 bpo dc 3nc13nc 4+v dd 14 i out 5 dcom 15 acom 6Cv dd 16 acom 7 le 17 serv dc 8nc18nc 9 nc 19 rfe dc 10 nc 20 Cv cc pin assignments (sop package) grade marking (sop package) model package pcm1702u marked pcm1702. pcm1702u-j marked with white dot by pin 10. pcm1702u-k marked with red dot by pin 10. connection diagram r nf v out clock data le 16 15 14 11 10 9 13 12 47? 47? + 2 1 6 3 4 5 + + +5v v cc + + ?v v cc + + 47? 100? 22? ?v v dd +5v v dd 47? 47? = sop = dip 2 1 7 4 5 6 20 19 17 14 12 11 16 15
4 pcm1702 typical performance curves all specifications at 25 c, v a and v d = 5.0v unless otherwise noted. thd+n vs frequency ?0 ?0 ?00 ?20 ?0 20 100 1k 10k output frequency (hz) thd+n (db) ?0db ?0db ?0db 0db 16-bit level linearity (dithered fade-to-noise) 8 6 4 2 0 ? ? ? ? deviation from ideal level (db) ?20 output signal level (db) ?10 ?00 ?0 ?0 ?0 ?0 16-bit monotonicity 8.83ms/div 1.5 1 0.5 0 ?.5 ? ?.5 output voltage (mv) ?0db signal spectrum (100hz bandwidth) ?0 ?00 ?20 ?40 ?60 power spectrum (db) 0 4k 8k 12k 16k 20k frequency (hz) ?0db signal (10hz to 20khz bandwidth) 200 100 0 ?00 ?00 output level (?) 0 400 800 1200 1600 2000 time (?) ?10db signal (10hz to 20khz bandwidth) 40 20 0 ?0 ?0 output level (?) 0 400 800 1200 1600 2000 time (?)
5 pcm1702 discussion of specifications dynamic specifications total harmonic distortion + noise the key specifications for the pcm1702 is total harmonic distortion plus noise (thd+n). digital data words are read into the pcm1702 at eight times the standard compact disk audio sampling frequency of 44.1khz (352.8khz) so that a sine wave output of 1002hz is realized. for production testing, the output of the dac goes to an i to v converter, then through a 40khz low pass filter, and then to a programmable gain amplifier to provide gain at lower signal output test levels before being fed into an analog-type distortion analyzer. figure 1 shows a block diagram of the production thd+n test setup. for the audio bandwidth, thd+n of the pcm1702 is essentially flat for all frequencies. the typical performance curve, thd+n vs frequency, shows four different output signal levels: 0db, C20db, C40db, and C60db. the test signals are derived from a special compact test disk (the cbs cd-1). it is interesting to note that the C20db signal falls only about 10db below the full scale signal instead of the expected 20db. this is primarily due to the superior low level signal performance of the advanced sign magnitude architecture of the pcm1702. in terms of signal measurement, thd+n is the ratio of distortion rms + noise rms / signal rms expressed in db. for the pcm1702, thd+n is 100% tested at all three specified output levels using the test setup shown in figure 1. it is significant to note that this test setup does not include any output deglitching circuitry. all specifications are achieved without the use of external deglitchers. dynamic range dynamic range in audio converters is specified as the mea- sure of thd+n at an effective output signal level of C60db referred to 0db. resolution is commonly used as a theoreti- cal measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. the advanced sign magnitude architecture of the pcm1702, with its ideal performance around bipolar zero, provides a more usable dynamic range, even using the strict audio definition, than any previously available d/a con- verter. theory of operation advanced sign magnitude digital audio systems have traditionally used laser-trimmed, current-source dacs in order to achieve sufficient accuracy. however, even the best of these suffer from potential low- level nonlinearity due to errors at the major carry bipolar zero transition. more recently, dacs employing a different architecture which utilizes noise shaping techniques and very high over-sampling frequencies, have been introduced (bitstream, mash, or 1-bit dac). these dacs over- come the low level linearity problem, but only at the expense of signal-to-noise performance, and often to the detriment of channel separation and intermodulation distortion if the succeeding circuitry is not carefully designed. the pcm1702 is a new solution to the problem. it combines all the advantages of a conventional dac (excellent full scale performance, high signal-to-noise ratio and ease of use) with superior low-level performance. two dacs are combined in a complementary arrangement to produce an extremely linear output. the two dacs share a common reference, and a common r-2r ladder for bit current sources by dual balanced current segments to ensure perfect tracking under all conditions. by interleaving the individual bits of each dac and employing precise laser trimming of resis- tors, the highly accurate match required between dacs is achieved. this new, complementary linear or advanced sign magni- tude approach, which steps away from zero with small steps in both directions, avoids any glitching or large linearity errors and provides an absolute current output. the low level performance of the pcm1702 is such that real 20-bit reso- lution can be realized, especially around the critical bipolar zero point. table 1 shows the conversion made by the internal logic of the pcm1702 from binary twos complement (btc). also, the resulting internal codes to the upper and lower dacs (see front page block diagram) are listed. notice that only the lsb portions of either internal dac are changing around bipolar zero. this accounts for the superlative per- formance of the pcm1702 in this area of operation. input code lower dac code upper dac code analog output (20-bit binary two's complement) (19-bit straight binary) (19-bit straight binary) +full scale 011...111 111...111+1lsb (1) 111...111 +full scale C1lsb 011...110 111...111+1lsb (1) 111...110 bipolar zero +2lsb 000...010 111...111+1lsb (1) 000...010 bipolar zero +1lsb 000...001 111...111+1lsb (1) 000...001 bipolar zero 000...000 111...111+1lsb (1) 000...000 bipolar zero C1lsb 111...111 111...111 000...000 bipolar zero C2lsb 111...110 111...110 000...000 Cfull scale +lsb 100...001 000...001 000...000 Cfull scale 100...000 000...000 000...000 note: (1) the extra weight of 1lsb is added at this point to make the transfer function symmetrical around bipolar zero. table i. binary two's complement to sign magnitude conversion chart.
6 pcm1702 level linearity deviation from ideal versus actual signal level is sometimes called level linearity in digital audio converter testing. see the C90db signal spectrum plot in the typical perfor- mance curves section for the power spectrum of a pcm1702 at a C90db output level. (the C90db signal plot shows the actual C90db output of the dac). the deviation from ideal for pcm1702 at this signal level is typically less than 0.3db. for the C110db signal plot in the typical perfor- mance curves section, true 20-bit digital code is used to generate a C110db output signal. this type of performance is possible only with the low- noise, near-theoretical performance around bipolar zero of the pcm1702 advanced sign magnitude. a commonly tested digital audio parameter is the amount of deviation from ideal of a 1khz signal when its amplitude is decreased form C60db to C120db. a digitally dithered input signal is applied to reach effective output levels of C120db using only the available 16-bit code from a special compact disk test input. see the 16-bit level linearity plot in the typical performance curves section for the results of a pcm1702 tested using this 16-bit dithered fade-to-noise signal. note the very small deviation from ideal as the signal goes from C60db to C100db. dc specification idle channel snr another appropriate specification for a digital audio con- verter is idle channel signal-to-noise ratio (idle channel snr). this is the ratio of noise on the dac output at bipolar zero in relation to the full scale range of the dac. to make this measurement, the digital input is continuously fed the code for bipolar zero, while the output of the dac is band- limited from 20hz to 20khz and an a-weighted filter is applied. the idle channel snr for the pcm1702 is typically greater than 120db, making it ideal for low-noise applica- tions. monotonicity because of the unique advanced sign magnitude architecture of the pcm1702, increasing values of digital input will always result in increasing values of dac output as the signal moves away from bipolar zero in one-lsb steps (in either direction). the 16-bit monotonicity plot in the typical performance curves section was generated using 16-bit digital code from a test compact disk. the test starts with 10 periods of bipolar zero. next are 10 periods of alternating 1lsbs above and below zero, and then 10 periods of alternating 2lsbs above and below zero, and so on until 10lsbs above and below zero are reached. the signal pattern then begins again at bipolar zero. with pcm1702, the low-noise steps are clearly defined and increase in near-perfect proportion. this performance is achieved without any external adjustments. by contrast, sigma-delta (bit-stream, mash, or 1-bit dac) archi- tectures are too noisy to even see the first 3 or 4 bits change (at 16 bits), other than by a change in the noise level. absolute linearity even though absolute integral and differential linearity specs are not given for the pcm1702, the extremely low thd+n performance is typically indicative of 17-bit integral linearity in the dac. the relationship between thd+n and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. offset, gain, and temperature drift although the pcm1702 is primarily meant for use in dy- namic applications, specifications are also given for more traditional dc parameters such as gain error, bipolar zero offset error, and temperature gain and offset drift. digital input timing considerations the pcm1702 accepts ttl compatible logic input levels. the data format of the pcm1702 is binary twos comple- ment (btc) with the most significant bit (msb) being first figure 1. production thd+n test setup. timing logic binary counter digital code (eprom) parallel-to-serial conversion dut (pcm1702) i to v converter opa627 distortion analyzer programmable gain amp 0db to 60db low-pass filter 40khz 3rd order gic type data (shiba soku model 725 or equivalent) use 400hz high-pass filter and 30khz low-pass filter meter settings sampling rate = 44.1khz x 8(352.8khz) output frequency = 1002hz le (latch enable) clock
7 pcm1702 in the serial input bit stream. table ii describes the exact relationship of input data to voltage output coding. any number of bits can precede the 20 bits to be loaded, since only the last 20 will be transferred to the parallel dac register after latch enable (pin6 , pin7 , le) has gone low. all dac serial input data (pin1, data) bit transfers are triggered on positive clock (pin2, clock), edges. the serial-to-parallel data transfer to the dac occurs on the falling edge of latch enable. the change in the output of the dac occurs at a rising edge of the 4th clock of the clock after the falling edge of latch enable. refer to figure 2 for graphical relationships of these signals. maximum clock rate a typical clock rate of 16.9mhz for the pcm1702 is derived by multiplying the standard audio sample rate of 44.1khz by sixteen times (16 x over-sampling) the standard audio word bit length of 24 bits (44.1khz x 16 x 24 = 16.9mhz). note that this clock rate accommodates a 24-bit word length, even though only 20 bits are actually being used. the setup and hold timing relationships are shown in figure 3. stopped clock operation the pcm1702 is normally operated with a continuous clock input signal. if the clock is to be stopped between input data words, the last 20 bits shifted in are not actually shifted from the serial register to the latched parallel dac register until latch enable goes low. latch enable must remain low until after the first clock cycle of the next data word to insure proper dac operation. in any case, the setup and hold times for data and le must be observed as shown in figure 3. installation power supplies refer to connection diagram for proper connection of the pcm1702. the pcm1702 only requires a 5v sup- ply. both positive supplies should be tied together at a single point. similarly, both negative supplies should be connected together. no real advantage is gained by using separate analog and digital supplies. it is more important that both these supplies be as clean as possible to reduce coupling of supply noise to the output. power supply decoupling capacitors should be used at each supply pin to maximize power supply rejection, as shown in connection dia- gram regardless of how good the supplies are. both commons should be connected to an analog ground plane as close to the pcm1702 as possible. filter capacitor requirements as shown in connection diagram, various size decoupling capacitors can be used, with no special tolerances being required. the size of the offset decoupling capacitor is not critical either, with larger values (up to 100 m f) giving slightly better snr readings. all capacitors should be as close to the appropriate pins of the pcm1702 as possible to reduce noise pickup from surrounding circuitry. > 15ns > 15ns > 40ns lsb data input msb > 20ns > 20ns > 15ns > one clock cycle > one clock cycle latch enable clock input > 15ns digital input analog output current output 1,048,576lsbs full scale range 2.40000000ma 1lsb na 2.28882054na 7ffff hex +full scale C1.19999771ma 00000 hex bipolar zero C1lsb 0.00000000ma 80000 hex Cfull scale +1.20000000ma table ii. digital input/output relationships. figure 3. setup and hold timing diagram. figure 2. timing diagram. 1234 13141516171819201 msb lsb data clock latch enable n n-1 i out 12 data "n" notes : (1) if clock is stopped between input of 20-bit data words, "latch" enable (le) must remain low until after the first clock cycle of the next 20-bit data word stream. (2) data format is binary two's complement (btc). individual data bits are clocked in on the corresponding positive clock edge. (3) latch enable (le) must remain low at least one clock cycle after going negative. (4) latch enable (le) must be high for at least one clock cycle before going negative. (5) i out changes on positive going edge of the 4th clock after negative going edge of latch enable (le).
8 pcm1702 figure 4. typical application for stereo audio 8x oversampling system. 1m w 16.9344mhz 2 1 11 10 5 4 3 8x interpolation digital filter 17 22 3 +5v 23 100pf 14 21 16 4.7? 1 28 2 26 25 24 4.7? 6 10 4 digital interface format receiver 17 +5v 8 4700pf 314 5 6 12 15 17 0.1? 28 4 4.7? w 17.1k +5v (192f ) s 10pf 10pf interleaved digital input 150 w f a bco l/r da yamaha ym3623 pcm1702p burr-brown df1700p 8 dor bco wck dol 4.7? +5v + + + 6 bck data gnd ?v le c 42 3.3? + c 44 3.3? + 13 12 16 14 15 c 54 100? + c 48 3.3? + 9 +5v bpo dc i out c 50 100? + c 52 100? + c 46 3.3? + ?v v cc +5v v cc ?v v cc c 56 220p rf 2 2.5k w ?v 2 1 11 10 5 4 3 pcm1702p +5v 6 bck data gnd ?v le c 41 3.3? + c 49 3.3? + 13 12 16 14 15 c 54 100? + c 47 3.3? + 9 +5v bpo dc i out c 49 100? + c 51 100? + c 45 3.3? + +5v v cc ?v v cc c 55 220p rf 2 2.5k w ?v +5v v cc r 21 2k w v o c 62 1000pf low-pass 3-pole butterworth f ?db = 40khz r 13 6.04k w r 17 4.02k w r 18 4.02k w c 60 1000pf c 59 1000pf r 19 5.36k w r 20 2k w v o c 61 1000pf low-pass 3-pole butterworth f ?db = 40khz r 12 6.04k w r 14 4.02k w r 15 4.02k w c 58 1000pf c 57 1000pf r 16 5.36k w see application bulletin ab-026 for information on gic filters. ic3 ic3 ic4 ic4 ic1 ic2 ic1-4: opa2604 ic2 ic1
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) pcm1702p active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702p-j active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702p-jg4 active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702p-k active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702p-kg4 active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702pg4 active pdip n 16 25 green (rohs & no sb/br) cu nipdau n / a for pkg type pcm1702u active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u-2/2k obsolete so ns 20 tbd call ti call ti pcm1702u-2/2ke6 obsolete so ns 20 tbd call ti call ti pcm1702u-j active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u-je6 active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u-k active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u-ke6 active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u/2k active so ns 20 2000 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702u/2ke6 active so ns 20 2000 pb-free (rohs) cu snbi level-2-260c-1 year pcm1702ue6 active so ns 20 38 pb-free (rohs) cu snbi level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. package option addendum www.ti.com 14-oct-2008 addendum-page 1
important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 14-oct-2008 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant pcm1702u/2k so ns 20 2000 330.0 25.4 8.8 13.1 2.8 12.0 24.0 q1 package materials information www.ti.com 8-aug-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) pcm1702u/2k so ns 20 2000 346.0 346.0 41.0 package materials information www.ti.com 8-aug-2008 pack materials-page 2
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