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july 2012 altera corporation cf52012-3.0 datasheet ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers a re advised to obtain the latest version of device specifications before relying on any published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com feedback subscribe iso 9001:2008 registered quad-serial configuration (epcq) devices datasheet this datasheet describes quad-serial configuration (epcq) devices. supported devices ta b l e 1 lists the supported altera ? epcq devices. features epcq devices offer the following features: serial or quad-serial fpga configuration in devices that support active serial (as) x1 or as x4 configuration schemes low cost, low pin count, and non-volatile memory 2.7-v to 3.6-v operation available in 8- and 16-pin small-outline integrated circuit (soic) package reprogrammable memory with more than 100,000 erase or program cycles write protection support for memory sectors using status register bits fast read, extended dual input fast read, and extended quad input fast read of the entire memory using a single operation code write bytes, extended dual input fast write bytes, and extended quad input fast write bytes of the entire memory using a single operation code reprogrammable with an external microprocessor using the srunner software driver in-system programming (isp) support with the srunner software driver isp support with usb-blaster ? , ethernetblaster ii, or ethernetblaster download cables table 1. altera epcq devices device memory size (bits) on-chip decompression support isp support cascading support reprogrammable recommended operating voltage (v) epcq16 16,777,216 no yes no yes 3.3 epcq32 33,554,432 no yes no yes 3.3 epcq64 67,108,864 no yes no yes 3.3 epcq128 134,217,728 no yes no yes 3.3 epcq256 268,435,456 no yes no yes 3.3
page 2 memory array organization quad-serial configuration (epcq) devices datasheet july 2012 altera corporation by default, the memory array is erased and the bits are set to 1 memory array organization ta b l e 2 lists the memory array organization in supported epcq devices. address range for epcq16 ta b l e 3 lists the address range for each sector in epcq16 devices. table 2. memory array organization in epcq devices details epcq16 epcq32 epcq64 epcq128 epcq256 bytes 2,097,152 bytes [16 megabits (mb)] 4,194,304 bytes (32 mb) 8,388,608 bytes (64 mb) 16,777,216 bytes (128 mb) 33,554,432 bytes (256 mb) number of sectors 32 64 128 256 512 bytes per sector 65,536 bytes [512 kilobits (kb)] total number of subsectors (1) 512 1,024 2,048 4,096 8,192 bytes per subsector 4,096 bytes (32 kb) pages per sector 256 total number of pages 8,192 16,384 32,768 65,536 131,072 bytes per page 256 bytes note to table 2 : (1) every sector is further divided into 16 subsectors with 4 kb of memory. because of this, there are 512 (32 x16) subsectors for the epcq16 device, 1,024 (64 x 16) subsectors for the epcq32 device, 2,048 (128 x 16) subsectors for the epcq64 device, 4,096 (256 x 16) subsectors for the epcq128 device, and 8,192 (512 x 16) subsectors for the epcq256 device. table 3. address range for sectors 31..0 and subsectors 511..0 in epcq16 devices ?preliminary (part 1 of 2) sector subsector address range (byte addresses in hex) start end 31 511 1ff000 1fffff 510 1fe000 1fefff ... ... ... 498 1f2000 1f2fff 497 1f1000 1f1fff 496 1f0000 1f0fff 30 495 1ef000 1effff 494 1ee000 1eefff ... ... ... 482 1e2000 1e2fff 481 1e1000 1e1fff 480 1e0000 1e0fff
memory array organization page 3 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation address range for epcq32 ta b l e 4 lists the address range for each sector in epcq32 devices. 1 31 1f000 1ffff 30 1e000 1efff ... ... ... 18 12000 12fff 17 11000 11fff 16 10000 10fff 0 15 f000 ffff 14 e000 efff ... ... ... 2 2000 2fff 1 1000 1fff 0 h?0000000 h?0000fff table 3. address range for sectors 31..0 and subsectors 511..0 in epcq16 devices ?preliminary (part 2 of 2) sector subsector address range (byte addresses in hex) start end table 4. address range for sectors 63..0 and subsectors 1023..0 in epcq32 devices ?preliminary (part 1 of 2) sector subsector address range (byte addresses in hex) start end 63 1023 3ff000 3fffff 1022 3fe000 3fefff ... ... ... 1010 3f2000 3f2fff 1009 3f1000 3f1fff 1008 3f0000 3f0fff 62 1007 3ef000 3effff 1006 3ee000 3eefff ... ... ... 994 3e2000 3e2fff 993 3e1000 3e1fff 992 3e0000 3e0fff
page 4 memory array organization quad-serial configuration (epcq) devices datasheet july 2012 altera corporation address range for epcq64 ta b l e 5 lists the address range for each sector in epcq64 devices. 1 31 1f000 1ffff 30 1e000 1efff ... ... ... 18 12000 12fff 17 11000 11fff 16 10000 10fff 0 15 f000 ffff 14 e000 efff ... ... ... 2 2000 2fff 1 1000 1fff 0 h?0000000 h?0000fff table 4. address range for sectors 63..0 and subsectors 1023..0 in epcq32 devices ?preliminary (part 2 of 2) sector subsector address range (byte addresses in hex) start end table 5. address range for sectors 127..0 and subsectors 2047..0 in epcq64 devices ?preliminary (part 1 of 2) sector subsector address range (byte addresses in hex) start end 127 2047 7ff000 7fffff 2046 7fe000 7fefff ... ... ... 2034 7f2000 7f2fff 2033 7f1000 7f1fff 2032 7f0000 7f0fff 64 1039 40f000 40ffff 1038 40e000 40efff ... ... ... 1026 402000 402fff 1025 401000 401fff 1024 400000 400fff
memory array organization page 5 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation 63 1023 3ff000 3fffff 1022 3fe000 3fefff ... ... ... 1010 3f2000 3f2fff 1009 3f1000 3f1fff 1008 3f0000 3f0fff 62 1007 3ef000 3effff 1006 3ee000 3eefff ... ... ... 994 3e2000 3e2fff 993 3e1000 3e1fff 992 3e0000 3e0fff 1 31 1f000 1ffff 30 1e000 1efff ... ... ... 18 12000 12fff 17 11000 11fff 16 10000 10fff 0 15 f000 ffff 14 e000 efff ... ... ... 2 2000 2fff 1 1000 1fff 0 h?0000000 h?0000fff table 5. address range for sectors 127..0 and subsectors 2047..0 in epcq64 devices ?preliminary (part 2 of 2) sector subsector address range (byte addresses in hex) start end
page 6 memory array organization quad-serial configuration (epcq) devices datasheet july 2012 altera corporation address range for epcq128 ta b l e 6 lists the address range for each sector in epcq128 devices. table 6. address range for sectors 255..0 and subsectors 4095..0 in epcq128 devices ?preliminary (part 1 of 2) sector subsector address range (byte addresses in hex) start end 255 4095 fff000 ffffff 4094 ffe000 ffefff ... ... ... 4082 ff2000 ff2fff 4081 ff1000 ff1fff 4080 ff0000 ff0fff 254 4079 fef000 feffff 4078 fee000 feefff ... ... ... 4066 fe2000 fe2fff 4065 fe1000 fe1fff 4064 fe0000 fe0fff 129 2079 81f000 81ffff 2078 81e000 81efff ... ... ... 2066 812000 812fff 2065 811000 811fff 2064 810000 810fff 128 2063 80f000 80ffff 2062 80e000 80efff ... ... ... 2050 802000 802fff 2049 801000 801fff 2048 800000 800fff 127 2047 7ff000 7fffff 2046 7fe000 7fefff ... ... ... 2034 7f2000 7f2fff 2033 7f1000 7f1fff 2032 7f0000 7f0fff
memory array organization page 7 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation 64 1039 40f000 40ffff 1038 40e000 40efff ... ... ... 1026 402000 402fff 1025 401000 401fff 1024 400000 400fff 63 1023 3ff000 3fffff 1022 3fe000 3fefff ... ... ... 1010 3f2000 3f2fff 1009 3f1000 3f1fff 1008 3f0000 3f0fff 62 1007 3ef000 3effff 1006 3ee000 3eefff ... ... ... 994 3e2000 3e2fff 993 3e1000 3e1fff 992 3e0000 3e0fff 1 31 1f000 1ffff 30 1e000 1efff ... ... ... 18 12000 12fff 17 11000 11fff 16 10000 10fff 0 15 f000 ffff 14 e000 efff ... ... ... 2 2000 2fff 1 1000 1fff 0 h?0000000 h?0000fff table 6. address range for sectors 255..0 and subsectors 4095..0 in epcq128 devices ?preliminary (part 2 of 2) sector subsector address range (byte addresses in hex) start end
page 8 memory array organization quad-serial configuration (epcq) devices datasheet july 2012 altera corporation address range for epcq256 ta b l e 7 lists the address range for each sector in epcq256 devices. table 7. address range for sectors 511..0 and subsectors 8191..0 in epcq256 devices ?preliminary (part 1 of 3) sector subsector address range (byte addresses in hex) start end 511 8191 1fff000 1ffffff 8190 1ffe000 1ffefff ... ... ... 8178 1ff2000 1ff2fff 8177 1ff1000 1ff1fff 8176 1ff0000 1ff0fff 510 8175 1fef000 1feffff 8174 1fee000 1feefff ... ... ... 8162 1fe2000 1fe2fff 8161 1fe1000 1fe1fff 8160 1fe0000 1fe0fff 257 4127 101f000 101ffff 4126 101e000 101efff ... ... ... 4114 1012000 1012fff 4113 1011000 1011fff 4112 1010000 1010fff 256 4111 100f000 100ffff 4110 100e000 100efff ... ... ... 4098 1002000 1002fff 4097 1001000 1001fff 4096 1000000 1000fff 255 4095 fff000 ffffff 4094 ffe000 ffefff ... ... ... 4082 ff2000 ff2fff 4081 ff1000 ff1fff 4080 ff0000 ff0fff
memory array organization page 9 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation 254 4079 fef000 feffff 4078 fee000 feefff ... ... ... 4066 fe2000 fe2fff 4065 fe1000 fe1fff 4064 fe0000 fe0fff 129 2079 81f000 81ffff 2078 81e000 81efff ... ... ... 2066 812000 812fff 2065 811000 811fff 2064 810000 810fff 128 2063 80f000 80ffff 2062 80e000 80efff ... ... ... 2050 802000 802fff 2049 801000 801fff 2048 800000 800fff 127 2047 7ff000 7fffff 2046 7fe000 7fefff ... ... ... 2034 7f2000 7f2fff 2033 7f1000 7f1fff 2032 7f0000 7f0fff 64 1039 40f000 40ffff 1038 40e000 40efff ... ... ... 1026 402000 402fff 1025 401000 401fff 1024 400000 400fff 63 1023 3ff000 3fffff 1022 3fe000 3fefff ... ... ... 1010 3f2000 3f2fff 1009 3f1000 3f1fff 1008 3f0000 3f0fff table 7. address range for sectors 511..0 and subsectors 8191..0 in epcq256 devices ?preliminary (part 2 of 3) sector subsector address range (byte addresses in hex) start end
page 10 memory array organization quad-serial configuration (epcq) devices datasheet july 2012 altera corporation 62 1007 3ef000 3effff 1006 3ee000 3eefff ... ... ... 994 3e2000 3e2fff 993 3e1000 3e1fff 992 3e0000 3e0fff 1 31 1f000 1ffff 30 1e000 1efff ... ... ... 18 12000 12fff 17 11000 11fff 16 10000 10fff 0 15 f000 ffff 14 e000 efff ... ... ... 2 2000 2fff 1 1000 1fff 0 h?0000000 h?0000fff table 7. address range for sectors 511..0 and subsectors 8191..0 in epcq256 devices ?preliminary (part 3 of 3) sector subsector address range (byte addresses in hex) start end
memory operations page 11 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation memory operations this section describes the operations that you can use to access the memory in epcq devices. when performing the operation, addresses and data are shifted in and out of the device serially, with the msb first. timing requirements when the active low chip select ( ncs ) signal is driven low, shift in the operation code into the epcq device using the serial data ( data ) pin. each operation code bit is latched into the epcq device on the rising edge of the dclk . while executing an operation, shift in the desired operation code, followed by the address or data bytes as listed in table 8 . the device must drive the ncs pin high after the last bit of the operation sequence is shifted in. for read operations, the data read is shifted out on the data pin. you can drive the ncs pin high when any bit of the data is shifted out. for write and erase operations, drive the ncs pin high at a byte boundary, that is in a multiple of eight clock pulses. otherwise, the operation is rejected and not executed. all attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected. addressing mode the 3-byte addressing mode is enabled by default. to access the epcq256 memory, you must use the 4-byte addressing mode. in 4-byte addressing mode, the address width is 32-bit address. to enable the 4-byte addressing mode, you must execute the 4byteaddren operation. this addressing mode takes effect immediately after you execute the 4byteaddren operation and remains active in the subsequent power-ups. to disable the 4-byte addressing mode, you must execute the 4byteaddrex operation. 1 if you are using the quartus ? ii software or the srunner software to program the epcq256 device, you do not need to execute the 4byteaddren operation. these software automatically enable the 4-byte addressing mode when programming the device.
page 12 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation summary of operation codes ta b l e 8 lists the supported operations. table 8. operation codes for epcq devices?preliminary operation operation code (1) address bytes dummy bytes data bytes dclk f max (mhz) (2) read status b?0000 0101 0 0 1 to infinite (3) 100 read bytes b?0000 0011 3 or 4 0 1 to infinite (3) 50 read device identification b?1001 111x 001 to 20 (3) 100 fast read b?0000 1011 3 or 4 8 (5) 1 to infinite (3) 100 extended dual input fast read b?1011 1011 3 or 4 8 (5) 1 to infinite (3) 100 extended quad input fast read b?1110 1011 3 or 4 10 (5) 1 to infinite (3) 100 write enable b?0000 0110 000 100 write disable b?0000 0100 000 100 write status b?0000 0001 001 100 write bytes b?0000 0010 3 or 4 0 1 to 256 (4) 100 extended dual input fast write bytes b?1101 0010 3 or 4 0 1 to 256 (4) 100 extended quad input fast write bytes b?0001 0010 3 or 4 0 1 to 256 (4) 100 erase bulk b?1100 0111 000 100 erase sector b?1101 1000 3 or 4 0 0 100 4byteaddren (6) b?1011 0111 000 100 4byteassrex (6) b?1110 1001 000 100 notes to table 8 : (1) list msb first and lsb last. (2) pending characterization data. (3) the status register, data, or read device identification is read out at least once on the data1 pin and is continuously read out until the ncs pin is driven high. (4) a write bytes operation requires at least one data byte on the data1 pin. if more than 256 bytes are sent to the device, only the last 256 bytes are written to the memory. (5) you can configure the number of dummy bytes. (6) this operation is applicable for epcq256 device only.
memory operations page 13 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation 4byteaddren and 4byteaddrex operations to enable 4byteaddren or 4byteaddrex operations, you can select the device by driving the ncs signal low, followed by shifting in the operation code through data0 . 1 you must execute a write enable operation before you can enable the 4byteaddren or 4byteaddrex operations. for more information, refer to ?write enable operation? . figure 1 shows the timing diagram for the 4byteaddren operation. figure 2 shows the timing diagram for the 4byteaddrex operation. write enable operation when you enable the write enable operation, the write enable latch bit is set to 1 in the status register. you must execute this operation before the write bytes, write status, erase bulk, erase sector, extended dual input fast write bytes, extended quad input fast write bytes, 4byteaddren, and 4byteaddrex operations. figure 3 shows the timing diagram for the write enable operation. figure 1. 4byteaddren timing diagram figure 2. 4byteaddrex timing diagram figure 3. write enable operation timing diagram dclk 2 13 4567 0 ncs data0 operation code dclk 2 13 4567 0 ncs data0 operation code ncs dclk data 0 data 01 2 34567 operation code high impedance
page 14 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation write disable operation the write disable operation resets the write enable latch bit in the status register. to prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation, and under the following conditions: power up write bytes operation completion write status operation completion erase bulk operation completion erase sector operation completion extended dual input fast write bytes operation completion extended quad input fast write bytes operation completion figure 4 shows the timing diagram for the write disable operation. figure 4. write disable operation timing diagram ncs dclk data 0 data 01234567 operation code high impedance
memory operations page 15 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation read status operation you can use the read status operation to read the status register. figure 5 and figure 6 show the status bits in the status register of the epcq devices. if you set the write in progress bit to 1 , the epcq device executes a write or erase cycle and 0 indicates that no write or erase cycle is in progress. if you set the write enable latch bit to 0 , the epcq device rejects a write or erase cycle. you must set the write enable latch bit to 1 before every write bytes, write status, erase bulk, and erase sector operations. use the top or bottom bit (tb bit) with the block protect bits to determine that the protected area starts from the top or bottom of the memory array. when the top or bottom bit is set to 0 , the protected area starts from the top of the memory array. when the top or bottom bit is set to 1 , the protected area starts from the bottom of the memory array. the non-volatile block protect bits determine the area of the memory protected from being written or erased unintentionally. ta b l e 9 through table 18 on page 20 list the protected area in epcq16, epcq32, epcq64, epcq128, and epcq256 devices with reference to the block protect bits. the erase bulk operation is only available when all the block protect bits are set to 0 . when any of the block protect bits are set to 1 , the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation. figure 5. epcq16 and epcq32 stat us register status bits figure 6. epcq64, epcq128, and epcq256 status register status bits bit 7 bit 0 block protect bits write in progress bit write enable latch bit bp2 bp1 bp0 wel wip tb top/bottom bit reserved bit 7 bit 0 block protect bits write in progress bit write enable latch bit bp2 bp1 bp0 wel wip bp3 tb top/bottom bit block protect bit
page 16 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation table 9. block protection bits in epcq16 when tb bit is set to 0 status register content memory content tb bit bp2 bit bp1 bit bp0 bi t protected area unprotected area 0000 none all sectors 0 0 0 1 upper 32 sectors 0 to 30 0 0 1 0 upper 16 sectors 0 to 29 0 0 1 1 upper 8 sectors 0 to 27 0 1 0 0 upper 4 sectors 0 to 23 0 1 0 1 upper half sectors 0 to 15 0110 all sectors none 0111 all sectors none table 10. block protection bits in epcq16 when tb bit is set to 1 status register content memory content tb bit bp2 bit bp1 bit bp0 bi t protected area unprotected area 1000 none all sectors 1 0 0 1 lower 32 sectors 1 to 31 1 0 1 0 lower 16 sectors 2 to 31 1 0 1 1 lower 8 sectors 4 to 31 1 1 0 0 lower 4 sectors 8 to 31 1 1 0 1 lower half sectors 16 to 31 1110 all sectors none 1111 all sectors none
memory operations page 17 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation table 11. block protection bits in epcq32 when tb bit is set to 0 status register content memory content tb bit bp2 bit bp1 bit bp0 bi t protected area unprotected area 0000 none all sectors 0 0 0 1 upper 64 sectors 0 to 62 0 0 1 0 upper 32 sectors 0 to 61 0 0 1 1 upper 16 sectors 0 to 59 0 1 0 0 upper 8 sectors 0 to 55 0 1 0 1 upper 4 sectors 0 to 47 0 1 1 0 upper half sectors 0 to 31 0111 all sectors none table 12. block protection bits in epcq32 when tb bit is set to 1 status register content memory content tb bit bp2 bit bp1 bit bp0 bi t protected area unprotected area 1000 none all sectors 1 0 0 1 lower 64 sectors 1 to 63 1 0 1 0 lower 32 sectors 2 to 63 1 0 1 1 lower 16 sectors 4 to 63 1 1 0 0 lower 8 sectors 8 to 63 1 1 0 1 lower 4 sectors 16 to 63 1 1 1 0 lower half sectors 32 to 63 1111 all sectors none
page 18 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation table 13. block protection bits in epcq64 when tb bit is set to 0 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 00000 none all sectors 0 0 0 0 1 upper 128 sectors 0 to 126 0 0 0 1 0 upper 64 sectors 0 to 125 0 0 0 1 1 upper 32 sectors 0 to 123 0 0 1 0 0 upper 16 sectors 0 to 119 0 0 1 0 1 upper 8 sectors 0 to 111 0 0 1 1 0 upper quarter sectors 0 to 95 0 0 1 1 1 upper half sectors 0 to 63 01000 all sectors none 01001 all sectors none 01010 all sectors none 01011 all sectors none 01100 all sectors none 01101 all sectors none 01110 all sectors none 01111 all sectors none table 14. block protection bits in epcq64 when tb bit is set to 1 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 10000 none all sectors 1 0 0 0 1 lower 128 sectors 1 to 127 1 0 0 1 0 lower 64 sectors 2 to 127 1 0 0 1 1 lower 32 sectors 4 to 127 1 0 1 0 0 lower 16 sectors 8 to 127 10101 lower 8 sectors 16 to 127 1 0 1 1 0 lower quarter sectors 32 to 127 1 0 1 1 1 lower half sectors 64 to 127 11000 all sectors none 11001 all sectors none 11010 all sectors none 11011 all sectors none 11100 all sectors none 11101 all sectors none 11110 all sectors none 11111 all sectors none
memory operations page 19 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation table 15. block protection bits in epcq128 when tb bit is set to 0 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 00000 none all sectors (sectors 0 to 255) 00001 upper 256 sectors 0 to 254 00010 upper 128 sectors 0 to 253 00011 upper 64 sectors 0 to 251 00100 upper 32 sectors 0 to 247 00101 upper 16 sectors 0 to 239 00110 upper 8 sectors 0 to 223 00111 upper quarter sectors 0 to 191 01000 upper half (sector 255) lower half (sectors 0 to 127) 01001 all sectors none 01010 all sectors none 01011 all sectors none 01100 all sectors none 01101 all sectors none 01110 all sectors none 01111 all sectors (128 mb, 256 sectors) none table 16. block protection bits in epcq128 when tb bit is set to 1 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 10000 none all sectors (sectors 0 to 255) 10001 lower 256 sectors 1 to 255 10010 lower 128 sectors 2 to 255 10011 lower 64 sectors 4 to 255 10100 lower 32 sectors 8 to 255 10101 lower 16 sectors 16 to 255 10110 lower 8 sectors 32 to 255 10111 lower quarter sectors 64 to 255 11000 lower half sectors 128 to 255 11001 all sectors none 11010 all sectors none 11011 all sectors none 11100 all sectors none 11101 all sectors none 11110 all sectors none 11111 all sectors none
page 20 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation table 17. block protection bits in epcq256 when tb bit is set to 0 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 00000 none all sectors 00001 upper 512 sectors 0 to 511 00010 upper 256 sectors 0 to 510 00011 upper 128 sectors 0 to 508 00100 upper 64 sectors 0 to 504 00101 upper 32 sectors 0 to 496 00110 upper 16 sectors 0 to 480 00111 upper 8 sectors 0 to 448 01000 upper quarter sectors 0 to 384 01001 upper half sectors 0 to 256 01010 all sectors none 01011 all sectors none 01100 all sectors none 01101 all sectors none 01110 all sectors none 01111 all sectors none table 18. block protection bits in epcq256 when tb bit is set to 1 status register content memory content tb bit bp3 bit bp2 bit bp1 bit bp0 bit protected area unprotected area 10000 none all sectors 10001 lower 512 sectors 1 to 511 10010 lower 256 sectors 2 to 511 10011 lower 128 sectors 4 to 511 10100 lower 64 sectors 8 to 511 10101 lower 32 sectors 16 to 511 10110 lower 16 sectors 32 to 511 10111 lower 8 sectors 64 to 511 11000 lower quarter sectors 128 to 511 11001 lower half sectors 256 to 511 11010 all sectors none 11011 all sectors none 11100 all sectors none 11101 all sectors none 11110 all sectors none 11111 all sectors none
memory operations page 21 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation write status operation the write status operation does not affect the write enable latch and write in progress bits. you can use the write status operation to set the status register block protection and top or bottom bits. therefore, you can implement this operation to protect certain memory sectors. for more information, refer to table 15 on page 19 through table 18 . after setting the block protect bits, the protected memory sectors are treated as read-only memory. you must execute the write enable operation before the write status operation. figure 7 shows the timing diagram for the write status operation. immediately after the ncs signal drives high, the device initiates the self-timed write status cycle. the self-timed write status cycle usually takes 5 ms for all epcq devices and is guaranteed to be less than 8 ms. for more information, refer to t ws in ta b l e 20 on page 32 . you must account for this delay to ensure that the status register is written with the desired block protect bits. alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed write status cycle is in progress. set the write in progress bit to 1 during the self-timed write status cycle and 0 when it is complete. figure 7. write status operation timing diagram ncs dclk data 0 data 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 operation code status register 76543210 msb high impedance
page 22 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation read bytes operation when you execute the read bytes operation, you first shift in the read bytes operation code, followed by a 3-byte addressing mode ( a[23..0] ) or a 4-byte addressing mode ( a[31..0] ). each address bit must be latched in on the rising edge of the dclk signal. after the address is latched in, the memory contents of the specified address are shifted out serially on the data1 pin, beginning with the msb. for reading raw programming data file ( .rpd ), the content is shifted out serially beginning with the lsb. each data bit is shifted out on the falling edge of the dclk signal. the maximum dclk frequency during the read bytes operation is 50 mhz. figure 8 shows the timing diagram for the read bytes operation. the first byte address can be at any location. the device automatically increases the address to the next higher address after shifting out each byte of data. therefore, the device can read the whole memory with a single read bytes operation. when the device reaches the highest address, the address counter restarts at 0x000000 , allowing the memory contents to be read out indefinitely until the read bytes operation is terminated by driving the ncs signal high. if the read bytes operation is shifted in while a write or erase cycle is in progress, the operation is not executed and does not affect the write or erase cycle in progress. figure 8. read bytes operation timing diagram note to figure 8 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. ncs dclk data 0 data 1 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 operation code 24-bit address (1) 23 22 21 3 2 1 0 77 65 43 210 msb msb high impedance data out 1 data out 2
memory operations page 23 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation fast read operation when you execute the fast read operation, you first shift in the fast read operation code, followed by a 3-byte addressing mode ( a[23..0] ) or a 4-byte addressing mode ( a[31..0] ), and a dummy byte with each bit being latched-in during the rising edge of the dclk signal. then, the memory contents at that address is shifted out on data1 with each bit being shifted out at a maximum frequency of 100 mhz during the falling edge of the dclk signal. figure 9 shows the operation sequence of the fast read operation. the first byte address can be at any location. the device automatically increases the address to the next higher address after shifting out each byte of data. therefore, the device can read the whole memory with a single fast read operation. when the device reaches the highest address, the address counter restarts at 0x000000 , allowing the read sequence to continue indefinitely. you can terminate the fast read operation by driving the ncs signal high at any time during data output. if the fast read operation is shifted in while an erase, program, or write cycle is in progress, the operation is not executed and does not affect the erase, program, or write cycle in progress. figure 9. fast read operation timing diagram note to figure 9 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. ncs dclk data 0 data 1 ncs dclk data 0 data 1 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 operation code dummy byte 24-bit address (1) msb msb msb msb high impedance 23 22 21 3 2 1 0 data out 1 data out 2 765432 0 1 7 6543210 7 765432 0 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
page 24 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation extended dual input fast read operation this operation is similar to the fast read operation except that the data and addresses are shifted in and out on the data0 and data1 pins. figure 10 shows the operation sequence of the extended dual input fast read operation. figure 10. extended dual input fast read operation timing diagram note to figure 10 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. 1 0 2 3 4 5 6 7 8 9 1011121314151617181920 22 20 18 16 14 12 10 8 6 4 2 0 23 21 19 17 15 13 11 9 7 5 3 1 64206420642064206 75317531753175317 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 operation code dummy cycles byte 1 byte 2 byte 3 byte 4 ncs dclk data0 data1 ncs dclk data0 data1 24-bit address (1) io switches from input to output
memory operations page 25 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation extended quad input fast read operation this operation is similar to the extended dual input fast read operation except that the data and addresses are shifted in and out on the data0 , data1 , data2 , and data3 pins. figure 11 shows the operation sequence of the extended quad input fast read operation. figure 11. extended quad input fast read operation timing diagram note to figure 11 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. 2 1 345678910 11 12 13 14 0 dclk data0 ncs operating code 15 16 24 21 22 23 40 20 16 12 8 40 0 4 4 26 25 27 51 21 17 13 9 data1 don?t care byte 1 51 1 5 5 73 3 7 7 73 23 19 15 11 6 22 6 6 62 22 18 14 10 data2 don?t care byte 2 dummy cycles 24-bit address (1) data3 ?1? io switches from input to output
page 26 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation read device identification operation this operation reads the 8-bit device identification of the epcq device from the data1 output pin. if this operation is shifted in while an erase or write cycle is in progress, the operation is not executed and does not affect the erase or write cycle in progress. ta b l e 1 9 lists the epcq device identifications. the 8-bit device identification of the epcq device is shifted out on the data1 pin on the falling edge of the dclk signal. figure 12 shows the operation sequence of the read device identification operation. table 19. epcq device identification epcq device silicon id (binary value) epcq16 b?0001 0101 epcq32 b?0001 0110 epcq64 b?0001 0111 epcq128 b?0001 1000 epcq256 b?0001 1001 figure 12. read device identification operation timing diagram ncs dclk data 0 data 1 0 1 2 3 4 5 6 7 8 9 10 20 21 23 24 25 26 27 28 29 30 31 32 operation code two dummy bytes 15 14 13 3210 765 43 210 msb msb high impedance silicon id
memory operations page 27 july 2012 altera corporation quad-serial configuration (epcq) devices datasheet write bytes operation this operation allows bytes to be written to the memory. you must execute the write enable operation before the write bytes operation. after the write bytes operation is completed, the write enable latch bit in the status register is set to 0 . when you execute the write bytes operation, you shift in the write bytes operation code, followed by a 3-byte addressing mode ( a[23..0] ) or a 4-byte addressing mode ( a[31..0] ), and at least one data byte on the data0 pin. if the eight lsbs ( a[7..0] ) are not all 0 , all sent data that goes beyond the end of the current page is not written into the next page. instead, this data is written at the start address of the same page. you must ensure the ncs signal is set low during the entire write bytes operation. figure 13 shows the operation sequence of the write bytes operation. if more than 256 data bytes are shifted into the epcq device with a write bytes operation, the previously latched data is discarded and the last 256 bytes are written to the page. however, if less than 256 data bytes are shifted into the epcq device , they are guaranteed to be written at the specified addresses and the other bytes of the same page are not affected. the device initiates a self-timed write cycle immediately after the ncs signal is driven high. for more information about the self-timed write cycle time, refer to t wb in table 20 on page 32 . you must account for this amount of delay before another page of memory is written. alternatively, you can check the write in progress bit in the status register by executing the read statu s operation while the self-timed write cycle is in progress. the write in progress bit is set to 1 during the self-timed write cycle and 0 when it is complete. 1 you must erase all the memory bytes of epcq devices before you implement the write bytes operation. you can erase all the memory bytes by executing the erase sector operation in a sector or the erase bulk operation throughout the entire memory. figure 13. write bytes operation timing diagram note to figure 13 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. ncs dclk data 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 2072 2073 2074 2075 2076 2077 2078 2079 operation code 24-bit address (1) 23 22 21 3 2 1 0 7654 msb msb msb msb data byte 1 data byte 2 data byte 256 3210 7654 7654 3210 3210
page 28 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation extended dual input fast write bytes operation this operation is similar to the write bytes operation except that the data and addresses are shifted in on the data0 and data1 pins. figure 14 shows the operation sequence of the extended dual input fast write bytes operation. figure 14. extended dual input fast write bytes timing diagram note to figure 14 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. 2 1 345678910 11 12 13 14 0 14 12 10 8 dclk data0 ncs data1 operation code dclk data0 ncs data1 33 21 22 23 24 25 26 27 28 29 30 31 32 7531 75 1 3 7 531 6420 642064 0 2 15 16 17 18 19 20 23 21 19 17 15 13 11 9 7531 22 20 18 16 6420 24-bit address (1) 34 msb 35 6420 7531 msb msb msb data in 4 data in 1 data in 3 data in 2 64 0 2 7531 msb data in 256 18 19 20
memory operations page 29 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation extended quad input fast write bytes operation this operation is similar to the extended dual input fast write bytes operation except that the data and addresses are shifted in on the data0 , data1 , data2 , and data3 pins. figure 15 shows the operation sequence of the extended quad input fast write bytes operation. figure 15. extended quad input fast write bytes operation timing diagram note to figure 15 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. data0 ncs data1 operation code don?t care msb data3 data2 don?t care ?1? data in 2 1 345678910 0 dclk 20 17 18 19 11 12 13 14 15 16 22 21 23 25 24 26 msb msb msb msb msb 24-bit address (1) data in data in 2 134 5 6 27 20 16 12 8 04 40 4 0 4 0 4 0 44 0 04 0 26 62 6 2 6 2 6 2 66 2 26 2 15 51 5 1 5 1 5 1 55 1 15 1 21 17 13 9 22 18 14 10 23 19 15 37 73 7 3 7 3 7 3 77 3 37 3 11 7 msb
page 30 memory operations quad-serial configuration (epcq) devices datasheet july 2012 altera corporation erase bulk operation this operation sets all the memory bits to 1 or 0xff . similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation. you can implement the erase bulk operation by driving the ncs signal low and then shifting in the erase bulk operation code on the data0 pin. the ncs signal must be driven high after the eighth bit of the erase bulk operation code has been latched in. figure 16 shows the erase bulk operation. the device initiates a self-timed erase bulk cycle immediately after the ncs signal is driven high. for more information about the self-timed erase bulk cycle time, refer to t wb in table 20 on page 32 . you must account for this delay before accessing the memory contents. alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. the write in progress bit is set to 1 during the self-timed erase cycle and 0 when it is complete. the write enable latch bit in the status register is reset to 0 before the erase cycle is complete. figure 16. erase bulk operation timing diagram ncs dclk data 0 01234567 operation code
power mode page 31 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation erase sector operation the erase sector operation allows you to erase a certain sector in the epcq device by setting all the bits inside the sector to 1 or 0xff . this operation is useful if you want to access the unused sectors as a general purpose memory in your applications. you must execute the write enable operation before the erase sector operation. when you execute the erase sector operation, you must first shift in the erase sector operation code, followed by the 3-byte addressing mode ( a[23..0] ) or the 4-byte addressing mode ( a[31..0] ) of the chosen sector on the data0 pin. the 3-byte addressing mode or the 4-byte addressing mode for the erase sector operation can be any address inside the specified sector. for more information about the sector address range, refer to table 6 on page 6 and tabl e 7 on page 8 . drive the ncs signal high after the eighth bit of the erase sector operation code has been latched in. figure 17 shows the erase sector operation. the device initiates a self-timed erase sector cycle immediately after the ncs signal is driven high. for more information about the self-timed erase sector cycle time, refer to t es in table 20 on page 32 . you must account for this amount of delay before another page of memory is written. alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. the write in progress bit is set to 1 during the self-timed erase cycle and 0 when it is complete. the write enable latch bit in the status register is set to 0 before the self-timed erase cycle is complete. power mode epcq devices support active and standby power modes. when the ncs signal is low, the device is enabled and is in active power mode. the fpga is configured while the epcq device is in active power mode. when the ncs signal is high, the device is disabled but remains in active power mode until all internal cycles are completed, such as write or erase operations. the epcq device then goes into standby power mode. the i cc1 and i cc0 parameters list the v cc supply current when the device is in active and standby power modes. for more information, refer to table 25 on page 36 . figure 17. erase sector operation timing diagram note to figure 17 : (1) to access the entire epcq256 memory, use 4-byte addressing mode. in the 4-byte addressing mode, the address width is 32-bit address. ncs dclk data 0 0 1 2 3 4 5 6 7 8 9 28 29 30 31 operation code 24-bit address (1) 23 22 3 2 1 0 msb
page 32 timing information quad-serial configuration (epcq) devices datasheet july 2012 altera corporation timing information figure 18 shows the timing waveform for the write operation. ta b l e 2 0 lists the epcq device timing parameters for the write operation. figure 18. write operation timing diagram ncs dclk data0 data t ncsh t dsu t ncssu t ch t cl t csh t dh bit n bit 0 bit n ? 1 high impedance table 20. write operation parameters?preliminary (part 1 of 2) symbol parameter min typical max unit f wclk write clock frequency (from the fpga, download cable, or embedded processor) for write enable, write disable, read status, read device identification, write bytes, erase bulk, and erase sector operations ? ? 100 mhz t ch (1) dclk high time 4 ? ? ns t cl (1) dclk low time 4 ? ? ns t ncssu chip select ( ncs ) setup time 4 ? ? ns t ncsh chip select ( ncs ) hold time 4 ? ? ns t dsu data[] in setup time before the rising edge on dclk 2??ns t dh data[] hold time after the rising edge on dclk 3??ns t csh chip select ( ncs ) high time 50 ? ? ns t wb (2) write bytes cycle time ? 0.6 5 ms t ws (2) write status cycle time ? 1.3 8 ms t eb (2) erase bulk cycle time for epcq16 ? 170 250 s erase bulk cycle time for epcq32 ? 170 250 s erase bulk cycle time for epcq64 ? 60 250 s erase bulk cycle time for epcq128 ? 170 250 s erase bulk cycle time for epcq256 ? 240 480 s t es (2) erase sector cycle time for epcq16 ?0.7 3 s erase sector cycle time for epcq32 erase sector cycle time for epcq64 erase sector cycle time for epcq128 erase sector cycle time for epcq256
timing information page 33 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation figure 19 shows the timing waveform for the read operation. ta b l e 2 1 lists the epcq device timing parameters for the read operation. t ess (2) erase subsector cycle time for epcq16 ?0.31.5 s erase subsector cycle time for epcq32 erase subsector cycle time for epcq64 erase subsector cycle time for epcq128 erase subsector cycle time for epcq256 notes to table 20 : (1) the value must be larger than or equal to 1/f wclk . (2) figure 18 does not show these parameters. table 20. write operation parameters?preliminary (part 2 of 2) symbol parameter min typical max unit figure 19. read operation timing diagram ncs dclk data data0 t nclk2d t cl t ch t odis bit n bit 0 bit n ? 1 add_bit 0 table 21. read operation parameters?preliminary symbol parameter min max unit f rclk read clock frequency (from the fpga or embedded processor) for read bytes operations ?50mhz fast read clock frequency (from the fpga or embedded processor) for fast read bytes operation ? 100 mhz t ch dclk high time 4 ? ns t cl dclk low time 4 ? ns t odis output disable time after read ? 8 ns t nclk2d clock falling edge to data ?7ns
page 34 programming and configuration file support quad-serial configuration (epcq) devices datasheet july 2012 altera corporation programming and configuration file support the quartus ii software provides programming support for epcq devices. when you select an epcq device, the quartus ii software automatically generates the programmer object file ( .pof ) to program the device. the software allows you to select the appropriate epcq device density that most efficiently stores the configuration data for the selected fpga. you can program the epcq device in-system by an external microprocessor using the srunner software driver. the srunner software driver is developed for embedded epcq device programming that you can customize to fit in different embedded systems. the srunner software driver reads .rpd files and writes to the epcq devices. the programming time is comparable to the quartus ii software programming time. because the fpga reads the lsb of the .rpd data first during the configuration process, the lsb of .rpd bytes must be shifted out first during the read bytes operation and shifted in first during the write bytes operation. 1 writing and reading the .rpd file to and from the epcq device is different from the other data and address bytes. during the isp of an epcq device using the usb-blaster, ethernetblaster ii, or ethernetblaster download cable, the cable pulls the nconfig signal low to reset the fpga and overrides the 10-k ? pull-down resistor on the nce pin of the fpga. the download cable then uses the interface pins depending on the selected as mode to program the epcq device. when programming is complete, the download cable releases the interface pins of the epcq device and the nce pin of the fpga and pulses the nconfig signal to start the configuration process. the fpga can program the epcq device in-system using the jtag interface with the serial flash loader (sfl). this solution allows you to indirectly program the epcq device using the same jtag interface that is used to configure the fpga. f for more information about configuration, refer to the configuration chapter in the appropriate device handbook. f for more information about sfl, refer to an 370: using the serial flashloader with the quartus ii software . f for more information about programming and configuration support, refer to the following documents: usb-blaster download cable user guide ethernetblaster ii communications cable user guide ethernetblaster communications cable user guide
operating conditions page 35 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation operating conditions ta b l e 2 2 through table 26 list information about the absolute maximum ratings, recommended operating conditions, dc operating conditions, i cc supply current, and capacitance for epcq devices. table 22. absolute maximum ratings?preliminary symbol parameter condition min max unit v cc supply voltage with respect to gnd ?0.6 4.0 v v i dc input voltage with respect to gnd ?0.6 4.0 v i max dc v cc or gnd current ? ? 20 ma i out dc output current per pin ? ?25 25 ma p d power dissipation ? ? 54 mw t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature under bias ? 135 c table 23. recommended operating conditions?preliminary symbol parameter condition min max unit v cc supply voltage (1) 2.7 3.6 v v i input voltage with respect to gnd ?0.5 0.4 + v cc v v o output voltage ? 0 v cc v t a operating temperature for commercial use 0 70 c for industrial use ?40 85 c t r input rise time ? ? 5 ns t f input fall time ? ? 5 ns note to table 23 : (1) the maximum v cc rise time is 100 ms. table 24. dc operating conditions?preliminary symbol parameter condition min max unit v ih high-level input voltage ? 0.7 x v cc v cc +0.4 v v il low-level input voltage ? ?0.5 0.3 x v cc v v oh high-level output voltage i oh = ?100 a (1) v cc -0.2 ? v v ol low-level output voltage i ol =1.6ma (2) ?0.4v i i input leakage current v i =v cc or gnd ?10 10 a i oz tri-state output off-state current v o =v cc or gnd ?10 10 a notes to table 24 : (1) the i oh parameter refers to the high-level ttl or cmos output current. (2) the i ol parameter refers to the low-level ttl or cmos output current.
page 36 pin information quad-serial configuration (epcq) devices datasheet july 2012 altera corporation pin information figure 20 and figure 21 show the epcq device in an 8-pin device. figure 22 and figure 23 show the epcq device in a 16-pin device. the following lists the control pins on the epcq device: serial data 3 ( data3 ) serial data 2 ( data2 ) serial data 1 ( data1 ) serial data 0 ( data0 ) serial clock ( dclk ) chip select ( ncs ) f for more information about configuration, refer to the configuration chapter in the appropriate device handbook. table 25. i cc supply current?preliminary symbol parameter condition min max unit i cc0 v cc supply current (standby) ? ? 100 a i cc1 v cc supply current (during active power mode) ?520ma table 26. capacitance (1) ?preliminary symbol parameter condition min max unit c in input pin capacitance v in =0v ? 6 pf c out output pin capacitance v out =0v ? 8 pf note to table 26 : (1) capacitance is sample-tested only at t a = 25 x c and at a 20-mhz frequency. figure 20. as x1 pin-out diagram for epcq16 and epcq32 devices figure 21. as x4 pin-out diagram for epcq16 and epcq32 devices dclk data 0 v cc 1 2 3 4 8 7 6 5 v cc v cc gnd data 1 ncs dclk data 0 1 2 3 4 8 7 6 5 v cc gnd data 1 data 3 data 2 ncs
pin information page 37 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation figure 22. as x1 pin-out diagram for epcq64, epcq128, and epcq256 devices note to figure 22 : (1) you can leave these pins floating or you can connect them to v cc or gnd. figure 23. as x4 pin-out diagram for epcq64, epcq128, and epcq256 devices note to figure 23 : (1) you can leave these pins floating or you can connect them to v cc or gnd. dclk data 0 n.c. n.c. n.c. n.c. v cc n.c. n.c. gnd ncs data 1 n.c. n.c. 1 2 3 (1) 4 (1) 16 15 14 (1) 13 (1) 5 (1) 6 (1) 7 8 12 (1) 11 (1) 10 9 v cc v cc dclk data 0 n.c. n.c. n.c. n.c. data 3 v cc n.c. n.c. gnd data 2 ncs data 1 n.c. n.c. 1 2 3 (1) 4 (1) 16 15 14 (1) 13 (1) 5 (1) 6 (1) 7 8 12 (1) 11 (1) 10 9
page 38 pin information quad-serial configuration (epcq) devices datasheet july 2012 altera corporation ta b l e 2 7 lists the pin description of the epcq device. table 27. epcq device pin descript ion?preliminary (part 1 of 3) pin name as x1 pin-out diagra m as x4 pin-out diagram pin type description pin number in 8-pin soic package pin number in 16-pin soic package pin number in 8-pin soic package pin number in 16-pin soic package data0 5 15 5 15 i/o for as x1 mode, use this pin as an input signal pin to write or program the epcq device. during write or program operations, the data is latched on the rising edge of the dclk signal. for as x4 mode, use this pin as an i/o signal pin. during write or program operations, this pin acts as an input pin that serially transfers data into the epcq device. the data is latched on the rising edge of the dclk signal. during read or configuration operations, this pin acts as an output signal pin that serially transfers data out of the epcq device to the fpga. the data is shifted out on the falling edge of the dclk signal. during the extended quad input fast write bytes or extended dual input fast write bytes operations, this pin acts as an input pin that serially transfers data into the epcq device. the data is latched on the rising edge of the dclk signal. during extended dual input fast read or extended quad input fast read operations, this pin acts as an output signal pin that serially transfers data out of the epcq device to the fpga. the data is shifted out on the falling edge of the dclk signal. data1 2828i/o for as x1 and x4 modes, use this pin as an output signal pin that serially transfers data out of the epcq device to the fpga during read or configuration operations. the transition of the signal is on the falling edge of the dclk signal. during the extended dual input fast write bytes or extended quad input fast write bytes operation, this pin acts as an input signal pin that serially transfers data into the epcq device. the data is latched on the rising edge of the dclk signal. during extended dual input fast read or extended quad input fast read operations, this pin acts as an output signal pin that serially transfer data out of the epcq device to the fpga. the data is shifted out on the falling edge of the dclk signal. during read, configuration, or program operations, you can enable the epcq device by pulling the ncs signal low.
pin information page 39 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation data2 ? ? 3 9 i/o for as x1 mode, extended dual input fast write bytes operation and extended dual input fast read operation, this pin must connect to a 3.3-v power supply. for as x4 mode, use this pin as an output signal that serially transfers data out of the epcq device to the fpga during read or configuration operations. the transition of the signal is on the falling edge of the dclk signal. during the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the epcq device. the data is latched on the rising edge of the dclk signal. during the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the epcq device to the fpga. the data is shifted out on the falling edge of the dclk signal. data3 ? ? 7 1 i/o for as x1 mode, extended dual input fast write bytes operation and extended dual input fast read operation, this pin must connect to a 3.3-v power supply. for as x4 mode, use this pin as an output signal that serially transfers data out of the epcq device to the fpga during read or configuration operations. the transition of the signal is on the falling edge of the dclk signal. during the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the epcq device. the data is latched on the rising edge of the dclk signal. during the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the epcq device to the fpga. the data is shifted out on the falling edge of the dclk signal. ncs 1717input the active low ncs input signal toggles at the beginning and end of a valid operation. when this signal is high, the device is deselected and the data pin is tri-stated. when this signal is low, the device is enabled and is in active mode. after power up, the epcq device requires a falling edge on the ncs signal before you begin any operation. table 27. epcq device pin descript ion?preliminary (part 2 of 3) pin name as x1 pin-out diagra m as x4 pin-out diagram pin type description pin number in 8-pin soic package pin number in 16-pin soic package pin number in 8-pin soic package pin number in 16-pin soic package
page 40 pin information quad-serial configuration (epcq) devices datasheet july 2012 altera corporation dclk 6 16 6 16 input the fpga provides the dclk signal. this signal provides the timing for the serial interface. the data presented on the data0 pin is latched to the epcq device on the rising edge of the dclk signal. the data on the data pin changes after the falling edge of the dclk signal and is latched in to the fpga on the next falling edge of the dclk signal. v cc 3, 7, 8 1, 2, 9 8 2 power connect the power pins to a 3.3-v power supply. gnd 4 10 4 10 ground ground pin. table 27. epcq device pin descript ion?preliminary (part 3 of 3) pin name as x1 pin-out diagra m as x4 pin-out diagram pin type description pin number in 8-pin soic package pin number in 16-pin soic package pin number in 8-pin soic package pin number in 16-pin soic package
device package and ordering code page 41 quad-serial configuration (epcq) devices datasheet july 2012 altera corporation device package and ordering code this section describes the package offered in epcq devices and the ordering codes for each epcq device. package the epcq16 and epcq32 devices are available in 8-pin soic packages. the epcq64, epcq128, and epcq256 devices are available in 16-pin soic packages. for a 16-pin soic package, you can migrate vertically from the epcq128 device to the epcq256 device. if you use the as x1 configuration scheme, you can migrate to the epcs16, epcs64, or epcs128 serial configuration devices. f for more information about migration to epcs, refer to the serial configuration (epcs) devices datasheet . ordering code ta b l e 2 8 lists the ordering codes for epcq devices. table 28. epcq device ordering codes device ordering code (1) epcq16 epcq16si8n epcq32 epcq32si8n epcq64 epcq64si16n epcq128 epcq128si16n epcq256 EPCQ256SI16N note to table 28 : (1) n indicates that the device is lead free.
page 42 document revision history quad-serial configuration (epcq) devices datasheet july 2012 altera corporation document revision history ta b l e 2 9 lists the revision history for this document. table 29. document revision history date version changes july 2012 3.0 added table 3 , table 4 , and table 5 to include the address range for epcq16, epcq32, and epcq64 devices. added table 9 , table 10 , table 11 , table 12 , ta b le 1 3 , and table 14 to include the block protection bits for epcq16, epcq32, and epcq64 devices. added figure 5 , figure 20 and figure 21 to include epcq16 and epcq32 devices. updated the ?device package and ordering code? section. updated table 1 , table 2 , table 19 , table 20 , ta b le 2 7 , and table 28 to include epcq16, epcq32, and epcq64 devices. updated the address bytes for the extended quad input fast write bytes operation in table 8 . updated figure 22 and figure 23 to include epcq64 devices. january 2012 2.0 added figure 2. updated ?read bytes operation? and ?fast read operation? sections. updated figure 1, figure 3, figure 4, figure 7, and figure 13. updated table 5, table 11, table 12, and table 14. minor text edits. june 2011 1.0 initial release.

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