6 decade predetermining up/down counter features: ? +4.75v to +15v (vss - v d d ) ? preset, presignal and mainsignal store ? dc to 250khz count frequency ? fully synchronous operation three comparators with output flags automatic or manual preset/reset control ? thumbwheel interface for storage selects ? prescale on count input selectable ? count inhibit ? up/down control ? scan rate up to 150khz ? scan oscillator has override capability ? blanking override for decimal point operaton ? multiplexed 7 segment and bcd data output ? output latches ? reset ? hysteresis on count input ? cmos type noise immunity on all other inputs ? LS7055, ls7056 (dip) - see figure 1 description: the LS7055/ls7056 is a mos synchronous 6 decade up/down counter. the circuit includes storages and comparators, zero de- tect, automatic presetting and resetting, output latches, multi- plexed output bcd and seven segment data. thumbwheel switches can be used to provide bcd data to the storage net- works in the circuit. count (pin 40) counter operates at speeds up to 250khz and advances on the positive edge of the input count pulse. up/down (pin 39) counter operates in up or down mode. a high input causes the counter to operate in the up mode while a low input causes it to operate in the down mode. count inhibit (pin 1) a high input inhibits counting and the counter remains at its last count. a low input enables counting. data transfer input (pin 37) a high input allows the seven segment display and bcd data to follow the count (the internal latches become transparent). a low input prevents updating of the latches as the count advances and the seven segment display and bcd data outputs remain fixed. reset (pin 4) a high input resets and holds all counter stages at zero. a low input allows counter operation. january 2003 7055-012703-1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 12 3 5 w a l t w h i t m a n ro a d , m e l v i l l e , n y 1 174 7 ( 631 ) 2 71 - 0 40 0 f a x ( 631 ) 2 7 1 - 0 4 0 5 LS7055 ls7056 lsi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 figure 1 pin assignment - top view count input up/down input zero detect output data transfer input presignal output b1 b2 b4 b8 blanking override g f e v ss (+v) c b lsd v dd (-v) reset input count inhibit input divide control input 1 divide control input 2 main signal output b8 b4 b2 b1 bcd data outputs digit select outputs LS7055 segment outputs inhibit internal reset input inhibit internal preset input preset input bcd data inputs select storage input 1 select storage input 2 lsd+1 lsd+2 lsd+3 lsd+4 scan oscillator input msd a d * optional choice-lamp test (specify ls7056) digit select outputs inhibit internal reset (pin 5) a high input prevents the automatic reset of the counter to zero when in the up mode and when the counter reaches the number in the main signal store. preset (pin 7) a high level presets the bcd counter to the number set in the preset store. a low input allows counter operation. inhibit internal preset (pin 6) a high input prevents the automatic preset of the counter to the number set in preset store when in the down mode and the counter reaches zero. select storage of data inputs (pins 15, 16) two inputs which allow bcd data to be stored in either the preset, presignal or main signal store. the proper method for loading the stores is depicted in figure 4. pin 15 pin16 storage 0 0 no selection 1 0 presignal 0 1 main signal 1 1 preset u l a3800 *
lamp test (ls7056 only) (pin 31) a high input will cause the seven segment outputs to provide all 8's to a display (bcd outputs are not affected). zero detect output (pin 38) a high output occurs whenever the counter is at zero. in the auto- matic mode and with the up/down input in the down mode, the counter presets to the number in the preset store and the zero detect output is typically a 1.5 ? pulse. in the manual mode (inhibit internal preset is high), the counter remains at zero until a preset or a count input pulse is applied. digit select outputs (pins 17, 18, 19, 20, 21, 22) six positive outputs for digit identification. the outputs occur sequentially going from msd to lsd and can be applied directly to thumbwheel switches. they must be buffered before being applied to the seven segment displays either by a cmos or transistor buf- fer as shown in figure 5. figure 3 indicates the timing relationship between the digit select outputs and the bcd data outputs. seven segment outputs (pins 24, 25, 26, 27, 28, 29, 30) capable of sourcing current into the base of a common emitter npn transistor for interfacing to a seven segment display. small displays needing an average current of 0.5 ma can be interfaced to the circuit without external transistors. a typcial example of a 12v circuit is shown in figure 5. bcd outputs (pins 32, 33, 34, 35) four outputs corresponding to the bcd data stored in the latches. the outputs can be demultiplexed using the circuitry shown in fig- ure 4. as can be seen from the timing diagram of figure 3, the bcd data output and seven segment outputs are completely stable during the positive digit select outputs. power-on-reset an external rc network applied to the reset input as shown in fig- ure 4 can be used to reset the counter to zero upon application of power. the preset input must be held low at this time. the rc time constant should be larger than the power supply rise time. for ex- ample, a 100k w resistor and a 0.1? capacitor could be used if the power supply rise time was 5 ms. power supplies the circuit operates over the range of +4.75v to +15v. at +4.75v, the inputs are ttl and cmos compatible (external pull-up re- sistors must be provided on any input which does not pull up to vss) when using ttl inputs. at +15v, inputs are cmos compat- ible. all outputs are cmos compatible from +4.75v to +15v. bcd data inputs (pins 10, 11, 12, 13) four inputs containing bcd data which are applied to either the preset, presignal or main signal stores one decade at a time. this data can be provided by a set of thumbwheel switches which are driven by the digit select outputs. referring to figure 4, the bcd data inputs have built in pull down resistors (typically 51k ohms). divide control (pin 2, pin 3) two inputs for selection to divide the count input by either 5, 6 or 1. pin 2 pin 3 0 0 divide by 5 1 0 divide by 6 1 1 divide by 1 main signal output (pin 9) an internal comparator provides a high level output when the num- ber set into the main signal store is reached by the counter. in the automatic mode and with the up/down control in the up position, the counter is reset to zero and the main signal output is typically a 2.5 ? wide pulse. in the manual mode (inhibit internal reset is high) the output remains high until the next count input or a reset is ap- plied. presignal output (pin 36) the presignal comparator provides a high level output when the number set into the presignal storage is reached. the output re- mains high until the next count input or a reset or preset is applied. scan clock input (pin 23) a dc to 150khz oscillator input port for driving the internal scan counter is provided. up to 150khz may be used when de- multiplexilng bcd data using the digit select outputs. the fre- quency of the oscillator is determined by an external rc network as shown in figure 4. table 1 indicates several frequencies and their associated rc networks. the oscillator can be overridden using an external driver. table 2 indicates the external drive requriements. when displaying, leading zero blanking and unblanking on lsd is provided. blanking override (LS7055 only) (pin 31) on circuits with this option, unblanking can be made to occur on any digit by connecting that digit select output to the unblanking in- put. since the input has an internal pull down resistor, it can be left floating when not in use. table 1 typical resistor/capacitor values for the scan oscillator resistor capacitor typical frequency 12k w 1000pf 100khz 100k w 1000pf 10khz 1.0m w 1000pf 1khz table 2 driver requirements for overriding scan oscillator input power supply (v) sink current source current 5 1.0ma 0 10 4.5ma 0 15 10.0ma 0 7055-012703-2
maximum ratings parameter symbol value units storage temperature tstg -65 to +150 ? operating temperature t a -25 to +70 ? voltage (any pin to vss) vmax -30 to +0.5 v dc electrical characteristics (v dd = v gg = 0v, vss = +4.75 to +15v, -25? t a +70? unless otherwise specified.) parameter sym min max units quescent supply current - - - - (all input pins tied to vss) (all output pins left open) vss = 4.75v i dd - 20 ma vss = 15v i dd - 25 ma input capacitance all inputs cin - 10 pf hysteresis on count input 30%(vss - v dd ) - v noise immunity all other inputs v nl 30%(vss - v dd ) - v v nh 30%(vss - v dd ) - v output levels all outputs v ol - 0.5 v (all output pins left open) v oh vss - 1 - v 7 segment output current source current vss = 4.75v, v out = 0.7v, 70? i seg 0.3 - ma vss = 4.75v, v out = 0.7v, 25? i seg 0.4 - ma vss = 10v, v out = 7v, 25? i seg 2.0 - ma vss = 15v, v out = 13v, 70? i seg 3.0 - ma note: limit segment source current to 4.5ma max. sink current (v out = 0.4v) vss = 4.75v, 25? i seg -21 - ? vss = 10v, 25? i seg -17 - ? vss = 15v, 25? i seg -15 - ? vss = 15v, 70? i seg -10 - ? bcd, zero detect, mainsignal and presignal output current source current vss = 4.75v, v out = 4.5v, 70? io h 0.10 - ma vss = 4.75v, v out = 4.5v, 25? io h 0.13 - ma vss = 10v, v out = 9.0v, 25? io h 0.7 - ma vss = 15v, v out = 13v, 25? io h 2.5 - ma note: limit segment source current to 4.5ma max. sink current (v out = 0.4v) vss = 4.75v, 25? io l -7.5 - ? vss = 10v, 25? io l -6.0 - ? vss = 15v, 25? io l -5.5 - ? vss = 15v, 70? io l -4.0 - ? digit select output current source current vss = 4.75v, v out = 4.5v, 70? io h 0.28 - ma vss = 4.75v, v out = 4.5v, 25? io h 0.35 - ma vss = 10v, v out = 9v, 25? io h 2.0 - ma vss = 15v, v out = 13.5v, 70? io h 7.0 - ma note: limit digit select current to 10ma. sink current (v out = 0.4v) vss = 4.75v, 25? io l -15 - ? vss = 10v, 25? io l -12 - ? vss = 15v, 25? io l -11 - ? vss = 15v, 70? io l - ? dynamic electrical characteristics (v dd = v gg = 0v, vss = +4.75 to +15v, -25? t a +70? unless otherwise specified.) parameter sym min max units count input frequency vss = 4.75v fc dc 250 khz vss = 10v fc dc 175 khz vss = 15v fc dc 125 khz pulse width vss = 4.75v tcw 2 - ? vss = 10v tcw 2.8 - ? vss = 15v tcw 4 - ? rise time tcr - ? fall time tcf - ? scan input frequency fsc dc 100 khz divide control set-up time tds 2 - ? hold time tdh 8 - ? reset pulse width ** trpw 2 - ? reset set up time trs 0 - ? hold time trh 6 - ? inhibit internal reset set up time tis 0 - ? hold time * tirh 3 - ? preset pulse width ** tppw 2 - ? preset enable set up time tips 0 - ? hold time * tiph 6 - ? data transfer pulse width ** tdtw 2 - ? data transfer set up time tdts 0 - ? hold time tdth 6 - ? up/down set up time tuds 0 - ? hold time tud 10 - ? count inhibit set up time tcs 2 - ? hold time tch 10 - ? data outputs (c l = 10pf) rise time tdr - 1.0 ? fall time vss = 4.75v tdf - 2.0 ? vss = 10v tdf - 3.0 ? vss = 15v tdf - 4.0 ? digit select outputs guard band time within 7 segment & bcd outputs tgb 0.5 - ? see figure 3 main signal, presignal, zero detect outputs delay with respect to positive edge of count input tdo - 3 ? set-up and hold times are defined with respect to positive edge of count input except where indicated by asterisks. * indicates a hold time which must last for at least one whole count cycle plus 5? past the next positive edge of count input. ** reset, preset and data transfer pulse width is as specified except if applied when a count input is going positive. in that case the set-up and hold times govern. 7055-012703-3 the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
counter at mainsignal value counter at presignal value counter at zero mainsignal output presignal output zero detect output manual reset figure 2. automatic or manual operation in up mode automatic reset counter at preset number counter at presignal value counter at zero mainsignal output presignal output zero detect output manual preset figure 3. automatic or manual operation in down mode counter at mainsignal number automatic preset t udh t udh t ds t dh t cs t ch t rpw t ppw t do t do t gb t gb t dth
7055-012703-5 6 digit select output 4 bcd data outputs mainsignal output presignal output zero detect output reset input inhibit internal reset input inhibit internal preset input preset enable input up/down input 7 segment outputs divide control inputs count input count inhibit load command vss blanking override or lamp test data transfer input vss 100k (typical) le latch enable le le le le vss vss v dd thumbwheel switches figure 5. system interconnection diagram bcd data inputs buffer buffer led display 51k v dd select storage inputs LS7055/ls7056 scan input 1? (typical) 10k ext. latch
7055-012703-6 thumbwheel switches LS7055/ls7056 7 segment output 2.5k w (typical) 10k w (typical) digital select outputs figure 6. driving a small led display (typically 1/8") at 12v power supply. the 2.7k w resistors provide approximately 3 ma segment drive. preset store bcd to 7 segment decoder multiplexer blanking generator latch mainsignal store mainsignal comparator presignal store presignal comparator zero detector 6 decade up/down counter counter reset counter preset up/down control blanking override input lamp test input (optional-ls7056) 7 segment outputs bcd outputs digit select outputs digit select generator scan oscillator data transfer input decoder storage select 1 storage select 2 divide control input 1 divide control input 2 bcd data inputs count input count inhibit input +1, 5, 6 select mainsignal store presignal store preset store count 15 16 1 40 3 2 31 mainsignal output presignal output zero detect output inhibit internal preset input reset input preset enable input up/down input inhibit internal reset input 9 36 38 5 4 6 7 39 figure 7. LS7055/ls7056 block diagram scan input clock 10 11 12 13 b1 b4 b2 b8 17 18 19 20 21 22 32 33 34 35 24 25 26 27 28 29 30
|
