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SM803020 flexible ultra - low jitter clock synthesizer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com july 22, 2013 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 general description the SM803020 is a dual - pll clock generator that achieves ultra - low , 74.2 fs _rms output jitter at 156.25mhz output frequency . it accepts a crystal input or a reference input. each output channel is individually configurable to a differential pecl, lvds, hcsl , or cmos output logic level. pecl is selected by default, but can be overridden through spi. it is packaged in a dual - row 84 - pin 7 mm x 7mm pac kage. datasheets and support documentation are available on micrels web site at : www.micrel.com . typical application features ? generates twelve 156.25mhz outputs ? independently programmable output logic: ? output logic: lvpecl (default) , lvds, hcsl, lvcmos ? 74.2fs jitter at 156.25mhz (1.875mhz to 20mhz) ? selectable inputs require 39.0625mhz input frequency ? xtal (default) ? differential or single - ended reference clock ( spi selectable) ? 2.5v or 3.3v operating power supp ly ? separate output power supplies: ? different banks can be at different levels ? industrial temperature range ( C 40 c to +85 c) ? green, rohs, and pfos compliant ? available in 84 - pin 7mm 7mm qfn package applications ? 1/10/40/100 gigabit ethernet
micrel, inc. SM803020 july 22, 2013 2 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 ordering information part number marking shipping ambient temp erature range package sm80302 0 umy 80302 0 tray C 40 c to +85c 84- pin qfn sm80302 0 umyr 80302 0 tape and reel C 40 c to +85c 84- pin qfn pin configuration 84- pin qfn 7mm x 7mm
micrel, inc. SM803020 july 22, 2013 3 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin type pin level pin function a19, a20 a17, a18 a15, a16 a13, a14 a10, a11 a8, a9 a36, a37 a38, a39 a40, a41 a42, a43 a1, a2 a3, a4 qa1, /qa1 qa2, /qa2 qa3, /qa3 qb1, /qb1 qb2, /qb2 qb3, /qb3 qc1, /qc1 qc2, /qc2 qc3, /qc3 qd1, /qd1 qd2, /qd2 qd3, /qd3 o, (dif/se) lvpecl differential lvpecl (default) , hcsl, or lvds clock output s or phase - adjustable differential or single- ended cmos outputs b12 b11 b40 a44 fsel_a fsel_b fsel_c fsel_d i, (se) lvcmos frequency select, 75k ? pull -up 1 = primary selection 0 = secondary selection a21, a35 vdd pwr power supply b18 b17 vddoa1 vddoa2 vddoa3 pwr power supply for outputs qa1 3 b8 b9 vddob1 vddob2 vddob3 pwr power supply for outputs qb1 3 b33 b37 vddoc1 vddoc2 vddoc3 pwr power supply for outputs qc1 3 b2 b3 vddod1 vddod2 vddod3 pwr power supply for outputs qd1 3 b20 vddap1 pwr power supply for pll1 b31 vddap2 pwr power supply for pll2 a27, b25 vddi1 pwr 3.3v only power supply for vcxo, reference1, feedback 1 a28 vddi2 pwr power supply for xo, reference2, feedback 2 b30 b36 vss (exposed pad) pwr core power supply ground. the exposed pad must be connected to the vss ground plane. b15 b16 vssoa1 vssoa2 vssoa3 pwr power supply ground for outputs qa1 3 b10 b13 vssob1 vssob2 vssob3 pwr power supply ground for outputs qb1 3
micrel, inc. SM803020 july 22, 2013 4 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 pin number pin name pin type pin level pin function b34 b35 vssoc1 vssoc2 vssoc3 pwr power supply ground for outputs qc1 ? 3 b4 b39 vssod1 vssod2 vssod3 pwr power supply ground for outputs qd1 ? 3 a34 vssap1 pwr power supply ground for pll1 a22 vssap2 pwr power supply ground for pll2 a23 vssi1 pwr power supply ground for vcxo, reference1, feedback 1 a31 vssi2 pwr power supply ground for xo, reference2, feedback 2 b14 oea1/2/3 i, (se) lvcmos output enable, outputs q0 C q3 disable to tri - state, 0 = disabled, 1 = enabled, 75k sxoo - up a12 oeb1/2/3 i, (se) lvcmos output enable, outputs q4 C q7 disable to tri - state, 0 = disabled, 1 = enabled, 75k sxoo - up b38 oec1/2/3 i, (se) lvcmos output enable, outputs q4 C q7 disable to tri - state, 0 = disabled, 1 = enabled, 75 k sxoo - up b1 oed1/2/3 i, (se) lvcmos output enable, outputs q4 C q7 disable to tri - state, 0 = disabled, 1 = enabled, 75 k sxoo - up a5, a6, a7, b5, b6, b7 test - - factory test pins . d o not connect anything to these pins. a32 a33 refout_p, refout_n i, (diff/se) lvpecl lvds hcsl lvcmos reference clock output b21 b22 ref1_p, ref1_n i, (diff/se) lvpecl lvds hcsl lvcmos reference clock input 1 b28 b29 ref2_p, ref2_n i, (diff/se) lvpecl lvds hcsl lvcmos reference clock input2 b23 b24 fb1_p, fb1_n i, (diff/se) lvpecl lvds hcsl lvcmos feedback clock input1 b26 b27 fb2_p, fb2_n i, (diff/se) lvpecl lvds hcsl lvcmos feedback clock input2 a29 xtal_in i, (se) 12pf crystal crystal reference input, no load caps needed (see figure 9 . ) a30 xtal_out o, (se) 12pf crystal crystal reference output, no load caps needed (see figure 9 . )
micrel, inc. SM803020 july 22, 2013 5 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 pin number pin name pin type pin level pin function b19, b32 nc a25 vcxo_out o, se vcxo out put, 8 to 10p f , programmable a26 vcxo_in i, se vcxo in put, 8 to 10p f , programmable a24 vc i control v oltage for vcxo, p ositive s lope truth tables pll_bypass xtal_sel oea oeb oec oed i nput o utput 0 ? 1 1 1 1 ? pll 1 ? 1 1 1 1 ? xtal/ref_in ? 0 1 1 1 1 ref_in ? ? 1 1 1 1 1 xtal ? ? ? 0 1 1 1 ? qa tri - state ? ? 1 0 1 1 ? qb tri - state ? ? 1 1 0 1 ? qc tri - state ? ? 1 1 1 0 ? qd tri - state fsel output frequency (mhz) 1 primary 0 secondary output l ogic programming available output logic types are lvpecl (default) , lvds, hcsl and lvcmos. each output can be programmed individually to any of the four logic types through spi . unused outputs can be disabled to high impedance. all logic types are differential except lvcmos. lvcmos signals are single ended coming out of the qx pins. during lvcm os operation the /qx pins are disabled.
micrel, inc. SM803020 july 22, 2013 6 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings ( 2 ) supply voltage ( v dd, v dda , v ddi , v ddo ) ........................ + 4.6 v input voltage (v in ) ........................................ ? 0.5 v to +4.6v lead temperature (soldering, 20 s) ............................ 260c storage temperature (ts ) ......................... ? 65c to +150 c esd machine model .................................................... 200 v esd human body model ........................................... 2000v operating ratings ( 3 ) supply v oltage ( v dd, v ddo ) ................... + 2.375v to +3.465 v ambient operating temperature (t a ) ......... C 40c to +85c maximum allowable junction temp .......................... 12 5c junction thermal resistance 84- pin qfn 7mm x 7mm ja still air ................. 24 c/w electrical characteristics typical values ar e t a = 25c , min/max across C 40c t a +85c, unless otherwise noted. symbo l parameter condition min . typ . max . units v dd , v ddo supply v oltage 2.5v operation 2.375 2.5 2.625 v 3.3v operation 3.135 3.3 3.465 v ddi _ 1 analog supply voltage note 3 3.135 3.3 3.465 v v ddi _ 2 analog supply voltage note 3 2.375 3.465 v v dda pll core voltage 2.375 3.465 v i dda pll core current consumption per active pll 60 ma i dd current consumption 8 ma i ddi_1 input 1 supply c urrent xo i nput ( 3 ) 0 ma ref i nput 2 ma i ddi_2 input 2 supply c urrent xo i nput ( 3 ) 4 ma ref i nput 2 ma lvpecl dc electrical characteristics v ddcore = v dd = v dd0 = 3.3v 5% or 2.5v 5%, t a = C 40 c to +85 c, unless otherwise noted. r l = 50 to v ddo ? 2v symbol parameter condition min. typ. max. units v oh output high voltage wr9 ddo ? 2v v ddo C 1.35 v ddo C 1.01 v ddo C 0.8 v v ol output low voltage wr9 ddo ? 2v v ddo C 2 v ddo C 1.78 v ddo C 1.6 v v swing peak -to - peak output voltage figure 2 0.65 0.77 0.95 v lvds dc electrical characteristics v ddcore = v dd = v dd0 = 3.3v 5% or 2.5v 5%, t a = C 40 c to +85 c, unless otherwise noted. r l = 100 between q and /q. symbol parameter condition min. typ. max. units v od differential output voltage figure 2 245 350 454 mv v cm common mode voltage 1.125 1.2 1.375 v v oh output high voltage 1.248 1.375 1.602 v v ol output low voltage 0.898 1.025 1.252 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. exposure to absolute maximum rating co nditions for extend ed periods may affect device reliability. 2. the datasheet limits are not guaranteed if the device exceeds the operating ratings. 3. crystal input is powered from v ddi_2 analog supply voltage source.
micrel, inc. SM803020 july 22, 2013 7 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 hcsl dc electrical characteristics v ddcore = v dd = v dd0 = 3.3 v 5% or 2.5v 5%, t a = C 40 c to +85 c, unless otherwise noted. r l = 50 to v ss . symbol parameter condition min. typ. max. units v oh output high voltage 600 7 00 850 mv v ol output low voltage 150 0 27 mv v cross crossing point voltage 0. 350 v ref_in dc electrical characteristics v dd = 3.3v 5% or 2.5v 5%, t a = C 40 c to +85 c. symbol parameter condition min. typ. max. units v cmr input common mode voltage 0.3 v dd 0.3 v v swing input voltage swing peak to peak, each side of the diff input 0.2 v pp crystal characteristics parameter condition min. typ. max. units mode of oscillation 12pf load typica l fundamental, parallel resonant frequency 39.0625 mhz equivalent series resistance (esr) 6 0 load capacitance , c l 12 pf shunt capacitor, c0 2 4 pf correlation drive level 10 1 00 w
micrel, inc. SM803020 july 22, 2013 8 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 ac electrical characteristics v dd = v ddo1/2 = 3.3v 5% or 2.5v 5% v dd = 3.3v 5%, v ddo1/2 = 3.3v 5% or 2.5v 5% t a = ? 40 c to +85c symbol parameter condition min. typ. max. units f in input frequency 39.0625 mhz f out output frequency lvpecl, lvds, hcsl , lvcmos 156.25 mhz t r /t f output rise/fall time 20% C 80% lvpecl output 85 135 350 ps lvds output 85 140 300 ps hcsl output 175 340 700 ps lvcmos output 100 200 400 ps odc output duty cycle 45 50 55 % tpd input to output propagation delay zdb mode ? 100 100 ps synthesizer/bypass mode 4 ns t skew output -to - output skew ( 4 ) note 5 , same output bank 50 ps t lock pll lock time 5 20 m s t jit (? ) rms phase jitter ( 6 ) integration range (12khz to 20mhz) 180 fs notes: 4. defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points. 5. output - to - output skew is only defined for outputs in the same pll bank [a:b, c:d] with the same output type setting. 6. all phase noise measurements were taken with an agilent 5052b phase noise system.
micrel, inc. SM803020 july 22, 2013 9 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 phase noise performance 156.25 mhz, integration range 1.875mhz to 20mhz: 74.2fs rms 156.25mhz, inte gration range 12k hz to 20mhz: 182.4 fs rms
micrel, inc. SM803020 july 22, 2013 10 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 application information input reference when operating with a crystal input reference, do not apply a switching signal to a ref_in . crystal layout keep the layers under the crystal as open as possible and do not place switching signals or noisy supplies under the crystal. crystal load capacitanc e is built inside the die so no external capacitance is needed. see the selecting a quartz c rystal for the clockworks flex i family of precision synthesizers application note for more details. contact micrels hbw applications group if you need help select ing a suitable crystal for your application at: hbwhelp@micrel.com . power supply filtering recommendations figure 1 . recommended power supply filtering ? use the power supply filtering shown in figure 1 for vddap1, vddap2, vddi1 and vddi2. ? connect the vddo and vdd pins directly to the vdd p ower p lane. ? connect all vss pins directly to the g round p ower p lane. figure 2 . duty cycle timing figure 3 . all outputs rise/fall time
micrel, inc. SM803020 july 22, 2013 11 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 figure 4 . rms phase/ noise jitter figure 5 . lvpe cl output load and test circuit figure 6 . hcsl output load and test circuit figure 7 . lvds output load and test circuit figure 8 . lvcmos output load and test circuit
micrel, inc. SM803020 july 22, 2013 12 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 figure 9 . crystal input interface ac - coupled signal interfacing pecl thevenin equivalent conventional termination micrel any -in internal termination lvds lvds: v source = 1.25v micrel any - in internal termination
micrel, inc. SM803020 july 22, 2013 13 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 dc- coupled signal interfacing pecl parallel termination (thevenin equivalent) notes: 7. power - saving alternative to thevenin termination. 8. place termination resistors as close to destination inputs as possible. 9. r b resistor set the dc bias voltage, equal to v t . 10. for 2.5v systems, r b = 19 . for 3.3v systems, r b = 50 . parallel termination (3 - resistor) y - termination lvds conventional method micrel any - in internal termination
micrel, inc. SM803020 july 22, 2013 14 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 package information ( 11) 84- pin qfn 7mm x 7mm note: 11. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474- 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warr anty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intende d for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, dev ices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 13 micrel, incorporated.

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