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HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 1 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description the HFC0100 is a peak current mode controller with green mode operation. its high efficiency feature over the entire line and load range meets the stringent world-wide energy efficiency requirements. the HFC0100 integrated with a high voltage current source, its valley detector ensures minimum drain-source voltage switching (quasi-resonant operation). when the output power falls below a given level, the controller enters the burst mode. the HFC0100 features variable protections like thermal shutdown (tsd), vcc under voltage lockout (uvlo), over load protection (olp), over voltage protection (ovp). the HFC0100 is available in the 8-pin soic8 package. features ? universal main input voltage (85~265vac) ? quasi-resonant operation ? valley switching for high efficiency and emi ? active burst mode for low standby power consumption ? internal high voltage current source ? high level of integration, allows a very low number external component count ? maximum frequency limited ? internal soft start ? internal 250ns leading edge blanking ? thermal shutdown (auto restart with hysteresis) ? vcc under voltage lockout with hysteresis (uvlo) ? over voltage protection ? over load protection. applications ? battery charger: cellular phone, digital camera, video camera, electrical shaver, emergency lighting system, etc ? standby power supply: crt-tv, projection- tv, lcd-tv, pdp-tv, desk top pc, audio system, etc ? smps: inc jet printer, dvd player/recorder, vcr, cd player, set top box, air conditioner, refrigerator, washing machine, dish washer, adapter for nb, etc for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc.
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 2 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical application rtn * * * t1 vsd 1 2 3 45 6 7 8 cs hv n/c drive gnd fb vcc + +
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 3 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) HFC0100hs soic8 hfc100 -40 c to +125 c *for tape & reel, add suffix ?z (e.g. HFC0100hs?z); for rohs compliant packaging, add suffix ?lf (e.g. HFC0100hs?lf?z) package reference absolute maximum ratings (1) hv break down voltage .............. -0.7v to 700v vcc, drv to gnd ...........................-0.3v to 22v fb, cs, vsd to gnd ........................-0.3v to 7v continuous power dissipation?(t a = +25c) (2) ??????????????????....1.3w junction temperature ...............................150 c thermal shut down ..................................150 c thermal shut down hysteresis ..................50 c lead temperature ....................................260 c storage temperature .............. -60c to +150 c esd capability human body model (all pins except hv) ............................................... 2.0kv esd capability machine model ................. 200v recommended operation conditions (3) operating vcc range ...........................8v to 20v maximum junction temp. (t j ) ............. +125c thermal resistance (4) ja jc soic8 .....................................96 ...... 45 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. vsd vcc nc hv fb gnd cs drive 1 2 3 4 8 7 6 5 top view
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 4 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. electrical characterics for typical value t j =25 parameter symbol conditions min typ max unit start-up current source (pin hv) charging current from pin hv i charge vcc=6v;v hv =400v 1.4 2 2.6 ma leakage current from pin hv i leak with auxiliary supply; v hv =400v, vcc=13v -- 20 -- a break down voltage v br 700 -- -- v supply voltage management (pin vcc) vcc upper level at which the internal high voltage current source stops v cch 10.6 11.8 13 v vcc lower level at which the internal high voltage current source triggers v ccl 7.2 8 8.8 v vcc re-charge level at which the protection occurs vccp -- 5.5 -- v internal ic consumption, 1nf load on drive pin, icc1 fs=100khz, vcc=12v -- 2.0 -- ma internal ic consumption, latch off phase, icc2 vcc=6v -- 450 -- a feedback management (pin fb) internal pull up resistor r fb -- 10 -- k ? internal pull up voltage vup -- 4.5 -- v fb pin to current limit division ratio i div -- 3 -- -- internal soft-start time tss -- 2.4 -- ms fb decreasing level at which the controller enter the burst mode v burl -- 0.5 -- v fb increasing level at which the controller leave the burst mode v burh -- 0.7 -- v over load set point v olp -- 3.7 -- v valley switching management (pin vsd) valley switching threshold voltage v vsd 40 55 70 mv valley switching hysteresis v hys -- 10 -- mv v vsdh high state; ipin2=3.0ma 7 7.5 8 pin vsd clamp voltage v vsdl low state; ipin2=-2.0ma -0.8 -0.65 -0.5 v valley switching propagation delay t vsd pull down from 2v to -100mv 120 160 200 ns minimum off time t min 6.6 7.8 9 s re-start time after last valley detect transition t restart -- 4.6 -- s ovp sampling delay t ovps -- 3.5 -- s pin vsd ovp reference level v ovp -- 6 -- v internal impedance rint -- 24 -- k ? current sampling management (pin cs) leading edge blanking t leb -- 250 -- ns driving signal (pin drive) sourcing resistor r h -- 17 -- ? sinking resistor r l -- 7 -- ?
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 5 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. pin functions pin # name description 1 vsd input from the auxiliary flyback signal, it ensures discontinuous operation and valley switching. it also offers a fixed ovp detection. 2 vcc supply voltage pin. this pin is connected to an external bulk capacitor of typically 22uf and a ceramic capacitor of typically 0.1uf. 3 n/c this pin ensures adequate creepage distance. 4 hv input for the start up current unit. 5 drive output of the driving signal. 6 cs input of t he current sense. 7 gnd ground. 8 fb the pin sets the peak current limit, by conne cting an optocoupler to this pin. a feedback voltage of 3.7v will trigger an over load protec tion, and a feedback voltage of 0.5v will trigger a burst mode operation.
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 6 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. typical performance characteristics t a =25 400 500 600 700 800 900 1000 1100 10 11 12 13 14 15 16 17 18 v cc (v) v cc (v) i cc 1 (ua) f s =60khz f s =60khz f s =100khz f s =100khz ic consumption vs vcc (no output load) 1000 1400 1800 2200 2600 3000 3400 10 11 12 13 14 15 16 17 18 i cc 1 (ua) v cch (v) v ccl (v) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) 1 1.5 2 2.5 3 -40 -20 0 25 50 85 105 125 icharge (ma) charging current from pin hv (vcc=6v, vhv=400v) vs temperature ic consumption vs vcc (1nf output load) 11 11.2 11.4 11.6 11.8 12 -40 -20 0 25 50 85 105 125 vcc upper level at which the internal high voltage current source stops vs temperature 7.5 7.7 7.9 8.1 8.3 8.5 -40 -20 0 25 50 85 105 125 vcc lower level at which the internal high voltage current source triggers vs temperature 8 9 10 11 12 -40 -20 0 25 50 85 105 125 pin fb internal pull up resistor vs temperature temperature ( o c) temperature ( o c) temperature ( o c) t min (us) v vsd (mv) v olp (v) minimum off time vs temperature 7 7.5 8 8.5 9 -40 -20 0 25 50 85 105 125 valley switching threshold voltage vs temperature 30 40 50 60 70 80 -40 -20 0 25 50 85 105 125 over load set point vs temperature 3.4 3.6 3.8 4 -40 -20 0 25 50 85 105 125
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 7 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics (continues) t a =25 600 650 700 750 800 -40 -20 0 25 50 85 105 125 temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) v burh(mv) v burh(mv) v ref (v) t sample (us) fb increasing level at which the controller leave the burst mode vs temperature fb decreasing level at which the controller enter the burst mode vs temperature 400 450 500 550 600 -40 -20 0 25 50 85 105 125 0 5 10 15 20 -40 -20 0 25 50 85 105 125 sinking resistor vs temperature sourcing resistor vs temperature 10 15 20 25 30 -40 -20 0 25 50 85 105 125 pin vsd internal impedance vs temperature 20 22 24 26 28 30 -40 -20 0 25 50 85 105 125 pin vsd ovp reference level vs temperature 5.8 5.9 6 6.1 6.2 -40 -20 0 25 50 85 105 125 ovp sampling delay vs temperature 3 3.2 3.4 3.6 3.8 4 -40 -20 0 25 50 85 105 125
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 8 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. block diagrame d r i v e ( 5 ) c s ( 6 ) f b ( 8 ) n . c . ( 3 ) g n d ( 7 ) v c c ( 2 ) h v ( 4 ) v s d ( 1 ) s t a r t u p u n i t v a l l e y d e t e c t o r p r o t e c t i o n u n i t p e a k c u r r e n t l i m i t a t i o n p o w e r m a n a g e m e n t b u r s t m o d e c o n t r o l d r i v i n g s i g n a l m a n a g m e n t figure 1? block diagram
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 9 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. operation the HFC0100 incorporates all the necessary features needed to a reliable switch mode power supply. its valley detector ensures minimum drain-source voltage switching (quasi-resonant operation). when the output power falls below a given level, the regulator enters the burst mode. an internal minimum off time limiter prevents the free running frequency to exceed 150khz. start-up initially, the ic is self supplying from the internal high voltage current source unit which drawn from the hv pin. the ic starts switching and the internal high voltage current source unit is stopped as soon as the voltage on pin vcc reaches the threshold v cch ?11.8v. before the supply is taken over by the auxiliary winding of the transformer, the vcc capacitor supplies HFC0100 to maintain vcc. quasi-resonant operation the HFC0100 operates in discontinuous conduction mode (dcm). the valley detector ensures minimum drain-source voltage switching (quasi-resonant operation) as a result, there are virtually no primary switch turn on losses and no secondary diode recovery losses. it ensures the reduction of the emi noise. figure2 shows the valley detector unit. when the voltage: aux ds in pri vsd n 24k (v v )x x 55mv n24kr ?< + v ds ?drain source voltage of the primary fet v in ?input voltage n aux ?auxiliary winding turns of the transformer n pri ?primary winding turns of the transformer the valley detector sends out a valley signal to turn on the primary fet. figure3 shows a typical drain source voltage waveform with valley switching. figure 2?valley detector v ds 100v/div 4us/div figure 3?valley switching to ensure the switching frequency below the en55022 start limit---150khz, HFC0100 employs an internal minimum off time limiter---7.8 s, shows as figure 4. v ds 100v/div 2us/div figure 4?minimum off time limit valley switching t off 7.8us
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 10 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. v cc under-voltage lock-out when the vcc below the uvlo threshold-8v, the HFC0100 stops switching and the internal high voltage current source unit re-starts, the vcc external bulk capacitor is re-charged by it. figure 5 shows the typical waveform with vcc under voltage lock out. v cch =11.8v v ccl =8v v cc internal current source driving signal on off the auxiliary winding take over figure 5?vcc under-voltage lock out over-voltage protection (ovp) the positive plateau of auxiliary winding voltage is proportional to the output voltage, the ovp use the auxiliary winding voltage instead of directly monitoring the output voltage. the figure 6 shows the ovp sample unit. if the voltage: 6v r 24k ? 24k ? n n v vsd sec aux o > + v o ?output voltage n aux ?auxiliary winding turns of the transformer n sec ?secondary winding turns of the transformer the ovp circuit is triggered, and the HFC0100 stops the switching cycle and goes into latched fault condition. the controller stays fully latched in this position until the vcc is decreased down to 3v, e.g. when the user unplugs the power supply from the main supply and re-plugs it. figure 6?ovp sample unit to avoid the mis-trigger due to the oscillation of the leakage inductance and the parasitic capacitance, the ovp sampling has a t ovps blanking, typical 3.5 s, shows as figure 7. v vsd 0v t ovps sampling here figure 7 over load protection (olp) the maximum output power is limited by the maximum switching frequency and maximum primary peak current. if the output consumes more than the maximum output power, the output voltage is drawn below the set point, this reduces the current through the optocoupler led, which also reduces the transistor current, thus increases the fb voltage. by continuously monitoring the pin fb voltage, when the feedback voltage exceeds the threshold v olp ?3.7v, it shuts off the switching cycle. the HFC0100 enters a safe low power operation that prevents from any lethal thermal or stress damage. as soon as the default disappears, the power supply resumes operation. during the start up or load transient, the fb voltage will be high enough temporarily to mis- trigger the olp, to prevent this undesired protection, olp circuit is designed to be triggered after vcc is decreased below 8.5v.
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 11 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. burst operation to minimize the power dissipation in no load or light load, the HFC0100 enters the burst mode operation. as the load decreases, the fb voltage decreases,, the HFC0100 stops the switching cycle when the fb voltage drops below the threshold v burl ?0.5v. and the output voltage starts to drop at a rate dependent on the load. this causes the fb voltage to rise again. once the fb voltage exceeds the threshold v burh ? 0.7v, switching resumes. the fb voltage then falls and rises repeatedly. the burst mode operation alternately enables and disables switching cycle of the mosfet thereby reducing switching loss in the no load or light load conditions. figure 8 shows the typical fb and drive waveform during the burst mode. v drive 5v/div v fb 200mv/div 40us/div figure 8?burst mode thermal shutdown (tsd) to prevents from any lethal thermal damage. the HFC0100 shuts down switching cycle when the inner temperature exceeds 150degc. as soon as the inner temperature drops below 100degc, the power supply resumes operation. soft-start to reduce the stress on primary mosfet and secondary diode during start up, to smoothly establish the output voltage, the HFC0100 has an internal soft-start circuit that increases the current comparator inverting input voltage, together with the mosfet current, slowly after it starts up. the pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. current limit setting the switch current is sensed by the resistor series between the source of the fet and the ground. and the current limit is determined by the fb signal, 3 v i v v fb div fb limit = = . to limit the maximum output power, the current limit is clamped at 1v when v fb is bigger than 3.3v. leading edge blanking in order to avoid the premature termination of the switching pulse due to the parasitic capacitance, an internal leading edge blanking (leb) unit is employed between the cs pin and the current comparator input. during the blanking time, the path, cs pin to the current comparator input, is blocked. figure 9 shows the leading edge blanking. t leb =250 ns v limit t figure 9?leading edge blanking over power compensation in the case of current sensing, shows as figure 10, the turn off of the fet is delayed due to the propagation delay of the control circuit, the delay time is the inherent characteristic of the control circuit, so t delay can be seen fixed. this delay will cause an overshoot of the peak current. i2 is bigger than i1 due to the bigger rising ratio(the higher input voltage, the bigger rising ratio). v burl :0.5v v burh :0.7v
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 12 9/23/2011 mps proprietary information. pa tent protected. unauthorized phot ocopy and duplication prohibited. ? 2011 mps. all rights reserved. the propagation delay is done by means of the feedforward resistor, shown as figure 11. through this method, adding one offset voltage at cs pin (the higher input voltage, the bigger offset voltage.). t delay t delay t delay t delay i limit i limit1 i lim it t i1 i2 i limit2 figure 10?propagation delay of the current limit cs 6 v ref HFC0100 current comparator r feedforward r sense r1 c1 q1 t1 v_bulk figure 11?over power compensation figure 12 shows the HFC0100 control flow chart. figure 13 shows the HFC0100 evolution of the signals in presence of faults
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 13 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. start vcc>11.8v vcc<8.5v? and olp=logic high internal high voltage current source on toff<7.8us y n soft start monitor v fb monitor vcc v fb >3.7v 0.5v0 . 7v y n n y olp=logic high y thermal monitor y vcc decrease to 5.5v shut down internal high voltage current source latch off the switching pulse n continuous fault monitor vcc<8v y n ovp = logic high? n y otp= logic high? y n uvlo, otp & olp are auto restart, ovp is latch release from the latch condition , need to unplug from the main input . pin vsd monitor vcc<3v? y n shut off the switching pulse y figure 12?control flow chart
HFC0100 quasi resonant controller HFC0100 rev. 1.01 www.monolithicpower.com 14 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. 11.8v 8.5v 5.5v vcc driver ifault flag ovp fault occurs here driver pluses regulation occurs here high voltage current source start up normal operation normal operation normal operation olp fault occurs here on off over voltage occurs here normal operation otp fault occurs here normal operat ion unplug from main input normal operation normal operation figure 13?evolution of the signals in presence of faults
HFC0100 quasi resonant controller notice: the information in this document is subject to change wi thout notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. HFC0100 rev. 1.01 www.monolithicpower.com 15 9/23/2011 mps proprietary information. pat ent protected. unauthorized photoc opy and duplication prohibited. ? 2011 mps. all rights reserved. package information soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation aa. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane

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