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53 PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 1 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug. 2005 PAC107 single-chip cmos qqvga image sensor with embedded twin-t urbo 8032 micro-processor general description the PAC107 is a qqvga cmos imager sensor with an embedded 40mhz twin-turbo 8032 micro control unit (mcu). to have excellent application flexibility, the PAC107 controls the embedded cmos imager through 8032?s sfr. a one-cycle ex ecution multiplier is available for instruction ?mul?. it?s suitable for recognition applications. the PAC107 had on-chip 16kb program rom and 1kb on-chip sram. there are two 8- b it pwm ports with pre-scale function. hence melody play and simple board level control function can be implemented. a dedicate image data write to external sram sequence is provided to have a fast and efficient image data caption through port0 of 8032. the exposure-time control of imager can be done by on-chip real time hardware control, and extend the operation luminance range through firmware. features 164x124 pixels, 1/11? lens risc-like twin-turbo 8032 auto/manual exposure-gain control. 2 uart with programmable baud-rate automatic de-flicker 2 pwm firmware controlled imager power down 1 cycle execution mul instruction on-chip 10-bit adc software controllable sensor shut down continuous variable exposure time movx direct dump image data to sram continuous variable frame time(1/2s~1/30s) 1kb on-chip sram crystal mode: 4~40 mhz 16kb on-chip program rom operating voltage: 2.6v ~ 3.6v external program rom bus supported power supply 2.6v ~ 3.6v fpn < 0.2% saturation array elements 164 x 124 pga gain 16x (24db) optical format 1/11 ? digital gain 4x(12db) pixel size 7.25 m x 7.25 m frame rate 60fps master clock up to 40mhz scan mode progressive max. pixel rate 1.5mhz package 80-pin lcc and 48-pin lcc
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 2 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 1. pin description 1.1 80-pin lcc pin no. name type definition 1 vrt bypass top-voltage reference for analog circuit 2 gnda g analog ground 3 /ea i enable bar of external rom, ?1? for internal rom 4 rom_ar13 o address for external rom, bit 13 5 rom_ar12 o address for external rom, bit 12 6 rom_ar11 o address for external rom, bit 11 7 pwm1 o 8032, programmable pulse-width-modulation output 8 rom_ar10 o address for external rom, bit 10 9 rom_ar9 o address for external rom, bit 9 10 ale o address latch pulse for sram-address 11 rst i chip reset 12 rom_ar8 o address for external rom, bit 8 13 rom_ar7 o address for external rom, bit 7 14 rom_ar6 o address for external rom, bit 6 15 rom_ar5 o address for external rom, bit 5 16 vddd p digital power 17 rom_ar4 o address for external rom, bit 4 18 rom_ar3 o address for external rom, bit 3 19 rom_ar2 o address for external rom, bit 2 20 rom_ar1 o address for external rom, bit 1 21 rom_ar0 o address for external rom, bit 0 22 rom_d0 i data from external rom, bit 0 23 rom_d1 i data from external rom, bit 1 24 gndd g digital ground 25 rom_d2 i data from external rom, bit 2 26 rom_d3 i data from external rom, bit 3 27 rom_d4 i data from external rom, bit 4 28 rom_d5 i data from external rom, bit 5 29 rom_d6 i data from external rom, bit 6 30 p3_6(/wr) o 8032, p3_6 (/wr) ? write pulse of sram 31 p3_7(/rd) o 8032, p3_7 (/rd) ? read pulse of sram 32 nc nc not connected 33 rom_d7 i data from external rom, bit 7 34 p2_0 io 8032, p2_0 35 p2_1 io 8032, p2_1 36 pwm2 o 8032, programmable pulse-width-modulation output 37 p2_2 io 8032, p2_2 38 p2_3 io 8032, p2_3 39 vddd p digital power
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 3 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 40 gndd g digital ground 41 p2_4 io 8032, p2_4 42 p2_5 io 8032, p2_5 43 p2_6 io 8032, p2_6 44 p2_7 io 8032, p2_7 45 p3_3(/int1) io 8032, p3_3 46 p3_4(t0) io 8032, p3_4 47 p1_2(/rxd1) io 8032, p1_2(/rxd1) ? uart1 rxd 48 p1_1(t2ex) io 8032, p1_1 49 p1_0(t2) io 8032, p1_0 50 p3_5(t1) io 8032, p3_5 51 nc nc not connected 52 lcd_4b0 o specific data pin connect to color lcm 53 lcd_4b1 o specific data pin connect to color lcm 54 xtal1 clock differential input of crystal oscillator 55 xtal2 clock differential output of crystal oscillator 56 lcd_4b2 o specific data pin connect to color lcm 57 lcd_4b3 o specific data pin connect to color lcm 58 vddd p digital power 59 gndd g digital ground 60 lcd_wrb o specific write pulse pin connect to color lcm 61 p1_6 io 8032, p1_6 62 p0_0 io 8032, p0_0 63 p0_1 io 8032, p0_1 64 p0_2 io 8032, p0_2 65 p0_3 io 8032, p0_3 66 p1_5 io 8032, p1_5 67 p0_4 io 8032, p0_4 68 p0_5 io 8032, p0_5 69 p0_6 io 8032, p0_6 70 p0_7 io 8032, p0_7 71 nc nc not connected 72 p1_4 io 8032, p1_4 73 p1_3(/txd1) io 8032, p1_3(/txd1) ? uart1 txd 74 p3_1(/txd0) io 8032, p3_1(/txd0) ? uart0 txd 75 p3_0(/rxd0) io 8032, p3_0(/rxd0) ? uart0 rxd 76 p3_2(/int0) i p3_2(/int0) ? int0 to asic 77 vdda p analog power 78 vdday1 bypass sensor power 79 vrb bypass bottom-voltage reference for analog circuit 80 vcm bypass common-mode-voltage reference for analog circuit
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 4 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 1.2 48-pin lcc pin no. name type definition 1 vdda p analog power 2 vdday1 bypass sensor power 3 vrb bypass bottom-voltage reference for analog circuit 4 vcm bypass common-mode-voltage reference for analog circuit 5 vrt bypass top-voltage reference for analog circuit 6 gnda g analog ground 7 /ea i enable bar of external rom, ?1? for internal rom 8 nc nc not connected 9 nc nc not connected 10 ale o address latch pulse for sram-address 11 rst i chip reset 12 vddd p digital power 13 nc nc not connected 14 nc nc not connected 15 gndd g digital ground 16 p3_6 (/wr) o 8032, p3_6 (/wr) ? write pulse of sram 17 p3_7 (/rd) o 8032, p3_7 (/rd) ? read pulse of sram 18 p2_0 io 8032, p2_0 19 p2_1 io 8032, p2_1 20 pwm2 o 8032, programmable pulse-width-modulation output 21 p2_2 io 8032, p2_2 22 p2_3 io 8032, p2_3 23 p2_4 io 8032, p2_4 24 p2_5 io 8032, p2_5 25 p2_6 io 8032, p2_6 26 p2_7 io 8032, p2_7 27 p1_2 io 8032, p1_2 28 p1_1 io 8032, p1_1 29 p1_0 io 8032, p1_0 30 p3_5 io 8032, p3_5 31 xtal1 clock differential input of crystal oscillator 32 xtal2 clock differential input of crystal oscillator 33 vddd p digital power 34 p1_6 io 8032, p1_6 35 p0_0 io 8032, p0_0 36 p0_1 io 8032, p0_1 37 p0_2 io 8032, p0_2 38 p0_3 io 8032, p0_3 39 p0_4 io 8032, p0_4 40 p0_5 io 8032, p0_5
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 5 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 41 p0_6 io 8032, p0_6 42 p0_7 io 8032, p0_7 43 gndd g digital ground 44 p1_4 io 8032, p1_4 45 p1_3 io 8032, p1_3 46 p3_1(/txd) io 8032, p3_1(/txd) ? uart txd 47 p3_0(/rxd) io 8032, p3_0(/rxd) ? uart rxd 48 p3_2(/int0) i p3_2(/int0) ? int0 to asic
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 6 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 2. block diagram sensor (16 kb) i-rom on-chip ext-sram 0~1023 rxd addr[15:8] p2 p0 8 14 we#, rd# addr i_data addr[7:0] or data[7:0] pwm p3.0 txd 1 2 3 int0# int1# t0 4 t1 5 6/7 we#, rd# p1.0 1 2 3 4 5 6 - - - pwm - ale rst addr[9:0] 8032 core *see sfr mapping t2 rxd_1 txd_1 fig 2.1 ? block diagram of PAC107 as the block diagram of PAC107 is shown in figure 2.1. by pulling the csb register in sfr(special function register) to low, the 164x124 sensor starts to produce a signal according to the amount of the light integrated in pixels. the integrated analog signal will be readout and amplifier with adc output in 8-bit. the output 8 bit digital sensor data then be received by 8051 core by software. 16kb program rom and 1kb sram is provided in PAC107 and two pwm ports are supported.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 7 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 3. register table of cmos image sensor address name r/w default recommended setting description reg_0[7:0] pdct_id[11:4] r 0000_0001 - product id reg_1[7:4] pdct_id[3:0] r 1001 - product id reg_1[3:0] ver_id[3:0] r 0000 - version id reg_2[7:1] ysum_report[6:0] r - - ysum report in ae/ag calculation reg_2[0] s_valid r - - ysum valid flag reg_3[7] rsv - - - reserved reg_3[6:0] ae_wait[6:0] r/w 000_0001 0 frame wait for ae/ag calculation reg_4[7:4] ysum_hi[3:0] r/w 1010 - ysum high threshold reg_4[3:0] ysum_lo[3:0] r/w 1000 - ysum low threshold reg_5[7:6] ae_max[1:0] r/w 11 - maximum ae index in auto mode reg_5[5:1] ag_max[4:0] r/w 1_1111 - maximum gain index in auto mode reg_5[0] dac[8] r/w 0 - sign bit of dac reg_6[7:0] dac[7:0] r/w 0000_0000 - magnitude of dac reg_7[7] rsv - - - reserved reg_7[6:0] ny3[6:0] r/w 000_1011 0 raw exposure set #4 for ae reg_8[7:0] ne3[7:0] r/w 0101_1000 0 fine exposure set #4 for ae reg_9[7] rsv - - - reserved reg_9[6:0] ny2[6:0] r/w 010_1000 0 raw exposure set #3 for ae reg_10[7:0] ne2[7:0] r/w 0000_1000 0 fine exposure set #3 for ae reg_11[7] rsv - - - reserved reg_11[6:0] ny1[6:0] r/w 100_0100 010_1011 raw exposure set #2 for ae reg_12[7:0] ne1[7:0] r/w 1000_1101 0 fine exposure set #2 for ae reg_13[7:6] rsv - - - reserved reg_13[5:0] np[5:0] r/w 00_0110 01_0000 pxclk = sysclk / np reg_14[7:0] lpf[7:0] r/w 0111_1101 0111_1111 line per frame reg_15[7] adc8b r/w 0 1 1: adc 8_bit valid 0: adc 10_bit valid reg_15[6:4] comp[2:0] r/w 011 - companding curve selection reg_15[3:2] cgn_b[1:0] r/w 10 11 color gain for blue reg_15[1:0] cgn_r[1:0] r/w 10 01 color gain for red reg_16[7:5] rsv - - - reserved reg_16[4:0] pga[4:0] r/w 0_0100 - pga global gain reg_17[7] rsv - - - reserved reg_17[6:0] ny0[6:0] r/w 110_0001 101_0110 raw exposure set #1 for ae reg_18[7:0] ne0[7:0] r/w 0100_0111 0 fine exposure set #1 for ae reg_19[7:1] rsv - - - reserved reg_19[0] flag r/w 0 - synchronization flag for i2c update reg_20[7:0] rsv - 1000_0000 - reserved reg_21[7] col_reverse r/w 0 - line readout reverse reg_21[6:5] pack[1:0] r/w 00 - 8, 4, 2, 1 bit packing selection
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 8 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 reg_21[4] toyt r/w 0 - toy timing enable reg_21[3] aegenh r/w 1 - ae/ag enable reg_21[2:1] edge-gn[1:0] r/w 00 - edge gain reg_21[0] vlrst_outh r/w 0 0 external vlrst enable reg_22[7] shr_we2 r/w 1 0 cds extension reg_22[6] intvddy r/w 1 - internal array vdd reg_22[5] intvref r/w 1 - in ternal voltage reference reg_22[4] cdsenh r/w 1 - cds enable reg_22[3] dacenh r/w 1 0 dac enable reg_22[2] pgaenh r/w 1 - pga enable reg_22[1] adcenh r/w 1 - adc enable reg_22[0] dqioenl r/w 0 - dqio enable / tri-stage reg_23[7] vlrst_enh r/w 0 0 vlrst enable reg_23[6] vr r/w 0 1 vref option reg_23[5] vy r/w 0 1 array vdd option reg_23[4:3] regfast[1:0] r/w 00 - fast mode for regulator reg_23[2] cdsfast r/w 0 - fast mode for cds reg_23[1] pgafast r/w 0 - fast mode for pga reg_23[0] adcfast r/w 0 - fast mode for adc reg_24[7:3] rsv r/w - - reserved reg_24[2] dacscan r/w 0 - dac test mode reg_24[1] pgascan r/w 0 - pga test mode reg_24[0] frstenl r/w 1 - frame reset enable reg_25[7:1] rsv - - - reserved reg_25[0] fast_i2c r/w 0 - fast update for reg_13 ~ reg_18 reg_26[7:5] rsv r/ w- - - reserved reg_26[4:0] pga_report[ 4:0] r - - pga code report (ae enable) reg_27[7:0] ne_report[7:0] r - - ne report (ae enable) reg_28[7] rsv - - - reserved reg)28[6:0] ny_report[6:0] r - - ny report (ae enable)
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 9 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 3.1. memory organization in the risc 52 the memory is organized as three address spaces and the program counter. the memory spaces shown in memory map. - 16-bit program counter - 16kb program memory address space - 64kb external data memory address space - 256-byte internal data memory address the 14-bit program counter register provi des the risc 52 with its 16kb addressing capabilities. the program counter allows the user to execute calls and branches to any location within the program memory space. th ere are no instructions that permit program execution to move from the program memory space to any of the data memory spaces. the 64k-byte external data memory address space is automatically accessed when the movx instruction is executed. note that us er can extend the addressable data ram space by mux the general i/o pins in port 1 and 3. the internal sram address space is 0 to 255 cp u internal usage. four 8-register banks occupy locations 0 through 31. the stack can be located anywhere in the internal data ram address space. in addition, 128 bit lo cations of the on-chip ram are accessible through direct addressing.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 10 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 64k program memory space 64k external data memory space 64k 0 64k 0 program counter memory organization special function register indirect addressing ram direct & indirect addressing ram internal data memory ffh 80h 7fh 00h 07 06 05 04 03 02 01 00 bank3 bank2 bank1 bank0 08 09 0a 0b 0c 0d 0e 0f 17 16 15 14 13 12 11 10 18 19 1a 1b 1c 1d 1e 1f 07 26 25 24 23 22 21 20 2f 2e 2d 2c 2b 2a 29 28 3c 3b 3a 39 38 30 31 32 33 34 35 37 37 44 45 46 47 3f 3e 3d 43 4d 4c 4b 4a 49 48 40 41 42 57 4f 4e 5b 5a 59 58 50 51 52 53 54 55 56 5c 64 64 66 67 5f 5e 5d 6c 6b 6a 69 68 60 61 62 63 6d 6e 6f 77 76 75 74 73 72 71 70 78 79 7a 7b 7c 7d 7e 7f (msb) (lsb) ffh 80h 7fh 2fh 2eh 2d h 2c h 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh 18h 17h 10h 0fh 08h 07h 00h 47 46 40 41 42 43 44 45 35 36 37 38 39 32 33 34 31 24 15 16 23 8 7 0 127 128 256 r7 r0 r0 r7 r0 r7 r7 r0 indirect ram ram bit addresses addressable bits 20h-2fh
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 11 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 3.2. special function register table the special function register address space is from 80h to ffh. all registers except the program counter and the four 8-register banks reside here. the sfrs are accessed by using direct addressing only. all of the sfrs are the compatible with standard 8032 with image sensor control registers. the sfr in red color are those different with standard 8032. f8h f0h b pwm21conf pwm11conf e8h cdinswtst i2c pixst cap e0h acc pdcon vstart vend hstart hend d8h wdtcon pwm2conf pwm1conf pwmdata1 pwmdata2 d0h psw c8h t2con t2mod rcap2l rcap2h tl2 th2 c0h scon1 sbuf1 pmr status b8h ip b0h p3 a8h ie a0h p2 98h scon sbuf 90h p1 88h tcon tmod tl0 tl1 th0 th1 ckcon 80h p0 sp dpl dph dpl1 dph1 dps pcon
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 12 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 the b register is used for both a source a nd destination in mul and div instructions. accumulator. psw address: d0h bit 7 bit 0 cy ac f0 rs1 rs0 ov f1 parity program status word. cy: carry flag ac: auxiliary-carry flag f0: flag 0 available to th e user for general-purpose. rs1, rs0: 2-bit register bank address selector. rs1 rs0 register bank address 0 0 0 00h-07h 0 1 1 08h-0fh 1 0 2 10h-17h 1 1 3 18h-1fh ov: overflow flag ud: user-definable flag, general- purpose flag, available for user. p: parity flag. set/cleared by hardware each instruction cycle to indicate an odd/even number of ?1? bit in the acc. b address:f0h bit 7 bit 0 b.3 b.6 b.4 b.7 b.5 b.2 b.1 b.0 acc address:e0h bit 7 bit 0 acc.3 acc.6 acc.4 acc.7 acc.5 acc.2 acc.1 acc.0 t2con address:c8h bit 7 bit 0 exen2 tr2 exf2 tclk tf2 rclk c/t2 cp/rl2
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 13 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 timer 2 control register. tf2: timer2 overflow flag. cleared by so ftware. tf2 can not be set when rclk=1or tclk=1. exf2: timer 2 external flag. set when either a capture or reload is caused by a negative transition on t2ex, exen2=1. when time r2 interrupt is enabled, exf2=1 will cause the cpu to vector of timer2 is r. exf2 must be cleared by software. rclk: receive clock flag. selects time r 2 overflow pulses (rclk=1) or timer 1overfiow pulses (rclk=0) as the baud rate generator for uart modes 1 & 3. tclk: transmit clock flag. select timer2 overflow pulses (tclk=1) or timer 1 overflow pulses (tclk=0) as the baud rate generator for serial port modes 1 & 3. exen2:timer 2 external enable flag. exen 2=1: capture or reload when a negative transition on t2ex unless timer 2 is being used as the baud rate generator for the serial port. clearing exen2 causes tim er 2 to ignore events at t2ex. tr2: timer 2 run control flag. setting this bit starts the timer. c/ 2 t : timer 2 counter/timer select c/ 2 t = 0 timer 2 counts the divided-down system clock. c/ 2 t = 1 timer 2 counts when external pin t2 goes low. cp/ 2 rl : capture/reload bit cp/ 2 rl =1: (if exen2=1), captures occurred at negative edge of t2ex. cp/ 2 rl =0: (if exen2=1), auto-reloads occurre d at negative edge of t2ex or when timer 2 overflowed. (if rclk =1 or tclk = 1).cp/ 2 rl is ignored and timer 2 is auto-reloaded when timer 2 overflow, timer 2 mode control register. bit7-bit2: reserved t2oe: timer 2 output enable flag. in the timer 2 clock-out mode, connects the programmable clock output to external pin t2. dcen: down count enable flag. confi gures timer 2 as an up/down counter. t2mod address:c9h bit 7 bit 0 t2oe dcen
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 low byte of timer2 capture rcap2l stores data to be loaded into or cap tured from the timer register tl2 for timer2 high byte of timer2 capture rcap2h stores data to be loaded into or captured from the th2 for timer2 interrupt priority control register ip.7: reserved bits ps1: serial port 1 priority control bit. 1: high priority interrupt pt2: timer 2 interrupt priority control bit. 1: ps0: serial port0 priority control bit. 1: high priority interrupt pt1: timer 1 interrupt priority control bit. px1: external interrupt 1 priority co ntrol bit. 1: high priority interrupt pt0: timer 0 interrupt priority control bit. px0: external interrupt 0 priority control bit.1 interrupt enable register. rcap2h address:cbh bit 7 bit 0 rcap2h.3 rcap2h.6 rcap2h.4 rcap2h.7 rcap2h.5 rcap2h.1 rcap2h.0 rcap2h.2 rcap2l address:cah bit 7 bit 0 rcap2l.3 rcap2l.6 rcap2l.4 rcap2l.7 rcap2l.5 rcap2l.1 rcap2l.0 rcap2l.2 ip address:b8h bit 7 bit 0 pt1 pt0 px0 px1 pt2 ps ps1 ie address:a8h bit 7 bit 0 et1 et0 ex0 ex1 ea et2 es es1
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 15 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 ea: global interrupt enable/mask. (ea=1/ea=0) es1: serial port 1 interrupt enable et2: timer 2 overflow interrupt enable es0: serial port0 interrupt enable et1: timer 1 overflow interrupt enable ex1: external interrupt 1 enable et0: timer 0 overflow interrupt enable ex0: external interrupt 0 enable serial data buffer. writing to sbuf loads th e transmit buffer to the serial i/o port. reading sbuf reads the receive buffer of the serial port. timer/counter control register. tf1: timer 1 overflow flag. set by hardware when the timer 1 overflowed. cleared by hardware when the interrupt service routine (isr) is executed. tr1: timer 1 run control bit. timer 1 is on/off, when tr1 is set/cleared by software. tf0: timer 0 overflow flag. set when timer 0 overflows. cleared by hardware when isr is executed. tr0: timer 0 run control bit. timer 0 is on/off, when tr0 is set/cleared by software. sbuf address:99h bit 7 bit 0 sbuf.7 sbuf.5 sbuf.4 sbuf.3 sbuf.1 sbuf.0 sbuf.6 sbuf.2 tcon address:88h bit 7 bit 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 16 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 ie1: interrupt 1 edge detect. set by hardware when interrupted at pin- 1 int . cleared when isr is processed for edge-triggered. it1: interrupt 1 trigger type selection bit. it1=1: edge-triggered (hi-to-lo) . it1=0: level-tri ggered (active low). ie0: interrupt 0 edge detect. set by hardware when interrupted at pin- 0 int . cleared when isr is processed for edge-triggered. it0: interrupt 0 trigger type selection bit. it0=1: edge-triggered (hi-to-lo) . it0=0: level-tri ggered (active low). timer/counter mode control register. gate (tmod.7 or tmod.3): timer1/timer0 toggling gate control when trx(in tcon) is set and ga te=1, timer/counterx will run only while intx pin is high(hardware control). wh en gate=0, timer/counterx will run only while trx=1(software control). c/ t : timer or counter selector c/ t = 0: timer operation: timerx(input from internal system clock). c/ t = 1: counter operation: counterx c ounts at falling-edge of pin-tx. m1 (tmod.5), m0 (tmod.4) :mode select of timer 1 m1 m0 mode operation 0 0 0 1 bit timer. 8-bit timer/counter (thx) with 5-bit pre-scalar (tlx) 0 1 1 16-bit timer/counter 1 0 2 8-bit auto-reload timer/counter. reload from thx when overflow. 1 1 3 (timer 0) tl0 is an 8-bit timer and is controlled by timer 1 control bits. 1 1 3 (timer 1) timer/counter 1 is stopped. tmod address:89h bit 7 bit 0 gate m1 m0 gate m1 m0 timer1 timer0 c/t c/t
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 17 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 p3: port 3 of i/o port, p3.2 is modified as an input address:0b0h p2: port 2 of i/o port. address:0a0h p1: port 1 of i/o port, p1.7 is modi fied for dumping sensor data. address:090h p0: port 0 of i/o port. address:080h th0: high byte of timer 0. address:08ch tl0: low byte of timer 0. address:08ah th1: high byte of timer 1. address:08dh tl1: low byte of timer 1. address:08bh th2: high byte of timer 2. address:0cdh tl2: low byte of timer 2. address:0cch dph1: high byte of dptr1. address:085h dpl1: low byte of dptr1. address:084h dph: high byte of dptr. address:083h dpl: low byte of dptr. address:082h dps address:86h bit 7 bit 0 ? ? ? ? ? ? ? dps data point selection bit. dps=1: dptr will be selected. dps=0: dptr1 will be selected
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 18 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 stack pointer. 8-bit sp memo the address of last address pushed to the stacker. sp is advanced before push exactly executed and can be read or written through software. power control register. smod1: double baud rate bit. 1 for timer 1 in mode 1, 2, or 3 is selected in scon. smod0: framing error detection enable. this bit selects function of the scon0.7 and scon1 bits. 0: scon1.7 control the sm0 functi on defined for the scon0 and scon1 1: scon1.7 are converted to the fe flag for respective serial port gf1, gf0: general purpose flag it will be (1, 1) when it came form idle mode pd: set=1 to activates power-down mode. clear by hardware when interrupted or reset. idl: set=1 to activates idle mode. clear by hardware when interrupted or reset. pdcon address: e1h bit 7 bit 0 pwm2on pwm1on wc3 wc2 wc1 wc0 jwp pdc power down controller register pdc: power down control 0: original (pull-high), 1: sfr value (default) jwp: just wake up 0: execute interrupt af ter wake up (default) 1: don't execute interrupt after wake up sp address:81h bit 7 bit 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 pcon address:87h bit 7 bit 0 gf1 pd idl gf0 smod0 smod1
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 19 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 wc3, wc2, wc1, wc0: power wake up counter 0, 0, 0, 0: 1-bit counter; 0, 0, 0, 1: 2-bits counter; 0, 0, 1, 0: 3-bits counter; 0, 0, 1, 1: 4-bits counter; 0, 1, 0, 0: 5-bits counter; 0, 1, 0, 1: 6-bits counter; 0, 1, 1, 0: 7-bits counter; 0, 1, 1, 1: 8-bits counter; 1, 0, 0, 0: 9-bits counter; 1, 0, 0, 1: 10-bits counter; 1, 0, 1, 0: 11-bits counter; 1, 0, 1, 1: 12-bits counter; 1, 1, 0, 0: 13-bits counter; 1, 1, 0, 1: 14-bits counter; 1, 1, 1, 0: 15-bits counter; 1, 1, 1, 1: 16-bits counter (default) pwm2on: channel 2 on / off (default = 0 / off) pwm1on: channel 1 on / off (default = 0 / off) wdtcon address: d8h bit 7 bit 0 smod_1 ? ? ? ? wdten wdtrst watch dog timer controller register smod_1: serial modification. doubling th e baud-rate of uart1 in modes 1, 2, 3 wdten: watchdog timer enable, set to ?1? to enable watchdog timer wdtrst: watchdog timer reset, set to ?1? to re set timer, and be clear when counter reset to 0. pmr address: c4h bit 7 bit 0 uartoff ? ? ? ? aleoff cd1 cd0 power manager register aleoff: 0: ale toggling is enabled. 1: ale toggling is disabled uartoff: 0: enable the clock input of uart. 1: disable the clock input of uart {cd1, cd0}: output to system clock of sensor.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 20 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 (0, 0) => default (0, 1) => PAC107?s system clk/2 (1, 0) => PAC107?s system clk/4 (1, 1) => PAC107?s system clk/8 ckcon address: 8eh bit 7 bit 0 wdt1 wdt0 t2m t1m t0m md2 md1 md0 clock control register wdt1, wdt0: wdt time-out counter select 0, 0 - 17 bit counter 0, 1 - 20 bit counter 1, 0 - 23 bit counter 1, 1 - 26 bit counter t2m: timer2 clock = sysclk/4(t2m=1) or sysclk/12(t2m=0) t1m: timer1 clock = sysclk/4(t2m=1) or sysclk/12(t2m=0) t0m: timer0 clock = sysclk/4(t2m=1) or sysclk/12(t2m=0) md2, md1, md0: insert wait-state of movx (0, 0, 0): no wait-state (0, 0, 1): original + 4t (0, 1, 0): original + 8t (0, 1, 1): original + 12t (1, 0, 0): original + 16t (1, 0, 1): original + 20t (1, 1, 0): original + 24t (1, 1, 1): original + 28t scon1 address: c0h bit 7 bit 0 sm0_1/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 scon_1 register fe_1: framing error bit. set by receiver when an inva lid stop bit is detected. the fe is not cleared by valid frames but should be clear by software. th e "smod0" must be set to enable access to the fe bit.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 21 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 sm0_1: serial port mode control set/cleared by software sm2_1: set by software to disable recep tion of frames for which bit8 zero ren_1: receiver enable b it. set/cleared by software. tb8_1: set/cleared by hardware. the state of 9 th bit transmitted in 9-bit mode rb8_1: set/cleared by hardware to indi cate state of ninth data bit received ti_1: transmit interrupt flag. set by hardware when byte transmitted. cleared by software after serving. ri_1: received interrupt flag. set by hardware when byte received. cleared by software after serving. sm1_1: sm2_1 select 00: shift reg. i/o expansion 01: 8 bit uart, variable data rate 10: 9 bit uart, fixed data rate 11: 9 bit uart, variable data rate scon address: 98h bit 7 bit 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe: framing error bit. set by receiver when an inva lid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the "smod0" bit must be set to enable access to the fe. sm0, sm1: serial port op eration mode specifier. sm0 sm1 mode description baud rate 0 0 0 shift register. fosc/12 0 1 1 8 bit uart, variable data rate 1 0 2 9 bit uart, fosc/32 or fosc/64 1 1 3 9 bit uart, variable data rate sm2: enable the multiprocessor communication feature in mode 2 & 3. in mode 2 or 3, if sm2 is set to 1 then ri will not be activated if the received 9 th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was not received. in mode0, sm2 should be 0.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 22 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 mode scon sm2 variation 0 10h 1 50h 2 90h 3 d0h single processor equivalent (sm2=0) 0 10h 1 50h 2 90h 3 d0h multi processor equivalent (sm2=1) ren: set/cleared by software to enable/disable reception. tb8: the 9 th bit that will be transmitted in mode 2 & 3. set/clear by software. rb8: the 9 th bit in mode 2 & 3. in m ode 1, if sm2=0, rb8 is the stop bit that was received. in mode0, rb8 is not used. ti: transmit interrupt flag. set by hardware at the end of 8 th bit time in mode0, or at the beginning of the stop bit in other m odes. must be cleared by software. ri: receive interrupt flag. set by hardware at the end of 8 th bit time in mode0, or halfway through the stop bit time in other modes (except see sm2). must be cleared by software. status address: c5h bit 7 bit 0 (r1) hip lip (r2) spta1 spra1 spta0 spra0 (r1) : power fail prio rity interrupt status hip : high priority interrupt status lip : low priority interrupt status (r2) : crystal osc warm-up status spta1: serial port1 transmit activity monitor spra1: serial port1 receive activity monitor spta0: serial port0 transmit activity monitor spra0: serial port0 receive activity monitor
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 23 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 cdinswtst address: eah bit 7 bit 0 ? ? cdw3 cdw2 cdw1 cdw0 insert wait-state of program code. {cdw3, cdw2, cdw1, cdw0} = rom wait-state default rom wait-state = 7 3.3 miscellaneous sfr(pixart defined) h h a a r r d d w w a a r r e e w w i i n n d d o o w w i i n n g g r r e e g g i i s s t t e e r r s s vstart [6:0] ? 0e4?h (default : 7?b0000100) vend [6:0] ? 0e5?h (default : 7?b1111100) hstart [7:0] ? 0e6?h (default : 8?b00000100) hend [7:0] ? 0e7?h (default : 8?b10100100) pwm registers (pwm1 and pwm2) pwm1conf - 0dd'h, pre-scaling of pwm1 clock, m1 pwm1conf1 - 0f7'h, pos-scaling of pwm1 clock, n1 pwm1 data - 0de'h, high duty width of pwm1, d1 => frequency = sysclk / (m1 +1)(n1 +1) => duty ratio = d1 / n1, (note: d1 must < n1) pwm2conf - 0dc'h, pre-scaling of pwm2 clock, m2 pwm2conf1 - 0f6'h, pos-scaling of pwm2 clock, n2 pwm2 data - 0df'h, high duty width of pwm2, d2 => frequency = sysclk / (m2 +1)(n2 +1) => duty ratio = d2 / n2, (note: d2 must < n2)
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 24 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 pixst (default:8?b01000011) address:eeh bit 7 bit 0 iram_enh dis_exint clr_exint clr_inint mode1 mode0 skip1 skip0 iram_enh: when 1, movx will access internal 1kb sram dis_exint: when 1, disable external interrupt clr_exint: when 1, clear external inte rrupts, then have to clear to 0 clr_inint: when 1, clear internal in terrupts, then have to clear to 0 {mode1, mode0}: {0, 0} = normal capture mode. {0, 1} = compressed capture mode (dpcm). {1, 0} = full window display on lcm mode (through p0). {1, 1} = hardware windowing display on lcm mode (through p0). {skip1, skip0}: {0, 0} = no skip pixel when display on lcm {0, 1} = skip 1 pixel when display on lcm {1, 0} = skip 2 pixel when display on lcm {1, 1} = skip 4 pixel when display on lcm cap (default: 8?b00000000) address: efh bit 7 bit 0 - - - capture cap_no3 cap_no2 cap_no1 cap_no0 capture: when 1, capture {cap_no3 : cap_no0} image through asic. i2c: sensor command register address: edh bit 7 bit 0 intp_pd lcdwrb sdao int4lcd int4cap csb scl sdai intp_pd: when 1, disable interrupt block, 0 enable interrupt block. lcdwrb: control output pin lcd_wrb. sdao: i2c data output of sensor. int4lcd: during lcd mode, each frame w ill generate interrupt called int4lcd. int4cap: when set capture at cap register and asic finish its capture job. asic will generate interrupt called int4cap. csb: when 1, disable sensor, 0 enable sensor
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 25 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 scl: i2c clock of sensor. sdai: i2c data in of sensor.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 26 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 4. on-chip peripherals 4.1 interrupts interrupt source request flag priority flag enable flag vector address priority- within-level flog cleared by hardware? external request ie0/tcon.1 px0/ip.0 ex0/ie.0 0003h 1 edge-yes level-no internal timer0/counter0 tf0/tcon.5 pt0/ip.1 et0/ie.1 000bh 2 yes external request ie1/tcon.3 px1/ip.2 ex1/ie.2 0013h 3 edge-yes level-no internal timer1/counter1 tf1/tcon.7 pt1/ip.3 et1/ie.3 001bh 4 yes xmit ti/scon.1 internal serial port rcvr ri/scon.0 ps/ip.4 es/ie.4 0023h 5 no tf2/t2con.7 internal timer2/counter2 exf2/tscon.6 pt2/ip.5 et2/ie.5 002bh 6 no interrupt system table external interrupt external interrupt 0 int is modified as a sensor control pin. the 1 int pins can be 0 1 tf0 0 1 ie0 timer 0 ea ex0 et0 ex1 interrupt enable ip priority enable highest priority interrupt interrupt polling squence interrupt control system configuration int1 int0 it0 it1 pfi power fail detector ie1 timer 1 tf1 et1 ri ti receive transmit es et2 exf2 tf2 timer 2 t2ex epfi px0 pt0 px1 pt1 ps pt2
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 27 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 programmed to be level-triggere d or edge triggered. it1 = 0, 1 int is triggered by detected low at the pin. if it1 = 1, 1 int is negative-edge triggere d. external interrupts are enabled with bits ex1in the ie register. ev ens on the external interrupt pins set the interrupt flags ie1 in tcon. these request bits are cleared by hardwa re vectors to service routines only if the interrupt is negative-edge triggered. if the interrupt is level-triggered, the interrupt service routine must clear the re quest bit. external ha rdware must release 1 int before the service routine completes, or an additional interrupt is requested. external interrupt pins are sampled once when rising edge of oscillator clock. the interrupt pin should hold for at least 3 clocks for le vel-detection. and hold one clock for edge- triggered interrupt. ex1 is se t if external interrupt is detected. and the ex1 is automatically cleared during service routine fetch cycles for edge -triggered interrupts. timer interrupts three interrupt request tf0, tf1 and tf2 are set by timer 0 ,timer 1 and timer 2 overflow. tf0 and tf1 are cleared by hardware vectors an d jump to interrupt service routine when timer 0 and timer 1 interrupts are generated. tf 2 is different to tf0/tf1. tf2 is clear by software when timer 2 interrupt is generated. the relative enable bit of timre0, timer1, ti mer2 are et0, et1, and et2 in register ie. timer 2 interrupts are generated by a logical or of bits tf2 and exf2 in register t2con. neither flag is cleared by a ha rdware vector to a service r outine. in fact , the interrupt service routine must determine if tf2 or exef 2 generated the interrupt, and then clear the bit. timer 2 interrupt is enabled by et2 in register ie. serial port interrupt serial port interrupts are genera ted by the logical or of bits ri and ti in the scon register. neither flag is cleared by a hardware vector to the servic e routine. the service routine resolves ri and ti interrupt generation and clea rs the serial port request flag. the serial port interrupt is enabled by bit es in the ie re gister. in the same wa y by using serial port 1. serial port 1 control register is scon1, and the buffer is sbuf1. here is one thing to be noticed that serial port 1 only uses timer 1 to generate baud rate.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 28 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 interrupt priority PAC107 has 2 level priorities. se tting / clearing a bit in the interrupt priority register (ip) or extent interrupt priority register (eip) es tablished its associated interrupt request as a high / low priority. if a low-priority level interrupt is being serviced, a high-priority level interrupt will interrupt it. however, an inte rrupt source cannot interru pt a service program of the same or higher level. the interrupt pr iority is shown on interrupt control system configuration. interrupt response time the minimum interrupt response time is eight cl ocks that when an interrupt request asserts as last instruction executed. the maximum interrupt response time is 24 clocks. djnz direct, rel or others instruc tion sets which operation period is 16 clocks, is decoded ok. when a high priority interrupt asserts during a low priority interrupt service program, the minimum and maximum interrupt response times are 8 clocks and 24 clocks. osc call isr push pc ending instructions interrupt vector address interrupt response time interrupt response time int0 or int1
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 29 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 4.2 timer/counters timer 0 timer 0 can be a timer or event counter in f our modes of operation. it?s controlled by the high-nibble of the tmod register and bits 5, 4, 1, and 0 of the tcon register. the tmod register selects the method of timer gati ng (gate), timer or counter operation (c/ t ), and mode of operation (m1, m0). the tcon regi ster provides timer 0 control functions: overflag (tf0), run control (tr0), interrupt flag (ie0), and interrupt type control (it0). for normal timer operation (gate = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate and tr0 allows 0 int to control timer operation. timer0/mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer whic h is set up as an 8-bit timer (th0 register) with a modulo 32 pre-scalar implemented with the lower five bits of the tl0 register. the upper three bits of tl0 register are indete rminate and should be ignored. pre-scalar overflow increments the th0 register. timer 0 / mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 connected in cascade. the selected input increments tl0. timer 0/ mode 2 (8-bit timer with auto-reload) 12 0 1 xtal1 tx thx (8 bits) tlx (8 bits) overflow interrupt request tfx gatex trx x = 0 or 1 mode 0: 13-bit time/counter mode 1: 16-bit time/counter c/ tx intx timer 0/1 in mode 0 and mode 1
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 30 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from the th0 register. tl0 overflow sets the timer overflow flag (tf0) in the tcon register and reloads tl0 with the contents of th0, whic h is preset by software. when the interrupt request is serviced, hard ware clears tf0. the reload leaves th0 unchanged. timer 0/ mode 3(two 8-bit timers) mode 3: tl0 and th0 operate as 8-bit timers independently. counter tl0 is configured by uses timer?s c/ t and gate in tmod, and tr0 in tcon. th0 worked as a timer (free running at frequency= fosc/12) and takes over by timer 1 interrupt (tf1) and run control bits(tr1). thus, operation of timer 1 is restricted when timer 0 is in mode 3. timer 1 timer 1 can be a timer or event counter in three modes of operation. the configuration for 12 0 1 xtal1 tx tlx (8 bits) overflow interrupt request tfx gatex trx x = 0 or 1 thx (8 bits) reload c/ tx intx timer 0/1 in mode 2,auto-reload 12 0 1 xtal1 t0 tl0 (8 bits) overflow interrupt request gate0 tr0 1/12 fosc th0 (8 bits) tf0 tf1 1/12 fosc tr1 interrupt request overflow c/t0 int0 timer 0 in mode 3 two 8-bit timers
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 31 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 modes 0,1 and 2 are same as timer 0. timer 1?s mode 3 is a hold-count mode. timer 1 is controlled by high-nibble of th e tmod register and bits 7,6,3,and 2 of the tcon register. tmod selects the method of timer gating (gate), timer or counter operation (c/ t ), and mode of operation (m1 and m0). tcon set timer 1 control functions: overflow flag (tf1),run control (tr1),interrupt flag(ie1), and interrupt type control (it1). for normal timer operation (gate = 0), setting tr1 allows timer register tl1 to be incremented by the selected input. setting gate and tr1 allows external pin 1 int to control timer operation. this setup can be us ed to make pulse width measurements. timer 1/ mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer, whic h is set up as an 8-b it timer (th1 register) with a modulo-32 prescalar implemented with the lower 5 bits of the tl1 register. the upper 3 bits of the tl1 register are ignored. pr escalar overflow increment the th1 register. timer1/ mode 1 (16-bit timer) mode 1 configures timer 1 as a16-bit timer with th1 and tl1 connected in cascade. the selected input increments tl1. timer 1/ mode 2 (8-bit timer) mode 2 configures timer 1 as an 8-bit timer ( tl1 register) with automatic reload from the th1 register on overflow. overflow from tl1 se ts overflow flag tf1 in the tcon register and reloads tl1 with the contents of th1, whic h is preset by software. the reload leaves th1 unchanged. timer 1/ mode3 (halt) placing timer in mode 3 causes it to halt and its count. this can be used to halt timer 1 when the tr1 run control bit is not availa ble, i.e., when timer 0 is in mode 3. timer 2 timer 2 is a 16-bit timer/count constructed by {th2, tl2}. the mode control t2mod and the configure t2con control the operation of timer 2. operating modes: capture mode, auto-reload mode, (default) baud rate generator mode, programmable clock-out mode.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 32 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 rclk and/or tclk selects the baud rate generator mode. timer 2 is similar to timer 0 and timer 1. c/ 2 t selects fosc/12 (timer operation) or external pin t2 (counter operation) as the time r register input. setting tf2 to be advanced by the selected input. timer 2/ capture mode timer 2 function as a 16-bit timer or counter. an overflow condition sets bit tf2 to execute isr. set the external enable bit exen2 allows the rcap2hand rcap2l registers to report the current value in timer registers th2 and tl2 in response to a hi-to-lo transition at external input t2ex. the transition at t2 ex also sets bit exf2 on t2con. the exf2 bit, like tf2, can generate an interrupt . tr2 must be enabled in this mode. timer 2/ auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. the timer operates an as an up counter or as an up/down counter, as determined by the down counter enable bit (dcen). at de vice reset, dcen is cleared, so in the auto-reload mode, timer 2 defaults to opera tion as an up counter. tr2 must be enabled when running this mode. up counter operation when dcen = 0, timer 2 operates as an up counter. if exen = 0, timer 2 counts up to ffffh and sets the tf2 overflow flag. the overflow condition lo ads the 16-bit value in the 12 0 1 xtal1 t2 tl2 (8 bits) overflow interrupt request th2 (8 bits) tf2 rcap2h rcap2l t2ex exf2 exen2 tr2 capture c/ t2 timer 2:capture mode
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 33 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 reload/capture registers (rcap2h, rcap2l) into the timer registers (th2, tl2). the values in rcap2h and rcap2l are preset by software. if exen2 = 1, the timer registers are reloaded by either a timer overflow or a high-to-low transition at external input t2 ex. this transition also sets the exf2 bit in the t2con register. either tf2 or exf2 bit can generate a timer 2 interrupt request. tr2 must be enabled when running this mode. up/down counter operation when dcen = 1, timer 2 operates as an up/down counter. external pin t2ex controls the direction of the count. when t2ex is high, ti mer 2 counts up. the timer overflow occurs at ffffh which sets the timer 2 overflow flag (tf2) and generates an interrupt request. the overflow also causes the 16-bit value in rcap2 h and rcap2l to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers (th2, tl2) equals the value stored in rcap2h and rcap2l. the underflow sets the tf2 bit and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows changing the direction of the count. when timer 2 operates as an up/down c ounter, exf2 does not generate an interrupt. this bit can be used to provide 17-bit resolu tion. tr2 must be enable d when running this mode.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 34 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 timer 2/ baud rate generator mode this mode configures timer 2 as a baud rate ge nerator for use with the serial port. select this mode by setting the rclk and/ or tclk bits in t2con. timer 2/ clock-out mode in the clock-out mode, timer 2 functions as a 50%-duty-cycle, va riable-frequency clock. 12 0 1 xtal1 t2 tl2 (8 bits) overflow interrupt request th2 (8 bits) rcap2h rcap2l t2ex exf2 exen2 tr2 tf2 reload c/ t2 timer 2: auto reload mode (decn = 0) t2ex tr2 tl2 (8 bits) overflow th2 (8 bits) rcap2h rcap2l ffh ffh 12 xtal1 t2 0 1 count direction 1 = up 0 = down interrupt request tf2 exf2 (down counting reload value) (up counting reload value) c/ t2 timer 2:auto reload mode (decn = 1)
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 35 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 the input clock advances tl0 at frequency of fosc/2. the timer repeatedly counts to overflow from a preloaded value. at overflo w, the contents of the rcap2h and rcap2l registers are loaded into th2/tl2. in this mode, timer 2 overflows do not generates interrupts. the formula gives the clock-out freq uency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers: watchdog timer the watchdog timer has system reset functi ons. by setting wd1-1, wd1-0 (ckcon, 8eh) to choose 17 2, 20 2, 23 2or 26 2 counter for watchdog timer. as the watchdog timer overflow, sets wdtrstfg (in register wdc on, d8h) and finally resets the mcu. if mcu is reset by watchdog timer , wdtrstfg remains one and por (in register wdcon, d8h) is zero. on the other han d, if risc 52 has been power-on reset, wdtrstfg is zero and por one. clock-out frequency = 4x(65536 - rcap2h, rcap2l) fosc mode auto-reload mode capture mode baud rate generator mode programmable clock-out rclk or tclk (in t2coon) cp/rl2# (in t2mod) t2oe (in t2mod) 0 0 1 x 0 1 x 0 0 0 x 1 timer 2 modes of operation t2oe xtal1 tr2 t2 0 1 tl2 (8 bits) overflow th2 (8 bits) rcap2h rcap2l 2 2 interrupt request exf2 exen2 t2ex c/ t2 timer 2: clock out mode
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 36 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 4.3 serial i/o port both synchronous and asynchronous communicati on modes are provided in the serial i/o port. it operates as uart in three full- duplex modes (modes 1, 2, and 3). asynchronous transmission and reception can occur simultaneous ly and at different baud rates. the serial port also operates in a single synchronous mode (mode 0). mode 0 ? synchronous mode: opera tes at a single baud rate. mode 1 - operate over a wide range of baud rate generated by timer 1 and timer 2. mode 2 - operates at two baud rates. mode 3 - operate over a wide range of baud rates genera ted by timer 1 and timer 2. asynchronous modes, pin-txd: transmits. pin-rxd: receives. synchronous mode (mode 0), pin-txd: clock output. pin-rxd: sends and receives data. sbuf holds received data byte and data to be transmitted, actually consists of two buffers. the receive shift register allo ws reception of a second byte before the byte be read from sbuf. and the 1 st byte will be override by 2 nd byte if software doesn?t read it. the uart sets interrupt bits ti and ri for transmissi on and reception, respectively. both of these two bits share a same interrupt vector. watchdog timer 1 reset rwt ewt xtal 1 overflow counter wd1-1 wd1-0 counting 00 0 0 1 1 11 17 2 20 2 23 2 26 2 wdtrstfg 0000000h
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 37 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 serial port signals function name type description multiplexed with txd o transmit data. in mode 0, txd transmits the clock signal. in modes 1, 2,and 3,txd transmits serial data. p3.1 rxd i/o receive data. in mode 0, rxd transmits and receives serial data. in mode 1, 2,and 3, rxd receives serial data. p3.0 synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand i/o capabilities of device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses which the receive data (rxd) pin transmits or receives a byte of data. the transmission and reception are all least-significant bit (lsb) first. shifts occurred in the last phase (s6p2) of every peri pheral cycle. baud rate = fosc/12. transmission (mode 0) follow these steps to begin a transmission: 1. write to the scon register, clearing bits sm0,sm1, and ren. 2. write 8-bit data to be transmitted to sbuf. subf (transmit) scon write sbuf read sbuf subf (receive) receive shift register mode 0 transmit load sbuf interrupt request ti ri serin i/o control txd rxd serial port block diagram transmit shift register
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 38 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 at s6p2 of the following cycle, hardware shifts the lsb (d0) onto the rxd pin. at s3p1 of the next cycle, the txd pin goes low for th e first clock-signal pulse. shifts continue every peripheral cycle. in the 9 th cycle after the write to sbuf, the msb (d7) is on the rxd pin. at the beginning of the tenth cycle, hardware drives the r xd pin high and assert ti (s1p1) to indicate an end of transmission. reception (mode 0) to start a reception in mode 0, write to the scon register. clear sm0, sm1, and ri and set ren. hardware executes the write to scon in th e last phase (s6p2) of a peripheral cycle. write to scon in the second peripheral cycle, txd goes low at s3p1 for the first clock, and the lsb (d0) is sampled on rxd pin at s5 p2. d0 bit is then shifted into the shift txd write to sbuf shift rxd ti txd write to sbuf shift rxd ri s3p1 s6p1 s6p2 s6p2 s6p2 s6p2 s6p2 s6p2 s6p2 s1p1 d0 d1 d2 d6 d7 s3p1 s6p1 s6p2 s6p2 s6p2 s6p2 s6p2 s6p2 s6p2 s5p2 s1p1 d0 d1 d6 d0 d7 transmit receive mode 0 timing set ren, clear ri
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 39 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 register. as eight shifts at s6p2 of every peripheral cycle, the lsb (d7) is done, then hardware asserts ri (s1p1) to indicate rece ption completed. software can read the received byte from sbuf. asynchronous modes (modes 1, 2, and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame consists of 10 bits. they are one start bit, 8 data bits, and one stop bit. serial data is transmitted via txd pin and received through rxd pin. when a data frame is received, the stop bit is read from rb8 bit in scon. the baud rate is generated by overflow of timer 1 or timer 2. mode 2 and mode 3 modes 2 and 3 are full-duplex, asynchronous mode s. there are 11 bits per transfer frame. they are one start bit, 8 data bi ts (lsb first), one programmable 9 th data bit, and one stop bit is read from the rb8 bit in the scon register. when transmit, the 9 th data bit is written to tb8 bit in scon. the 9 th data bit can be used as a command/data flag. - in mode 2, the baud rate is programmable to 1/32 or 1/64 of the oscillator frequency. - in mode 3, the baud rate is genera ted by overflow of timer 1 or timer 2. transmission (modes 1, 2, 3) follow these steps to initiate a transmission: 1. write to the scon register. select the mode with the sm0 and sm1 bits, and clear the ren bit. for modes 2 and 3, also write the ninth bit to the tb8 bit. 2. write the byte to be transmitted to the sbuf register. this write stars the transmission. reception (modes 1, 2, 3) to prepare for a reception, set the ren bit in the scon register. the actual reception is d0 d1 d2 d3 d4 d5 d6 d7 d8 start bit data byte ninth data bit (modes 2 and 3 only) stop bit data frame (modes 1, 2, and 3)
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 40 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 then initiated by a detected high- to-low transition on the rxd pin. baud rates baud rate for mode 0: the baud rate for mode 0 id fixed at fosc/12. baud rtes for mode 2 mode 2 has two baud rates, which are selected by the smod bit in the pcon register. the following expression defines the baud rate: baud rates for modes 1 and 3 in modes 1 and 3, the baud rate is generated by overflow of timer (default) and/or timer 2. you may select either or both timer(s) to generate the baud rate(s) for the transmitter and/or the receiver. timer 1 generated baud rates (mode 1 and 3) timer 1 is the default baud rate generator fo r the transmitter and the receiver in modes 1 and 3. the baud rate is determined by the timer 1 overflow rate and the value of smod, as shown in the following formula: selecting timer 1 as the baud rate generator to select timer 1 as the baud rate generator: ? disable the timer interrupt by clearing the ie0 register. ? configure timer 1 as a timer or an even t counter (set or clear the c/t bit in the tmod register). ? select timer mode 0-3 by programming the m1, m0 bits in the tmod register. sreial i/o mode 2 baud rate 2 smod fosc 64 sreial i/o mode 1 and 3 baud rate 2 smod timer 1 onerflow rate 32
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 41 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 in most applications, timer 1 is configured as a timer in auto-reload mode (high nibble of tmod = 0010b). the resulting baud rate is defined by the following expression: timer 1 can generate very low baud rates with the following setup: ? enable the timer 1 interrupt by setting the et1 bit in the ie register. ? configure timer 1 to run as a 16 -bit timer (high nibble of tmod = 0001b). ? use the timer 1 interrupt to initiate a 16-bit software reload. timer 2 generated baud rates (modes 1 and 3) timer 2 may be selected as the baud rate generator for the transmitter and/or receiver. the timer 2 baud rate generator mode is similar to the auto-reload mode. a rollover in the th2 register reloads registers th2 and tl2 w ith the 16-bit value on registers rcap2h and rcap2l, which are preset by software. the timer 2 baud rate is expre ssed by the following formula: selecting timer 2 as the baud rate generator program the rclck and tclck bits in the t2 con. a rollover in the th2 register does not set the tf2 bit in the t2con register. and a high-to-low transition at t2ex pin sets the exf2 bit in the t2con register but does not cause a reload from (rcap2h, rcap2l) to (th2, tl2). tt2ex pin cab be used as an additional external interrupt by setting the exen2 bit in t2con. note : please turn off the timer before accessing registers th2, tl2, rcap2h, and rcap2l(clear the tr2 bit in the t2con register). you may configure timer 2 as a timer or a counter . in most applications, it is configured for timer operation (i.e., the c/t2 bit is clear in the t2con register). selecting the baud rate generator(s) 2 smod fosc 32 x 12 x [256 - (th1)] sreial i/o mode 1 and 3 baud rate timer 2 onerflow rate 16 sreial i/o mode 1 and 3 baud rate
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 42 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 rclk bit tclck bit receiver baud rate generator transmitter baud rate generator 0 0 timer 1 timer 1 0 1 timer 1 timer 2 1 0 timer 2 timer 1 1 1 timer 2 timer 2 note: timer 2 advanced for every state time (2 tosc) when it is in the baud rate generator mode. in the baud rate formula that follows , ?rcap2h,rcap2l? denotes the contents of rcap2h and rcap2l taken as a 16-bit unsigned integer: note : when timer 2 is configured as a timer and is in baud rate generator mode, do not read or write the th2 or tl2 registers. the timer is being incremented every state time, and the result of a read or write may not be accurate. in addition, you may read, but not write to, the rcap2 registers; a write may overlap a reload a nd cause write and/or reload errors. xtal1 tr2 t2 0 1 2 c/ t2 timer 2 in baud rate generator mode tl2 (8 bits) th2 (8 bits) rcap2h rcap2l 2 0 1 timer 1 overflow smod 0 1 tclck interrup t request exf2 exen2 t2ex 16 tx clock note: oscillator frequency is divided by 2, not 12. note availability of additional external interrupt 0 1 rclck 16 rx clock 0 1 smod1 16 tx1 clock 16 rx1 clock fosc 32 x [65536 - (rcap2h,racap2l)] sreial i/o mode 1 and 3 baud rate
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 43 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 serial i/o port 1 serial i/o port 1 is the same as serial i/o port mentioned above. rxd1 is at p1.2 and txd1 at p1.3. the serial i/o port 1 has its own buffer (sbuf1, c1h) and control register (scon1, c0h). all functions and structures are the same as serial i/o port. but the only difference is that serial i/o port 1 only uses timer 1 for baud rate at mode 1 and mode 3. the double baud rate bit smode1 is at wdcon (d8h) register. ?.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 44 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 5. electrical specifications dc electrical characteristics (vdd=3.0v20%, ta=10c~40c ) symbol parameter min. typ. max. unit type :pwr vdd analog and digital operating voltage 2.4 3.0 3.6 v icc1f operation current of full function, full speed 30 ma icc1m operation current of full function, 14.3181mhz 14 ma icc2f operation current of mcu, sensor shut down 24 30 ma icc2m operation current of mcu, sensor shut down 8 14 ma icc3 power down mcu, sensor alive 2.5 6 8 ma type :in & i/o reset and sysclk vih input voltage high 2.0 vdd v vil input voltage low 0 0.8 v cin input capacitor 10 pf ilkg input leakage current tbd ua ac operating condition symbol parameter min. typ. max. unit sysclk system clock frequency 14.3181 40 mhz senclk sensor clock frequency 4 mhz pxclk pixel clock output frequency 1.5 mhz
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 45 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 6. package information 6.1 80-pin lcc 6.1.1 pin connection diagram -- top view --
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 46 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 6.1.2 package outline
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 47 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 6.2 48-pin lcc 6.2.1 pin connection diagram -- top view --
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 48 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 6.2.2 package outline pin#1 ref.
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 49 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 7. lens information 7.1 lens for 48-pin lcc package-1 7.1.1 lens digital imaging lens model no: pnl0263226c-p lens specification : efl (f) (focal length): 2.80 mm bfl (back focal length) : 2.50 mm flange back focal length : 1.50 mm f/# : 2.6 diagonal field of view : 32 distortion : < -3.5% lens construction : 1plastic & 1 filter mount : m7 x p0.5 mm ir cut-off filter : 650+/-10 nm @ t50%
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 50 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 7.1.2 holder digital imaging holder model no: pnh0365424-p
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 51 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 7.2 lens for 48-pin lcc package-2 7.2.1 lens
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 52 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 7.2.2 holder
pixart imaging inc. PAC107 a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 53 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.4, aug, 2005 7.3 lens for 80-pin lcc package 7.3.1 lens specification efl : 2.0 mm bfl : 1.89 mm fno: 2.0 flange back focal length : 1.12 mm field of view (for pixart sensor) horizontal field of view : 38.5 vertical field of view: 32.5 diagonal field of view: 40 distortion: -2% 7.3.2 holder

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