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smsc USB5532B revision 1.2 (05-31-13) datasheet datasheet product features general description the smsc USB5532B hub is a 2-port superspeed/hi- speed, low-power, configurable hub controller family fully compliant with the usb 3.0 specification . the USB5532B supports 5 gbps superspeed (ss), 480 mbps hi-speed (hs), 12 mbps full-speed (fs) and 1.5 mbps low-speed (ls) usb signalling for complete coverage of all defined usb operating speeds. the USB5532B supports legacy usb speeds through its usb 2.0 hub controller. the new superspeed hub controller operates in parallel with the usb 2.0 controller, so the 5 gbps superspeed data transfers are not affected by the slower usb 2.0 traffic. the USB5532B supports battery charging on a per port basis. on battery charging enabled ports, the devices provide automatic usb data line handshaking. the handshaking supports usb 1.2 charging downstream port (cdp), dedicated char ging port (dcp) and legacy devices. the USB5532B is confi gured for operation through internal default settings, where custom configurations are supported through an on-chip otp rom, an external spi rom, or smbus. features ? usb 3.0 compliant 5 gbps, 480 mbps, 12 mbps and 1.5 mbps operation, usb pins are 5 v tolerant ? integrated termination and pull-up/pull-down resistors ? two downstream usb 3.0 ports ? supports battery charging of most popular battery powered devices ? usb-if battery charging rev. 1.2 support (dcp & cdp) ? apple portable product charger emulation ? blackberry charger emulation ? chinese yd/t 1591-2006 charger emulation ? chinese yd/t 1591-2009 charger emulation ? supports additional portable devices ? emulates portable/handheld native wall chargers ? charging profiles emulat e a handheld device?s wall charger to enable fast charging (minutes vs. hours) ? enables charging from a mobile platform that is off ? support tablets? high current requirements ? optimized for low-power operation and low thermal dissipation ? vendor specific messaging (vsm) support for firmware upload over usb ? configuration via otp ro m, spi rom, or smbus ? on-chip 8051 c manages vbus, and other hub signals ? 8k ram, 32k rom ? one time programmable (otp) rom: 8 kbit ? includes on-chip charge pump ? single 25 mhz xtal or clock input for all on-chip pll and clocking requirements ? supports jtag boundary scan ? phyboost (usb 2.0) ? selectable drive strength for improved signal integrity ? varisense (usb 2.0) ? controls the receiver sensitivity enabling four programmable levels of usb signal receive sensitivity ? ietf rfc 4122 compliant 128-bit uuid software features ? compatible with microsoft windows 7, vista, xp, mac osx10.4+, and linux hub drivers USB5532B 2-port ss/hs usb hub controller
order numbers: * add ?tr? to the end of any order number to order tape and reel. reel size is 2500 pieces. this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs please contact your smsc sales representative fo r additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. order numbers * description rohs compliant package temperature range USB5532B-5000jzx usb 3.0 2-port hub with vsm & apple/bc 1.2 charging 64qfn 9 x 9mm 6.0 mm exposed pad 0oc to 70oc 2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 2 smsc USB5532B datasheet copyright ? 2013 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. the microchip name and logo, and the microchip logo are registered trademarks of microchip technology incorporated in the u.s.a . and other countries. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
conventions within this manual, the following abbreviations and symbols are used to improve readability. example description bit name of a single bit within a field field.bit name of a single bit (bit) in field x?y range from x to y, inclusive bits[m:n] groups of bits from m to n, inclusive pin pin name zzzzb binary number (value zzzz) 0xzzz hexadecimal number (value zzz) zzh hexadecimal number (value zz) rsvd reserved memory lo cation. must write 0, read value indeterminate code instruction code, or api function or parameter section name section or document name x don?t care <> indicate a parameter is optiona l or is only used under some conditions {,parameter} braces indicate paramete r(s) that repeat one or more times [parameter] brackets indicate a nested parameter. this parameter is not real and actually decodes into one or more real parameters. 2-port ss/hs usb hub controller datasheet smsc USB5532B 3 revision 1.2 (05-31-13) datasheet
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 4 smsc USB5532B datasheet table of contents chapter 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 configurable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 3.1 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 pin descriptions (grouped by function). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 buffer type descriptio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 chapter 4 configuration options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 spi rom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.1 smbus legacy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 smbus advanced mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chapter 5 interfacing to the USB5532B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 operation of the hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 operation of the dual hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 32-byte cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.4 interface operation to spi port when not doing fast reads. . . . . . . . . . . . . . . . . . . . . 19 5.1.5 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 smbus slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 pull-up resistor for smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 protocol implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.3 slave device timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.4 stretching the sclk signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.5 bus reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.6 smbus alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.7 smbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 internal por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.2 external hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 6 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 maximum guaranteed ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.5 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 chapter 7 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 oscillator/crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.1 smbus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.2 usb 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 8 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2-port ss/hs usb hub controller datasheet smsc USB5532B 5 revision 1.2 (05-31-13) datasheet chapter 9 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 appendix a (acronyms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 appendix b (references) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 6 smsc USB5532B datasheet list of figures figure 1.1 USB5532B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3.1 USB5532B 64-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5.1 spi hi-speed read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5.2 spi hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5.3 spi dual hi-speed read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5.4 spi dual hi-speed read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 5.5 spi internally-contro lled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5.6 spi erase sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5.7 spi byte program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5.8 spi command only sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5.9 spi jedec-id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5.10 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5.11 smbus slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5.12 block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5.13 block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5.14 smbus slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6.1 supply rise time model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7.1 typical crystal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7.2 formula to find the value of c1 and c2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 8.1 USB5532B 64 pin qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 figure 8.2 USB5532B recommended pcb land pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2-port ss/hs usb hub controller datasheet smsc USB5532B 7 revision 1.2 (05-31-13) datasheet list of tables table 3.1 USB5532B pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3.2 prt_pwr[2 :1 ] configuration strap states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.3 buffer type descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5.1 spi timing operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5.2 smbus slave timing modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6.2 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7.1 crystal circuit legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8.1 USB5532B 64-pin qfn dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8.2 USB5532B recommended pcb land pattern dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9.1 customer revision histo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 8 smsc USB5532B datasheet chapter 1 block diagram figure 1.1 USB5532B block diagram usb 3.0 hub controller tx ss phy rx ss phy usb2.0 phy usb 2.0 hub controller buffer hs/fs/ls routing logic common block & pll registers & hub i/o vbus control buffer tx ss phy rx ss phy usb2.0 phy buffer buffer tx ss phy rx ss phy usb2.0 phy buffer buffer upstream usb port downstream usb port 1 downstream usb port 2 embedded 8051 c registers & hub i/o 32k rom 8k ram apb bus xdata xdata to apb bridge downstream rx ss bus downstream tx ss bus reset & 8051 boot seq. 2k otp spi master timer spi
2-port ss/hs usb hub controller datasheet smsc USB5532B 9 revision 1.2 (05-31-13) datasheet chapter 2 overview the smsc USB5532B hub is a 2-port, low-power, c onfigurable hub controller fully compliant with the usb 3.0 specification [2] . the USB5532B supports 5 gbps superspeed (ss), 480 mbps hi-speed (hs), 12 mbps full-speed (fs) and 1.5 mbps low-speed (ls) usb signalling for complete coverage of all defined usb operating speeds. all required resistors on the usb ports are integrated into the hub. this includes all series termination resistors and all required pull-down and pull-up resi stors on d+ and d- pins. the over-current sense inputs for the downstream facing ports have internal pull-up resistors. the USB5532B hub includes programmable features such as: ? multitrak tm technology : implements a dedicated transaction translator (tt) for each port. dedicated tts help maintain consistent full-spe ed data throughput regardless of the number of active downstream connections. ? portswap : allows direct alignment of usb signals (d+/d-) to connectors to avoid uneven trace length or crossing of the usb differential signals on the pcb. ? phyboost : enables 4 programmable levels of usb si gnal drive strength in downstream port transceivers. phyboost will also attempt to restore usb signal integrity. 2.1 configurable features the smsc USB5532B hub controller provides a defaul t configuration that is sufficient for most applications. when the hub is initialized in the defau lt configuration, the following features may be configured: ? downstream non-removable ports, where the hub will automatically report as a compound device ? downstream disabled ports ? downstream port power control and over-curr ent detection on a ganged or individual basis ? usb signal drive strength ? usb differential pair pin location the USB5532B hub controllers can alternatively be configured by otp or as an smbus slave device. when the hub is configured by an otp or over smbu s, the following configurable features are provided: ? support for compound devices on a port-by-port basis ? selectable over-current sensing and port power c ontrol on an individual or ganged basis to match the circuit board component selection ? customizable vendor id, product id, and device id ? configurable delay time for filter ing the over-current sense inputs ? indication of the maximum cu rrent that the hub consumes from the usb upstream port ? indication of the maximum current required for the hub controller ? custom string descriptors (up to 30 characters): product, manufacturer, and serial number
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 10 smsc USB5532B datasheet chapter 3 pin information this chapter outlines the pinning configurations for each chip. the detailed pin descriptions are listed by function in section 3.2: pin descriptions (grouped by function) on page 11 . 3.1 pin configurations figure 3.1 USB5532B 64-pin qfn ground pad (must be connected to vss with a via field) smsc USB5532B (top view qfn-64) vdd33 64 usb2dm_dn2 63 usb2dp_dn2 62 usb3dm_rxdn2 61 usb3dp_rxdn2 60 vdd12 59 usb3dm_txdn2 58 usb3dp_txdn2 57 usb2dm_dn1 56 usb3dm_rxdn1 54 usb3dp_rxdn1 53 vdd12 52 usb3dm_txdn1 51 usb3dp_txdn1 50 vdd12 49 usb2dp_dn1 55 tck/ocs1 16 trst 15 14 13 12 11 10 9 8 6 5 4 3 2 1 7 prt_ctl2 32 prt_ctl1 31 sm_dat 30 spi_di 28 spi_do 27 spi_clk 26 spi_ce_n 25 vdd12 24 sm_clk 23 22 21 tdi 20 tdo 19 tms/ocs2 18 vdd33 17 vdd33 48 rbias 47 xtalin/clk_in 46 xtalout 45 usb3dm_rxup 44 usb3dp_rxup 43 vdd12 42 usb3dm_txup 41 usb3dp_txup 40 usb2dm_up 39 usb2dp_up 38 vdd33 37 vbus 36 atest 35 reset_n 34 test 33 nc vdd12 29 nc nc nc nc vdd12 nc nc nc nc nc vdd12 nc nc nc nc indicates pins on the bottom of the device.
2-port ss/hs usb hub controller datasheet smsc USB5532B 11 revision 1.2 (05-31-13) datasheet 3.2 pin descriptions (grouped by function) an n at the end of a signal name indicates that the active (asserted) state occurs when the signal is at a low voltage level. when the n is not present, the signal is asserted when it is at a high voltage level. the terms assertion and negation are used exclusively in order to avoid confusion when working with a mixture of active low and active high signals . the term assert, or asse rtion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate, or negation, indicates that a signal is inactive. table 3.1 USB5532B pin descriptions symbol buffer type description usb 3.0 interface usb3dp_txup io-u usb 3 upstream upstream superspeed transmit data plus usb3dm_txup io-u usb 3 upstream upstream superspeed transmit data minus usb3dp_rxup io-u usb 3 upstream upstream superspeed receive data plus usb3dm_rxup io-u usb 3 upstream upstream superspeed receive data minus usb3dp_txdn[2:1] io-u usb 3 downstream downstream superspeed transmit data plus for ports 1 through 2. usb3dm_txdn[2:1] io-u usb 3 downstream downstream superspeed transmit data minus for ports 1 through 2. usb3dp_rxdn[2:1] io-u usb 3 downstream downstream superspeed receive data plus for ports 1 through 2. usb3dm_rxdn[2:1] io-u usb 3 downstream downstream superspeed receive data minus for ports 1 through 2. usb 2.0 interface usb2dp_up io-u usb bus data these pins connect to the upstream usb bus data signals. usb2dm_up io-u usb bus data these pins connect to the upstream usb bus data signals. usb2dp_dn[2:1] io-u usb downstream downstream hi-speed data plus for ports 1 through 2. usb2dm_dn[2:1] io-u usb downstream downstream hi-speed data minus for ports 1 through 2.
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 12 smsc USB5532B datasheet usb port control prt_pwr[2:1]/ prt_ctl[2:1] o12 usb power enable enables power to usb peripheral devices downstream. note: this pin also provides c onfiguration strap functions. see note 3.1 . vbus i upstream vbus power detect this pin can be used to detect the state of the upstream bus power. spi interface (4 pins) spi_ce_n o12 spi enable spi_clk o12 spi clock spi_do o12 spi serial data out the output for the spi port. note: this pin also provides c onfiguration strap functions. see note 3.2 . spi_di i spi serial data in the spi data in to the controller fr om the rom. this pin has a weak internal pull-down applied at all times to prevent floating. jtag/ocs interface trst i jtag asynchronous reset note: if using the smbus interface, a pull-up on this signal will enable legacy mode, while leav ing it unconnected or pulled- down will enable advanced mode. note: only available in test mode. tck i jtag clock this input is used for jtag boundary scan and has a weak pull-down. it can be left floating or grounded when not used. if the jtag is connected, then this signal will be detected high, and the software disables the pull up after reset. note: only available in test mode. ocs1 over-current sense 1 input from external current monitor indicating an over-current condition. note: this pin also provides c onfiguration strap functions. see note 3.3 . table 3.1 USB5532B pin descriptions (continued) symbol buffer type description
2-port ss/hs usb hub controller datasheet smsc USB5532B 13 revision 1.2 (05-31-13) datasheet tms i jtag tms used for jtag boundary scan. note: only available in test mode. ocs2 over-current sense 2 input from external current monitor indicating an over-current condition. note: this pin also provides c onfiguration strap functions. see note 3.3 . tdi i jtag tdi used for jtag boundary scan. note: only available in test mode. tdo o12 jtag tdo used for jtag boundary scan. note: only available in test mode. misc reset_n is reset input the system uses this active low signal to reset the chip. the active low pulse should be at least 1 s wide. xtalin iclkx crystal input: 25 mhz crystal. this pin connects to either one termi nal of the crystal or to an external 25 mhz clock when a crystal is not used. clk_in external clock input this pin connects to either one termi nal of the crystal or to an external 25 mhz clock when a crystal is not used. xtalout oclkx crystal output the clock output, providing a crystal 25 mhz. when an external clock source is used to drive xtalin/clk_in , this pin becomes a no connect. test ipd test pin treat as a no connect pin or connec t to ground. no trace or signal should be routed or attached to this pin. rbias i-r usb transceiver bias a12.0 k (+/- 1%) resistor is attached from ground to this pin to set the transceiver?s internal bias settings. atest a analog test pin this signal is used for testing the chip and must always be connected to ground. sm_clk i/o12 smbus clock sm_dat i/o12 smbus data pin table 3.1 USB5532B pin descriptions (continued) symbol buffer type description
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 14 smsc USB5532B datasheet note 3.1 the prt_pwr[2:1] pins can opt ionally provide additional configuration strap functions to enable/disable the associated port and configure its battery charging capabilities. configuration strap values are latched on device reset. ta b l e 3 . 2 details the functions associated with the various strap settings. strapping features are enabled by default and can be optionally disabled via the smsc pro-touch software programming tool. for additional information on the pro-touch programming tool, contact your local smsc sales representative. strapping functions are not supported for designs that support ocs but not power switching. note 3.2 the spi_do pin provides an additional spi_spd_sel configuration strap function. spi_spd_sel selects between the 30mhz spi mode when pulled-down to ground (default) and the 60mhz spi mode when pulled-up to vdd33. the spi_spd_sel strap value is latched on power-on reset (por) or reset_n deassertion. note 3.3 the ocs[2:1] pins can optionally provide additi onal configuration strap functions. to set the associated port into the non-removable st ate, the ocs pin must be configured with a pull-down (<10 k to vss). otherwise, the port will be configured in the removable state. configuration strap values are latched on device reset. strapping features are enabled by default and can be optionally disabled via the smsc pro-touch software programming tool. for additional information on the pro-touch programming tool, contact your local smsc sales representative. strapping functions are not supported for designs that support ocs but not power switching. (14) nc - no connect pins digital and power (4) vdd33 3.3 v power (8) vdd12 1.25 v power vss ground pad this exposed pad is the device?s only connection to vss and the primary thermal conduction path. connect to an appropriate via field. table 3.2 prt_pwr[2:1] configuration strap states prt_pwr[2:1] strap setting port state battery charging no pull-up or pull-down enabled disabled pull-down: <10 k to vss disabled n/a pull-up: <10 k and >1 k to vdd33 enabled enabled table 3.1 USB5532B pin descriptions (continued) symbol buffer type description
2-port ss/hs usb hub controller datasheet smsc USB5532B 15 revision 1.2 (05-31-13) datasheet 3.3 buffer type descriptions table 3.3 buffer type descriptions buffer type description i input i/o input/output ipd input with internal weak pull-down resistor ipu input with internal weak pull-up resistor is input with schmitt trigger o12 output 12 ma i/o12 input/output buffer with 12 ma sink and 12 ma source i/osd12 open drain with schmitt trigger and 12 ma sink. iclkx xtal clock input oclkx xtal clock output i-r rbias i/o-u analog input/output de fined in usb specification
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 16 smsc USB5532B datasheet chapter 4 configuration options the USB5532B must be configured in order to correctly function when attached to a usb host controller. the hub can be configured either internally or externally depending on the implemented interface (see chapter 5: interfacing to the USB5532B on page 17 for details). 4.1 spi rom when the spi interface is configur ed, the USB5532B is will perform code execution from an external spi rom. 4.2 smbus two smbus modes (based on the used slave addr ess) are available: legacy and advanced. 4.2.1 smbus legacy mode the smbus legacy mode provides access to all internal usb 2.0 registers, and is enabled based on the 7-bit slave address of 0101100b. the hub will not respond to the general call address of 0000000b. 4.2.2 smbus advanced mode the smbus advanced mode provides access to all usb 2.0 and usb 3.0 registers, and is enabled based on the 7-bit slave address of 0101101b. th e hub will not respond to the general call address of 0000000b. the protocol is based on the smbus bl ock read/write, except the register offset is extended to 16 bits (high byte, low byte).
2-port ss/hs usb hub controller datasheet smsc USB5532B 17 revision 1.2 (05-31-13) datasheet chapter 5 interfacing to the USB5532B the hub will interface to external memory depending on configuration of the USB5532B pins associated with each interface type. the USB5532B will first check to see whether an external spi flash is present. if not, the USB5532B will operate from internal rom. if spi flash is present, the chip will operate from the external ro m. next, the USB5532B will look to receive configuration and commands from an optional smbus master (if pres ent). when smbus is enabled, the smbus can operate in either legacy (usb 2.0 only) or advanc ed mode (access to both usb 2.0 and 3.0 registers). next, the USB5532B will look for (optional) configuration present in the internal otp memory. any register settings that are modifi ed via the smbus interface will overwrite the internal otp settings. 5.1 spi interface the USB5532B is capable of code execution from an external spi rom. on power up, the firmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the code execution begins at address 0x0000 in the exte rnal spi device. if a valid signature is not found, then execution continues from inte rnal rom. the following sections describe the interface options to the external spi rom. 5.1.1 operation of the hi-speed read sequence the spi controller will automatically handle code r eads going out to the spi rom address. when the controller detects a read, the controller drops the spi_ce , and puts out a 0x0b, followed by the 24-bit address. the spi contro ller then puts out a dummy byte. the next eight clocks clock in the first byte. when the first byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more than the last address, the spi controller will clock out one more by te. if the address in anything other than one more than the last address, the spi controller will terminate the transaction by taking spi_ce high. as long as the addresses are sequential, the spi controller will keep clocking in data. figure 5.1 spi hi-speed read operation spi controller spi rom serial to parllel ce# clk si so smsc usb hub address control cache spi_di
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 18 smsc USB5532B datasheet figure 5.2 spi hi-speed read sequence 5.1.2 operation of the dual hi-speed read sequence the spi controller also supports dual data mode (at 30 mhz spi speed only). when configured in dual mode, the spi controller will automatically handle read s going out to the spi rom. when the controller detects a read, the controller drops the spi_ce_n , and puts out a 0x3b, followed by the 24-bit address. the spi controller then puts out a dummy byte. the next four clocks clock in the first byte. the data appears two bits at a time on data out and data in. when the first byte is clocked in a ready signal is sent back to the processor, an d the processor gets one byte. after the processor gets the first byte, the addre ss will change. if the address is one more than the last address, the spi controller wi ll clock out one more byte. if the add ress in anything other than one more than the last address, the spi contro ller will terminate the transaction by taking spi_ce_n high. as long as the addresses are sequential, the spi controller will keep clocking in data. figure 5.3 spi dual hi-speed read operation spi_cen spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d out add. 23 24 add. add. x 39 40 31 32 47 48 55 56 63 64 71 72 80 d out nn+1 d out n+2 d out n+3 d out n+4 msb msb spi controller spi rom 2-serial to 8-parallel ce# clk si so address control cache spi_di smsc usb hub
2-port ss/hs usb hub controller datasheet smsc USB5532B 19 revision 1.2 (05-31-13) datasheet figure 5.4 spi dual hi-speed read sequence 5.1.3 32-byte cache there is a 32-byte pipeline cache, and associat ed with the cache is a base address pointer and a length pointer. once the spi controller detects a jump, the base address pointer is initialized to that address. as each new sequential data byte is fetched, the data is written into the cache, and the length is incremented. if the sequential run exceeds 32 bytes, the base address pointer is incremented to indicate the last 32 bytes fetched. if the USB5532B does a jump, and the jump is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access. 5.1.4 interface operati on to spi port when not doing fast reads there is an 8-byte command buffer: spi_cmd_buf[7:0]; an 8-byte response buffer: spi_resp_buf[7:0]; and a length register that counts out the number of bytes: spi_cmd_len. additionally, there is a self-clearing go bit in the spi_ctl register. once the go bit is set, the device drops spi_ce_n , and starts clocking. it will put out spi_cmd_len x 8 number of clocks. after the first byte, the command, has been sent out, and the spi_di is stored in the spi_resp buffer. if the spi_cmd_len is longer than the spi_cmd_buf, don?t cares are sent out on the spi_do line. this mode is used for program executio n out of inter nal ram or rom. figure 5.5 spi internally-controlled operation spi_cen spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d1 add. 23 24 add. add. x 39 40 31 32 44 47 48 51 52 55 56 59 d2 nn+1 d3 n+2 d4 n+3 d5 n+4 msb msb d1 d2 n n+1 d3 n+2 d4 n+3 d5 n+4 msb 43 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-7,5,3,1 bits-6,4,2,0 spi controller spi rom spi_rsp_buf[7:0] spi_cmd_buf[3:0] spi_cmd_len ce# clk si so smsc usb hub
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 20 smsc USB5532B datasheet 5.1.4.1 erase example to perform a sctr_erase, 32blk_erase, or 64bl k_erase, the device writes 0x20, 0x52, or 0xd8, respectively to the first byte of the comm and buffer, followed by a 3-byte address. the length of the transfer is set to 4 bytes. to do this, the device first drops spi_ce_n , then counts out 8 clocks. it then puts out the 8 bits of command, followed by 24 bits of address of the location to be erased on the spi_do pin. when the transfer is complete, the spi_ce_n goes high, while the spi_di line is ignored in this example. figure 5.6 spi erase sequence 5.1.4.2 byte program example to perform a byte program, the device writes 0x02 to the first byte of the command buffer, followed by a 3-byte address of the location that will be writ ten to, and one data byte. the length of the transfer is set to 5 bytes. the device first drops spi_ce_n , 8 bits of command are clocked out, followed by 24 bits of address, and one byte of data on the spi_do pin. the spi_di line is not used in this example. figure 5.7 spi byte program spi_cen spi_clk 16 23 24 31 15 123 4 05 7 6 add. spi_do spi_di 8 command msb msb add. add. high impedance spi_cen spi_clk 16 23 24 31 15 39 123 4 05 7 6 0x00 spi_do spi_di 8 0xdb msb msb 0xfe /0xff data msb lsb 32 high impedance 0xbf
2-port ss/hs usb hub controller datasheet smsc USB5532B 21 revision 1.2 (05-31-13) datasheet 5.1.4.3 command only program example to perform a single byte command such as the following: - wrdi - wren - ewsr - chip_erase - ebsy - dbsy the device writes the opcode into the first by te of the spi_cmd_buf and the spi_cmd_len is set to one. the device first drops spi_ce , then 8 bits of the command are clocked out on the spi_do pin. the spi_di is not used in this example. figure 5.8 spi command only sequence 5.1.4.4 jedec-id read example to perform a jedec-id command, the device writes 0x9f into the first byte of the spi_cmd_buf and the length of the transfer is 4 bytes. the device first drops spi_ce_n , then 8 bits of the command are clocked out, followed by the 24 bits of dummy bytes (due to the length being set to 4) on the spi_do pin. when the transfer is complete, the spi_ce_n goes high. after the first byte, the data on spi_di spi_cen spi_clk 1234 057 6 spi_do spi_di command msb high impedance
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 22 smsc USB5532B datasheet is clocked into the spi_rsp_buf. at the end of the command, ther e are three valid bytes in the spi_rsp_buf. in this example, 0xbf, 0x25, 0x8e. figure 5.9 spi jedec-id sequence spi_cen spi_clk spi_do spi_di 8 9f msb high impedance 11 12 13 14 15 16 123 4 05 7 6 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bf 25 8e msb msb
2-port ss/hs usb hub controller datasheet smsc USB5532B 23 revision 1.2 (05-31-13) datasheet 5.1.5 spi timing figure 5.10 spi timing table 5.1 spi timing operation name parameter min max unit t fc clock frequency 60 mhz t ceh chip enable high time 50 ns t clq clock to input data 9 ns t dh input data hold time 0 ns t os output set up time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns spi_cen spi_clk spi_di spi_do t dh input data valid t clq output data valid t ov t oh output data valid t os t oh t fc t ceh
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 24 smsc USB5532B datasheet 5.2 smbus slave interface the smbus slave interface is enabled when pull-up resistors are detected on both sm_dat and sm_clk for the first millisecond after reset. for operation in smbus legacy mode, an additional pull- up resistor is required on trst . if the smbus interface is enabled, then the USB5532B will wait indefinitely for the smbus host to configure the de vice. once smbus configur ation is complete, device initialization will proceed. to disable the smbus, a pull-down resistor of 10 k must be applied to sm_dat . if smbus is disabled, the device proceeds dire ctly to device initialization using the internal otp rom. 5.2.1 pull-up resistor for smbus external pull-up resistors (10 k recommended) are required on the sm_dat and sm_clk pins when implementing either smbus mode. figure 5.11 smbus slave connection 5.2.2 protocol implementation typical block write and block read protocols are shown in figure 5.12 and figure 5.13 . smbus ram buffer offset accesses are performed using 7-bit sl ave addressing, an 8- or 16-bit smbus ram buffer offset field (for legacy and advanced modes, res pectively), and an 8-bit data field. the shading shown in the figures during a read or write indicates the hub is driving data on the sm_dat line; otherwise, host data is on the sm_dat line. the smbus slave address assigned to the hub (0101 100b or 0101101b) allows it to be identified on the smbus. the smbus ram buffer offset field is the internal offset in smbus ram to be accessed. the data field is the data that the host is attempting to read/write from/to the smbus ram buffer. note: data bytes are transferred msb first. 5.2.2.1 block write/read the block write begins with a slave address and a write condition. after the command code, the host issues a byte count which describes how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be zero. a block write or re ad allows a transfer maximum of 32 data bytes. smbus master sm_clk sm_dat scl sda vdd 10 k smsc usb hub 10 k
2-port ss/hs usb hub controller datasheet smsc USB5532B 25 revision 1.2 (05-31-13) datasheet note: for the following smbus tables: figure 5.12 block write 5.2.2.2 block read a block read differs from a block write in that the repeated start condition exists to satisfy the i 2 c specification?s requirement for a ch ange in the transfer direction. figure 5.13 block read 5.2.2.3 invalid protocol response behavior note that any attempt to update registers with an invalid protocol will not be updated. the only valid protocols are write block and read block (described above), where the hub only responds to the 7-bit hardware selected slave addresses (0101100b or 010110 1b). additionally, the only valid registers for the hub are outlined in the USB5532B configuration release notes documentation. 5.2.3 slave device timeout devices in a transfer can abort the transfer in prog ress and release the bus when any single clock low interval exceeds 25 ms (t timeout, min ). the master must detect this condition and generate a stop condition within or after the tran sfer of the interrupted data byte. slave devices must reset their communication and be able to receive a new start condition no later than 35 ms (t timeout, max ). note: some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its communications port after a start or stop condition. the sl ave device timeout must be implemented. 5.2.4 stretching the sclk signal the hub supports stretching of the sclk by other devices on the smbus. the hub will stretch the clock as needed. denotes master-to-slave denotes slave-to-master s slave address smbus ram buffer offset wr a 1 7 1 1 8/16 a 1 ... 1 81 byte count = n a data byte 1 a data byte 2 a 81 1 1 88 data byte n a p 1 s s slave address smbus ram buffer offset wr 1 7 1 1 8/16 a 1 slave address rd a 711 ... a 81 1 1 88 1 81 p a a a a byte count = n data byte 2 data byte 1 data byte n
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 26 smsc USB5532B datasheet 5.2.5 bus reset sequence the smbus slave interface resets and returns to the idle state upon a start condition followed immediately by a stop condition. 5.2.6 smbus alert response address the smbalert# signal is not supported by the USB5532B. 5.2.7 smbus timing the smbus slave interface complies with the smbus specification revision 1.0 . see section 2.1, ac specifications on page 3 for more information. figure 5.14 smbus slave timing diagram table 5.2 smbus slave timing modes symbol parameter min max unit f scl sm_clk clock frequency 0 100 khz t hd;sta hold time start condition 4 - s t low low period of the sm_clk clock 4.7 - s t high high period of the sm_clk clock 4 - s t su;sta set-up time for a repeated start condition 4.7 - s t hd;dat data hold time\ 0 - ns t su;dat data set-up time 250 - ns t r rise time of both sm_data and sm_clk signals - 1000 ns t f fall time of both sm_clk and sm_data lines - 300 ns t su;sto set-up time for a stop condition 4 - s t buf bus free time between a stop and start condition 4.7 - s sm_data sm_clk t buf t hd;sta t su;sto t su;sta t su;dat t high t hd;dat t hd;sta t low t r t f
2-port ss/hs usb hub controller datasheet smsc USB5532B 27 revision 1.2 (05-31-13) datasheet 5.3 reset there are two different resets that the device expe riences. one is a hardware reset (either from the internal por reset circuit or via the reset_n pin) and the second is a usb bus reset. 5.3.1 internal por all reset timing parameters are guaranteed by design. 5.3.2 external hardware reset a valid hardware reset is defined as assertion of reset_n for a minimum of 1 s after all power supplies are within operating range. assertion of reset_n (external pin) causes the following: 1. the phy is disabled, and the different ial pairs will be in a high-impedance state. 2. all transactions immediately terminate; no states are saved. 3. all internal registers return to the default state. 4. the external crystal oscillator is halted. 5. the pll is halted.
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 28 smsc USB5532B datasheet chapter 6 dc parameters 6.1 maximum guaranteed ratings notes: ? stresses above the specified parameters could c ause permanent damage to the device. this is a stress rating only. therefore, functional opera tion of the device at any condition above those indicated in the operation sections of this specification are not implied. ? when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac pow er is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. when this possibility exists, it is suggested that a clamp circuit be used. parameter symbol min max units comments storage temperature t a -55 150 c lead temperature c refer to jedec specification j-std- 020d. 1.25 v supply voltage v dd12 -0.5 1.6 v 3.3 v supply voltage v dd33 -0.5 4.0 v voltage on usb+ and usb- pins -0.5 (3.3 v supply voltage + 2) 6 v voltage on any signal powered by vdd33 rail -0.5 v dd33 + 0.3 v voltage on any signal pin powered by the vdd12 -0.5 vdd12 + 0.3 v hbm esd performance 2kv power consumption 1.4 w
2-port ss/hs usb hub controller datasheet smsc USB5532B 29 revision 1.2 (05-31-13) datasheet 6.2 operating conditions figure 6.1 supply rise time model parameter symbol min max units comments USB5532B operating temperature t a 070c die temperature t j 115 c 1.25 v supply voltage v dd12 1.22 1.31 v 3.3 v supply voltage v dd33 3.0 3.6 v 1.25 v supply rise time t rt 0400 s( figure 6.1 ) 3.3 v supply rise time t rt 0400 s( figure 6.1 ) voltage on usb+ and usb- pins -0.3 5.5 v if any 3.3 v supply voltage drops below 3.0 v, then the max becomes: (3.3 v supply voltage) + 0.5 5.5 voltage on any signal powered by vdd33 rail -0.3 v dd33 v t 10% 10% 90% voltage t rtxx t 90% time 100% 3.3 v vss vdd33 90% 100% 1.25 v vdd12
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 30 smsc USB5532B datasheet 6.3 power consumption this section details the power consumption of the device as measured during various modes of operation. all typical measurements were taken with power supplies at nominal values (vdd12 = 1.25 v, vdd33 = 3.3 v). 6.4 dc electrical characteristics typical supply current (ma) typical power (mw) vdd33 vdd12 reset 0.2 5.0 7.0 no vbus 5.6 25.0 48.6 global suspend 92965 2 fs ports 23 70 158 2 hs ports 43 75 231 2 ss ports 17 813 907 2 ss/hs ports 50 873 1077 table 6.1 dc electrical characteristics parameter symbol min typ max units comments is type input buffer low input level v ili 0.8 v ttl levels high input level v ihi 2.0 v hysteresis (is only) v hysi 420 mv i, ipu, ipd type input buffer low input level v ili 0.8 v ttl levels high input level v ihi 2.0 v pull down pd 72 av in = 0 pull up pu 58 av in = vdd33 iclk input buffer low input level v ilck 0.3 v high input level v ihck 0.8 v input leakage i il -10 +10 av in = 0 to vdd33
2-port ss/hs usb hub controller datasheet smsc USB5532B 31 revision 1.2 (05-31-13) datasheet note 6.1 output leakage is measured with the current pins in high impedance. note 6.2 see usb 2.0 specification [1] for usb dc electrical characteristics. input leakage (all i and is buffers) low input leakage i il -10 +10 av in = 0 high input leakage i ih -10 +10 av in = vdd33 o12 type buffer low output level v ol 0.4 v i ol = 12 ma @ vdd33 = 3.3 v high output level v oh v dd33 -0.4 vi oh = -12 ma @ vdd33 = 3.3 v output leakage i ol -10 +10 av in = 0 to vdd33 ( note 6.1 ) i/o12, i/o12pu & i/o12pd type buffer low output level v ol 0.4 v i ol = 12 ma @ vdd33 = 3.3 v high output level v oh v dd33 -0.4 vi oh = -12 ma @ vdd33 = 3.3 v output leakage i ol -10 +10 av in = 0 to vdd33 ( note 6.1 ) pull down pd 72 a pull up pu 58 a io-u ( note 6.2 ) table 6.1 dc electrical ch aracteristics (continued) parameter symbol min typ max units comments
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 32 smsc USB5532B datasheet 6.5 capacitance note 6.3 capacitance t a = 25c; fc = 1 mhz; vdd33 = 3.3 v table 6.2 pin capacitance limits parameter symbol min typ ma x unit test condition clock input capacitance c xtal 2 pf all pins except usb pins and the pins under the test tied to ac ground input capacitance c in 5pf output capacitance c out 10 pf
2-port ss/hs usb hub controller datasheet smsc USB5532B 33 revision 1.2 (05-31-13) datasheet chapter 7 ac specifications 7.1 oscillator/crystal crystal: parallel resonant, fundamental mode, 25 mhz 30 ppm external clock: 50% duty cycle 10%, 25 mhz 30 ppm, jitter < 100 ps rms figure 7.1 typical crystal circuit figure 7.2 formula to find the value of c 1 and c 2 note 7.1 c 0 is usually included (subtracted by the crys tal manufacturer) in the specification for c l and should be set to 0 for use in the calculation of the capacitance formulas in figure 7.2 . however, the pcb itself may presen t a parasitic capacitance between xtalin and xtalout . for an accurate calculation of c 1 and c 2 , take the parasitic capacitance between traces xtalin and xtalout into account. note 7.2 consult crystal manufacturer documentation for recommended capacitance values. table 7.1 crystal circuit legend symbol description in accordance with c 0 crystal shunt capacitance crystal manufacturer?s specification ( note 7.1 ) c l crystal load capacitance c b total board or trace capacitance oem board design c s stray capacitance smsc ic and oem board design c xtal xtal pin input capacitance smsc ic c 1 load capacitors installed on oem board calculated values based on figure 7.2 ( note 7.2 ) c 2 c 1 c 2 c l crystal xtal2 (c s2 = c b2 + c xtal2 ) xtal1 (c s1 = c b1 + c xtal1 ) c 0 c 1 = 2 x (c l ? c 0 ) ? c s1 c 2 = 2 x (c l ? c 0 ) ? c s2
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 34 smsc USB5532B datasheet 7.2 external clock 50% duty cycle 10%, 25 mhz 30 ppm, jitter < 100 ps rms. note: the external clock is based upon 1.2 v cmos logic. xtalout should be treated as a no connect when an external clock is supplied. 7.2.1 smbus clock the maximum frequency allowed on the smbus clock line is 100 khz. 7.2.2 usb 2.0 the smsc hub conforms to all voltage, power, a nd timing characteristics and specifications as set forth in the usb 2.0 specification [1] .
2-port ss/hs usb hub controller datasheet smsc USB5532B 35 revision 1.2 (05-31-13) datasheet chapter 8 package drawing figure 8.1 USB5532B 64 pin qfn package notes: 1. all dimensions are in mill imeters unless otherwise noted. 2. dimension ?b? applies to plated terminals and is m easured between 0.15 and 0.30 mm from the terminal tip. 3. the pin 1 identifier may vary, but is always located within the zone indicated. table 8.1 USB5532B 64-pin qfn dimensions min nominal max remarks a 0.80 0.85 1.00 overall package height a1 0 0.02 0.05 standoff a2 - 0.65 0.80 mold cap thickness d/e 8.90 9.00 9.10 x/y body size d1/e1 8.65 8.75 8.85 x/y mold cap size d2/e2 5.90 6.00 6.10 x/y exposed pad size l 0.30 0.40 0.50 terminal length b 0.18 0.25 0.30 terminal width k 0.90 - - center pad to pin clearance e 0.50 bsc terminal pitch
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 36 smsc USB5532B datasheet figure 8.2 USB5532B recommended pcb land pattern table 8.2 USB5532B recommended pcb land pattern dimensions min (mm) nominal (mm) max (mm) gd/ge 7.93 - - d2?/e2? - 6.00 - x- - 0.28 y- - 0.69 e0.50
2-port ss/hs usb hub controller datasheet smsc USB5532B 37 revision 1.2 (05-31-13) datasheet chapter 9 datasheet revision history table 9.1 customer revision history revision level & date secti on/figure/entry correction rev. 1.2 (05-31-13) all removed industrial temp. sku information from document. section 6.1: maximum guaranteed ratings on page 28 added maximum power consumption row/data to table. section 6.2: operating conditions on page 29 added maximum die temperature row/data to table. section 6.3: power consumption on page 30 added power consumption numbers note 3.1 on page 14 and note 3.3 on page 14 updated note to reflect configuration straps are enabled by default. chapter 3: pin information on page 10 updated trst pin description with the following note: ?if using the smbus interface, a pull-up on this signal will enable legacy mode, while leaving it unconnected or pulled-down will enable advanced mode.? chapter 8: package drawing on page 35 updated recommended land pattern drawings and information.
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 38 smsc USB5532B datasheet rev. 1.1 (03-05-13) ordering codes updated ordering codes to for a2 material ordering codes corrected tape and reel quantity from 3000 to 2500. section 3.2: pin descriptions (grouped by function) on page 11 added note 3.1 and note 3.3 explaining the configuration strap functions on the prt_pwrx and ocsx pins. section 5.1.2: operation of the dual hi-speed read sequence on page 18 updated first sentence to state that dual data mode is supported only at an spi speed of 30 mhz chapter 5: interfacing to the USB5532B on page 17 clarified interface ordering explanation. section 5.2: smbus slave interface on page 24 removed ?either an external i2c (if present) and? from last sentence of section. section 5.2: smbus slave interface on page 24 added additional sentence: ?for operation in smbus legacy mode, an additional pull-up resistor is required on trst .? section 5.2.2: protocol implementation on page 24 , figure 5.12: block write on page 25 , figure 5.13: block read on page 25 updated ?register address? references to ?smbus ram buffer offset?. spi_do pin description & note 3.2 added note to descr ibe the spi_spd_sel configuration strap function on the spi_do. all removed references to gpios and leds rev. 1.0 (09-06-12) all initial revision. table 9.1 customer revision history revision level & date secti on/figure/entry correction
2-port ss/hs usb hub controller datasheet smsc USB5532B 39 revision 1.2 (05-31-13) datasheet appendix a (acronyms) i 2 c ? : inter-integrated circuit 1 ocs: over-current sense pcb: printed circuit board phy: physical layer pll: phase-locked loop qfn: quad flat no leads rohs: restriction of hazardou s substances directive scl: serial clock sie: serial interface engine smbus: system management bus tt: transaction translator 1.i 2 c is a registered trademark of philips corporation.
2-port ss/hs usb hub controller datasheet revision 1.2 (05-31-13) 40 smsc USB5532B datasheet appendix b (references) [1] universal serial bus specification, version 2. 0, april 27, 2000 (12/7/2000 and 5/28/2002 errata) usb implementers forum, inc. http://www.usb.org [2] universal serial bus specificatio n, version 3.0, november 13, 2008 usb implementers forum, inc. http://www.usb.org [3] system management bus specification, version 1.0 smbus. http://smbus.org/specs/ [4] microchip 24aa02/24lc02b (revision c) microchip technology inc. http://www.microchip.com/

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