caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright intersil corporation 1998 1 tm hIP2030 30v mct/igbt gate driver description the hIP2030 is a medium voltage integrated circuit (mvic) capable of driving large capacitive loads at high voltage slew rates (dv/dts). this device is optimized for driving 60nf of mos gate capacitance at 30v peak to peak in less than 200ns. the half bridge gate driver is ideal for driving mos controlled thyristor (mct) and igbt modules. the architecture of the hIP2030 includes four comparator input channels, a 5v regulator, a 12v clamp, and a high side charge pump. the device provides the user with the ability to control minimum low time (mlt) and minimum high time (mht) at the gate channel output (go) by varying two exter- nal capacitances. in addition, the device contains two uncommitted comparator channels (channels a and b) that can be used as monitors (temperature sensing), indicators (leds or opto-couplers), input signal conditioning (both con- tain schmitt triggers), or oscillators. the power requirements of the hIP2030 are low. the driver can be easily con?ured to operate in one of three power con?urations. this allows the use of a small pcb mount- able transformer or battery to provide isolated power to the driver chip. the hIP2030 supplies high output current drive to large capacitive loads and requires few external components to implement a wide variety of mos gate driver circuits. features polarity gate drive high output voltage swing . . . . . . . . . . . . . . . . . . . . 30v peak output current . . . . . . . . . . . . . . . . . . . . . . . . 6.0a fast rise time . . . . . . . . . . . . . . . . . .200ns at 60,000pf ability to interface and drive p-mcts programmable minimum on/off time gate output inhibit latch 5v reference . . . . . . . . . . . . . . . . . . .sinks up to 30ma high side charge pump 120khz operation. . . . . . . . . . . . . . . . . . . . . at 15,000pf applications motor controllers uninterruptible power supplies resonant inverters static circuit breakers inverters converters arc welders ordering information part number temperature range package hIP2030im -40 o c to +110 o c 28 lead plcc july 1998 pinout hIP2030 (plcc) top view ao go p0 pos bo cpa clmp a+ a- p+ nc lo b1+ b1- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 b2+ l- l+ r- b2- g- r+ mht reg p- cpb nc g+ mlt functional block diagram + - + - + - + - + - 25 24 26 21 19 23 20 22 15 16 1 2 3 4 5 6 7 8 11 12 9 10 min low time latch logic power up reset charge pump ao bo lo pos cpa cpb p+ go p0 clmp p- reg a 1 2 l r g cmos pmos nmos mlt mht + - + - min high time 17 28 13 14 q file number 3691.3 p ar t withdra wn pr ocess obsolete no new designs
2 speci?ations hIP2030 - absolute maximum ratings thermal information gate channel supply voltage, p+ to p- . . . . . . . . . . . . . . . -0.5v to 32v logic supply voltage, p0 to p- . . . . . . . . . . . . . . . . . . . . . . . . 7v to 18v all other pin voltages (a+, a-, b1+, b1-, b2+, b2-, l+, l-, r+, r-) . . . . .(p-)-0.5 to (p+)+0.5 thermal resistance ja plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 o c/w storage temperature range. . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. recommended operating conditions t j = -40 o c to +150 o c unless otherwise noted, all voltages referenced to p- gate channel supply voltage, p+ to p- . . . . . . . . . . . . . . . -0.5v to 30v logic supply voltage, p0 to p- . . . . . . . . . . . . . . . . . . . . . . . 10v to 15v all other pin voltages (a+, a-, b1+, b1-, b2+, b2-, l+, l-, r+, r-) . . . . . (p-)+2v to (p0)+2v max output source current, channels a, b . . . . . . . . . . . 10ma max output sink current, channels a, l. . . . . . . . . . . . . . 10ma min load current, reg to p- . . . . . . . . . . . . . . . . . . . . . . . . 2ma (required for proper chip operation) max load current, reg to p-. . . . . . . . . . . . . . . . . . . . . . . 30ma static electrical speci?ations p0 to p- = 15v, p+ to p- = 30v, p- = 0v, reg to p- = 2ma. full temp t j = -40 o c to +150 o c symbol parameter test conditions temp min typ max units i p0 p0 quiescent supply current full - 3.5 5 ma i p+ p+ quiescent supply current +25 o c- 1 10 a full - - 250 a i qpos pos quiescent supply current osc freq = 100khz full - 3 5 ma bv p+ p+ to p- breakdown voltage i bv = 100 a full 30 35 - v v reg regulator voltage, p0 to reg i reg = 2ma +25 o c 4.4 5.2 6.0 v full 4.0 - 6.5 v r reg regulator impedance, p0 to reg i reg = 10ma, 30ma full 3 8 17 ? v clmp clamp voltage, clmp to p- i clmp = 15ma full 11 12.5 14 v r clmp clamp impedance, clmp to p- i clmp = 15ma, 30ma full 7 20 32 ? f cp charge pump frequency full - 200 - khz d cp charge pump duty cycle full - 50 - % vo cp charge pump v out, p+ to p- ip+ = 500 a full 28 28.5 29 v vo cp charge pump v out, p+ to p- ip+ = 4ma full 26.5 27.5 28.5 v i in comparator input leakage vin cmp = vp0/2 full - .01 1 a v os comparator offset voltage v cm = vp0/2 full - 10 50 mv vcm comparator common mode voltage range full (vp-)+2 - vp0+2 v rgo src go output rds, sourcing i src = 2a +25 o c - .6 1 ? full - - 1.5 ? rgo snk go output rds, sinking i snk = 2a +25 o c- 2 3 ? full - - 4 ? rds src ao, bo output rds, sourcing i src = 10ma +25 o c - 85 150 ? full - - 175 ? rds snk ao, lo output rds, sinking i snk = 10ma +25 o c - 75 125 ? full - - 150 ? dynamic electrical speci?ations p0 to p- = 15v, p+ to p- = 30v, p- = 0v, ref to p- = 2ma. full temp t j = -40 o c to +150 o c symbol parameter test conditions temp min typ max units th min min go output hi duration c load = 20pf full 600 1100 1600 ns tl min min go output lo duration c load = 20pf full 200 750 1500 ns tp lhab prop delay, lo - hi, chs. a, b c load = 300pf full - 90 150 ns tp lhl prop delay, lo - hi, ch. l c load = 300pf, v od = 2v full - 115 170 ns
3 speci?ations hIP2030 tp hla prop delay, hi - lo, ch. a c load = 300pf, v od = 2v full - 200 320 ns tr ab rise time, channels a, b c load = 300pf, v od = 2v full - 20 50 ns tf al fall time channels a, l c load = 300pf, v od = 2v full - 50 75 ns tp lhg prop delay, lo - hi, ch. g c load = 60nf, v od = 2v +25 o c - 135 200 ns full - - 275 ns tp hlg prop delay, hi - lo, ch. g c load = 60nf, v od = 2v +25 o c - 280 400 ns full - - 475 ns tr g rise time, channel g c load = 60nf, v od = 2v +25 o c - 150 300 ns full - - 450 ns tf g fall time channel g c load = 60nf, v od = 2v +25 o c - 235 340 ns full - - 500 ns timing waveforms figure 1. figure 2. dynamic electrical speci?ations p0 to p- = 15v, p+ to p- = 30v, p- = 0v, ref to p- = 2ma. full temp t j = -40 o c to +150 o c (continued) symbol parameter test conditions temp min typ max units lo (output) l ? r ? g ? (low) (high) (last state) go (output) go g ? lo r ? l ? (output) (output) (high) (last state) (undefined state) ? refers to the state of the input comparator output
4 hIP2030 pin descriptions pin number symbol description 1 a- negative comparator input for a channel. this input has a protected comparator input that is clamped to p+ and p- through a 330 ohm resistor. the common mode input voltage, for the protected comparator input, rang- es from (vp-) +2v and (vp0) +2v. the cmos output ao (pin 24) is low when input a- is ?rue and input a+ is ?alse? 2 a+ positive comparator input for a channel. the cmos output ao (pin 24) is high when input a+ is ?rue and input a- is ?alse? 3 b1- negative comparator input for b1 channel. the output of the internal b1-channel comparator is low when input b1- is ?rue?and input b1+ is ?alse? 4 b1+ positive comparator input for b1 channel. the output of the internal b1-channel comparator is high when input b1+ is ?rue?and input b1- is ?alse? 5 b2- negative comparator input for b2 channel. the output of the internal b2-channel comparator is low when input b2- is ?rue?and input b2+ is ?alse? 6 b2+ positive comparator input for b2 channel. the output of the internal b2-channel comparator is high when input b2+ is ?rue?and input b2- is ?alse? 7 l- negative comparator input for l (latch) channel. latch mode operation is disabled when l- is ?rue and l+ is ?alse? nmos output lo (pin 26) is active high in a no latch state. the go output (pin 23) is controlled by g- channel inputs. 8 l+ positive comparator input for l (latch) channel. latch mode operation is enabled when l+ is ?rue and l- is ?alse? nmos output lo (pin 26) is active low in latch state. the go output (pin 23) goes to a ?-mct off state (vgo = vp+) and is controlled by the internal l-channel latch; which bypasses the g-chan- nel inputs. latch mode always overrides the r-channel. 9 r- negative comparator input for r (reset) channel. reset mode, for the internal l-channel latch, is disabled when r- is ?rue?and r+ is ?alse? 10 r+ positive comparator input for r (reset) channel. reset mode, for the internal l-channel latch, is enabled when r+ is ?rue and r- is ?alse? reset mode (enabled) unlatches the internal l-channel latch; which allows the g-channel inputs to control the go output (pin 23). latch mode must be disabled to operate in reset mode. 11 g- negative comparator input for g (main) channel. the g-channel output (pin 23) goes to a ?-mct off state (vgo = vp+) when g- is ?rue?and g+ is ?alse? 12 g+ positive comparator input for g (main) channel. the g-channel output (pin 23) goes to a ?-mct on state (vgo = vp-) when g+ is ?rue?and g- is ?alse? 13 mlt input for programmable minimum low time timing capacitor (c t ). mlt is set by connecting a capacitor between p0 (pin 22) and mlt (pin 13). mlt is approximated by the equation: (c t )(5v)/(100ua). 14 mht input for programmable minimum high time timing capacitor (c t ). mht is set by connecting a capacitor be- tween p0 (pin 22) and mht (pin 14). mht is approximated by the equation: (c t )(5v)/(100 a). mht becomes minimum low time function for turning on n-mct s. 15 reg 5v regulator output. an opto-coupler or ?er-optic receiver may be power by connecting the positive voltage pin of the ic to p0 (pin 22) and the ic common to reg (pin 15). the internal regulator (reg) must sink 2ma of current minimum for the mlt and mht functions to work properly. 16 p- chip negative supply. this pin is generally used as the dc bias power supply common. the regulator transistor, charge pump and logic are referenced to p- (pin 16). 17 cpb output of the charge pump oscillator inverter stage. a 0.47 f capacitor is normally connected from this output to cpa (pin 19). 18 nc unused pin. 19 cpa input of the charge pump steering diode. a 0.47 f capacitor is normally connected from this input to cpb (pin 18).
5 hIP2030 20 clmp an internal 12v clamp that can be used for additional regulation across p0 (pin 22) and p- (pin 16). 21 pos positive supply rail for the charge pump. 22 p0 chip positive supply. this pin is generally used as the dc bias power supply positive input. 23 go main channel output (gate output). the gate output controls the switching of power devices and is normally connected to the p-mct gate. go can sink or source greater than 6a peak at vp+ equal to 30v. 24 ao a-channel output. ao has a cmos output that switches from p0 (pin 22) to p- (pin 16). ao can source or sink 10ma of dc current. 25 bo b-channel output. b-channel has a pmos output that connects bo to p0 (pin 22) when turned on. bo can source 10ma of dc current from p0. 26 lo l-channel output. l-channel has a nmos output that connects lo to p- (pin 16) in latch mode. lo can sink 10ma of dc current. 27 nc unused pin. 28 p+ high side output. connects to the output of a charge pump steering diode. a 10.0 f capacitor is normally con- nected from this output to p0 (pin 22) to supply the high side of the gate voltage. pin descriptions (continued) pin number symbol description hIP2030 application information the intersil photo-coupled isolated gate drive (hpcigd) circuit, illustrated in figure 3, contains four subcircuits: a single supply dc bias, a regulated voltage divider reference, a local energy source capacitance, and a photo-couple receiver. the single supply dc bias circuit , shown in figure 3, con- sists of a single external dropping resistor (r1) connected between pins p+ (u1-28) and p0 (u1-22). when an input volt- age of 30v is applied across pins p+ and p- (u1-16), r1 forms a resistive divider network with the input impedance located between pins p0 and p- (rvp0). this allows the circuit designer to adjust the value of r1 to obtain a desired bias volt- age between pins p0 and p- (vp0.). the value of rvp0 can be calculated by evaluating the equivalent quiescent input imped- ance (rq) and the 5v reference impedance (rr) as parallel resistances. the values for r1, rq, rr, and rvp0 can be determined by using equations 1(a, b, c, d) as shown in appendix a, exercise 1.1. the regulated voltage divider reference is comprised of two resistors (r3 and r4) connected in series and are located across pins p0 and reg. this voltage divider provides a stable voltage reference to all of the hIP2030 comparator inputs. resistors r3 and r4 are selected equal in value to create a midpoint bias reference between the peak to peak input signal of u2. also, the midpoint bias method ensures that input signals generated from u2 and midpoint bias reference voltages are within a safe common mode voltage range of the comparators. the local energy source capacitances , c1 and c2, are needed to supply the charge required to drive large capaci- tance loads at high dv/dts. the hpcigd circuit uses low cost ?versized tantalum capacitors (c = 10 f) that are used for c1 and c2. if rise times and overshoot are critical, ceramic capaci- tors with low esl and esr should be used to improve gate drive signals. in a power circuit, where the gate driver is exposed to high dv/dts, the network of c1 and c2 directs noise current away from the hIP2030. this allows the hfoigd circuit to operate well in half bridge power circuits that use a trans- former coupled power source. the photo-coupled receiver subcircuit consists of u2, r5, c4, and r6. u2 is a photocoupler which combines an infrared emitter diode (ired) and a high speed photo detector to translate light pulses to low voltage input signals. these signals are routed to the g channel and are used to control the output go. compo- nent r5 is used to limit the dc current through the ired when the input signal voltage switches to its most positive level. a wide range of input voltages may be accommodated by varying r5 to limit the ired current to 25ma. c4 is a speed up capacitor and is selected to match the forward bias capacitance of the ir diode. the last component, r6, is an optional part and is intended to be a termination resistor with the value set by the user. the intersil hIP2030 evaluation board (hIP2030eval) is a printed circuit board (pcb) developed to help evaluate the performance of the hIP2030 mct/igbt driver ic in power switching circuits. the component layout of the hIP2030db circuit enables the user to conveniently populate the pcb for either photo-coupled or fiber-optic receivers. in addition, the pcb layout has provisions for ?n board prototyping and spe- cial function components. this facilitates the gate drive circuit design and allows the user to exercise the internal architec- ture and special functions of the hIP2030. the schematic of the hIP2030db, illustrated in figure 4, uses the basic hpcigd circuitry and has provisions for ?n board prototyp- ing?and special function components.
6 hIP2030 figure 3. intersil photo-coupled isolated gate drive table 1. logic inputs outputs glrlogo 000lsh 001hh 010lh 011lh 100lsu 101hl 110lh 111lh 1 = input true 0 = input false u = undefined ls = last state ao go p0 pos bo cpa clmp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 b2+ l- l+ r- b2- g- r+ b1+ b1- a+ a- p+ nc lo g+ mlt reg p- cpb nc mht u1 intersil hIP2030 28 lead plcc r3 r4 tlp2601 u2 5v - + signal control r5 p- c1 p+ r2 c2 c3 a g k pmct gate return p0 r snubber l snubber l load c snubber c source v source pwr gnd power circuit r1 r6 c4
7 hIP2030 figure 4. intersil hIP2030 evaluation board (note 9) notes: 1. capacitors c5 and c6 are special function components which control mlt and mht. 2. asymmetrical gate drive may be obtained by opening j2 and adjusting r1 and r2 for the desired voltage ratio. 3. insert c7 for charge pump operation. 4. open j3 to disable the charge pump oscillator. 5. open j1 to disable the internal 12v regulator. 6. r5 is added for noise rejection at high cdv/dts. 7. the internal 5v reference (ref) must be operational for mht and mlt functions to work properly. 8. p1 - p12 are access pads for all comparator inputs. 9. request intersil file #3918 for a full description of the hIP2030eval board. p0 c5 c6 r2 c2 10 f c7 r3 1k r4 1k jp1 jp2 c4 47pf r6 510 r13 r14 r11 10 r8 10 r12 j1 g gr p+ p0 p - 30vdc j2 j3 5v input - + mos gate r9 820 8 7 6 5 4 3 2 1 tlp2601 r1 c1 10.0 p1 p2 p3 p4 p5 p7 p9 u2 r10 signal r5 100 p - po 0.10 p+ jp3 go p0 pos cpa clmp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 b2+ l - l+ r - b2 - g- r+ b1+ b1- a+ a- p+ nc g+ mlt reg p- cpb nc mht u1 hIP2030 p11 p6 p8 p10 p12 bo ao lo c3 r7 1k
8 hIP2030 typical performance curves figure 5. supply current (ip0) vs supply voltage (p0) figure 6. supply current (ipos) vs supply voltage (pos) figure 7. regulator voltage vs load current figure 8. clamp voltage vs clamp current 8 1012141618 1.0 1.5 2.0 2.5 3.0 3.5 4.0 voltage +100 o c +150 o c +25 o c 0 o c -40 o c supply current (ma) 8 9 10 11 12 13 14 0.0 0.5 1.0 1.5 2.0 2.5 3.0 voltage (charge pump) +150 o c +100 o c +25 o c 0 o c -40 o c supply current (ma) 2468101214161820 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 load current (ma) regulator voltage (v) -40 o c 0 o c +25 o c +100 o c +150 o c 2 4 6 8 101214161820 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 clamp current (ma) clamp voltage (v) -40 o c 0 o c +25 o c +100 o c +150 o c
9 figure 9. propagation delay vs voltage overdrive for a, b1, and b2 channels figure 10. propagation delay vs voltage overdrive for g channel typical performance curves (continued) 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 50 100 200 300 500 overdrive voltage (v) propagation delay (ns) +150 o c +100 o c +25 o c 0 o c -40 o c 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 50 100 200 300 500 overdrive voltage (v) propagation delay (ns) +150 o c +100 o c +25 o c 0 o c -40 o c 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 50 100 200 300 500 overdrive voltage (v) propagation delay (ns) +150 o c +100 o c +25 o c 0 o c -40 o c 140 160 180 200 -25 0 +25 +50 +75 +100 +125 +150 temperature ( o c) frequency (khz) hIP2030 appendix a exercises exercise 1.1 q: how do i calculate the value of the series dropping resis- tor r1, shown in figure 3? a: the values for r1, r q ,r r and r vpo can be determined by using equations 1 (a, b, c, and d). where: v po = voltage between pins p0 and p- (u1 - u22 and u1 - u16). i qpo = quiescent current ?wing into pin p0. i qpto = quiescent current of the hbr-2521 ?er- optic receiver. i vdr = current ?wing through r3 and r4 (volt- age divider reference). i rp = current ?wing through pull up resistor r2 (in ?n?or ?ff?state) r q v po i qpo ------------- - = (eq. 1a) r r v po i opto i vdr i rp ++ ----------------------------------------------------- = (eq. 1b) r vpo 1 1 r q -------- - 1 r r -------- + ------------------------ - = (eq. 1c) the maximum value of r1 can easily be determined in four design steps: 1. assume the following values: v in = 30v dc i qpo = 2.75ma at v p0 = 15v i opto = 5ma i vdr = 2.5ma i rp(on) = 5ma, r2 = 1k, vr2 = 5v 2. select a usable value of v p0 between 7v and 15v dc. use v p0 = 15v 3. solve for r vp0 using equations 1 (a, b, and c): 4. solve for r1 using equation 1(d): r q 15v 2.75ma ------------------ - 5.45k == r r 15v 5ma 2.5ma 5ma ++ () -------------------------------------------------------- - 1.20k == r vp0 1 1 5.45k ------------- - 1 1.20k ------------- - + ---------------------------------- - 984 == r1 r vp0 v in v p0 () v p0 --------------------------------------------- - = (eq. 1d) r1 984 30v 15v () 15v --------------------------------------- 984 ==
10 hIP2030 n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 1 3/95 notes: 1. controlling dimension: inch. converted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allow- able mold protrusion is 0.010 inch (0.25mm) per side. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ??is the number of terminal positions. a1 a seating plane 0.020 (0.51) min view ? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ??typ. 0.004 (0.10) c -c- d2/e2 c l -c- plastic leaded chip carrier packages (plcc)
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