www.siliconstandard.com 1 of 7 n-channel insulated-gate bipolar transistor v ces 450v v ce(sat) 5v typ. i cp 130a the ssm20g45e acheives fast switching performance with low gate charge without a complex drive circuit. it is suitable for use in short-duration, high-current strobe pb-free; rohs-compliant to-251 (ipak) product summary description notes: 1.pulse width must be limited to avoid exceeding the safe operating area. 2.pulse width <300us, duty cycle <2%. applications, such as still-camera flash. the SSM20G45EGH is in a to-252 package, which is widely used for commercial and industrial surface-mount applications. the through-hole version, the ssm20g45egj in to-251, is available for vertical mounting, where a small footprint and to-252 (dpak) g d s to-252 (suffix h) g d s to-251 (suffix j) is required on the board, and/or an external heatsink is to be attached. these devices are manufactured with an advanced process, providing improved on-resistance and switching performance. the gate has internal esd protection. absolute maximum ratings symbol parameter value units v ces v ge v v gep i cp a p d t stg t j symbol parameter value units r q jc maximum thermal resistance, junction-case 6 c/w collector-emitter voltage 450 v gate-emitter voltage 6 pulsed gate-emitter voltage 8 v pulsed collector current 1 130 total power dissipation, t c = 25c 20 w -55 to 150 c operating junction temperature range -55 to 150 c thermal characteristics storage temperature range ssm 20g45e g h/j 5 /16/200 6 re v. 3 . 0 1
ssm 20g45e g h/j 5 /16/200 6 re v. 3 . 0 1 electrical characteristics tj = 25c (unless otherwise specified) symbol min. typ. max. units i ges - - 10 ua i ces - - 10 ua v ce(sate -58v v ge(th) - - 1.2 v q g -5 1- nc q ge -2- nc q gc - 5.4 - nc t d(on) - 5.5 - ns t r -7 2- ns t d(off) - 640 - ns t f - 2.6 - us c ies - 2095 - pf c oes - 145 - pf c res -3 5- pf v cc =200v gate-emitter charge parameter reverse transfer capacitance v ce =450v, v ge =0v v ge =4.5v, i cp =130a (pulsed) v ce =v ge , i c =250ua i c =40a v ce =300v v ge =5v v ce =25v test conditions collector-emitter saturation voltage gate threshold voltage total gate charge gate-emitter leakage current collector-emitter leakage current v ge =6v, v ce =0v turn-off delay time v ge =0v i c =40a r g =25w rise time gate-collector charge turn-on delay time v ge =5v fall fime input capacitance output capacitance f=1.0mhz www.siliconstandard.com 2 of 7
www.siliconstandard.com 3 of 7 ssm 20g45e g h/j 5 /16/200 6 re v. 3 . 0 1 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. collector current vs. fig 4. collector- emitter saturation voltage gate-emitter voltage vs. case temperature 0 40 80 120 160 024681 0 12 v ce , collector emitter voltage (v) i c , collector current ( a) t c =25 o c v g =5.0v v g =4.5v v g =4.0v v g =3.0v v g =2.0v v g =1.0v 0 40 80 120 024681 0 12 v ce , collector-emitter voltage (v) i c , collector current ( a) t c =150 o c v g =5.0v v g =4.5v v g =4.0v v g =3.0v v g =2.0v v g =1.0v 0 40 80 120 160 0123456 v ge , gate- emitter voltage (v) i c , collector current ( a) t c =25 o c t c =70 o c t c =100 o c t c =150 o c v ce =8v 0 2 4 6 8 10 12 0 20 40 60 80 100 120 140 160 t c , case temperature ( o c ) v ce(sat) , saturation voltage ( v) i c = 130a i c = 100a i c = 70a i c = 35a v ge = 4.5 v
www.siliconstandard.com 4 of 7 SSM20G45EGH/j 5/16/2006 rev.3.01 fig 5. gate-emitter cut-off voltage fig 6. safe operating area vs. case temperature fig 7. collector vs. collector-emitter voltage fig 8. gate charge waveform 0 0.5 1 1.5 -50 0 50 100 150 t c , case temperature ( o c ) v ge(th) gate threshold voltage ( v) 0 2 4 6 8 0 1 53 04 56 07 5 q g , gate charge (nc) v ge , gate-e m itter voltage (v) i cp =40a v ce =300v 0 40 80 120 160 02468 v ge , gate-emitter voltage (v) i cp , peak collector current ( a) v g =4.5v t c = 25 o c 10 100 1000 10000 1 8 15 22 29 v ce , collector-emitter voltage (v) capacitance (pf) f =1.0mhz cies coes cres
www.siliconstandard.com 5 of 7 SSM20G45EGH/j 5/16/2006 rev.3.01 fig 9. switching time test circuit fig 10. switching time waveform fig 11. gate charge test circuit fig 12. application test circuit t d(on) t r t d(off) t f v ce v ge 10% 90% v =200v to the oscilloscope - + 5v c g e v ce v ge r r c g cc 300v to the oscilloscope - + c g v ce v ge i c i g 1~3 ma e v cm v cm = 300v c m = 160uf i cp = 130a v g = 5v + _ c m r g v trig igbt v g flasher
www.siliconstandard.com 6 of 7 physical dimensions: to-251 (i-pak) ssm 20g45e g h/j 5 /16/200 6 re v. 3 . 0 1 millimeters min nom max a 2.20 2.30 2.40 a1 0.90 1.20 1.50 b1 0.50 0.60 0.70 b2 0.60 0.72 0.90 c 0.45 0.50 0.60 c1 0.45 0.50 0.55 d 6.40 6.60 6.80 d1 5.20 5.35 5.50 e 6.80 7.00 7.20 e1 5.40 5.60 5.80 e2 1.40 1.50 1.60 e -- 2.30 -- f 7.20 7.50 7.80 f1 1.50 1.60 1.80 1.all dimensions are in m illimeters. 2.dimensions do not include mold protrusions. symbols a c1 a1 c e d e2 e1 f1 e b1 b2 f d1 e physical dimensions: to-252 (d-pak) millimeters to-252-3l max. 2.80 a s y m b o l min. 1.80 0.13 5.90 0.65 0.89 6.30 7.00 1.00 0.00 4.80 0.35 0.40 5.10 6.00 7.80 1.00 0.50 0.50 0.40 c2 see view b a h b3 a a e e d l3 l4 c base metal with plating b section a-a seating plane view b a1 l l1 gauge pla ne l2 0 8 11.05 2.55 2.03 1.20 2.30 bsc a1 b b3 c2 e d c h l l1 2.20 3.05 l2 0.35 0.65 l4 l3 e
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 7 of 7 part marking packing: moisture sensitivity level msl3 to-251: 1000pcs in tubes packed inside a moisture barrier bag (mbb). part number: 20g45egh or 20g45egj xxxxxx ywwsss ssm 20g45e g h/j 5 /16/200 6 re v. 3 . 0 1 date/lot code: (ywwsss) y = last digit of the year ww = week sss = lot code sequence to-252: 3000 pcs in antistatic tape on a reel packed inside a moisture barrier bag (mbb).
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