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NB6381 high efficiency, fast transient, 8a, 28v synchronous step-down converter in a tiny qfn20 (3x4mm) package NB6381 rev. 1.15 www.monolithicpower.com 1 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the NB6381 is a fully integrated, high frequency synchronous rectified step-down switch mode converter. it offers a very compact solution to achieve 8a continuous output current over a wide input supply range with excellent load and line regulation. the NB6381 operates at high efficiency over a wide output current load range. constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. full protection features include scp, ocp, ovp, uvp and thermal shutdown. the NB6381 requires a minimum number of readily available standard external components and is available in a space-saving qfn20 (3x4mm) package. features ? wide 4.5v to 28v operating input range ? 8a output current ? internal 30m ? high-side, 12m ? low-side power mosfets ? proprietary switching loss reduction technique ? 1% reference voltage ? programmable soft start time ? soft shutdown ? 200khz to 1mhz switching frequency ? scp, ocp, ovp, uvp protection and thermal shutdown ? output adjustable from 0.8v to 13v ? available in a qfn20 (3x4mm) package applications ? notebook systems and i/o power ? networking systems ? optical communication systems ? distributed power and pol systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. . ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application 5 4 3 2 7 9,10,17,18 1 20 8,19 11-16 in vcc pgood freq en pgnd agnd ss sw fb bst r7 c ss 33nf c4 220pf NB6381 vin en vout 1.05v
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 2 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking NB6381dl qfn20 (3x4mm) 6381 * for tape & reel, add suffix ?z (e.g. NB6381dl?z) for rohs compliant packaging, add suffix ?lf (e.g. NB6381dl?lf?z) package reference top view 1 2 3 4 5 6 16 15 14 13 12 agnd freq fb ss en pgood pgnd pgnd pgnd pgnd pgnd pgnd sw sw bst exposed pad on backside in sw sw vcc in in in in sw sw 78910 11 20 19 18 17 absolute maxi mum ratings (1) supply voltage v in ....................................... 30v v sw ........................................-0.3v to v in + 0.3v v bs ....................................................... v sw + 6v i vin (rms) ........................................................ 3.5a v pgood ....................................-0.3v to v cc +0.6v all other pins ..................................-0.3v to +6v continuous power dissipation (t a = +25c) (2) ????????????? ?????.2.6w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.5v to 28v output voltage v out .........................0.8v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc qfn20 (3x4mm) ......................48 ...... 10 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 3 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units supply current (shutdown) i in v en = 0v 0 a supply current (quiescent) i in v en = 2v v fb = 1v 500 a hs switch on resistance (5) hs rds-on 30 m ? ls switch on resistance (5) ls rds-on 12 m ? switch leakage sw lkg v en = 0v v sw = 0v or 12v 0 10 a current limit i limit 12 a one-shot on time t on r7=348k ? v out =1.05v 360 ns minimum off time (5) t off 100 ns fold-back off time (5) t fb ilim=1(high) 1.4 ms ocp hold-off time (5) t oc ilim=1(high) 40 ms feedback voltage v fb 807 815 823 mv feedback current i fb v fb = 815mv 10 50 na soft start charging current + iss v ss =0v 8.5 a soft stop discharging current - iss v ss =0.815v 8.5 a power good rising threshold pgood vth-hi 0.85 v fb power good falling threshold pgood vth-lo 0.9 v fb power good rising delay t pgood t ss =1ms 1 ms power good rising delay t pgood t ss =2ms 1.5 ms power good rising delay t pgood t ss =3ms 2 ms en rising threshold en vth-hi 1.05 1.35 1.60 v en threshold hysteresis en vth-hys 250 420 550 mv en input current i en v en = 2v 2 a v in under-voltage lockout threshold rising inuv vth 3.8 4.0 4.2 v v in under-voltage lockout threshold hysteresis inuv hys 880 mv v cc regulator v cc 5 v v cc load regulation i cc =5ma 5 % vo over voltage protection threshold v ovp 1.25 v fb vo under voltage detection threshold v uvp 0.7 v fb thermal shutdown t sd 150 c thermal shutdown hysteresis t sd-hys 25 c note: 5) guaranteed by design.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 4 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions pin # name description 1 agnd analog ground. 2 freq frequency set during ccm operation. the on period is determined by the input voltage and the frequency-set resistor conne cted to freq pin. connect a resistor to in for line feed-forward. decouple with a 1nf capacitor. 3 fb feedback. an external resistor divider fr om the output to gnd, tapped to the fb pin, sets the output voltage. 4 ss soft start. connect an external ss capacito r to program the soft start time for the switch mode regulator. when the en pin becomes high, an internal current source (8.5ua) charges up the ss capacitor and t he ss voltage slowly ramps up from 0 to v fb smoothly. when the en pin becomes low, an internal current source (8.5 a ) discharges the ss capacitor and the ss voltage slowly ramps down. 5 en en=1 to enable the NB6381. for automatic start-up, connect en pin to in with a 100k ? resistor. it includes an internal 1m ? pull-down resistor. 6 pgood power good output. the output of this pin is an open drain and is high if the output voltage is higher than 90% of the nominal voltage. there is delay from fb 90% to pgood high, which is 50% of ss time plus 0.5ms. 7 bst bootstrap. a 0.1f-1f capacitor connec ted between sw and bs pins is required to form a floating supply across the high-side switch driver. 8, 19 in supply voltage. the NB6381 operates from a +4.5v to +28v input rail. c in is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 9, 10, 17, 18 sw switch output. use wide pcb trac es and multiple vias to make the connection. 11-16 pgnd system ground. this pin is the referenc e ground of the regulated output voltage. for this reason care must be taken in pcb layout. 20 vcc internal bias supply. decouple with a 1f capacitor as close to the pin as possible.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 5 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 6 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 7 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.05v, l=1h, t a =+25c, unless otherwise noted. 1ms/div 1ms/div 1ms/div 1ms/div sw 10v/div i l 5a/div v out /ac 500mv/div start-up through en i out =0a start-up through en i out =8a shutdown through en i out =0a shutdown through en i out =8a en 10v/div i l 2a/div v out 500mv/div sw 10v/div en 10v/div i l 5a/div v out 500mv/div sw 10v/div en 10v/div i l 2a/div v out 500mv/div sw 10v/div en 10v/div i l 5a/div v out 500mv/div sw 10v/div short-circuit protection v out 50mv/div. v sw 10v/div. i l 5a/div.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 8 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. block diagram figure 1?functional block diagram
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 9 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the NB6381 is a fully integrated synchronous rectified step-down switch mode converter. constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ) which indicates insufficient output voltage. the on period is determined by the input voltage and the frequency-set resistor as follows: on in 12 r7(k ) t(ns) 40ns v(v) 0.4 =+ ? (1) after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when v fb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs-fet and ls-fet are turned on at the same time. it?s called shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-fet off and ls- fet on, or ls-fet off and hs-fet on. heavy-load operation figure 2?heavy load operation as figure 2 shows, when the output current is high, the hs-fet and ls-fet repeat on/off as described above. in this operation, the inductor current will never go to zero. it?s called continuous-conduction-mode (ccm) operation. in ccm operation, the switching frequency (f sw ) is fairly constant. light-load operation when the load current decreases, the NB6381 reduces the switching frequency automatically to maintain high efficiency. the light load operation is shown in figure 3. the v fb does not reach v ref when the inductor current is approaching zero. as the output current reduces from heavy- load condition, the inductor current also decreases, and eventually comes close to zero. the ls-fet driver turns into tri-state (high z) whenever the inductor current reaches zero level. a current modulator takes over the control of ls- fet and limits the inductor current to less than 600 a. hence, the output capacitors discharge slowly to gnd through ls-fet as well as r1 and r2. as a result, the efficiency at light load condition is greatly improved. at light load condition, the hs-fet is not turned on as frequently as at heavy load condition. this is called skip mode.. figure 3?light load operation as the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. the hs-fet is turned on more frequently. hence, the switching frequency increases correspondingly. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined as follows:
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 10 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. in out out out sw in (v v ) v i 2lf v ? = (2) it turns into pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range. switching frequency constant-on-time (cot) control is used in the NB6381 and there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on-time one-shot timer through the resistor r7. the duty ratio is kept as v out /v in . hence, the switching frequency is fairly constant over the input voltage range. the switching frequency can be set as follows: 6 sw in delay in out 10 f(khz) v(v) 12 r7(k ) t(ns) v(v) 0.4 v (v) = + ? (3) where t delay is the comparator delay. it?s about 40ns. NB6381 is optimized to operate at high switching frequency with high efficiency. high switching frequency makes it possible to utilize small sized lc filter components to save system pcb space. jitter and fb ramp slope figure 4 and figure 5 show jitter occurring in both pwm mode and skip mode. when there is noise in the v fb downward slope, the on time of hs-fet deviates from its intended location and produces jitter. it is necessary to understand that there is a relationship between a system?s stability and the steepness of the v fb ripple?s downward slope. the slope steepness of the v fb ripple dominates in noise immunity. the magnitude of the v fb ripple doesn?t directly affect the noise immunity directly. figure 4?jitter in pwm mode figure 5?jitter in skip mode ramp with large esr cap in the case of poscap or other types of capacitor with larger esr is applied as output capacitor. the esr ripple dominates the output ripple, and the slope on the fb is quite esr related. figure 6 shows an equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. turn to application information section for design steps with large esr caps. r1 r2 esr poscap sw fb vo l figure 6?simplified circuit in pwm mode without external ramp compensation to realize the stability when no external ramp is used, usually the esr value should be chosen as follow:
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 11 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. sw on esr out tt 0.7 2 r c + (4) tsw is the switching period. ramp with small esr cap when the output capacitors are ceramic ones, the esr ripple is not high enough to stabilize the system, and external ramp compensation is needed. skip to application information section for design steps with small esr caps. r1 r2 ceramic sw fb vo l r4 c4 i r4 i c4 i fb r9 figure 7?simplified circuit in pwm mode with external ramp compensation in pwm mode, an equivalent circuit with hs-fet off and the use of an external ramp compensation circuit (r4, c4) is simplified in figure 7. the external ramp is derived from the inductor ripple current. if one chooses c4, r9, r1 and r2 to meet the following condition: 12 9 sw 4 1 2 rr 11 r 2f c 5rr ?? < + ?? + ?? (5) where: r4 c4 fb c4 iiii =+ (6) and the ramp on the v fb can then be estimated as: in o 12 ramp on 44 12 9 vv r//r vt rc r//rr ? = + (7) the downward slope of the v fb ripple then follows ? ? == out ramp slope1 off 4 4 v v v trc (8) as can be seen from equation 8, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 5, then we can only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 9. sw on -3 esr out slope1 o out sw on tt +-rc io 10 0.7 2 -v v + 2lc t -t (9) io is the load current. in skip mode, the downward slope of the v fb ripple is almost the same whether the external ramp is used or not. fig.8 shows the simplified circuit of the skip mode when both the hs-fet and ls-fet are off. r1 r2 cout fb vo ro figure 8?simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: () ref slope2 12 out v v (r r //ro) c ? = + (10) where ro is the equivalent load resistor. as described in fig.6, v slope2 in the skip mode is lower than that is in the pwm mode, so it is reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during ultra light load condition, the values of the v fb resistors should not be too big, however, that will decrease the light load efficiency. soft start/stop the NB6381 employs soft start/stop (ss) mechanism to ensure smooth output during power-up and power shutdown. when the en pin becomes high, an internal current source (8.5 a) charges up the ss cap. the ss cap voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 12 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. reaches the same level as the v ref , it keeps ramping up while v ref takes over the pwm comparator. at this point, the soft start finishes and it enters into steady state operation. when the en pin becomes low, the ss cap voltage is discharged through an 8.5ua internal current source. once the ss voltage reaches ref voltage, it takes over the pwm comparator. the output voltage will decrease smoothly with ss voltage until zero level. the ss cap value can be determined as follows: () ( ) ( ) () = ss ss ss ref tmsi a cnf vv (11) if the output capacitors have large capacitance value, it?s not recommended to set the ss time too small. otherwise, it?s easy to hit the current limit during ss. a minimum value of 4.7nf should be used if the output capacitance value is larger than 330uf. power good (pgood) the NB6381 has power-good (pgood) output. the pgood pin is the open drain of a mosfet. it should be connected to v cc or other voltage source through a resistor (e.g. 100k). after the input voltage is applied, the mosfet is turned on so that the pgood pin is pulled to gnd before ss is ready. after fb voltage reaches 90% of ref voltage, the pgood pin is pulled high after a delay. the pgood delay time is determined as follows: pgood ss t (ms) 0.5 t (ms) 0.5 = + (12) when the fb voltage drops to 85% of ref voltage, the pgood pin will be pulled low. over-current protection (ocp) and short- circuit protection (scp) the NB6381 has cycle-by-cycle over-current limit control. the inductor current is monitored during the on state. once it detects that the inductor current is higher than the current limit, the hs- fet is turned off. at the same time, the ocp timer is started. the ocp timer is set as 40 s. if in the following 40 s, the current limit is hit for every cycle, then it?ll trigger ocp latch-off. the converter needs power cycle to restart after it triggers ocp. if short circuit happens, then the current limit will be hit immediately and the fb voltage will become lower than 50% of the ref voltage. when the current limit is hit and the fb voltage is lower than 50% of the ref voltage (0.815v), the device considers this as a dead short on the output and triggers scp latch-off immediately. this is short-circuit protection (scp). over/under-voltage protection (ovp/uvp) the NB6381 monitors the output voltage through a resistor divider feedback (fb) voltage to detect overvoltage and undervoltage on the output. when the fb voltage is higher than 125% of the ref voltage (0.8v), it?ll trigger ovp latch-off. once it triggers ovp, the ls-fet is always on while the hs-fet is always off. it needs power cycle to power up again. when the fb voltage is below 50% of the ref voltage (0.8v), it is recognized as uv (under-voltage). usually, uvp accompanies a hit in current limit and this results in scp. uvlo protection NB6381 has under-voltage lock-out protection (uvlo). when the input voltage is higher than the uvlo rising threshold voltage, the NB6381 will be powered up. it shuts off when the input voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. thermal shutdown thermal shutdown is employed in the NB6381. the junction temperature of the ic is internally monitored. if the junction temperature exceeds the threshold value (typically 150oc), the converter shuts off. this is non-latch protection. there is about 25oc hysteresis. once the junction temperature drops to about 125oc, it initiates a soft start.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 13 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage-large esr caps for applications that electrolytic capacitor or pos capacitor with a controlled output of esr is set as output capacitors. the output voltage is set by feedback resistors r1 and r2. as figure 9 shows. r1 r2 esr poscap sw fb vo l figure 9?simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? - 50k ? for r2, using a comparatively larger r2 when vout is low, etc.,1.05v, and a smaller r2 when vout is high. then r1 is determined as follow with the output ripple considered: out out ref 12 ref 1 vvv 2 rr v ? ? = (13) out v is the output ripple determined by equation 22. setting the output voltage-small esr caps r1 r2 ceramic sw fb vo l r9 r4 c4 figure 10?simplified circuit of ceramic capacitor when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4.the output voltage is influenced by ramp voltage v ramp besides r divider as shown in figure 10. the v ramp can be calculated as shown in equation 7. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? -50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. and the value of r1 then is determined as follow: 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r (14) the v fb(avg) is the average value on the fb, v fb(avg) varies with the vin, vo, and load condition, etc., its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ,if one wants to gets a better load or line regulation, a lower vramp is suggested once it meets equation 9. for pwm operation, v fb(avg) value can be deduced from equation 15. 12 fb( avg) ref ramp 12 9 r//r 1 vvv 2r//rr =+ + (15) usually, r9 is set to 0 ? , and it can also be set following equation 16 for a better noise immunity. it should also set to be 5 timers smaller than r1//r2 to minimize its influence on vramp. 9 4sw 1 r 2c2f (16) using equation 14 to calculate the output voltage can be complicated. to simplify the calculation of r1 in equation 14, a dc-blocking capacitor cdc can be added to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using equation 17 for pwm mode operation.
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 14 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ?? = + out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 (17) cdc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should also not larger than 0.47 f considering start up performance. in case one wants to use larger cdc for a better fb noise immunity, combined with reduced r1 and r2 to limit the cdc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load and line regulation are still vramp related. r1 r2 ceramic sw fb vo l cdc r4 c4 figure 11?simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous. therefore, a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance. in the layout, it?s recommended to put the input capacitors as close to the in pin as possible. the capacitance varies significantly over temperature. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable over temperature. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv = ? (18) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 = (19) for simplification, choose the input capacitor whose rms current rating is greater than half of the maximum load current. the input voltage ripple can be estimated as follows: out out out in sw in in in iv v v(1) fc v v = ? (20) the worst-case condition occurs at v in = 2v out , where: out in sw in i 1 v 4f c = (21) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (22) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: out out out 2 sw out in vv v(1) 8f lc v = ? (23) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equation 5, 8 and 9. in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value around 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 15 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. approximated as: out out out esr sw in vv v(1)r fl v = ? (24) inductor the inductor is required to supply constant current to the output load while being driven by the switching input voltage. a larger value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. a good rule for determining the inductor value is to allow the peak-to-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit. also, make sure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated as: out out sw l in vv l(1) fi v =? (25) where i l is the peak-to-peak inductor ripple cu rrent. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated as: out out lp out sw in vv ii (1 ) 2f l v =+ ? (26) table 1?inductor selection guide part number manufacturer inductance (h) dcr (m ? ) current rating (a) dimensions l x w x h (mm 3 ) switching frequency (khz) pcmc-135t-r68mf cyntec 0.68 1.7 34 13.5 x 12.6 x 4.8 600 fda1254-1r0m toko 1 2 25.2 13.5 x 12.6 x 5.4 300~600 fda1254-1r2m toko 1.2 2.05 20.2 13.5 x 12.6 x 5.4 300~600 typical design parameter tables the following tables include recommended component values for typical output voltages (1.05v, 1.2v, 1.8v, 2.5v, 3.3v) and switching frequencies (300khz, 500khz, and 700khz). refer to tables 2-4 for design cases without external ramp compensation and tables 5-7 for design cases with external ramp compensation. external ramp is not needed when high-esr capacitors, such as electrolytic or poscaps are used. external ramp is needed when low-esr capacitors, such as ceramic capacitors are used. for cases not listed in this datasheet, a calculator in excel spreadsheet can also be requested through a local sales representative to assist with the calculation. table 2?300khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.05 2.2 12.1 43 301 1.2 2.2 12.1 24 360 1.8 2.2 19.6 15.8 499 2.5 2.2 30 14.7 680 3.3 2.2 40.2 13.3 806 table 3?500khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.05 1 12.1 43 180 1.2 1 12.1 24 200 1.8 1 19.6 15.8 309 2.5 1 30 14.7 402 3.3 1 40.2 13.3 523
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 16 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. table 4?700khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.05 1 12.1 43 120 1.2 1 12.1 24 140 1.8 1 19.6 15.8 210 2.5 1 30 14.7 309 3.3 1 40.2 12.4 402 table 5?300khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.05 2.2 12.1 43 330 220 301 1.2 2.2 12.1 24 330 220 360 1.8 2.2 19.6 15.2 499 220 499 2.5 2.2 30 14.7 499 220 680 3.3 2.2 40.2 13 604 220 806 table 6?500khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.05 1 12.1 43 330 220 180 1.2 1 12.1 24 330 220 196 1.8 1 19.6 15.8 330 220 309 2.5 1 30 14.7 383 220 402 3.3 1 40.2 12 499 220 522 table 7?700khz, 12v in v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.05 1 12.1 43 220 220 120 1.2 1 12.1 24 220 220 140 1.8 1 19.6 15.8 261 220 210 2.5 1 30 14.3 261 220 270 3.3 1 40.2 12 360 220 383
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 17 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application vin r7 174k 1.05v r5 100k c7 1nf r6 100k c6 33nf 1 4 5 6 20 2 8,19 u1 NB6381 in freq vcc pgood en ss agnd pgnd fb sw bst 7 9,10,17,18 3 11-16 r2 42.2k r1 12.1k r3 4.7 gnd pgood en vout gnd figure 12? typical application circuit with no external ramp vin r7 174k 1.05v r5 100k c7 1nf r6 100k c6 33nf 1 4 5 6 20 2 8,19 u1 NB6381 in freq vcc pgood en ss agnd pgnd fb sw bst 7 9,10,17,18 3 11-16 r2 43.2k r1 12.1k r9 0 r3 4.7 r4 360k c4 220pf gnd pgood en vout gnd figure 13? typical application circuit with low esr ceramic capacitor vin r7 174k 1.05v r5 100k c7 1nf r6 100k c6 33nf 1 4 5 6 20 2 8,19 u1 NB6381 in freq vcc pgood en ss agnd pgnd fb sw bst 7 9,10,17,18 3 11-16 r2 42.2k r1 12.1k r3 4.7 r4 360k c4 220pf gnd pgood en vout gnd 10nf figure 14? typical application circuit with low esr ceramic capacitor and dc-blocking capacitor .
NB6381?high efficiency, fast transient synchronous step-down converter NB6381 rev. 1.15 www.monolithicpower.com 18 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1. the high current paths (gnd, in, and sw) should be placed very close to the device with short, direct and wide traces. 2. put the input capacitors as close to the in and gnd pins as possible. 3. put the decoupling capacitor as close to the v cc and gnd pins as possible. 4. keep the switching node sw short and away from the feedback network. 5. the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c3, and sw) as short as possible. 7. keep the bottom in and sw pads connected with large copper to achieve better thermal performance. 8. four-layer layout is strongly recommended to achieve better thermal performance. top layer inner1 layer gnd inner2 layer bottom layer figure 15?pcb layout
NB6381?high efficiency, fast transient synchronous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. NB6381 rev. 1.15 www.monolithicpower.com 19 4/18/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn20 (3x4mm)

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