the m29306 provides the most complete physical-layer solution for flexible ds3/e3/sts-1 atm, packet and tdm services on a single chip. the m29306 aggressively drives down cost for existing solutions and as well as reduces pcb real-estate and power. each port of the m29306 operates independently allowing for a mix of different rates and protocols. this flexibility allows service providers to provide a combination of clear channel ds3/e3 for packet, ds3/e3 atm uni or t3/e3/sts-1 tdm services on the same card. this enables adms/oeds and mspps to deploy a single line card that supports the simultaneous mapping for sdh or sonet transport of both ds3 and e3. the m29306 integrates all the functional physical-layer blocks for a ds3/e3/sts-1 line card. it includes: 6 inde- pendent electrical line interface units (lius) with built-in digital jitter attenuators (djat), 12 ds3/e3 framers, and 6 sts-1 framers. each port is supported by a number of protocol options that may be selected on a per port basis from high level data link controllers (hdlc), atm cell delineators, or ds3/e3 sonet/sdh mappers/demappers. the only requirement on the line side is the addition of transformers and passive termination. the device incorporates flexible system interfaces to support cell/packet termination into an industry-standard system bus of utopia level 2 (ul2) for atm, pos-phy level 2 or spi-3 for hdlc packets, and sts-12/stm-4 support for the sonet/sdh traffic via a standard 8-bit, 77 mhz tdm telecom bus. thus, a channelized oc-12/stm-4 can be broken down to ds3/e3 streams by the m29306 on a channel-by- channel basis. the m29306 requires only one 19.44 mhz reference clock (passive crystal) for generating all the necessary internal line rate clocks and enabling the same reference clock to be available on an output pad. in addition it can use a 77.76 mhz or 155.52 mhz reference. fractional ds3/e3 service is also supported through a bypass mode that allows external access to the ds3/e3 channels data stream between the framer and the atm/hdlc control allowing for external processing of the payload. this bypass mode also provides the capability of chaining two m29306s together to support a 12 line to one system side implementation. a sts-1 bypass on each of the sts-1 framers also allows for external access to the sts-1 payload. > high integration C lius with djat, t3/e3, sts-1 framers/mappers, sts-12/stm-4 framer, atm & hdlc processors > flexibility C mix atm, tdm and packet as well as t3, e3 and sts-1 services on one device > easy implementation C tap software + high integration = faster time-to-market > parallel 8-bit, 77.76 mhz tdm telecom bus > atm/packet interfaces C spi-3, 8-bit 25C104 mhz C utopia level 2/pos-phy level 2, 16-bit 25-50 mhz > fractional t3/e3 support > t3/e3/sts-1 payload access > embedded clads for supported line rates > pattern generator/detector for bert > comprehensive loopbacks > > key features 6-port ds3/e3/sts-1 integrated line termination device for atm, packet processing and tdm transport m29306 C ds3/e3/sts-1 line-card-on-a-chip
www.mindspeed.com/salesoffices general information: headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 29306-BRF-001-A m04-0920 ? 2004 mindspeed technologies ? . all rights reserved. mindspeed and the mindspeed logo are trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non- infringement. mindspeed technologies shall not be liable for any special, indirect, inci- dental or consequential damages as a result of its use. ? 6 ds3/e3/sts-1e lius with jitter attenuation/desynchronization C adaptive receive equalizer enables > 1800 ft of cable reach C programmable transmit pulse mask configuration C dynamic loop bandwidth to comply with all standard intrinsic and output jitter requirements ? 12 t3/e3 framers support t3-m13, t3-m23, t3 c-bit parity e3-g.751, e3-g.832 ? 12 atm processors support both direct (for c-bit parity/m13/m23 t3 and g.832 e3) and plcp-based mapping (for c-bit parity ds3/m13/m23 and e3-g.751) ? 12 bit-synchronous hdlc processors ? 6 ds3/e3 mappers/demappers supporting t3/vc-3/au-3; t3/tug- 3/au-4; e3/vc-3/au-3; e3/tug- 3/au-4 ? 6 sts-1 sonet/sdh framers support transport overhead access; includes monitor and generator ? sts-12/stm-4 sonet/sdh tdm supporting mapping/demapping of sts-1e or tug-3 into/from sts-12/stm-4 frame ? pointer processing ? transport overhead insertion and extraction ? parallel 77.76 mhz x 8-bit telecom bus interface ? atm/packet interfaces C spi-3 8-bit 25C104 mhz for hdlc packets C utopia level 2/pos-phy level 2, 16-bit 25C50 mhz atm cells or hdlc packets ? fractional t3/e3 interface for external fpga or asic ? synchronous 16-bit microprocessor interface bus at 30C77 mhz bus rate C glueless connection to motorola mpc860 ? local (source) and remote (line) loopback capability at various internal points in the device ? prbs detector and generator supporting framed and unframed modes ? jtag (ieee 1149.1) boundary scan ? single rail 1.8 v core supply with 3.3 v lvttl i/o, 1.8v lvds i/o ? embedded clads internally generating the t3, e3, sts-1 clocks ? -40c to +85c operation applications ? sonet/sdh adm/oed ? mspp ? ngdlc/blc ? optical adm ? pon olt ? dcs ? media gateway ordering information ? m29306-12p product features for maintenance, the m29306 supports pseudo-random bit sequence (prbs) testing and a full set of loopback functions are provided at different functional blocks. using the telecom application package (tap) software to abstract the physical registers, developers can easily implement the m29306 solution, reducing design time. m29306 functional block diagram 6x t3/e3 or sts-1e liu + jat 12x t3/e3 framers 6x sts-1 framers 12x atm processors 12x hdlc processors 6x t3/e3 to sts-1e mapper/ demapper 6x prbs generator and monitor utopia l2 or pos-phy l2 (pos-spi-3 phy interface) oc-12 mux/demux/ mini-framer jtag microprocessor interface mpc860 16-bit 50 mhz 8 - b i t 1 0 4 m h z 8 - b i g 7 7 . 7 5 m h z cell or packet cell or packet telecom bus systems control 6 lines t3/e3/ sts-1e (ec-1) lines m29306 sts-1 overhead access sts-12 overhead access test i/f bypass/chaining i/f t3/e3 overhead access
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