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1 lt1310 sn1310 1310fs 1.5a boost dc/dc converter with phase-locked loop the lt ? 1310 boost dc/dc converter combines a 1.5a current mode pwm switcher with an integrated phase- locked loop, allowing the user to set the switching fre- quency anywhere from 10khz to 4.5mhz. intended for use in applications where switching frequency must be accu- rately controlled, the lt1310 can generate 12v at up to 400ma from a 5v input. switching frequency is set with an external capacitor, and the device can be operated in either free-running or phase- locked mode. a wide capture range of nearly 2:1 allows the free-running frequency to be set using standard 10% tolerance np0 dielectric capacitors. the lt1310 is available in the tiny thermally enhanced 10-lead msop package. n synchronizable or constant frequency low noise output n synchronizable up to 4.5mhz n wide input voltage range: 2.8v to 18v n low profile surface mount solution (all ceramic capacitors) n low v cesat switch: 240mv at 1a n adjustable output from v in to 35v n small thermally enhanced 10-lead msop package n instruments n avionics n data acquisition n communications n imaging n ultrasound , ltc and lt are registered trademarks of linear technology corporation. v in shdn shutdown sync 1.6mhz sync pll-lpf 3.01k v in 5v 15k 178k 20.5k 100pf np0 1310 f01a c2 4.7 f ceramic v out 12v 400ma 1500pf 820pf c1: 4.7 f, x5r or x7r, 6.3v c2: 4.7 f, x5r or x7r, 16v d1: microsemi ups120 or equivalent l1: panasonic ell6sh-5r6m *exposed pad must also be grounded c1 4.7 f ceramic fb c t v c sw d1 lt1310 l1 5.6 h gnd* load current (ma) 0 35 efficiency (%) 45 55 65 75 100 200 1310 f01b 400 300 85 40 50 60 70 80 90 3.3v in v out = 12v 5v in figure 1. 5v to 12v converter synchronized at 1.6mhz lt1310 efficiency descriptio u features applicatio s u typical applicatio u
2 lt1310 sn1310 1310fs parameter conditions min typ max units undervoltage lockout 2.8 v maximum input voltage 18 v feedback voltage 1.242 1.255 1.268 v l 1.236 1.268 v fb pin bias current 60 150 na reference line regulation v in = 2.9v to 18v 0.01 0.05 %/v error amplifier transconductance d i = 5 m a 350 m a/v error amplifier voltage gain 200 v/v sw current limit 1.5 2.1 2.8 a sw saturation voltage i sw = 1a 0.240 0.320 v sw maximum duty cycle c t = 220pf 80 84 % c t = 47pf 78 83 % sw minimum on time i sw = 150ma, v c = 0.25v 70 ns vco frequency c t = 220pf, pll-lpf = high 0.950 1.10 1.25 mhz c t = 220pf, pll-lpf = high l 0.800 1.30 mhz c t = 220pf, pll-lpf = low 500 630 khz c t = 47pf, pll-lpf = high 3.3 mhz frequency foldback c t = 220pf, pll-lpf = high, fb = 0v 200 khz pll lock range c t = 220pf, maximum 0.950 1.10 1.25 mhz c t = 220pf, minimum (percent change from max) C40 C50 % supply current shdn = high 11.5 15 ma shdn = low 1 m a sw leakage current switch off, sw = 3.3v 0.1 5 m a shdn pin bias current v shdn = 2.4v 35 65 m a shdn pin high active mode 2.4 v shdn pin low shutdown mode 0.4 v (note 1) sw voltage .............................................................. 36v v in voltage ............................................................. 18v shdn voltage ......................................................... 18v sync voltage ........................................................... 5v fb voltage ................................................................. 5v c t voltage ................................................................. 5v v c voltage ................................................................. 2v pll-lpf pin current ............................................... 1ma operating temperature range (note 2) .. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number lt1310emse t jmax = 125 c, q ja = 40 c/w exposed pad is ground (must be soldered to pcb) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v, v shdn = 3.3v, unless otherwise noted. (note 2) 1 2 3 4 5 fb shdn pll-lpf sync gnd 10 9 8 7 6 v c c t v in sw sw top view mse exposed pad package 10-lead plastic msop mse part marking ltrz consult ltc marketing for parts specified with wider operating temperature ranges. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the lt1310e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, chacterization and correlation with statistical process controls. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 lt1310 sn1310 1310fs feedback voltage temperature ( c) ?0 1.22 fb voltage (v) 1.23 1.24 1.25 1.26 1.27 ?5 02550 1310 g01 75 100 temperature ( c) ?0 140 120 100 80 60 40 20 0 25 75 1310 g02 ?5 0 50 100 feedback current (na) temperature ( c) ?0 2.50 undervoltage lockout (v) 2.55 2.60 2.65 2.70 2.80 ?5 02550 1310 g03 75 100 2.75 feedback pin current undervoltage lockout oscillator frequency vs c t capacitor capacitor (pf) 20 1000 frequency (khz) 3000 6000 40 60 lt1372 ?g10 2000 5000 4000 80 100 pll-lpf = high oscillator frequency vs c t capacitor capacitor (pf) 100 frequency (khz) 1200 1600 2000 900 1310 g05 800 400 0 300 500 700 1100 pll-lpf = high oscillator frequency vs feedback voltage feedback (v) 0 800 1000 1400 0.6 1.0 1310 g06 600 400 0.2 0.4 0.8 1.2 1.4 200 0 1200 frequency (khz) 220pf c t capacitor oscillator frequency 220pf capacitor on c t pin maximum duty cycle vs oscillator frequency temperature ( c) ?0 1600 1400 1200 1000 800 600 400 200 25 75 1310 g07 ?5 0 50 100 frequency (khz) pll-lpf = high oscillator frequency 47pf capacitor on c t pin temperature ( c) ?0 2000 frequency (khz) 2300 2600 2900 3200 3800 ?5 02550 1310 g08 75 100 3500 pll-lpf = high oscillator freqency (khz) 500 1000 50 max duty cycle (%) 70 100 1500 2500 3000 1310 g09 60 90 80 2000 3500 4000 100 c 25 c ?0 c typical perfor a ce characteristics uw
4 lt1310 sn1310 1310fs switch minimum on time pll lock range 220pf capacitor on c t pin supply current switch v cesat temperature ( c) ?0 40 minimum on time (ns) 50 60 70 80 100 ?5 02550 1310 g10 75 100 90 temperature ( c) ?0 200 frequency (khz) 400 600 800 1000 1400 ?5 02550 1310 g11 75 100 1200 maximum minimum temperature ( c) ?0 500 frequency (khz) 1000 1500 2000 2500 3500 ?5 02550 1310 g12 75 100 3000 maximum minimum pll lock range 47pf capacitor on c t pin temperature ( c) ?0 7 supply current (ma) 8 9 10 11 12 ?5 02550 1310 g13 75 100 switch current (a) 0 0 v cesat (mv) 100 200 300 400 0.5 1.0 1310 g15 1.5 transient response pll response start-up response v out 100mv/div i l 500ma/div 200ma 100ma i load f sync = 1.5mhz 50 m s/div lt1310 g16 v out 50mv/div i l 200ma/div 1.9mhz 1.2mhz f sync 50 m s/div lt1310 g17 v out 5v/div i l 1a/div v shdn no sync signal 20 m s/div lt1310 g18 f = 1.2mhz typical perfor a ce characteristics uw
5 lt1310 sn1310 1310fs fb (pin 1): feedback pin for error amplifier. connect the resistor divider here to set output voltage according to the formula: v out = 1.255(1 + r1/r2) fb r1 v out r2 minimize trace area at this pin. shdn (pin 2): shutdown pin. for active mode, tie this pin to a voltage between 2.4v and 18v. to disable the part and go into low current mode, pull this pin below 0.4v. pll-lpf (pin 3): phase locked-loop filter pin. this is the output of the phase detector and also the input to the voltage controlled oscillator (vco). connect an rc filter here. typically, r = 3k and c = 1500pf. the voltage range at the pll-lpf pin is approximately 0v to 1.5v with 1.5v corresponding to the maximum switching frequency. for applications not requiring synchronization, use a pull-up resistor at this pin; the pull-up voltage must be above 2.4v. set the pull-up resistor value according to: r vv a pullup pullup = () m . 15 300 for a pull-up voltage of 5v: r vv a k pullup = () m ? 515 300 11 6 . . sync (pin 4): frequency synchronization pin. inject the external synchronizing signal here. the phase detector is edge triggered and when locked the rising edge of the sync signal will be aligned with the turn-on of the power transistor. the sync signal must have a minimum high amplitude of 1.2v and a maximum low amplitude of 0.2v with the signal staying low for at least 100ns. 1.2v (min) 0.2v (max) 100ns (min) gnd (pin 5, exposed pad): ground. tie both pin 5 and the exposed pad directly to local ground plane . the ground metal to the exposed pad should be wide for better heat dissipation. multiple vias (local ground plane ? ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. the exposed pad must be soldered to ground for the lt1310 to function properly. sw (pins 6, 7): switch pin. must tie pin 6 to pin 7 . connect inductor/diode here. minimize trace area at this pin to keep emi down. v in (pin 8): supply pin. must be bypassed as close as possible to the pin. c t (pin 9): timing capacitor pin for vco. place the timing capacitor from this pin to ground to set the frequency range for the oscillator. minimize trace at this pin to reduce stray capacitance. v c (pin 10): compensation pin for error amplifier. tie an rc network here to compensate the voltage feedback loop. uu u pi fu ctio s
6 lt1310 sn1310 1310fs + s 1 fb 2 shdn shutdown 5 gnd v c a1 1.255v ref ramp gen. exposed pad phase detector vco + + + r s q q 10 c t 9 pll-lpf sync 3 4 sw 0.024 1310 bd 6, 7 5 a2 to understand operation, refer to the block diagram. the lt1310 contains a boost switching regulator that can be phase locked to an external synchronizing signal. the boost regulator uses current mode control and contains a 1.5a npn power transistor. this type of control uses two feedback loops. the main control loop sets output voltage and operates as follows: a load step causes v out and the fb voltage to be slightly perturbed. the error amplifier a1 responds to this change in fb by driving the v c pin either higher or lower. because switch current is proportional to the v c pin voltage, this change causes the switch current to be adjusted until v out is once again satisfied. loop compensation is taken care of by an rc network from the v c pin to ground. inside this main loop is another that sets current limit on a cycle-by-cycle basis. this loop utilizes current comparator a2 to control peak current. the oscil- lator issues a set pulse to the flip-flop at the beginning of each cycle, turning the switch on. with the switch now in the on state, the sw pin is effectively connected to ground. current ramps up in the inductor linearly at a rate of v in /l. switch current is set by the v c pin voltage and when the voltage across r sense trips the current com- parator, a reset pulse will be generated and the switch will be turned off. since the inductor is now loaded up with current, the sw pin will fly high until it is clamped by the catch diode, d1. current will flow through the diode decreasing at a rate of (v out C v in )/l until the oscillator issues a new set pulse, causing the cycle to repeat. the lt1310 is phase lockable up to 4.5mhz, giving the user precise control over switching frequency. the phase detector compares the incoming sync signal to the internal oscillator signal. if the switching frequency is lower than the sync signal, or if the phase lags the sync signal, then the phase detector output will source current into the pll-lpf pin, driving it higher. the pll-lpf pin is also the input to the voltage controlled oscillator. if the sync signal is slower than the switching frequency, the pll-lpf pin will sink current until the pll-lpf pin voltage drops. when locked, the pll-lpf pin rests at a voltage between 0v and 1.5v. the pll-lpf pin is capable of sinking or sourcing approximately 140 m a. block diagra w operatio u
7 lt1310 sn1310 1310fs c t selection for operating frequency to synchronize to an external input signal, the timing capacitor and pll filter components must be chosen properly. this is a simple process and can be done using the graph in figure 2a. in figure 2a, operating frequency is plotted versus timing capacitor (c t ) with the upper and lower lines correspond- ing to the minimum and maximum lock frequency given a specific c t value. to choose the right timing capacitor, find the intersection of the desired operating frequency and the dashed line. then move to the corresponding c t value. alternately, use the following equations as a starting point: for f lock 3 2mhz: c f t lock = ? ? ? ? 075 250 10 40 10 6 12 . for f lock 2mhz: c f t lock = ? ? ? ? 075 310 10 60 10 6 12 . figure 2a. c t vs operating frequency because the lock range for the pll is nearly 2:1, the nearest standard value np0 capacitor can be used. for the application shown in figure 1, a 1.6mhz switching frequency corresponds to an 100pf timing capacitor. since the switching frequency affects inductor ripple current, the inductor must also be scaled. table 1 shows recommended component values for various switching frequencies. table 1. recommended component values for various switching frequencies (r lp = 3.01k) switching frequency c t c c c lp r c l1 600khz 330pf 1500pf 2700pf 10k 10 m h 1mhz 180pf 1000pf 2200pf 10k 6.2 m h 1.6mhz 100pf 820pf 1500pf 15k 5.6 m h 2mhz 68pf 820pf 1500pf 15k 4.7 m h 2.5mhz 47pf 330pf 1500pf 20k 3.3 m h 3mhz 33pf 330pf 1000pf 20k 2.7 m h c t value (pf) frequency (hz) 10m 1310 f02a 10k 100k 10 100k 1m 1k 100 10k minimum lock frequecy maximum lock frequecy operatio u v in shdn shutdown sync in sync pll-lpf r lp v in 5v r c 178k 20.5k c t 1310 f02a c2 4.7 f ceramic c1 4.7 f ceramic v out 12v c lp c c fb c t v c sw lt1310 l1 gnd figure 2b. circuit used for c t selection
8 lt1310 sn1310 1310fs inductor selection several inductors that work well with the lt1310 are listed in table 2. this table is not exclusive; there are many other manufacturers and inductors that can be used. consult each manufacturer for more detailed information and for their entire selection of related parts, as many different sizes and shapes are available. ferrite core inductors should be used to obtain the best efficiency, as core losses at high frequency are much lower for ferrite cores than for the cheaper powdered-iron ones. choose an inductor that can handle at least 1.5a without saturating, and ensure that the inductor has a low dcr (copper wire resistance) to minimize i 2 r power losses. note that in some applica- tions, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one-half of the total switch current. switching frequency will also affect inductor require- ments with higher frequencies corresponding to lower inductance values. a good starting point is to set the inductor ripple current equal to one-third of the peak switch current. the inductors shown in table 2 were chosen for small size. for better efficiency, use similar valued inductors with a larger volume. table 2. recommended inductors max size l dcr l w h part ( m h) (m w ) (mm) vendor cdrh5d18-4r1 4.1 57 5.7 5.7 2 sumida cdrh5d18-5r4 5.4 76 (847) 956-0666 cdrh5d28-5r3 5.3 38 5.7 5.7 3 www.sumida.com cdrh5d28-6r2 6.2 45 cdrh5d28-8r2 8.2 53 cr43-2r2 2.2 71 4.5 4 3.2 cr43-3r3 3.3 86 ell6sh-4r7m 4.7 50 6.4 6 3 panasonic ell6sh-5r6m 5.6 59 (408) 945-5660 ell6sh-6r8m 6.8 62 www.panasonic.com rlf5018t-4r7m1r4 4.7 45 5.6 5.2 1.8 tdk rlf5018-1r5m2r1 1.5 25 5.2 5.6 1.8 (847) 803-6100 rlf5018-2r7m1r8 2.7 33 www.tdk.com rlf5018-4r7m1r4 4.7 45 rlf5018-100mr94 10 67 lpo1704-122mc 1.2 80 5.5 6.6 1 coilcraft lpo1704-222mc 2.2 120 (800) 322-2645 www.coilcraft.com applicatio s i for atio wu uu capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r dielectrics are preferred, followed by x7r, as these materials retain the capacitance over wide voltage and temperature ranges. a 4.7 m f to 20 m f output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1 m f or 2.2 m f output capacitor. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as close as possible to the lt1310. a 2.2 m f to 4.7 m f input capacitor is sufficient for most applications. table 3 shows a list of several ceramic capacitor manufacturers. consult the manufacturers for detailed information on their entire selection of ceramic parts. table 3. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com compensationadjustment to compensate the feedback loop of the lt1310, a series resistor-capacitor network should be connected from the v c pin to gnd. for most applications, a capacitor in the range of 220pf to 1500pf will suffice. with a switching frequency of 1.6mhz, a good starting value for the com- pensation capacitor, c c , is 820pf. the compensation resistor, r c , is usually in the range of 5k to 30k. a good technique to compensate a new application is to use a 30k w potentiometer in place of r c , and use a 820pf capacitor for c c . by adjusting the potentiometer while observing the transient response, the optimum value for r c can be found. figures 3a to 3c illustrate this process for the circuit of figure 1 with a load current stepped from
9 lt1310 sn1310 1310fs 100ma to 200ma. figure 3a shows the transient response with r c equal to 3k. the phase margin is poor as evi- denced by the excessive ringing in the output voltage and inductor current. in figure 3b, the value of r c is increased to 6k, which results in a more damped response. figure 3c shows the results when r c is increased further to 15k. the transient response is nicely damped and the compen- sation procedure is complete. compensationtheory like all other current mode switching regulators, the lt1310 needs to be compensated for stable and efficient operation. two feedback loops are used in the lt1310: a v out 100mv/div ac coupled i l 0.5a/div r c = 3k 200 m s/div 1310 f03a figure 3a. transient response shows excessive ringing v out 100mv/div ac coupled i l 0.5a/div r c = 6k 200 m s/div 1310 f03b figure 3b. transient response is better v out 100mv/div ac coupled i l 0.5a/div r c = 15k 200 m s/div 1310 f03b figure 3c. transient response is well damped fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 4 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by the equivalent transconductance amplifier g mp . g mp acts as a current source where the output current is proportional to the v c voltage. note that the maximum output current of g mp is finite due to the current limit in the ic. from figure 4, the dc gain, poles and zeroes can be calculated as follows: output pole: p1= 2 2 r error amp pole: p2 = 1 2 r error amp zero: z1= 1 2 r dc gain: a = 1.25 v l o c out p p p c c c grgr out c c ma o mp l in addition to the elements from figure 4, current mode control aslo results in some other poles and zeroes. these are as follows: rhp zero: z2 = output zero: z3 = current mode pole: p3 > vr vl esr c f in l out out s 2 2 2 1 2 3 p p the current mode zero is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. applicatio s i for atio wu uu
10 lt1310 sn1310 1310fs applicatio s i for atio wu uu using the circuit of figure 1 as an example, the following table shows the parameters used to generate the bode plot shown in figure 5. table 4. bode plot parameters parameter value units comment r l 30 w application specific c out 4.7 m f application specific r o 2m w not adjustable c c 820 pf adjustable r c 15 k w adjustable v out 12 v application specific v in 5 v application specific g ma 500 m mho not adjustable g mp 1.5 mho not adjustable l 5.6 m h application specific f s 1.6 mhz adjustable esr 10 m w not adjustable from figure 5, the phase is 120 when the gain reaches 0db giving a phase margin of 60 . this is more than adequate. the crossover frequency is 50khz, which is about three times lower than the frequency of the right half plane zero z2. it is important that the crossover frequency be at least three times lower than the frequency of the rhp zero to achieve adequate phase margin. + + g ma r c r o r2 c c : compensation capacitor c out : output capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out divided by i load(max) r o : output resistance of g ma r1, r2: feedback resistor divider network 1310 f04 r1 c out fb r l v out v c c c g mp 1.255v reference figure 4. boost converter equivalent model diode selection a schottky diode is recommended for use with the lt1310. the microsemi ups120 is a very good choice. where the input to output voltage differential exceeds 20v, use the ups140 (a 40v diode). these diodes are rated to handle an average forward current of 1a. for applications where the average forward current of the diode is less than 0.5a, an on semiconductor mbr0520 diode can be used. setting output voltage to set the output voltage, select the values of r1 and r2 (see figure 1) according to the following equation: rr v v out 12 1 255 1 = ? ? ? ? . a good range for r2 is from 5k to 30k. frequency (hz) 0 gain (db) 50 100 100 10k 100k 1m 1310 f05a ?0 1k frequency (hz) phase (deg) ?00 0 100 10k 100k 1m 1946 f05b ?00 ?80 1k 60 figure 5. bode plot of figure 1s circuit
11 lt1310 sn1310 1310fs u package descriptio mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) layout hints the high speed operation of the lt1310 demands careful attention to board layout. you will not get advertised performance with careless layout. figure 6 shows the recommended component placement for a boost converter. lt1310 r2 r lp shdn sync c lp gnd c out d1 1310 f06 l1 sw multiple vias v out v in c in r1 r c c t c c information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (mse) 0802 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.15 (1.93 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc 10 1 bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) applicatio s i for atio wu uu figure 6. recommended component placement for boost converter. note direct high current paths using wide pc traces. minimize trace area at pin 10 (v c ), pin 9 (c t ) and pin 1 (fb). use multiple vias to tie pin 5 copper and the exposed pad to ground plane. use vias at one location only to avoid introducing switching currents into the ground plane
12 lt1310 sn1310 1310fs ? linear technology corporation 2001 lt/tp 0103 2k ? printed in usa related parts part number description comments lt1613 550ma (i sw ), 1.4mhz high efficiency step-up dc/dc converter 90% efficiency, v in : 0.9v to 10v, v out(max) : 34v, i q : 3ma, i sd : <1 m a, thinsot tm package lt1618 1.5a (i sw ), 1.25mhz, high efficiency step-up dc/dc converter 90% efficiency, v in : 1.6v to 18v, v out(max) : 35v, i q : 1.8ma, i sd : <1 m a, 10-lead ms package lt1946/lt1946a 1.5a (i sw ), 1.2/2.7mhz, high efficiency step-up dc/dc converters v in : 2.45v to 16v, v out(max) : 34v, i q : 3.2ma, i sd : <1 m a, ms8 package lt1961 1.5a (i sw ), 1.25mhz, high efficiency step-up dc/dc converter 90% efficiency, v in : 3v to 25v, v out(max) : 35v, i q : 0.9ma, i sd : 6 m a, ms8e package ltc ? 3400/ltc3400b 600ma (i sw ), 1.2mhz, synchronous step-up dc/dc converters 92% efficiency, v in : 0.85v to 5v, v out(max) : 5v, i q : 19 m a/300 m a, i sd : <1 m a, thinsot package ltc3401 1a (i sw ), 3mhz, synchronous step-up dc/dc converter 97% efficiency, v in : 0.5v to 5v, v out(max) : 6v, i q : 38 m a, i sd : <1 m a, 10-lead ms package ltc3402 2a (i sw ), 3mhz, synchronous step-up dc/dc converter 97% efficiency, v in : 0.5v to 5v, v out(max) : 6v, i q : 38 m a, i sd : <1 m a, 10-lead ms package thinsot is a trademark of linear technology corporation. v in shdn shutdown sync in 3mhz sync pll-lpf r lp 3.01k v in 5v r c 10k r1 178k r2 20.5k c t 33pf np0 1310 ta01a c2 2.2 f v out 12v 400ma c lp 1000pf c c 680pf c1, c2: taiyo yuden lmk212bj225mg d1: motorola mbrm120 l1: panasonic ell6rh2r7m *exposed pad must also be grounded c1 2.2 f fb c t v c sw d1 lt1310 l1 3.3 h gnd* 3mhz 5v to 12v converter load current (ma) 0 35 efficiency (%) 45 55 65 75 100 200 1310 ta01b 400 300 85 40 50 60 70 80 90 3.3v in 5v in efficiency typical applicatio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com

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