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| general description the MAX9856 is a high-performance, low-power stereo audio codec designed for mp3, personal media play- ers (pmps), or other portable multimedia devices. using on-board stereo directdrive headphone ampli- fiers, the codec can output 30mw into stereo 32 headphones while operating from a single 1.8v power supply. very low 9mw playback power consumption makes it an ideal choice for battery-powered applica- tions. the MAX9856 provides microphone input ampli- fiers, plus flexible input selection, signal mixing, and automatic gain control (agc). comprehensive load- impedance sensing allows the MAX9856 to autodetect most common audio and audio/video headset and jack plug types. outputs include stereo directdrive line outputs and directdrive headphone amplifiers. the stereo adc can convert audio signals from either internal or external microphones that can be configured for single-ended or differential signal inputs. line inputs can be config- ured as stereo, differential, or mono and fed through one channel of the microphone path. the analog inputs selected can be gain ranged or mixed with other input sources prior to conversion to digital. the adc path also features programmable digital highpass filters to remove dc offset voltages and wind noise. the MAX9856 supports all common sample rates from 8khz to 48khz in both master and slave mode. the ser- ial digital audio interfaces support a variety of formats including i 2 s, left-justified, and pcm modes. the MAX9856 uses a thermally efficient, space-saving 40-pin, 6mm x 6mm x 0.8mm tqfn package. applications mp3 players personal media players handheld gaming consoles cellular phones features 1.71v to 3.6v single-supply operation stereo 30mw directdrive headphone amplifier stereo 1v rms directdrive line outputs (v dd = 1.8v) and stereo line inputs low-noise stereo and mono differential microphone inputs with automatic gain control and noise quieting 9mw playback power consumption (v dd = 1.8v) 91db 96khz 18-bit stereo dac 85db 48khz 18-bit stereo adc supports any master clock frequency from 10mhz to 60mhz adcs and dacs can run at independent sample rates flexible audio mixing and volume control clickless/popless operation headset detection logic i 2 c control interface MAX9856 low-power audio codec with directdrive headphone amplifiers ________________________________________________________________ maxim integrated products 1 part temp range pin-package MAX9856etl+ -40? to +85? 40 tqfn-ep* MAX9856gtl/v+ -40? to +105? 40 tqfn-ep* ordering information auxin linein1 linein2 sdout sdin bclk lrclk_d lrclk_a sda scl irq mux digital interface dac analog mixers dac adc adc i 2 c digital filtering and mixers dvdd and dvdds2 1.71v to 3.6v avdd and cpvdd 1.71v to 3.6v left line out right line out diff mic left ext mic right ext mic clock control mclk MAX9856 simplified block diagram 19-1288; rev 2; 12/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. pin configuration appears at end of data sheet. directdrive is a registered trademark of maxim integrated products, inc.
MAX9856 low-power audio codec with directdrive headphone amplifiers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages with respect to agnd.) avdd, dvdd, dvdds2, cpvdd .............................-0.3v to +4v pvss, svss........................................capacitor connection only agnd, dgnd, cpgnd.........................................-0.3v to +0.3v hpl, hpr .................................(v svss - 0.3v) to (v avdd + 0.3v) hgndsns, lgndsns, micgnd .........................-0.3v to +0.3v jacksns .................................(v svss - 0.3v) to (v avdd + 0.3v) loutl, loutr ........................(v svss - 0.3v) to (v avdd + 0.3v) linein1, linein2, auxin ...........................................-2v to +2v micl, micr, inlp, inlm, inrm..................................-2v to +2v c1n........................................(v pvss - 0.3v) to (v cpgnd + 0.3v) c1p .....................................(v cpgnd - 0.3v) to (v cpvdd + 0.3v) preg, ref, mbias, micbias................-0.3v to (v avdd + 0.3v) nreg ......................................................(v svss - 0.3v) to +0.3v mclk........................................................................-0.3v to +4v sda, scl, irq .........................................................-0.3v to +4v lrclk_a, lrclk_d, bclk, sdin, sdout ..................................-0.3v to (v dvdds2 + 0.3v) continuous current into/out of hpr/hpl/ loutl/loutr ...............................................................150ma cpvdd/cpgnd/c1p/c1n/pvss ......................................300ma any other pin ......................................................................20ma duration of hpr/hpl/loutl/loutr short circuit to avdd/agnd/cpvdd/cpgnd ............................continuous continuous power dissipation (t a = +70?) 40-pin tqfn (derate 26.3mw/? above +70?, single-layer board) ......................................................2105mw 40-pin tqfn (derate 37mw/? above +70?, multilayer board) .........................................................2963mw operating temperature ranges: e series.............................................................-40? to +85? g series ..........................................................-40? to +105? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units avdd = cpvdd (inferred from hp output psrr) 1.71 1.80 3.60 supply voltage range dvdd, dvdds2 (inferred from codec performance tests) 1.71 1.80 3.60 v i avdd + i cpvdd 2.9 5.1 dac playback mode (f s = 44.1khz) analog i dvdd + i dvdds2 2.3 i avdd + i cpvdd 2.9 4.3 line-only playback mode (dac/adc disabled) i dvdd + i dvdds2 0.14 0.20 i avdd + i cpvdd 3.9 5.4 dac + line input playback mode (f s = 44.1khz) i dvdd + i dvdds2 2.3 3.5 i avdd + i cpvdd 11.0 15.5 full operation, f s = 44.1khz (dac + adc + linein + mic + auxin) i dvdd + i dvdds2 3.7 4.5 i avdd + i cpvdd 6.6 9.1 dac playback, f s = 44.1khz mono adc record f s = 8khz i dvdd + i dvdds2 2.8 3.5 i avdd + i cpvdd 7.8 10.5 total supply current (note 2) i vdd adc record, f s = 44.1khz i dvdd + i dvdds2 2.3 3.5 ma i avdd + i cpvdd 2.2 10 shutdown supply current i dvdd + i dvdds2 0.6 10 ? shutdown to full operation 50 ms MAX9856 low-power audio codec with directdrive headphone amplifiers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units stereo dac (note 3) gain error ? ? % channel gain mismatch ? % dac dynamic specifications f s = 44.1khz, a-weighted, drate = 10 80 91 drate = 00 87 dynamic range (note 4) f s = 8khz to 96khz, a-weighted drate =10 91 db total harmonic distortion thd f in = 1khz, f s = 8khz to 96khz, 0dbfs 82 db drate = 00 87 signal-to-noise ratio snr f s = 8khz to 96khz, a-weighted (note 5) drate = 10 91 db crosstalk driven channel at -1dbfs, f in = 1khz, f s = 8khz 78 db f = 217hz, v ripple = 100mv, a vpga = 0db 93 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv, a vpga = 0db 60 db dac digital filter (8x interpolation, fir (f s = 7.8khz to 50khz)) passband cutoff f p -0.2db from peak 0.44 f s passband ripple f < 0.44 x f s ?.1 db stopband cutoff f s 0.58 f s stopband attenuation f > f s 58 db attenuation at f s /2 -6.02 db dac digital filter (4x interpolation, fir (f s = 50khz to 100khz)) passband cutoff f p -0.2db from peak 0.24 f s passband ripple f < 0.23 x f s ?.1 db stopband cutoff f s 0.5 f s stopband attenuation f > f s 54 db attenuation at f s /2 -60 db dac highpass filter dachp = 000 disabled dachp = 001; lrclk/1598 28 dachp = 010; lrclk/798 55 dachp = 011; lrclk/398 111 dachp = 100; lrclk/197 224 dachp = 101; lrclk/97 455 dachp = 110; lrclk/47 938 -3db corner frequency (f s = 44.1khz) hp filt dachp = 111; lrclk/22 2004 hz dc attenuation dc atten dachp 000 60 db electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units stereo adc (note 6) gain error ? ? % full-scale conversion 0dbfs f in = 1kh z , line input pga = 0db 2 v p-p channel gain mismatch ? % adc dynamic specifications f s = 8khz to 32khz, bw = 22hz to f s /2 80 f s = 44.1khz, bw = 22hz to 20khz, a-weighted 78 84 dynamic range (note 4) f s = 48khz, bw = 22hz to 20khz, a-weighted 85 db 1khz, 0dbfs, f s = 8khz -63 total harmonic distortion thd 1khz, 0dbfs, f s = 48khz -68 db 1khz, 0dbfs, f s = 8khz, bw = 22hz to 20khz, a-weighted 77 signal-to-noise ratio snr 1khz, 0dbfs, f s = 48khz, bw = 22hz to 20khz, a-weighted 77 db channel crosstalk driven channel at -1dbfs, f in = 1khz, f s = 8khz 65 db v avdd = 1.71v to 3.6v 60 100 f = 1khz, v ripple = 100mv 80 power-supply rejection ratio (note 7) psrr f = 10khz, v ripple = 100mv 50 db adc digital filter path passband cutoff f p -0.2db from peak 0.44 f s passband ripple f < f p ?.1 db stopband cutoff f s 0.56 f s stopband attenuation f > f s 60 db attenuation at f s /2 -6.02 db adc highpass filter adchp = 000 disabled adchp = 001; lrclk/1598 28 adchp = 010; lrclk/798 55 adchp = 011; lrclk/398 111 adchp = 100; lrclk/197 224 adchp = 101; lrclk/97 455 adchp = 110; lrclk/47 938 -3db corner frequency (f s = 44.1khz) hp filt adchp = 111; lrclk/22 2004 hz dc attenuation dc atten adchp anything other than 000 90 db dc output offset adchp = 000 -40 dbfs MAX9856 low-power audio codec with directdrive headphone amplifiers _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units adc/dac data rate accuracy lrclk_d and lrclk_a output average sample rate deviation (master mode, any mclk) (note 8) -0.025 +0.025 % lrclk_d output sample rate deviation (master mode) pclk/lrclk = 1536, 1024, 768, 512, 384, 256, 192, or 128 0% lrclk_a, lrclk_d (dhf = 0) 7.8 50 lrclk input sample rate range (slave mode) lrclk_d (dhf = 1) 15.6 100 khz lrclk_d and lrclk_a pll lock time t lock any allowable lrclk and pclk rates 12 25 ms lrclk_d and lrclk_a acceptable jitter for maintaining pll lock (all slave modes) allowable lrclk period change from nominal for slave pll mode at any allowable lrclk and pclk rates ?0 ns headphone amplifiers r l = 16 35 output power p out f = 1khz, thd < 1%, t a = +25 c r l = 32 15 28 mw 0dbfs dac output voltage +0db volume setting 3.40 3.51 3.80 v p-p line in to hp out voltage gain +4.5db volume setting, 0db pga setting 1.77 v/v output offset voltage v os t a = +25?, -40db volume setting ?.6 4 mv r l = 32 , p out = 25mw, f = 1khz 0.03 total harmonic distortion plus noise thd+n r l = 16 , p out = 25mw, f = 1khz 0.05 % dynamic range dr +5.5db volume setting, dac input at f s = 44.1khz (note 4) 80 91 db v avdd = 1.71v to 3.6v 70 94 v ripple = 100mv p-p , f = 217hz 80 power-supply rejection ratio psrr v ripple = 100mv p-p , f = 10khz 50 db capacitive drive c l no sustained oscillations 150 pf crosstalk p out = 1.6mw, f = 1khz, (hpl to hpr) or (hpr to hpl) 69 db channel gain matching a vmatch ? % into shutdown -70 click-and-pop level peak voltage, a-weighted, 32 samples per second out of shutdown -70 dbv line amplifiers 0dbfs dac output voltage 1.0 v rms line-in to line-out voltage gain 0db input pga setting 1.3 1.34 1.4 v/v output offset voltage v os t a = +25? ?.7 ?0 mv MAX9856 low-power audio codec with directdrive headphone amplifiers 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units total harmonic distortion plus noise thd+n v out = 1v rms , f = 1khz 0.024 % signal-to-noise ratio snr 98 db v avdd = 1.71v to 3.6v 70 108 v ripple = 100mv p-p , f = 217hz 93 power-supply rejection ratio psrr v ripple = 100mv p-p , f = 10khz 60 db capacitive drive c l no sustained oscillations 150 pf crosstalk v out = 2v p-p , f = 1khz, (loutl to loutr) or (loutr to loutl) 98 db channel gain matching a vmatch ? % volume control headphone volume control range -74.0 +5.5 db 5.5db to 2db 0.5 +2.5db to -2db 1 -2db to -46db 2 headphone volume control step size -46db to -74db 4 db headphone mute attenuation f = 1khz 92 db charge pump charge-pump oscillator frequency f osc t a = +25? 600 665 720 khz microphone amplifiers palen/paren = 01 -0.5 0 +0.5 palen/paren = 10 19 20 21 preamplifier gain a vpre micl or micr palen/paren = 11 28.5 30.0 31.5 db pgaml/r = 0x20 -0.5 0 +0.5 mic pga gain a vmicpga pgaml/r = 0x00 19.5 20.0 19.5 db mic pga gain step size 1db mic mute attenuation f = 1khz 92 db common-mode rejection ratio cmrr inl? v in = 100mv p-p at 217hz, a vpre = +20db 73 db inl , micl or micr, a vpre = +30db 4 8 10 inl , micl or micr, a vpre = +20db 12 18 28 mic input resistance r in_mic inl , micl or micr, a vpre = 0db 60 100 160 k mic input resistance matching r match inl+ to inl- or micl/micr to agnd 1 % mic input bias voltage v cml measured at inl? micr, micl, and agnd -0.05 0 +0.05 v input voltage noise f = 1khz, a vpre = +30db 15 nv/ hz electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units a vpre = 0db, a vmicpga = 0db, v in = 500mv p-p , f = 1khz, a-weighted 0.04 a vpre = +20db, a vmicpga = 0db, v in = 50mv p-p , f = 1khz, a-weighted 0.08 total harmonic distortion plus noise thd+n a vpre = +30db, a vmicpga = 0db, v in = 18mv p-p , f = 1khz, a-weighted 0.08 % v avdd =1.71v to 3.6v, t a = +25? 79 80 v ripple = 100mv at 1khz, input referred 80 mic power-supply rejection ratio psrr v ripple = 100mv at 10khz, input referred 50 db microphone bias v avdd = 1.8v (mbsel = 0 register setting) 1.4 1.5 1.6 micbias output voltage v micbias v avdd = 3.0v (mbsel = 1 register setting) 2.3 2.4 2.5 v micbias load regulation i micbias = 0 to 2ma 0.8 10 micbias capacitive load minimum capacitive load 1 f micbias short-circuit current to gnd 14 ma v avdd = 1.71v to 3.6v, mbsel = 0, t a = +25? 75 86 v ripple = 100mv at 1khz 86 micbias power-supply rejection ratio psrr v ripple = 100mv at 10khz 76 db f = 10hz to 20khz 3 v rms micbias noise voltage v noisemic bias mbset = 0 or 1 f = 1khz 20 nv/ hz automatic gain control threshold level set by agcsth[3:0] -3 -18 db attack time set by agcatk[1:0] 3 200 ms release time set by agcrls[2:0] 0.078 10.000 s hold time set by agchld[1:0] 50 400 ms a vpre = +30db 30 to 50 a vpre = +20db 20 to 40 gain adjustment range a vpre = 0db 0 to 20 db adc low-level quieting ng attack and release time full 12db quieting at 1db of attenuation/(gain) for every 2db decrease/(increase) of signal level (immediate release if pga < 20db gain when agc is enabled) 0.5 s ng threshold level anth[3:0] setting range (agc off) (agc on adjusts these values by 20db since low- level signals cause maximum agc gain in the pga) -64 -28 db ng attenuation 1db of attenuation for every 2db signal amplitude decrease from ng threshold 012db electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units linein1/linein2 inputs line input full-scale input voltage 0dbfs 2 v p-p input dc bias voltage 0v line input resistance r in pga = 0db (note 9) 12 21 k crosstalk linein1 to linein2 or linein2 to linein1, f = 1khz 97 db line channel-to-channel gain matching av match ? % pga gain range -32 +30 db pga gain step size -32db to +30db 2 db auxin input auxin full-scale input voltage 0dbfs auxdc = 0 2 v p-p input dc voltage range auxdc = 1 0 1 v input dc bias voltage auxdc = 0 0 v auxdc = 0 12 21 k auxin input resistance r in auxdc = 1 100 m line channel-to-channel gain matching av match ? % pga gain range -32 +30 db pga gain step size -32db to +30db 2 db jack sense operation (en[2:0] = 000) jacksns high threshold (jkmic) v th1 t a = +25? 0.92 x v micbias 0.95 x v micbias 0.98 x v micbias v jacksns deglitch period (jkmic) t glitch pulses shorter than t glitch are eliminated 12 ms jacksns voltage (jkmic) jdeten = 1 v av dd v headset impedance detect mode (en[2:0] = 111) jacksns/hpl/hpr high threshold (jsdet/ hsdetl/hsdetr) v th2 hpl/hpr disabled 0.32 0.40 0.48 v jacksns/hpl/hpr low threshold (jsdet/hsdetl/hsdetr) v th3 hpl/hpr disabled 0.075 0.100 0.125 v jacksns/hpl/hpr sense current (jsdet/hsdetl/hsdetr) i sns hpl/hpr disabled 1.7 2.0 2.3 ma electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmigpga = 0db, f mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers _______________________________________________________________________________________ 9 parameter symbol conditions min typ max units sleep mode (jdeten = 1, shdnb = 0) jacksns/hpl resistance r pu micbias = gnd 400 1000 k jacksns/hpl sense voltage v pu v avdd v jacksns/hpl sleep threshold (jksns/lsns) v th4 v avdd - 0.8v v avdd - 0.4v v avdd - 0.15v v parameter symbol conditions min typ max units mclk input characteristics input voltage high v ih 0.7 x v dvdd v input voltage low v il 0.4 v input leakage current i ih , i il -10 +10 ? input capacitance 3pf mclk input frequency 10 60 mhz mclk duty cycle 40 50 60 % maximum mclk input jitter for guaranteed performance limits 100 ps rms digital inputs (bclk, lrclk_a, lrclk_d, sdin, sda, scl) input voltage high v ih 0.7 x v dvdd v input voltage low v il 0.3 x v dvdd v input hysteresis 200 mv input leakage current i ih , i il -10 +10 ? input capacitance 10 pf cmos digital outputs (bclk, lrclk_a, lrclk_d, sdout) output low voltage v ol i ol = 3ma 0.4 v output high voltage v oh i oh = 3ma v dvdd - 0.4 v open-drain digital outputs ( irq , sda) output high current i oh v out = v dvdd 1 a output low voltage v ol i ol = 3ma 0.4 v digital audio interface timing characteristics t bclks slave operation 75 ns bclk cycle time t bclkm master operation 100 325 ns bclk high time t bclkh slave operation 30 ns bclk low time t bclkl master operation 30 ns bclk or lrclk_a/d rise and fall time t r , t f master operation, c l = 15pf 7 ns digital interface electrical characteristics (v dvdd = v dvdds2 = 1.8v, t a = t min to t max , unless otherwise noted.) (note 1) electrical characteristics (continued) (v avdd = v cpv dd = v dv dds2 = v dv dd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg = 1?, a v pre = +20db, c micbias = 1?, a vmicpga = 0db, mclk = 11.2896mhz, drate = 00, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers 10 ______________________________________________________________________________________ parameter symbol conditions min typ max units sdin or lrclk_a/d to bclk rising setup time t su bci = 0 (see the i 2 c register address map and definitions section) 30 ns sdin or lrclk_a/d to bclk rising hold time t hd bci = 0 (see the i 2 c register address map and definitions section) 5ns sdout delay time t dly bci = 0 (see the i 2 c register address map and definitions section), c l = 30pf 050ns i 2 c interface timing characteristics serial-clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? scl pulse width low t low 1.3 ? scl pulse width high t high 0.6 ? setup time for a repeated start condition t su,sta 0.6 ? data hold time t hd , dat 0 900 ns data setup time t su , dat 100 ns sda and scl receiving rise time t r (note 10) 20 + 0.1c b 300 ns sda and scl receiving fall time t f (note 10) 20 + 0.1c b 300 ns v dvdd = 1.8v (note 10) 20 + 0.1c b 250 sda transmitting fall time t f v dvdd = 3.6v (note 10) 20 + 0.05c b 250 ns setup time for stop condition t su , sto 0.6 ? bus capacitance c b 400 pf pulse width of suppressed spike t sp t a = +25? 0 50 ns note 1: all devices are 100% production tested at room temperature. all temperature limits are guaranteed by design. note 2: supply current measurements taken with no applied input signal to line and microphone inputs. a digital zero audio signal used for all digital serial audio inputs. speaker and headphone outputs are loaded as stated in the global conditions. note 3: dac performance measured at headphone outputs. note 4: dynamic range measured using the eiaj method . the input is applied at -60dbfs, f in = 1khz. the is thd+n referred to 0dbfs. note 5: signal-to-noise ratio measured using an all-zeros input signal, and is relative to 0db full scale. the dac is not muted for the snr measurement. note 6: performance measured from line inputs (unless otherwise noted). note 7: microphone amplifiers connected to adc, microphone inputs ac-grounded. note 8: in master-mode operation, the accuracy of the mclk input proportionally determines the accuracy of the sample clock rate. (v dvdd = 1.8v, unless otherwise noted). note 9: to enable the line input, make sure the desired input is selected by either the audio output mixer or the adc input mixer. note 10: c b is in pf. digital interface electrical characteristics (continued) (v dvdd = v dvdds2 = 1.8v, t a = t min to t max , unless otherwise noted.) (note 1) MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 11 total harmonic distortion plus noise vs. output power (dac to hp) MAX9856 toc01 output power (mw) thd+n (%) 35 30 25 20 15 10 5 0.01 0.1 1 10 100 0.001 040 hp gain = +5.5db r l = 32 1khz 20khz 10khz total harmonic distortion plus noise vs. output power (dac to hp) MAX9856 toc02 output power (mw) thd+n (%) 50 40 30 20 10 0.01 0.1 1 10 100 0.001 060 hp gain = +5.5db r l = 16 1khz 20hz 10khz total harmonic distortion + noise vs. frequency (dac to hp) MAX9856 toc03 frequency (hz) thd+n (%) 10e+3 1e+3 100e+0 0.01 0.1 1 10 0.001 10e+0 100e+ 3 hp gain = +5.5db r l = 32 5mw 20mw total harmonic distortion + noise vs. frequency (dac to hp) MAX9856 toc04 frequency (hz) thd+n (%) 10e+3 1e+3 100e+0 0.01 0.1 1 10 0.001 10e+0 100e+3 hp gain = +5.5db r l = 16 5mw 20mw total harmonic distortion + noise vs. frequency (dac to line out) MAX9856 toc05 frequency (hz) thd+n (%) 10e+3 1e+3 100e+0 0.01 0.1 1 10 0.001 10e+0 100e+3 v out = 2v p-p r l = 10k total harmonic distortion plus noise vs. frequency (line in to adc) MAX9856 toc06 frequency (hz) thd+n (%) 10k 1k 100 0.01 0.1 1 10 0.001 10 100k total harmonic distortion plus noise vs. frequency (intmic to adc) MAX9856 toc07 frequency (hz) thd+n (%) 10k 1k 100 0.01 0.1 1 10 0.001 10 100k adc out = -3dbfs mic preamp = +20db mic gain = 0db total harmonic distortion plus noise vs. frequency (intmic to adc) MAX9856 toc08 frequency (hz) thd+n (%) 10k 1k 100 0.01 0.1 1 10 0.001 10 100k adc out = -3dbfs mic preamp = +30db mic gain = 0db power out vs. headphone load MAX9856 toc09 headphone load ( ) power out (mw) 100 10 10 1000 1 100 1 f in = 1khz thd+n = 10% thd+n = 1% typical operating characteristics (v avdd = v cpvdd = v dvdds2 = v dvdd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg =1?, v avpre = +20db, c micbias = 1?, v av micpga = 0db, f mclk = 12.288mhz, drate = 10, t a = +25?, unless otherwise noted.) MAX9856 low-power audio codec with directdrive headphone amplifiers 12 ______________________________________________________________________________________ power-supply rejection ratio vs. frequency (dac to hp) MAX9856 toc10 frequency (hz) psrr (db) 10k 1k 100 -100 -80 -60 -40 -20 0 -120 10 100k v ripple = 100mv p-p power-supply rejection ratio vs. frequency (dac to line out) MAX9856 toc11 frequency (hz) psrr (db) 10k 1k 100 -100 -80 -60 -40 -20 0 -120 10 100k v ripple = 100mv p-p -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz synchronous slave mode, 0dbfs MAX9856 toc12 fre q uency ( hz ) amplitude (dbfs) mclk = 12.288mhz lrclk = 48khz pclk/2 -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz synchronous slave mode, -60dbfs MAX9856 toc13 frequency ( hz ) amplitude (dbfs) mclk = 12.288mhz lrclk = 48khz pclk/2 -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz asynchronous master mode, 0dbfs MAX9856 toc14 fre q uency ( hz ) amplitude (dbfs) mclk = 11.2896mhz lrclk = 48khz pclk/2 -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz asynchronous master mode, -60dbfs MAX9856 toc15 fre q uency ( hz ) amplitude (dbfs) mclk = 11.2896mhz lrclk = 48khz pclk/2 -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz asynchronous slave mode, 0dbfs MAX9856 toc16 fre q uency ( hz ) amplitude (dbfs) mclk = 11.2896mhz lrclk = 48khz pclk/2 -140 -100 -120 -80 -20 0 -40 -60 20 000e+0 4e+3 6e+3 8e+3 10e+3 2e+3 12e+3 14e+3 16e+3 18e+3 20e+3 fft, dac to line out, 48khz asynchronous slave mode, -60dbfs MAX9856 toc17 frequency (hz) amplitude (dbfs) mclk = 11.2896mhz lrclk = 48khz pclk/2 fft, line in to adc (48khz) synchronous master mode (0dbfs) MAX9856 toc18 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 12.288mhz lrclk = 48khz pclk/2 typical operating characteristics (continued) (v avdd = v cpvdd = v dvdds2 = v dvdd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg =1?, v avpre = +20db, c micbias = 1?, v av micpga = 0db, f mclk = 12.288mhz, drate = 10, t a = +25?, unless otherwise noted.) MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 13 fft, line in to adc (48khz) synchronous master mode (-60dbfs) MAX9856 toc19 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 12.288mhz lrclk = 48khz pclk/2 fft, line in to adc (48khz) asynchronous master mode (0dbfs) MAX9856 toc20 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 11.2896mhz lrclk = 48khz pclk/2 fft, line in to adc (48khz) asynchronous master mode (-60dbfs) MAX9856 toc21 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 11.2896mhz lrclk = 48khz pclk/2 fft, line in to adc (48khz) asynchronous slave mode (0dbfs) MAX9856 toc22 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 11.2896mhz lrclk = 48khz pclk/2 fft, line in to adc (48khz) asynchronous slave mode (-60dbfs) MAX9856 toc23 frequency (hz) amplitude (dbfs) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k mclk = 11.2896mhz lrclk = 48khz pclk/2 wideband fft, dac to hp amp, 48khz synchronous master mode, 0dbfs MAX9856 toc24 frequency (hz) amplitude (dbfs) 1m 100k 100 1k 10k -130 -110 -90 -70 -50 -30 -10 10 -150 10 10m c1 = 4.7 f wideband fft, dac to hp amp, 48khz synchronous master mode, -60dbfs MAX9856 toc25 frequency (hz) amplitude (dbfs) 1m 100k 100 1k 10k -130 -110 -90 -70 -50 -30 -10 10 -150 10 10m c1 = 4.7 f supply current vs. supply voltage MAX9856 toc26 supply voltage (v) supply current (ma) 3.5 3.0 2.5 2.0 1.5 2 4 6 8 10 12 14 16 18 20 0 1.0 4.0 stereo dac playback mode (48khz) supply current = i vdd + i dvdds2 dac digital filter frequency response MAX9856 toc27 frequency (hz) output amplitude (db) 20k 15k 10k 5k -6 -5 -4 -3 -2 -1 0 1 2 3 -7 0 25k typical operating characteristics (continued) (v avdd = v cpvdd = v dvdds2 = v dvdd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg =1?, v avpre = +20db, c micbias = 1?, v av micpga = 0db, f mclk = 12.288mhz, drate = 10, t a = +25?, unless otherwise noted.) MAX9856 low-power audio codec with directdrive headphone amplifiers 14 ______________________________________________________________________________________ adc digital filter frequency response MAX9856 toc28 frequency (hz) output amplitude (db) 20k 15k 10k 5k -6 -5 -4 -3 -2 -1 0 1 2 3 -7 0 25k click-pop MAX9856 toc29 time (200ms/div) scl 1v/div 0v 0v 0v sda 1v/div hpl 5mv/div dac soft-start MAX9856 toc30 time (4ms/div) scl 1v/div 0v 0v 0v sda 1v/div lineoutl 1v/div automatic gain control thresholds MAX9856 toc31 microphone input (dbv) adc output (dbfs) 0 -20 -80 -60 -40 -60 -50 -40 -30 -20 -10 0 10 -70 -100 20 total harmonic distortion + noise vs. mclk frequency, 0dbfs MAX9856 toc32 frequency (mhz) thd+n (%) 12 14 16 18 0.1 1 0.01 10 20 11 13 15 17 19 dac playback mode (48khz) dynamic range vs. mclk frequency (-60dbfs) MAX9856 toc33 frequency (mhz) dynamic range (db) 16 14 12 82 84 86 88 90 92 94 96 98 100 80 10 20 dac playback mode (48khz) typical operating characteristics (continued) (v avdd = v cpvdd = v dvdds2 = v dvdd = 1.8v, r hp = 32 , r line = 10k , c1 = 4.7?, c2 = 4.7?, c ref = c mbias = c preg = c nreg =1?, v avpre = +20db, c micbias = 1?, v av micpga = 0db, f mclk = 12.288mhz, drate = 10, t a = +25?, unless otherwise noted.) MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 15 pin description pin name function 1 linein1 line 1 input. ac-couple signal to linein1 with a 1? capacitor. 2 linein2 line 2 input. ac-couple signal to linein2 with a 1? capacitor. 3 auxin auxiliary input. input for beep and sound effect signals or can be used for dc measurements. 4 preg positive internally regulated supply (+1.6v ?%). bypass to agnd with 1? capacitor. 5 nreg negative internally regulated supply (-1.15v ?%). bypass to agnd with 1? capacitor. 6 mbias internal microphone bias regulator output (1.23v ?%). bypass to agnd with a 1? capacitor. 7 ref converter reference (1.23v ?%). bypass to agnd with a 1? capacitor. 8 lgndsns line output ground sense. feedback path to line-out amplifiers for noise reduction. connect to the ground pin of the line output jack. connect directly to agnd, if ground sense is not required. 9 loutl left-channel line output. ground-referenced directdrive output. 10 loutr right-channel line output. ground-referenced directdrive output. 11 hgndsns headphone ground sense. feedback path to headphone amplifiers for noise reduction. connect to the ground pin of the headphone jack. connect directly to agnd if ground sense is not required. 12 avdd analog power supply. bypass to agnd with 10? and 0.1? capacitors. 13 hpl left headphone directdrive output 14 hpr right headphone directdrive output 15 svss negative power-supply input. connect to pvss and bypass to cpgnd with a 4.7? capacitor. 16 pvss internally generated negative supply. connect to svss. 17 c1n charge-pump flying capacitor negative terminal. connect a 4.7? capacitor between c1n and c1p. 18 cpgnd charge-pump ground 19 c1p charge-pump flying capacitor positive terminal. connect a 4.7? capacitor between c1p and c1n. 20 cpvdd charge-pump positive supply. bypass to cpgnd with a 4.7? capacitor. 21 scl i 2 c serial-clock input. connect a 10k pullup resistor to dvdd. 22 sda i 2 c serial-data input/output. connect a 10k pullup resistor to dvdd. 23 irq hardware interrupt output. irq can be programmed to pull low when bits in the status register 0x00 change state. read status register 0x00 to clear irq once set. repeat faults have no effect on irq until it is cleared by reading the i 2 c status register 0x00. connect a 10k pullup resistor to dvdd for full output swing. 24 lrclk_d digital audio left-right clock input/output. lrclk_d is the audio sample rate clock that determines whether the audio data on sdin is routed to the left or right channel. lrclk_d is an input when the MAX9856 is in slave mode and an output when in master mode. lrclk_d is also used with sdout if lrclk_a is configured as a gpio. MAX9856 low-power audio codec with directdrive headphone amplifiers 16 ______________________________________________________________________________________ pin description (continued) pin name function 25 bclk digital audio bit clock input/output. bclk is an input when the MAX9856 is in slave mode and an output when in master mode. 26 sdout digital audio serial data adc output 27 sdin digital audio serial data dac input 28 dvdds2 digital audio interface i/o power supply. bypass to dgnd with 1? capacitor. 29 lrclk_a digital audio left-right clock input/output. lrclk_a is the audio sample rate clock that determines whether the audio data on sdout is routed to the left or right channel. when only one lrclk is needed (adc and dac are at the same sample rate), lrclk_a can be reprogrammed as a general-purpose input/output, gpio. 30 mclk master clock input (cmos input). acceptable input frequency range: 10mhz to 60mhz. 31 dvdd digital power supply. supply for the digital core and i 2 c interface. bypass to dgnd with a 1.0? capacitor. 32 dgnd digital ground 33 inln inverting left differential input. ac-couple to the low side of microphone, or connect to the negative line signal. ac-couple to ground when using with a single-ended line or microphone input. 34 inlp noninverting left differential input. ac-couple to the high side of microphone, or connect to the positive line signal. ac-couple to the signal when using with a single-ended line or microphone input. 35 micl left-channel single-ended microphone input. ac-couple to the microphone with a 1? capacitor. 36 micgnd microphone ground. allows the common return signal of a stereo microphone pair to be connected to the inverting input differential amps in a pseudo differential configuration. alternatively micgnd can be grounded for single-ended microphone applications. 37 micr right-channel single-ended microphone input. ac-couple to the microphone with a 1? capacitor. 38 micbias low-noise bias voltage. outputs a 1.5v or 2.4v microphone bias. an external resistor in the 2.2k to 470 range should be used to set the microphone current. 39 agnd analog ground (and chip substrate) 40 jacksns jack sense. detects the presence or absence of a jack, and can be configured to detect the impedance range of the external load. see the headset detection section. ?p exposed pad. the exposed pad lowers the package? thermal impedance by providing a direct heat conduction path from the die to the pcb. the exposed pad is internally connected to the substrate. connect the exposed thermal pad to agnd. MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 17 functional diagram MAX9856 1 f 4.7 f 1.71v to 3.6v 20 cpvdd linein1 ln1 -32db to +30db -32db to +30db 0 to 20db 0 to 20db pga 1 f 2 1 linein2 ln2 -32db to +30db 0 20db 30db pga 1 f 3 auxin 29 lrclk_a auxac auxdc pga digital audio interface digital filtering and gain left dac dacl dacr auxdc 24 lrclk_d 25 bclk 27 sdin 26 sdout dvdd dvdd 23 irq 30 mclk 10k left adc input mixer right dac digital filtering and gain left adc right adc auxac ln1 ln2 micl micr right adc input mixer auxac micr ln1 ln2 micl micr timing and control logic 21 scl 22 sda agnd 39 10k i 2 c serial port internal regulators automatic gain control 10k dgnd 32 cpgnd 18 preg 4 1 f nreg 5 1 f mbias 6 1 f ref c1n c1p svss pvss 7 19 17 16 1 f c1 4.7 f c2 4.7 f 2.2k charge pump 15 microphone bias and jack detection 38 micbias 40 jacksns 37 micr 36 micgnd 35 micl 34 inlp 33 inln 13 hpl pga preamplifier 1 f 1 f 1 f 1 f 1 f 0 20db 30db micl pga preamplifier 14 hpr 11 hgndsns left audio output mixer micl ln1 ln2 dacl pga -73db to +6db -73db to +6db auxac pga right audio output mixer micr ln1 ln2 dacr 9 loutl 10 loutr 8 lgndsns 12 avdd 1 f 0.1 f 10 f 1.71v to 3.6v 31 dvdd 1 f 28 dvdds2 MAX9856 low-power audio codec with directdrive headphone amplifiers 18 ______________________________________________________________________________________ detailed description the MAX9856 is a high-performance, low-power stereo audio codec designed to provide a complete audio solution. operating from a 1.8v supply, the MAX9856 achieves high performance and reasonable output power while consuming only 9mw in dac playback mode. the internal 18-bit sigma-delta dac accepts stereo di- gital audio signals, and converts them to stereo audio outputs that can be mixed with line inputs and/or micro- phone inputs. the dac is capable of operating at sam- ple rates ranging from 8khz to 96khz with any master clock frequency between 10mhz and 60mhz. the dac is capable of operating at a different sample rate than the adc. both master and slave modes are available when operating the interface in left-justified, i 2 s or pcm data format. the incoming data can be level shifted and highpass filtered in the digital domain. the highpass fil- tering allows only reproducible frequencies to be con- verted, saving power and improving sound quality. the MAX9856 features stereo directdrive headphone amplifiers and line outputs, which eliminate the need for large output-coupling capacitors. the audio output path includes high-quality mixing amplifiers to allow flexibility in choosing from the dac output and the stereo analog line inputs. volume control amplifiers provide adjustable gains between +5.5db and -74db for the headphones. the line outputs are capable of generating a 1v rms out- put signal from a full-scale digital input. the digital audio signals of the internal 18-bit sigma- delta adc outputs are converted from the analog micro- phone and line input paths. the adc is capable of operating at a sample rate ranging from 8khz to 48khz with any master clock frequency between 10mhz and 60mhz. the adc is capable of operating at a different sample rate than the dac. both master and slave modes are available when operating the interface in left- justified, i 2 s, or pcm data formats. the outgoing data can be level shifted and highpass filtered in the digital domain. the highpass filtering allows reduction of wind noise from microphone inputs. three microphone inputs are available. one fully differ- ential input can be used with internal microphones while a pair of single-ended inputs can be used with an external mono or stereo headset microphone. selectable gain of 0db, 20db, and 30db can be applied to the input signals in addition to a 0 to 20db input pga. the MAX9856 features agc on the micro- phone input path to automatically compensate for vary- ing input signal levels and the limited dynamic range of most microphones. the integrated noise gate provides low-level audio noise quieting to lower the audible noise floor. an auxiliary input is available for sending externally generated beeps and sound effects directly to the headphones. the auxiliary input can also be used to make dc measurements with the adc by providing a direct path to the adc. hpl, hpr, and jacksns provide a headset detection feature which can both detect the insertion of a jack and measure the load impedance. jack detection can be done in both shutdown and powered-on mode. the headphone and line outputs feature ground sensing to reduce ground noise. reduced output offset voltage and extensive click-and-pop suppression circuitry on headphone amplifiers eliminate audible clicks and pops at startup and shutdown i 2 c register address map and definitions the MAX9856 has 28 internal registers used for config- uration and status reporting. table 1 lists all the regis- ters, their addresses, and power-on-reset (por) states. registers 0x00 and 0x01 are read only, while all the other registers are read/write. write zeros to all unused bits in the register table when updating the register, unless otherwise noted. MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 19 register b7 b6 b5 b4 b3 b2 b1 b0 register address power-on reset state status cld sld ulk jkmic hpocl hpocr jdet gpi 0x00 status lsns jksns hsdetl hsdetr jsdet 0x01 interrupt enable icld isld iulk 0 ihpocl ihpocr ijdet igpi 0x02 0x00 clock control clock rates 0 psclk mas bsel 0x03 0x00 dac interface system dwci dbci drate ddly pcm dhf ws 0x04 interface dpllen dacni[14:8] 0x05 0x00 interface dacni[7:0] 0x06 0x00 adc interface system awci abci apin adly 0 0 0 0x07 0x00 interface apllen adcni[14:8] 0x08 0x00 interface adcni[7:0] 0x09 0x00 level again anth 0x0a 0x00 digital filters highpass filters 0 adchp 0 dachp 0x0b 0x00 automatic gain control agc control 0 agcrls agcatk agchld 0x0c 0x00 agc threshold 0 0 0 agcsrc agcsth 0x0d 0x00 analog mixers adc mixer 0 0 0 mxinl 0x0e 0x00 adc mixer 0 0 0 mxinr 0x0f 0x00 output mixer mxoutl mxoutr 0x10 0x00 audio inputs digital input gain pgads 0x11 0x00 auxin gain 0 0 0 pgaaux 0x12 0x00 linein1 gain 0 0 0 pgal1 0x13 0x00 linein2 gain 0 0 0 pgal2 0x14 0x00 micl gain 0 paenl pgaml 0x15 0x00 micr gain 0 paenr pgamr 0x16 0x00 mic mode 0 0 0 0 mmic mbsel 0 lmicdif 0x17 0x00 audio outputs hpl volume 0 hpmute hpvoll 0x18 0x00 hpr volume 0 0 hpvolr 0x19 0x00 output mode 0 vsen auxdc auxmix 0 0 hpmode 0x1a 0x00 headset detect system 0 0 0 0 jdeten en 0x1b 0x00 power management system shdn 0 digen louten dalen daren adlen adren 0x1c 0x00 table 1. register map MAX9856 low-power audio codec with directdrive headphone amplifiers 20 ______________________________________________________________________________________ status registers status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. the status register bits are cleared upon a read operation of the status register and are set the next time the event occurs. table 2 lists the status registers bit location and description. reg b7 b6 b5 b4 b3 b2 b1 b0 0x00 cld sld ulk jkmic hpocl hpocr jdet gpi 0x01 lsns jksns hsdetl hsdetr jsdet table 2. status registers bit location bit function cld clip detect flag. indicates that a signal has become clipped in the adc. sld slew-level detect flag. when volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate settings. when sld is set high, all slewing has completed and the volume or gain is at its final value. ulk digital pll unlock flag. indicates that the digital audio pll for the dac or adc has become unlocked and digital signal data is not reliable. jkmic jack microphone flag. indicates jacksns has been pulled up to the micbias voltage. the microphone bias must be enabled for this bit to function properly. hpocl/ hpocr headphone output left/right current overload flags. indicate that the headphone output amplifiers have exceeded the rated current. jdet headset configuration change flag. indicates a change in jkmic, lsns, or jksns. gpi gpi state. indicates the state of lrclk_a when configured as a general-purpose input. lsns headphone sense. lsns is set when the internal pullup current forces the voltage at hpl to exceed avdd - 0.4v. this indicates headphone jack insertion or removal has occurred. hpmode must be set to 00 and jdeten set to 1 for this bit to function. jksns jack s ense. jks n s i s set w hen the i nter nal p ul l up cur r ent for ces the vol tag e on jac ks n s to exceed avdd - 0.4v . thi s i nd i cates j ack i nser ti on or r em oval has occur r ed . jd e te n m ust b e set for thi s b i t to functi on. load impedance sense. indicates the approximate load connected to hpr, hpl, or jacksns. these bits are updated once each time the appropriate en bits are set high and cause an undefeatable hardware interrupt. bits headphone or jacksns load 00 200 < load < open 01 50 < load < 200 10 0 < load < 50 hsdetl, hsdetr, jsdet 11 idle state status register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 21 interrupt enables hardw are interrupts are reported on the open-drain irq pin. when an interrupt occurs, irq remains low until the interrupt is serviced by reading status register 0x00. if a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. each bit enables interrupts for the status flag in the respective bit location in register 0x00. table 3 lists the interrupt enable bit locations and description. reg b7 b6 b5 b4 b3 b2 b1 b0 0x02 icld isld iulk 0 ihpocl ihpocr ijdet igpi table 3. interrupt enable bit locations reg b7 b6 b5 b4 b3 b2 b1 b0 0x03 0 psclk mas bsel table 4. clock control register bits function psclk mclk prescaler. set psclk to appropriately divide down mclk to a usable frequency: 000?isable clock input 001?0mhz mclk 16mhz (pclk = mclk/1) 010?6mhz mclk 20mhz (pclk = mclk/1) 011?0mhz mclk 32mhz (pclk = mclk/2) 100?2mhz mclk 40mhz (pclk = mclk/2) 101?0mhz mclk 60mhz (pclk = mclk/4) 110?eserved 111?eserved mas master mode. selects between master and slave operation: 0 = slave mode (bclk, lrclk_d, and lrclk_a are inputs) 1 = master mode (bclk, lrclk_d, and lrclk_a are outputs) bsel bclk select. configures bclk when operating in master mode. set bsel to be a sufficiently high frequency to fully clock in all data bits for both the dac and adc, if operating at different sample rates: 000?ff 001?ff 010?clk = 48 x lrclk_d (recommended if the dac and adc operate at the same rate) 011?clk = 48 x lrclk_a 100?clk = pclk/2 (recommended if the dac and adc are not operating at the same rate) 101?clk = pclk/4 110?clk = pclk/8 111?clk = pclk/16 clock control register bit description clock control the MAX9856 can work with a master clock supplied from any system clock (mclk) within the range of 10mhz to 60mhz range. a clock prescaler divides by 1, 2, or 4 to create an internal clock (pclk) in the 10mhz to 20mhz range. there are two clock-generation circuits that operate independently for the adc and dac path, allowing the adc and dac to be operated at different sample rates. bclk services the lrclk signals for both the adc and dac. when the adc and dac operate at different lrclk rates, bclk should be set appropriately for the higher sample rate. the number of clock cycles per frame must be greater than or equal to the configured bit depth. the MAX9856 digital audio interface can operate in either master or slave mode. in master mode, the MAX9856 generates the bclk and lrclk signals, which control the data flow on the digital audio inter- face. in slave mode, the external master device gener- ates the bclk and lrclk signals. see table 4. MAX9856 dac interface the MAX9856 dac is capable of supporting any sam- ple rate from 8khz to 96khz in either master or slave mode, including all common sample rates (8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz, 88.2khz and 96khz). a 15-bit clock divider coefficient must be programmed into the device to set the dac sample rate relative to the prescaled mclk input (pclk). this allows high flexibility in both the mclk and lrclk_d frequencies. in slave mode, the interface accepts any lrclk_d sig- nal between 7.8khz to 100khz. there are two speed settings for the dac set by the drate control bits. the highest rate runs the modulator at an internal clock rate between 5mhz and 10mhz, and provides the highest audio performance. the low rate runs the modulator between 2.5mhz and 5mhz for reduced power consumption. the digital audio interface offers full functionality for several digital audio formats including left-justified, i 2 s, and pcm modes (figure 1). figure 2 shows the digital timing for various modes. table 5 shows the dac inter- face registers and descriptions. table 6 lists the common dacni and adcni values. low-power audio codec with directdrive headphone amplifiers 22 ______________________________________________________________________________________ reg b7 b6 b5 b4 b3 b2 b1 b0 0x04 dwci dbci drate ddly pcm dhf ws 0x05 dpllen dacni[14:8] 0x06 dacni[7:0] table 5. dac interface registers register function dwci dac word clock (lrclk_d) invert when pcm = 0: 0?eft-channel data is transmitted while lrclk_d is low. 1?ight-channel data is transmitted while lrclk_d is low. when pcm = 1: 0?tart of a new frame is signified by the falling edge of the lrclk_d pulse. 1?tart of a new frame is signified by the rising edge of the lrclk_d pulse. dbci dac bclk invert: 0?din is accepted on the rising edge of bclk. 1?din is accepted on the falling edge of bclk. in master mode: 0?rclk_d transitions occur on the falling edge of bclk. 1?rclk_d transitions occur on the rising edge of bclk. drate dac modulator rate: 00?ow-power mode 01?eserved 10?igh-performance mode 11?ac clock disabled ddly dac data delay: 0?he most significant bit of an audio word is latched at the first bclk edge after the lrclk_d transition. 1?he most significant bit of an audio word is latched at the second bclk edge after the lrclk_d transition. (ddly = 1 for i 2 s-compatible mode) dac interface register bit descriptions MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 23 register function pcm pcm mode select. pcm determines the format of the lrclk_d and lrclk_a signal: 0?he lrclk_d and lrclk_a signals have a 50% duty cycle. left-channel audio is transmitted during one state of and right-channel audio during the other state. 1?rclk_d and lrclk_a are pulses that indicate the start of a frame of audio data consisting of two channels. following the frame sync pulse, 16 bits of left-channel data is immediately followed by 16 bits of right-channel data. the ddly and ws bits are ignored when pcm = 1. dhf dac high-sample rate mode: 0?rclk_d is less than 50khz. 8x fir interpolation filter used. 1?rclk_d is greater than 50khz. 4x fir interpolation filter used. ws word size. this bit controls both the dac and adc: 0?6 bits. 1?8 bits. the dac interface can accept higher than 18-bit words but the additional least significant bits are ignored. dpllen dac pll enable: 0 (valid for slave and master mode)?he frequency of lrclk_d is set by the dacni divider bits. in master mode, the MAX9856 generates lrclk_d using the specified divide ratio. in slave mode, the MAX9856 expects an lrclk_d as specified by the divide ratio. 1 (valid for slave mode only)? digital pll locks on to any externally supplied lrclk_d signal regardless of the mclk frequency. dhf must set high for sample rates above 50khz. dacni dac lrclk divider. when dpllen is set low, the frequency of lrclk_d is determined by dacni. see table 6 for common dacni values: dacni = (65536 x 96 x f lrclk_d )/f pclk for (dhf = 0). dacni = (65536 x 48 x f lrclk_d )/f pclk for (dhf = 1). f lrclk_d = lrclk_d frequency. f pclk = prescaled mclk internal clock frequency (pclk). dac interface register bit descriptions (continued) lrclk mclk (mhz) psclk 8khz 16khz 32khz 44.1khz 48khz 88.2khz (dac only) 96khz (dac only) 11.2896 001 116a 22d4 45a9 6000 687d 6000 687d 12 001 1062 20c5 4189 5a51 624e 5a51 624e 12.288 001 1000 2000 4000 5833 6000 5833 6000 13 001 f20 1e3f 3c7f 535f 5abe 535f 5abe 16.9344 010 b9c 1738 2e71 4000 45a9 4000 45a9 18.432 010 aab 1555 2aab 3acd 4000 3acd 4000 19.2 010 960 4b0 258 1b3 190 1b3 190 24 011 1062 20c5 4189 5a51 624e 5a51 624e 26 011 f20 1e3f 3c7f 535f 5abe 535f 5abe 27 011 e90 1d21 3a41 5048 5762 5048 5762 table 6. common dacni and adcni values note: values in bold are exact integers that provide maximum full-scale performance. MAX9856 low-power audio codec with directdrive headphone amplifiers 24 ______________________________________________________________________________________ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 left right left right left right left right left right left right digital audio interface slave modes: (lrclk should transition on the unused bclk edge) dwci/awci = 0, dbci/abci = 0, ddly/adly = 0, ws = 0, pcm = 0 digital audio interface master mode: dwci/awci = 0, dbci/abci = 0, ddly/adly = 0, ws = 0, pcm = 0 dwci/awci = 1, dbci/abci = 1, ddly/adly = 0, ws = 0, pcm = 0 dwci/awci = 0, dbci/abci = 0, ddly/adly = 1, ws = 1, pcm = 0 dwci/awci = 0, dbci/abci = 0, ddly/adly = 0, ws = 0, pcm = 1 dwci/awci = 0, dbci/abci = 0, ddly/adly = 1, ws = 0, pcm = 0 figure 1. digital audio interface data format examples MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 25 adc interface the stereo adc is capable of outputting data at any sample rate from 8khz to 48khz. data can be output in common formats including left justified, i 2 s, and pcm (figure 1). figure 2 shows the digital timing in both slave and master modes. if the dac and adc operate at the same sample rate only the lrclk_d is needed, allowing the lrclk_a pin to be reassigned as a gpio. when configured as a general-purpose output, lrclk_a can be set high or low by the apin bits. when configured as a general- purpose input, the status is reported in register 0x00. table 7 lists and describes the adc interface registers. dai stereo serial interface timing diagram (slave mode) dai stereo serial interface timing diagram (master mode) sdin/lrclk (inputs) bclk (bci = 0, input) bclk (bci = 1, input) sdout (output) sdin (input) bclk (output) sdout/lrclk (outputs) t su t su t r, t f t r, t f t hd t hd t dly t dly t bclks t bclkm t bclkh, t bclkl t bclkh, t bclkl figure 2. digital audio interface timing diagrams reg b7 b6 b5 b4 b3 b2 b1 b0 0x07 awci abci apin adly 0 0 0 0x08 apllen adcni[14:8] 0x09 adcni[7:0] 0x0a again anth table 7. adc interface registers register function awci adc word clock (lrclk_a) invert when pcm = 0: 0?eft-channel data is transmitted while lrclk_a is low. 1?ight-channel data is transmitted while lrclk_a is low. when pcm = 1: 0?tart of a new frame is signified by the falling edge of the lrclk_a pulse. 1?tart of a new frame is signified by the rising edge of the lrclk_a pulse. abci adc bclk invert: 0?dout is valid on the rising edge of bclk. 1?dout is valid on the falling edge of bclk. if operating in master mode, the abci bit has no effect. the dbci bit controls bclk to lrclk_a timing. adc interface register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers 26 ______________________________________________________________________________________ register function apin lrclk_a/gpio configuration: 00 = general-purpose input 01 = word clock for the adc 10 = general-purpose output?ow 11 = general-purpose output?igh when apin 01, lrclk_d is used as the word clock for both the dac and adc. awci, abci, and adly are still active and independent from the dac mode bit settings when operating with a shared lrclk_d. adly adc data delay 0?he most significant bit of an audio word is valid at the first bclk edge after the lrclk_a transition. 1?he most significant bit of an audio word is valid at the second bclk edge after the lrclk_a transition. (adly = 1 for i 2 s-compatible mode) apllen adc pll enable. this bit only applies when apin = 01. when apin 01 use dpllen for both the dac and adc: 0 (valid for slave and master mode)?he frequency of lrclk_a is set by the adcni divider bits. in master mode, the MAX9856 generates lrclk_a using the specified divide ratio. in slave mode, the MAX9856 expects an lrclk_a using specified divide ratio. 1 (valid for slave mode only)? digital pll locks on to any externally supplied lrclk_a signal regardless of the mclk frequency. adcni adc lrclk divider. if apin 01, use dacni for both the dac and adc. when apllen is set low, the frequency of lrclk_a is determined by adcni. see table 6 for common adcni values: adcni = (65536 x 96 x f lrclk_a )/f pclk . f lrclk_a = lrclk_a frequency. f pclk = prescaled mclk internal clock frequency (pclk). adc output gain. specifies the gain applied to the digital output of the adc prior to being output from the device. value gain (db) 0x0 +3 0x1 +2 0x2 +1 0x3 0 0x4 -1 0x5 -2 0x6 -3 0x7 -4 0x8 -5 0x9 -6 0xa -7 0xb -8 0xc -9 0xd -10 0xe -11 again 0xf -12 adc interface register bit description (continued) MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 27 register function adc noise gate threshold. the MAX9856 features a noise gate that reduces the audible noise at low signal levels. the noise gate attenuates the output at a rate of 1db for each 2db the signal is below the threshold. anth specifies the noise gate threshold level relative to the final adc output signal level. the noise gate can be used in conjunction with agc or on its own. when agc is enabled, the noise gate reduces the output level only when the agc has set the gain to the maximum setting. choose a threshold between -28db and -48db when used in conjunction with the agc. when the agc is enabled, the effective noise gate thresholds are increased by 20db due to the microphone pga being set to maximum gain by the agc. adc noise gate threshold levels value threshold (db) 0x0 to 0x5 disabled 0x6 -64 0x7 -60 0x8 -56 0x9 -52 0xa -48 0xb -44 0xc -40 0xd -36 0xe -32 anth 0xf -28 adc interface register bit description (continued) digital filters the MAX9856 digital audio interface includes digital first-order highpass filters (table 8) for both the dac input and the adc output. the corner frequency for each filter is selectable from 5hz to 4khz. the dac fil- ter (dachp) can be used to reduce the low-frequency energy sent to speakers incapable of reproducing low frequencies. the adc filter (adchp) can reduce low- frequency noise such as wind noise from being con- verted. the cutoff frequency depends on sample rate and is shown in table 9. reg b7 b6 b5 b4 b3 b2 b1 b0 0x0b 0 adchp 0 dachp table 8. digital highpass filters MAX9856 automatic gain control the MAX9856 agc continuously adjusts the analog microphone pgas to maintain constant signal level. when the agc is enabled, manual control of the input pga is not possible. the pga includes zero-cross detection, which prevents gain changes, from being audible. the agc process consists of three main sections. when the agc threshold is exceeded, the gain is reduced exponentially with a time constant referred to as the attack time. once the large signal has passed, the agc waits the specified hold time before reducing the gain. the time required to reduce the gain from maximum attenuation to minimum attenuation is known as the release time. the agc circuitry only operates on the pga in the micro- phone path, but the digital level detector is based on the mixed signal. only use the agc when input signals from the linein and auxin are excluded or attenuated. table 10 lists the agc registers and shows the agc register bit description. low-power audio codec with directdrive headphone amplifiers 28 ______________________________________________________________________________________ adchp/dachp lrclk (khz) 000 001 (hz) 010 (hz) 011 (hz) 100 (hz) 101 (hz) 110 (hz) 111 (hz) 8 off 5 10 20 41 82 170 364 11.025 off 7 14 28 56 114 235 501 12 off 8 15 30 61 124 255 545 16 off 10 20 40 81 165 340 727 22.05 off 14 28 55 112 227 469 1002 24 off 15 30 60 122 247 511 1091 32 off 20 40 80 162 330 681 1455 44.1 off 28 55 111 224 455 938 2005 48 off 30 60 121 244 495 1021 2182 64 off 40 80 161 325 660 1362 2909 88 off 55 111 222 448 909 1877 4009 96 off 60 120 241 487 990 2043 4364 table 9. digital highpass filter cutoff frequencies reg b7 b6 b5 b4 b3 b2 b1 b0 0x0c 0 agcrls agcatk agchld 0x0d 0 0 0 agcsrc agcsth table 10. automatic gain control registers bits function agcrls agc release time. the release time is the time it takes for the gain to return to its normal level after the input signal has fallen below the threshold and the hold time has passed: 000?8ms 001?56ms 010?12ms (recommended) 011?25ms 100?.25s 101?.5s 110?s 111?0s agc register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 29 bits function agcatk agc attack time. the attack time is the time it takes to reduce the gain after the input signal has exceeded the threshold level. the gain attenuation during attack is exponential and the attack time is defined as one-time constant rather than the time it takes to reach the final gain: 00?ms 01?2ms 10?0ms (recommended) 11?00ms agchld agc hold time. hold time is the delay before the agc release begins. the hold time counter starts whenever the signal drops below the agc threshold and is reset by any signal that exceeds the threshold: 00?gc disabled 01?0ms 10?00ms (recommended) 11?00ms agcsrc agc and noise gate signal source. selects the audio signal that the agc and noise gate circuitry monitors: 0?eft-channel adc output 1?eft-channel + right channel adc output (results in 3db lower threshold for coherent signals) agc threshold. sets the signal level at which the agc begins gain reduction. the signal is monitored after the adc output gain has been applied. agc threshold levels agcsth level (db) 0000 -3 0001 -4 0010 -5 0011 -6 0100 -7 0101 -8 0110 -9 0111 -10 1000 -11 1001 -12 1010 -13 1011 -14 1100 -15 1101 -16 1110 -17 agcsth 1111 -18 agc register bit description (continued) MAX9856 analog mixers the MAX9856 has two main analog mixers. the first feeds signals into the headphone and line output amplifiers while the second supplies the adc input. each mixer is configurable independently for left and right channels. see table 11 for audio mixer control registers and register bit description. low-power audio codec with directdrive headphone amplifiers 30 ______________________________________________________________________________________ reg b7 b6 b5 b4 b3 b2 b1 b0 0x0e 0 0 0 mxinl 0x0f 0 0 0 mxinr 0x10 mxoutl mxoutr table 11. audio mixer control registers bits function adc input mixer description mxinl or mxinr selected input source 00000 no input source selected 1xxxx auxout selected x1xxx linein1 selected xx1xx linein2 selected xxx1x micl selected mxinl/mxinr xxxx1 micr selected audio output mixer description mxoutl or mxoutr selected input source 0000 no input source selected 1xxx mic l/r pga output selected x1xx linein1 selected xx1x linein2 selected mxoutl/mxoutr xxx1 dac output selected audio mixer register bit description analog inputs the MAX9856 features various analog inputs. all inputs have independent gain control for maximum flexibility. auxin is a mono auxiliary input that can be used for mixing alarms, beeps, and sound effects into the head- phone outputs or adc input. the auxin signal has a dedicated pga for gain adjustment and can be mixed into the headphone output signal directly, bypassing the output mixer and volume control. auxin can also serve as an input for making precise measurements in the system. in this mode, the pga is bypassed, increasing the impedance of the input, and is directly connected to the adc. three microphone inputs are available. two are pseudo- differential inputs with a shared ground connected to the inverting input of the microphone preamplifier. the third is a fully differential input. stereo microphones that share a common return path can take advantage of the pseudo-differential configuration by connecting the com- mon return to the micgnd, canceling common-mode noise. figure 3 shows the typical application circuit for both single-ended and differential microphones. the microphone preamplifier and pga provide a wide range of gain options. the microphone inputs can also be used as additional line inputs when the gain is set to 0db. a single low-noise bias voltage output is available (micbias) to bias microphones from a clean supply with an external bias resistor. there are two selectable microphone bias voltages that can be selected depending on the power-supply voltage. table 12 lists the audio input control registers and bit description. MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 31 reg b7 b6 b5 b4 b3 b2 b1 b0 0x11 pgads 0x12 0 0 0 pgaaux 0x13 0 0 0 pgal1 0x14 0 0 0 pgal2 0x15 0 paenl pgaml 0x16 0 paenr pgamr 0x17 0 0 0 0 mmic mbsel 0 lmicdif table 12. audio input control registers micl/micr micbias jacksns (a) 2.2k micgnd inlp micbias jacksns (b) 2.2k inln 2.2k figure 3. typical microphone connections: (a) pseudo-differential, (b) differential MAX9856 low-power audio codec with directdrive headphone amplifiers 32 ______________________________________________________________________________________ bits function programmable gain adjust for digital audio input digital audio input pga settings setting gain (db) setting gain (db) 0x00 0 0x93 -15 0x07 -0.5 0x96 -15.5 0x0e -1 0x99 -16 0x15 -1.5 0x9c -16.5 0x1c -2 0x9f -17 0x22 -2.5 0xa2 -17.5 0x29 -3 0xa5 -18 0x2f -3.5 0xa7 -18.5 0x35 -4 0xaa -19 0x3a -4.5 0xac -19.5 0x40 -5 0xae -20 0x45 -5.5 0xb3 -21 0x4a -6 0xb7 -22 0x50 -6.5 0xbb -23 0x55 -7 0xbf -24 0x59 -7.5 0xc2 -25 0x5e -8 0xc6 -26 0x63 -8.5 0xc9 -27 0x67 -9 0xcc -28 0x6b -9.5 0xcf -29 0x70 -10 0xd2 -30 0x74 -10.5 0xd4 -31 0x78 -11 0xd6 -32 0x7c -11.5 0xd9 -33 0x7f -12 0xdb -34 0x83 -12.5 0xdd -35 0x86 -13 0xdf -36 0x8a -13.5 0xe1 -37 0x8d -14 0xe2 -38 0x90 -14.5 0xe4 -39 pgads 0xe5 -40 audio input register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 33 bits function programmable gain adjust for line inputs line input pga settings setting gain (db) setting gain (db) 0x00 +30 0x10 -2 0x01 +28 0x11 -4 0x02 +26 0x12 -6 0x03 +24 0x13 -8 0x04 +22 0x14 -10 0x05 +20 0x15 -12 0x06 +18 0x16 -14 0x07 +16 0x17 -16 0x08 +14 0x18 -18 0x09 +12 0x19 -20 0x0a +10 0x1a -22 0x0b +8 0x1b -24 0x0c +6 0x1c -26 0x0d +4 0x1d -28 0x0e +2 0x1e -30 pgaaux/ pgal1/ pgal2 0x0f +0 0x1f -32 audio input register bit description (continued) MAX9856 low-power audio codec with directdrive headphone amplifiers 34 ______________________________________________________________________________________ bits function left/right programmable gain adjustment for microphone inputs. when agc is enabled, the pgaml and pgamr bits cannot be manually programmed. the pgaml register can be monitored to determine the gain set by the agc. microphone pga settings setting gain (db) setting gain (db) 0x00 +20 0x0b +9 0x01 +19 0x0c +8 0x02 +18 0x0d +7 0x03 +17 0x0e +6 0x04 +16 0x0f +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1f 0 pgaml/ pgamr 0x0a +10 paenl/paenr left/right microphone preamplifier enable. enables the microphone circuitry and sets the preamplifier gain: 00?icrophones disabled 01?db 10?0db 11?0db mmic microphone mute enable mbsel micbias voltage select: 0?icbias = 1.5v 1?icbias = 2.4v (use only when avdd 2.7v) lmicdif left microphone input select: 0?icl/micgnd (pseudo-differential input) 1?nlp/inln (differential input) audio input register bit description (continued) MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 35 audio outputs the MAX9856 features stereo headphone amplifiers and line output amplifiers with directdrive technology. directdrive eliminates the need for bulky and expensive dc-blocking capacitors on the outputs. the directdrive biasing scheme is illustrated in figure 4. the head- phone outputs have separate left/right volume controls while the line outputs produce a fixed level signal. the audio outputs feature ground sensing, which is intended to reduce the effect of ground noise. in many systems, the ground return for line outputs and head- phone jacks is used by other functions such as video signals and microphone signals. the sharing of gr ound can result in interference that is audible. the MAX9856? ground sense provides a path for the interfering signal to be input and combined with the output audio signal to reduce the audibility of the interference. connect hgnd- sns directly to the ground terminal of the headphone jack to enable ground sense on the headphones (figure 5). similarly connect lgndsns directly to the ground termi- nal of a line output jack to enable ground sense on the line outputs. if ground sense is not required, connect hgndsns and lgndsns to agnd. table 13 lists the audio output control registers and bit description. avdd avdd/2 gnd conventional amplifier biasing scheme directdrive amplifier biasing scheme avdd agnd svss figure 4. traditional amplifier output vs. MAX9856 directdrive output gnd hpr hpl hpl hpr hgndsns figure 5. ground sense connection MAX9856 low-power audio codec with directdrive headphone amplifiers 36 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 0x18 0 hpmute hpvoll 0x19 0 0 hpvolr 0x1a 0 vsen auxdc auxmix 0 0 hpmode table 13. audio output control registers bits function hpmute headphone mute enable headphone volume control headphone volume-control settings setting gain (db) setting gain (db) setting gain (db) 0x00 +5.5 0x0e -8 0x1c -36 0x01 +5 0x0f -10 0x1d -38 0x02 +4.5 0x10 -12 0x1e -40 0x03 +4 0x11 -14 0x1f -42 0x04 +3.5 0x12 -16 0x20 -46 0x05 +3 0x13 -18 0x21 -50 0x06 +2.5 0x14 -20 0x22 -54 0x07 +2 0x15 -22 0x23 -58 0x08 +1 0x16 -24 0x24 -62 0x09 0 0x17 -26 0x25 -66 0x0a -1 0x18 -28 0x26 -70 0x0b -2 0x19 -30 0x27 -74 0x0c -4 0x1a -32 0x28 to 0x3f mute hpvoll/hpvolr 0x0d -6 0x1b -34 vsen volume slewing enable. enables volume slewing so that when a volume change is made, the actual volume control steps though all intermediate settings to give a smooth sounding change. auxdc auxiliary input dc measurement mode: 0?uxin connected to the input pga for audio signals. 1?uxin directly connected to the adc input for dc measurements. set mxinl to 10000 for proper operation. auxmix auxiliary input connected to headphone amplifiers: 0?uxin not connected to the headphone amplifiers. 1?uxin mixed directly into the headphone amplifiers bypassing the output mixer. hpmode headphone output mode: 00?hutdown 01?tandard mono mode (hpl = mono, hpr = shutdown) 10?ual mono mode (hpl = hpr = mono) 11?tereo mode audio output register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 37 headset detection the MAX9856 features headset detection that can detect the insertion and removal of a jack as well as the load type. when a jack is detected, an interrupt on irq can be triggered to alert the microcontroller of the event. figure 6 shows the typical configuration for jack detection and table 14 shows the headset detect control register and bit description. sleep-mode jack detection when the MAX9856 is in shutdown and the power sup- ply is available, sleep mode jack detection can be enabled to detect jack insertion. sleep mode applies a 2? pullup current to jacksns and hpl, which forces the voltage on jacksns and hpl to avdd when no load is applied. when a jack is inserted, either jack- sns, hpl, or both are loaded sufficiently to reduce the output voltage to nearly 0v and clear the jksns or lsns bits, respectively. the change in the lsns and jksns bits sets jdet and triggers an interrupt on irq if ijdet is set. the interrupt signals the microcontroller that a jack has been inserted, allowing the microcon- troller to respond as desired. powered-on jack detection when the MAX9856 is in normal operation and the microphone interface is enabled, jack insertion and removal can be detected through the jacksns pin. as shown in figure 6, v mic is pulled up by micbias. when a microphone is connected, v mic is assumed to be between 0v and 95% of v micbias . if the jack is removed, v mic increases to v micbias . this event caus- es jkmic to be set, alerting the system that the head- set has been removed. alternatively, if the jack is inserted, v mic decreases to below 95% of v micbias and jkmic is cleared, alerting that a jack has been inserted. the jkmic bit can be configured to create a hardware interrupt that alerts the microcontroller of jack removal and insertion events. impedance detection the MAX9856 is able to detect the type of load con- nected by applying a 2ma pullup current to hpl, hpr, and jacksns. to minimize click-and-pop the current is ramped up and down over a 24ms period. the 2ma current can be individually applied to hpl, hpr, and jacksns by appropriately configuring the en bits. when the 2ma current has finished ramping, hsdetl, hsdetr, and jsdet are updated to reflect the mea- sured impedance. en must be cleared and reset to re- measure the impedance. figure 7 and table 15 illustrate the impedance detection process. figure 6. example jack configuration for jack detection i 2ma set en bits to 1 set en bits to 0 t o t f t o + 24ms t f - 24ms impedance detection complete read hsdetl, hsdetr, jsdet figure 7. current on hpl, hpr, or jacksns during impedance detection gnd mic hpr hpl hpl micbias jacksns hpr micl MAX9856 low-power audio codec with directdrive headphone amplifiers 38 ______________________________________________________________________________________ time event t 0 disable the headphone amplifiers. set en = 111 to enable the detection circuitry. t 0 + 24ms irq set high. indicates that the detection current has reached its final value and the impedance has been stored in hsdetl, hsdetr, and jsdet. t f -24ms once the impedance of hpl, hpr, and jacksns has been read, set en = 000 to shut down the detection circuitry. t f irq set high. indicates that the detection circuitry is completely shut down and the headphone amplifiers can be reenabled. table 15. impedance detection routine reg b7 b6 b5 b4 b3 b2 b1 b0 0x1b 0 0 0 0 jdeten en table 14. headset detect control register bit function jdeten jack detection enable sleep mode?nables pullups on hpl and jacksns to detect jack insertion. lsns and jksns are not valid unless jdeten = 1 and shdn = 0. normal mode?nables the comparator circuitry on jacksns to detect voltage changes. jkmic is not valid unless jdeten = 1 and the microphone circuitry is enabled. impedance detection enable. enables the impedance detection circuitry for hpl, hpr, and jacksns. when en = 000 hsdetl, hsdetr, and jsdet are set to 11. see table 2, status register bit description for details on reading the load impedance. impedance detection enable description en description 000 disabled 1xx jacksns pin impedance sense enabled x1x hpr pin impedance sense enabled en xx1 hpl pin impedance sense enabled headset detection register bit description MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 39 power management and control the MAX9856 has comprehensive power management that allows unused features to be disabled, thereby saving power. table 16 shows the power/management register and a register bit description. register b7 b6 b5 b4 b3 b2 b1 b0 0x1c shdn 0 digen louten dalen daren adlen adren table 16. power-management register bits function shdn shutdown. overrides all settings and forces the entire device into a shutdown state. digen digital core enable. set high to use either the dac or adc. louten line output enable. dalen left dac enable. daren right dac enable. adlen left adc enable. adren right adc enable. power-management register bit description smbus is a trademark of intel corp. scl sda start condition stop condition repeated start condition start condition t hd, sta t hd, sta t hd, sta t sp t buf t su, sto t low t su, dat t hd, dat t high t r t f figure 8. 2-wire interface timing diagram i 2 c serial interface the MAX9856 features an i 2 c/smbus -compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facil- itate communication between the MAX9856 and the master at clock rates up to 400khz. figure 8 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the MAX9856 by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) con- dition and a stop (p) condition. each word transmitted to the MAX9856 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX9856 transmits the proper slave address followed by a series of nine scl pulses. the MAX9856 transmits data on sda in sync with the master-generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowl- edge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typi- cally greater than 500 , is required on sda. scl oper- ates only as an input. a pullup resistor, typically greater than 500 , is required on scl if there are mul- tiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX9856 from high voltage spikes on the bus lines, and minimize crosstalk and under- shoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con- dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 9). a start condition from the master signals the beginning of a transmission to the MAX9856. the master terminates transmission, and frees the bus, by issuing a stop con- dition. the bus remains active if a repeated start condition is generated instead of a stop condition. early stop conditions the MAX9856 recognizes a stop condition at any point during data transmission except if the stop con- dition occurs in the same high pulse as a start condi- tion. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the MAX9856 is preprogrammed with a slave address of 0x20 or 0010000. the address is defined as the 7 most significant bits (msbs) followed by the read/write bit. setting the read/write bit to 1 configures the MAX9856 for read mode. setting the read/write bit to 0 configures the MAX9856 for write mode. the address is the first byte of information sent to the MAX9856 after the start condition. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX9856 uses to handshake receipt of each byte of data when in write mode (see figure 10). the MAX9856 pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuc- cessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master retries communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the MAX9856, followed by a stop condition. MAX9856 low-power audio codec with directdrive headphone amplifiers 40 ______________________________________________________________________________________ scl sda ssrp figure 9. start, stop, and repeated start conditions 1 scl start condition sda 289 clock pulse for acknowledgment acknowledge not acknowledge figure 10. acknowledge MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 41 a 0 slave address register address data byte acknowledge from MAX9856 r/w 1 byte autoincrement internal register address pointer acknowledge from MAX9856 acknowledge from MAX9856 b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 11. writing 1 byte of data to the MAX9856 1 byte autoincrement internal register address pointer acknowledge from MAX9856 acknowledge from MAX9856 b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from MAX9856 r/w s a 1 byte acknowledge from MAX9856 b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 12. writing n bytes of data to the MAX9856 write data format a write to the MAX9856 includes transmission of a start condition, the slave address with the r/ w bit set to 0, 1 byte of data to configure the internal register address pointer, 1 or more bytes of data, and a stop condition. figure 11 illustrates the proper frame format for writing 1 byte of data to the MAX9856. figure 12 illustrates the frame format for writing n-bytes of data to the MAX9856. the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the MAX9856. the MAX9856 acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master config- ures the MAX9856? internal register address pointer. the pointer tells the MAX9856 where to write the next byte of data. an acknowledge pulse is sent by the MAX9856 upon receipt of the address pointer data. the third byte sent to the MAX9856 contains the data that is written to the chosen register. an acknowledge pulse from the MAX9856 signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential registers within one continuous frame. figure 12 illustrates how to write to multiple registers with one frame. the master signals the end of transmission by issuing a stop condition. register addresses greater than 0x1c are reserved. do not write to these addresses. read data format send the slave address with the r/ w bit set to 1 to initi- ate a read operation. the MAX9856 acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start command followed by a read command resets the address pointer to reg- ister 0x00. the first byte transmitted from the MAX9856 is the contents of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincrements after each read data byte. this auto- increment feature allows all registers to be read sequentially within one continuous frame. a stop con- dition can be issued after any number of read data bytes. if a stop condition is issued, followed by anoth- er read operation, the first data byte to be read is from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the MAX9856? slave address with the r/ w bit set to 0 followed by the register address. a repeated start condition is then sent followed by the slave address with the r/ w bit set to 1. the MAX9856 then transmits the contents of the specified register. the address pointer autoincrements after transmitting the first byte. the master acknowl- edges receipt of each read byte during the acknowl- edge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condition. figure 13 illustrates the frame format for reading 1 byte from the MAX9856. figure 14 illustrates the frame format for reading multi- ple bytes from the MAX9856. MAX9856 low-power audio codec with directdrive headphone amplifiers 42 ______________________________________________________________________________________ acknowledge from MAX9856 1 byte autoincrement internal register address pointer acknowledge from MAX9856 not acknowledge from master a a p a 0 acknowledge from MAX9856 sa r/w r/w repeated start sr 1 slave address register address slave address data byte figure 13. reading 1 indexed byte of data from the MAX9856 acknowledge from MAX9856 1 byte autoincrement internal register address pointer acknowledge from MAX9856 a a a 0 acknowledge from MAX9856 r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 14. reading n bytes of indexed data from the MAX9856 pcb layout and bypassing proper layout and grounding are essential for optimum performance. use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. proper grounding improves audio performance, minimizes crosstalk between chan- nels, and prevents any switching noise from coupling into the audio signal. connect agnd, dgnd, cpgnd, and pgnd together at a single point on the pcb using the star grounding technique. route dgnd, cpgnd, and all traces that carry switching transients or digital signals separately from agnd and the analog audio signal paths. ground all components associated with the charge pump to cpgnd (cpvss bypassing and cpvdd bypassing). connect all digital i/o termination to dgnd including dvdd and dvdds2 bypassing. bypass ref and micbias to agnd. connect pvss and svss together at the device and place the charge-pump hold capacitor (c2) as close to svss as possible and ground to cpgnd. bypass cpvdd with a 1? capacitor to cpgnd and place the bypass capacitor as close to the device as possible. the MAX9856 thin qfn package features an exposed thermal pad on its underside. this pad lowers the pack- age? thermal resistance by providing a direct heat conduction path from the die to the pcb. connect the exposed thermal pad to agnd. an evaluation kit (ev kit) is available to provide an example layout for the MAX9856. the ev kit allows quick setup of the MAX9856 and includes easy-to-use software allowing all internal registers to be controlled. MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 43 chip information process: bicmos pin configuration MAX9856 thin qfn (6mm x 6mm) top view 35 36 34 33 12 11 13 linein2 preg nreg mbias ref 14 linein1 sdin bclk lrclk_d dvdds2 lrclk_a mclk irq sda 12 inlp 4567 27 28 29 30 26 24 23 22 micl micgnd cpgnd c1n pvss svss auxin sdout 3 25 37 micr hpr 38 39 *ep + * ep = exposed pad. 40 micbias agnd jacksns hpl avdd hgndsns inln 32 15 c1p dgnd 31 16 17 18 19 20 cpvdd lgndsns loutl loutr scl 8910 21 dvdd MAX9856 low-power audio codec with directdrive headphone amplifiers 44 ______________________________________________________________________________________ package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 40 tqfn t4066+5 21-0141 90-0055 MAX9856 low-power audio codec with directdrive headphone amplifiers ______________________________________________________________________________________ 45 package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. MAX9856 low-power audio codec with directdrive headphone amplifiers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 46 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/08 initial release 1 9/08 added new note 1 to ec table 2?0 2 12/11 added automotive qualified part information to data sheet 1, 2 |
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