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rev. 1.1 / may. 2012 1 2gb ddr3 sdr a m 2gb ddr3 sdram lead-free&halogen-free (rohs compliant) h5tq2g83dfr-xxc h5tq2g63dfr-xxc h5tq2g83dfr-xxi h5tq2g63dfr-xxi h5tq2g83dfr-xxj H5TQ2G63DFR-XXJ h5tq2g83dfr-xxl h5tq2g63dfr-xxl * sk hynix reserves the right to change products or specifications without notice. http://
rev. 1.1 / may. 2012 2 revision history revision no. history draft date remark 0.01 p r elimina r y v e rsion r e leas e j u l y . 2011 p r e l imina r y 0.02 add temper atu r e inf o r mation in f ea t ur e aug. 2011 p r e l imina r y 0.03 upda te oper ation f r equ e ncy o ct. 201 1 p re limina ry 0.04 u pda te idd 160 0,1 866,2133 no v . 2 011 p r e l imina r y 0.05 u pdate idd data no v . 2 011 p r e l imina r y 0.06 u pdate idd data (x8) dec. 201 1 p re limina ry 0.07 upd a te p a k a ge dimen sion (x16 ) - corr ected p a kage dimension (p ag e 34 , 78 balls to 96ba l ls) dec. 201 1 p re limina ry 0.08 u pdate idd data f e b . 2012 p a ge 24 , a l l idd specs ar e completed 0.09 of ficial v e rsion r e le ase m ar .20 1 2 d eleted ?p re limina ry? 1.0 o f f i cial v e rsion r e le ase & add l/j p a rt apr . 2012 add l/j p a rt supp ort 1 . 1 d el et e c o mm e n t s r e g a rd in g i d d6 t c & new r e v i se d logo (hynix to sk hy nix) ma y . 2012 p a ge 12/17/24
rev. 1.1 / may. 2012 3 description the h5tq2 g 83 dfr - xxc, h5tq2g63dfr - x xc,h5tq2g83dfr - x xi, h5tq2g63d fr - x xi, h5tq2g83dfr - xxl,h5tq2g63dfr - x xl,h5tq2g83dfr - x xj ,h5tq2g63dfr - x xj ar e a 2 , 14 7 , 4 83,648-bit cmos double data r a te iii (ddr 3) s y nchr onous dr am, ideal l y s u ited f o r the main memory applications which r e quir es l a r g e memory densit y and high bandwidth. sk hynix 2gb ddr 3 sdrams off e r f u l l y s y nchro n ous oper atio ns ref - er enced to both rising and f a lling e dges of the clock. while all addr esse s and contr o l inputs ar e latched on the rising edges of the ck (f alling edges of the c k ), data, data str o bes and w r ite data masks inputs ar e sampled on both risi ng and f a ll ing ed ges of it. the data paths ar e intern ally pipelined and 8-bit pref etched to ac hiev e v e ry high bandwidt h. device feat ures and ordering in formation featu r es * this product in compliance with the rohs directive. ? vd d=vdd q=1.5 v +/- 0.075v ? fully differential clock inputs (ck, ck ) o p er ati o n ? differential data strobe (dqs, dqs ) ? on chip dll align dq, dqs and dqs tr ansiti on wi th ck tr ans i tion ? dm mas k s write data -in at the both rising a n d f a lling edg e s of the data str o be ? all ad dr esses and contr o l inputs ex ce pt data , data str o bes and data m a sks l a tched on the rising e dges of the clock ? pr ogr a mma ble ca s la tency 5, 6, 7 , 8, 9, 10, 11, 12 , 13 and 14 supported ? pr ogr a mmable addi tive l a tency 0, cl -1, and cl -2 supported ? pr ogr a mma ble cas w r ite laten c y (cwl) = 5, 6, 7 , 8 ? pr ogr a mma ble burs t le ngth 4/8 with both n i bb le s e qu e n ti al and i n te rle a v e m o d e ? bl switch on th e fly ? 8b ank s ? a v er age r e f r esh cy cle ( t cas e 0 o c~ 9 5 o c) - 7 . 8 s a t 0 o c ~ 8 5 o c - 3.9 s at 85 o c ~ 95 o c commer c ial t e mpe r a t ur e( 0 o c ~ 85 o c) i n dustrial t emp er a t ur e( -40 o c ~ 95 o c) ? jedec sta n da rd 78ba l l fbga(x8 ) , 96b all fbga(x16) ? d r iv er s t re ngth selected b y emrs ? dy n a m i c on di e t e rm in a t ion s u p p o rte d ? as ynchr o nous reset pin s u pported ? zq ca libr ation supported ? tdqs ( t ermin a ti on data s t robe) su ppo r t e d (x 8 o n ly) ? w r ite lev e lization supported ? 8 bit pr e-f e tch
rev. 1.1 / may. 2012 4 ordering information * xx means speed bin gr ade operating frequency * xx means speed bin grade part no. configuration power consumption temperature pa cka g e h5tq2g83d fr -*xxc 256m x 8 norm al consum pti o n comme rcial 78 b a ll fb ga h5tq2g83d fr -*xxi i n dustr i a l h5tq2g83 dfr - * x xl low p o wer co nsumpti o n (idd6 on ly) comme rcial h5tq2g83 dfr - * x xj i n dustr i a l h5tq2g63d fr -*xxc 128m x 16 norm al consum pti o n comme rcial 96 b a ll fb ga h5tq2g63d fr -*xxi i n dustr i a l h5tq2g63 dfr - * x xl low p o wer co nsumpti o n (idd6 on ly) comme rcial h5tq2g63 dfr - * x xj i n dustr i a l speed grade (marking) frequency [mbps] remark (cl-trcd-trp) cl5 cl6 cl7 cl8 cl9 cl10 cl11 cl12 cl13 cl14 -g7 6 6 7 80 0 106 6 1066 ddr3 - 10 66 7-7-7 -h9 6 6 7 80 0 106 6 1066 13 33 1 333 ddr3 - 13 33 9-9-9 -pb 66 7 80 0 106 6 1066 13 33 1 333 1600 ddr3 - 16 00 11 -11 - 1 1 -rd 80 0 106 6 1066 13 33 1 333 1600 18 66 ddr3 - 18 66 13 -13 - 1 3 - t e 8 0 0 106 6 1066 13 33 1 333 1600 18 66 21 33 ddr3 - 21 33 14 -14 - 1 4
rev. 1.1 / may. 2012 5 x8 package ball out (top view): 78ball fbga package 1 2 3 4 5 6 7 8 9 a vss vdd nc nu/tdqs vss vdd a b vss vssq dq0 dm/tdqs vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq dq6 dqs vdd vss vssq d e vrefdq vddq dq4 dq7 dq5 vddq e f nc vss ras ck vss nc f g odt vdd cas ck vdd cke g h nc cs we a10/ap zq nc h j vss ba0 ba2 nc vrefca vss j k vdd a3 a0 a12/bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 12 a b c d e f g h j k l m n p o pula ted ba ll ball not populated 3 789 (top view: see the balls through the package)
rev. 1.1 / may. 2012 6 x16 package ball out (top vi ew): 96ball fbga package 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss a b vssq vdd vss dqsu dqu6 vssq b c vddq dqu3 dqu1 dqsu dqu2 vddq c d vssq vddq dmu dqu0 vssq vdd d e vss vssq dql0 dml vssq vddq e f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl vdd vss vssq g h vrefdq vddq dql4 dql7 dql5 vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 nc vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 nc a8 vss t 1 2 3 4 5 6 7 8 9 1 a b c d e f g h j k l m n p o pulated ball ball not populated 2 789 (top view: see the balls through the package) 3 p r t
rev. 1.1 / may. 2012 7 pin functional description symbol type function ck, ck input clock: ck and ck ar e dif f er entia l clock inputs. all a ddr ess a n d contr o l input s i g n als a r e sampled on the crossing of the positive edge of ck and negative edge of ck . cke, (ck e 0 ) , (cke1) in pu t clock enabl e : cke high activ a te s, and cke lo w deactiv a te s, internal clock signals and dev i ce input buf f e r s and output driv er s. t a king cke low pr ov id es pr e c har g e p o wer - down an d se lf - r ef r e sh op er a t io n (a ll ban k s i d l e ) , or activ e p o we r - down (r ow activ e in a n y ba nk). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke, are disabled during power- down. input buffers, excluding cke, are disabled during self-refresh. cs , (cs 0), (cs 1), (cs 2), (cs 3) in pu t chip select: all commands are masked when cs is r egister ed high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. od t , (od t 0), (od t 1) in pu t on die t e rminatio n: od t (r egister e d h i gh) enab l e s terminati o n re sistanc e internal to the dd r3 s d ra m. when en abled, od t is only app l ied to e a ch dq , d q s , d q s and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration, odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu , a n d d m l s i gnal. the od t pin will be ignor e d if mr1 is pr ogr a mme d to disa ble od t . ra s . cas . we input command inputs: ras , cas and we (along with cs ) de fine the command be ing enter e d. dm , (d mu ), (d ml ) in pu t input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that inpu t data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 in pu t bank addr ess i n p u ts: ba0 - ba2 de fine to which bank an activ e, r ead, w r ite or pr echa r g e command is being app l ied. bank a ddr ess a l s o d e termine s if the mod e r e gister or extended mode r e g i ste r is to be ac cessed during a mrs cy cle. a0 - a1 5 in pu t addr es s i n puts: p r o v ide the r o w addr es s f o r activ e comma nds a n d the column addr es s f o r r e ad/w ri te c o mmands to s e lect one loc a ti on out of the memory arr a y in the r e s p ective ba nk. (a10/ap and a12/bc h a v e add i tion al f u n c tions, se e below). the a ddr ess inputs also provide the op-code during mode register set commands. a10 / ap in pu t a u to-pr e char ge : a10 is s a mpled during r e ad/w rite commands to deter m i n e whe t her a u topr echa r g e should be pe rf orm ed to the a cce s s ed bank after the r e ad/ w ri te oper ation. (high: a u topr echa rg e; l o w : no a u topr ec har g e).a 10 is sa mpled during a pr echar g e command to determ ine whether the pr echar g e a pplie s to on e ba nk (a10 low) or all ba nks (a1 0 high). if only one bank is to be pr echar g ed, the bank is s e le cted b y ba nk ad dr esses . a1 2 / bc input bur s t cho p : a12 / bc is samp le d during r e ad a n d w r ite com m and s to determine if burs t chop (on-the-fly) will be perf ormed . (high, no burst chop ; low : burst choppe d). see comm and truth table f o r detai l s.
rev. 1.1 / may. 2012 8 reset in pu t active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset mu st be high d u ring n o r mal oper ation . rese t is a cmos r a il-to-r a il sign al with d c high an d low a t 80% an d 20% of v dd , i . e. 1.20v f o r dc h i gh an d 0.30v f o r dc low . dq in pu t / output data i n put/ output: b i -dir ectional da ta bus. dqu , dql , dqs , dqs , dqsu, dqsu , dqsl, dqsl in pu t / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. the data strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , r e spectiv e l y , to pro v ide di f f e re n tial pair s i gnali n g to the sy stem during r e a d s and writ e s. ddr3 sd ram s u pports d i f f er e n tial data str o b e only and does no t su pport singl e - e nded. tdqs , tdqs output t e rmina t ion data str o be: t d qs /tdqs is applicable for x8 dr ams only. when enabled via mode register a11 = 1 in mr1, the dram wi ll enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs is no t us ed. x4/x1 6 dra m s m u st disa ble the tdqs f u n c tion via mode r e g i s t e r a11 = 0 in mr1. nc no conne c t : no int e rnal e l ectr ical connection is pr esent. nu no use v ddq sup ply dq p o wer supp ly : 1.5 v +/- 0.075 v v ss q su ppl y dq groun d v dd su ppl y p o we r su pply: 1 . 5 v +/- 0.0 75 v v ss su ppl y gr o und v re f d q su ppl y r e fe re n c e v o l t a g e fo r d q v re f c a su ppl y r e fe re n c e v o l t a g e fo r c a zq su ppl y r e f e r e nce pin f o r zq ca libr ation note: i n p u t only pins (ba0 -ba2, a0- a 15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function
rev. 1.1 / may. 2012 9 row and column address table 2gb no te1 : p a g e siz e is th e n u mber of by tes of da ta de liv e re d fr om the arr a y t o the internal sense ampl ifiers wh en a n active com mand is r egister ed. p a ge siz e is per ban k , calculated as f o llows: page size = 2 colb i t s * o r g ? 8 where colbits = the numb er of column address bits, or g = the number of i/o (dq) b i ts configuration 256mb x 8 12 8mb x 16 # of banks 8 8 bank a ddr ess b a0 - ba2 ba0 - ba2 a u to pr ech a r g e a10 /ap a10/ap bl s w itch on th e f l y a 1 2 /bc a12/bc r o w a ddr ess a 0 - a1 4 a0 - a13 column addr ess a 0 - a9 a0 - a9 pa g e s i z e 1 1 kb 2 kb
rev. 1.1 / may. 2012 10 absolute maximum ratings absolute maximum dc ratings dram component operat ing temperature range abs o lute maximu m dc ra tings symbol parameter rating units no tes vd d v o ltage on v dd pin relative to v s s - 0.4 v ~ 1.975 v v 1,3 vd dq v o ltage on v ddq p i n relative to v s s - 0.4 v ~ 1.975 v v 1,3 v in , v ou t v o ltage on an y pin relative to v ss - 0.4 v ~ 1.975 v v 1 t stg stora g e tempera t ure -55 to +100 o c1 , 2 no tes: 1. stre sses gr eater than those listed under ? a b s olute ma ximum r a tings? m a y ca use perma n ent dama ge to the dev i ce . this is a str ess r a ting only and f u nctional op er a t io n of the d e vice a t these or an y o t her con d itio ns a b o v e those i n dicated in the oper ational se cti o ns of this spe c i f ication is no t implied. expo sur e to abso lute maximum r a t - ing condi t io ns f o r extended pe ri od s may affe c t re l i a b i l i ty . 2. s t or age t e mper atu r e is the ca se su rf ace temper atu r e on the cente r /top s i de of the dram. f o r the me asure ment conditions , plea se r e f e r to jesd 51-2 sta n da rd . 3. vdd and vd dq mu st be within 3 00mv of ea ch other a t all times ; and vref mu st n o t be gr eate r than 0.6xvdd q ,whe n vdd an d vd dq a r e less th an 5 00mv ; vref ma y be equa l to or less than 300m v . temperature range symbol parameter rating units no tes t oper nor m al o p er a t in g te m p er a t u r e r a ng e 0 to 85 o c 1,2 industr i a l tempe r atur e range -40 to 95 o c1 , 3 no tes: 1. oper ating t e mp er a t ur e t o per is the ca se sur f ace tempe r a t ur e on the ce nter / top side of th e dram . f o r meas ur e- men t co nditio ns, plea se r e f e r to th e jed e c do cumen t jes d 5 1 -2 . 2. the norma l t e mper atur e r a nge spe c ifies the tem p er atur es wher e a l l dram specificatio ns will be supported. dur - ing ope r ation, the dram case temper atu r e mus t be ma in tained between 0 - 85 o c un der a l l oper a t in g c o ndi t io ns. 3. some applica t ions r equir e oper ation of the dr am in the extend ed t e mpe r a t ur e r a nge between 85 o c and 9 5 o c cas e tempe r a t ur e. full sp ecifications a r e guar antee d in thi s r a nge, but the f o l l ow ing additional conditions a pply: a. r e f r esh com mands must be d o uble d in f r equency , ther ef or e r e du cin g the r e f r e s h in te rv al trefi to 3.9 s. b . if self -r e f re sh oper ation is r e quire d in the extende d t e mper atur e r a nge, the n it is mandatory to us e the ma n- ua l self -r ef re sh m o de with extended t e m p er atur e r a nge cap a bilit y (mr2 a6 = 0 b and mr 2 a7 = 1 b ).
rev. 1.1 / may. 2012 11 ac & dc operating c o nd itions recommended dc operat ing conditions recommended dc operating conditions symbol parameter rating units notes min. typ. ma x. vd d supply volta ge 1.425 1 . 5 0 0 1 .575 v 1 ,2 vd dq supply volta ge f o r o u tput 1.425 1 . 5 0 0 1 .575 v 1 ,2 no tes: 1. unde r all condition s, vdd q mu st be less than or equ a l to vdd . 2. vddq tr ac ks wi th vdd . ac par a me ters are meas ur ed with vdd and vddq tied together .
rev. 1.1 / may. 2012 12 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chap ter , idd and i d dq meas ur ement c o nditions such as t e st load and pat t e rns ar e defined. figure 1. s h ow s the setup a n d tes t lo ad f o r idd and iddq meas urements. ? i dd curr ent s (such as idd0, idd 1 , idd2n, idd2nt , idd2p0, idd2p 1, idd2q , idd3n, idd3p , idd4r, idd4w , idd 5 b , idd6, idd6et and idd7) ar e measur ed as time - a v e r a ged c u rr ents with all vdd balls of the ddr3 sdram under t e st tied t o get h er . an y iddq curr ent is not inc l uded in idd curr ents. ? i ddq curr ent s (such as iddq2nt and iddq4r) ar e measured as time- a v e r a ged currents wi th al l vddq balls of t h e dd r3 sdram u n der t e st tied toge ther . an y idd curr ent is not incl uded in iddq cur - re n t s . a t tention: id dq v a lues c a nnot be dir e c t ly used to calcul ate io p o wer of the ddr3 sdram . they can be used to support c o rr elation of simulated io p o we r to actual io power as outl ined in figur e 2. i n dram module application, i d dq c a nnot be measur ed separ a tely si nce vdd and vddq ar e using one merged-power la yer in module pcb . f o r i d d and iddq meas urements, the f o llo wi ng defi nitions appl y: ? ? 0? and ?l ow ? is defined as vin <= v ilac(max). ? ? 1? and ?high? is defined as vin >= v ihac(max). ? ? mid_level ? is defined as inputs ar e vr ef = vdd/2. ? timing used f o r idd and idd q measur ement - l o op p a t t erns are pro vided in t a ble 1. ? b asic idd and iddq measurement c o nditions ar e desc rib e d in t a ble 2. ? d etailed idd an d iddq measur ement - loop p a t t e rns ar e desc ribed in t a ble 3 thr o ugh t a ble 10. ? i dd mea s u r e m ent s ar e do ne afte r pr ope r ly init ia liz i ng the ddr 3 sdr a m. t h is includes but is not l i m- ited to set t ing ron = rzq/7 (34 ohm in mr1); qof f = 0 b (output b u f f er enabled in m r 1); r t t_nom = rzq/ 6 ( 40 ohm in mr1); r t t_w r = rzq/ 2 (120 ohm in mr2); tdqs f e atur e disabled in mr1 ? a t t e ntion: the idd and id dq measur e m ent - loop p a t t e r ns ne ed to be ex ecut ed at least one time bef o re act u al idd or iddq me as ur eme n t is s t a r te d. ? d efi n e d = {cs , ras , cas , we }:= {high, l o w , l o w , l o w} ? d efi n e d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 1.1 / may. 2012 13 figur e 1 - measur ement setup and t e st load f o r idd an d iddq (optional) measur ements [note: dimm lev e l output test load condition ma y be dif f er en t f r om abo v e] figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3 sdram v ddq re set ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, d m , t d q s , tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 1.1 / may. 2012 14 tab l e 1 -tim in g s u s ed for id d an d id dq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 uni t 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 t ck 1. 8 7 5 1 .5 1 . 2 5 1. 07 0. 9 3 5 n s cl 7 9 11 13 14 nck n rcd 7 9 11 13 14 nck n rc 27 3 3 39 45 50 nck n ras 20 2 4 28 32 36 nck n rp 7 9 11 13 14 nck n fa w 1kb pa g e size 20 2 0 24 26 27 nck 2kb pa g e size 27 3 0 32 33 38 nck n rrd 1kb pa g e size 44 5 5 6 n c k 2kb pa g e size 65 6 6 7 n c k n rfc -5 12mb 4 8 6 0 7 2 8 5 9 7 n ck n rfc -1 gb 59 7 4 88 103 118 nck n rfc - 2 gb 86 1 0 7 128 150 172 nck n rfc - 4 gb 160 2 0 0 240 281 321 nck n rfc - 8 gb 187 2 3 4 280 328 375 nck symbol descrip t io n i dd 0 operati n g one bank active-precharge curre nt cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; comma nd, add r ess, bank addr ess inputs : pa rtially toggling a c cording to table 3 ; da ta io: mid-level; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3.
rev. 1.1 / may. 2012 15 i dd 1 oper ating one ba nk activ e-r e a d-pr echar g e curr ent cke: high; exter n al cloc k: on; tck, nrc, nras , nrcd , cl: see t a b l e 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, data io: partially toggling according to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4. i dd2n pr echar g e standby curr ent cke: hi gh; external clock: on ; tck, cl: see t a ble 1; bl: 8 a) ; al: 0; cs : stable a t 1; comm and , add r ess, bank addr ess inputs : partially toggl in g a c cording to t a ble 5 ; da ta io: m i d_l e vel ; dm : stab le at 0; bank activity: all banks clos ed; output bu f f er and rtt: ena b led in mode reg i ste r s b) ; odt signal: stable at 0; pattern details: see table 5. i dd 2n t pr echar g e standby od t curr ent cke: hi gh; external clock: on ; tck, cl: see t a ble 1; bl: 8 a) ; al: 0; cs : stable a t 1; comm and , add r ess, bank addr ess inputs : partially toggl in g a c cording to t a ble 6 ; da ta io: m i d_l e vel ; dm : stab le at 0; bank activity: al l banks cl osed; output bu ff er and rtt: enabled in mode registe r s b) ; odt signal: tog - gling according to table 6; pattern details: see table 6. i dd2p0 pr echar g e p o wer - down cur r e n t slow exit cke: low; extern al clock: on; tck, cl: se e t a ble 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 pr echar g e p o wer - down cur r e n t f a st e xit cke: low; extern al clock: on; tck, cl: se e t a ble 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd 2q pr echar g e quiet sta n db y curr ent cke: hi gh; external clock: on ; tck, cl: see t a ble 1; bl: 8 a) ; al: 0; cs : stable a t 1; comm and , add r ess, ban k add r ess i n pu ts : stab le at 0; data io: m i d_l e vel ; dm : stab le at 0; ba nk activity: a l l ba nks close d; output buff er a n d rtt: enabled in mode re gis t ers b) ; odt s i gn al: stab le at 0 symbol description
rev. 1.1 / may. 2012 16 i dd3n activ e standb y cur r e n t cke: hi gh; external clock: on ; tck, cl: see t a ble 1; bl: 8 a) ; al: 0; cs : stable a t 1; comm and , add r ess, bank addr ess inputs : partially toggl in g a c cording to t a ble 5 ; da ta io: m i d_l e vel ; dm : stab le at 0; bank activity: al l banks open; output buff er and rtt: ena ble d in mode registers b) ; odt signal: s t able a t 0; p a t t er n de t a ils : s e e t a bl e 5 . i dd3p active p o wer - down current cke: low; extern al clock : on; tck, cl: see t a ble 1; bl: 8 a) ; al: 0; cs : s t able a t 1; comman d , addre ss, ban k addr ess in puts : stable a t 0; da ta io: mid_ level; d m : sta b le at 0; ba nk activ i ty : all ban k s open ; output buff er and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd4r oper ating burst r e ad curr ent cke: hig h ; external clock: o n ; tck, cl: see t a ble 1 ; bl: 8 a) ; a l : 0; cs : high be twe e n rd ; command, addre ss, bank add r ess i n puts : partially toggling accord ing to table 7 ; data io: se amless read data burs t wit h diff erent data between one bu rst an d the next one according to ta ble 7; d m : s t a b le at 0 ; bank activity: all banks open, rd comm ands cyclin g throug h ban k s: 0 , 0,1,1,2, 2 , ...(see table 7); output buff er and rtt: ena bled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd 4w oper ating burst w r i t e curr ent cke: hig h ; external clock: o n ; tck, cl: see t a ble 1 ; bl: 8 a) ; a l : 0; cs : high be twe e n wr; comma nd, addre ss, bank add r ess i n puts : partially toggling accord ing to table 8 ; data io: se amless read data burs t wit h diff erent data between one bu rst an d the next one according to ta ble 8; d m : s t a b le at 0 ; bank activity: a l l ba nks op en, wr com m ands cycling throug h ban k s: 0,0,1,1,2,2 , ...(see table 8 ) ; ou tput bu f- fe r and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd 5b burs t r e fr esh curr ent cke: hi g h ; external cl ock: o n ; tc k, cl , n r fc: see t a ble 1; bl : 8 a) ; al: 0; cs : high b e tween ref; com- mand, addr ess, bank ad dress inputs: p a rtially togglin g a ccord ing to table 9 ; da ta io: mid _ level; dm: stab le at 0; ba nk a c tiv i t y : ref comman d ev ery n r ef (s ee table 9); outp ut buf f er a n d rtt: e n abled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd 6 self -r ef r e sh curr ent: norm al t e mper ature r a nge t cas e : 0 - 85 o c; auto self -r ef r esh (a sr): disabled d) ;self - r e f r esh t e mper atur e r a nge (sr t ): normal e) ; cke: low ; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; out- put buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol descrip tion
rev. 1.1 / may. 2012 17 a) bu rst le ngth : bl8 fix e d b y mrs: s e t mr0 a[1 , 0]=00b b) output b u ff er enabl e : set mr1 a[12] = 0b; s e t mr1 a[ 5,1] = 01 b; r t t_nom e n ab le : set mr1 a[9 , 6,2] = 0 11b; r t t_ w r e n ab le : set mr2 a[10,9] = 10b c) pr ech a r g e p o wer d o wn mode: se t mr0 a 12=0b f o r slow exit or mr0 a12 = 1 b f o r f a s t exit d) a u to se lf -r ef r e sh (a sr): set mr2 a6 = 0b to disable or 1b to en able f e a t u r e e) se lf -r ef r e sh t e mper ature r a nge (sr t ): s e t mr2 a7 = 0b f o r norma l or 1b f o r exten d ed te mper atur e r a nge f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd6e t self -r ef r e sh curr ent: exte nded t e mper ature r a nge (optiona l) f) t cas e : 0 - 95 o c; auto self -r ef re sh (asr): disabled d) ;self - r e f r esh t e mpe r a t ur e r a nge (sr t ): exte nd- ed e) ; cke: low; exter n al clock : of f ; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended tempera- ture self-refresh operation; output buff er and rtt: enabled in mode registers b) ; odt signal: mid_level i dd 7 oper ating bank i n terlea ve r e ad curre nt cke: hi g h ; external cl ock: o n ; tck, nrc, nras , nr cd , nrrd , nf a w , cl: see t a ble 1; bl: 8 a), f) ; al: cl- 1; cs : hig h be t w e en act and rda ; comm and , ad dress, bank add r ess i n puts: partially toggling a ccord- ing to table 10 ; data io: rea d data bur s t with di ffe rent d a ta b e tween one burst and the next one according to table 10 ; dm: stab le at 0; ban k acti vity: two times i n terleaved cycling through banks (0, 1,...7) with dif f ere n t a ddress i ng, we e ta ble 10; ou tput buffe r and rtt: ena b le d in mod e registers b) ; odt si gn al: stab le at 0; p a ttern de tails: see t a ble 1 0 . symbol descrip tion
rev. 1.1 / may. 2012 18 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs ar e m i d- lev e l. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling static high 0 0 a c t 0 0 1 100 0 0 0 0 0 0 - 1 , 2 d , d 1 0 0 000 0 0 0 0 0 0 - 3, 4 d , d 1 1 1 100 0 0 0 0 0 0 - ... repeat pattern 1. .. 4 u n ti l n r as - 1, trun cate if neces s ary n r a s p r e 0 0 1 000 0 0 0 0 0 0 - ... repeat pattern 1. .. 4 u n ti l n rc - 1, tru n cate if nece ssary 1 * nrc+0 a ct 0 0 1 1 0 0 00 0 0 f 0 - 1 * nrc+1, 2 d , d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1 1 1 100 0 0 0 0 f 0 - ... repe at pa ttern 1 . ..4 un til 1*n rc + nra s - 1, trun cate if necess ary 1 * nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repe at pa ttern 1 . ..4 un til 2*n rc - 1, trunca t e if n e cessa ry 1 2 *nrc repe at sub-loop 0, use ba[2:0 ] = 1 in stea d 2 4 *nrc repe at sub-loop 0, use ba[2:0 ] = 2 in stea d 3 6 *nrc repe at sub-loop 0, use ba[2:0 ] = 3 in stea d 4 8 *nrc repe at sub-loop 0, use ba[2:0 ] = 4 in stea d 5 1 0*nrc repe at sub-loop 0, use ba[2:0 ] = 5 in stea d 6 1 2*nrc repe at sub-loop 0, use ba[2:0 ] = 6 in stea d 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 / may. 2012 19 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs ar e us ed ac cor din g to rd co mman ds, o t herwise m i d- lev e l. b) burs t sequ ence driv en on ea ch d q signa l b y r ea d co m m an d. ou tside bu rst oper ation , dq sign als ar e m i d_ lev e l. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling static high 0 0 act 0 0 1 1 0 0 0 0 0 0 0 0 - 1,2 d , d 1 0 0 0 0 0 0 0 0 0 0 0 - 3,4 d , d 11 1 1 0 0 0 0 0 0 0 0 - ... r epeat patter n 1...4 until n rcd - 1 , tru n ca te if ne cessar y n rcd rd 0 1 0 1 0 0 00 0 0 0 0 0000 0000 ... r epeat patter n 1...4 until nr as - 1, trun ca te if n e cessa ry nras pre 0 0 1 0 0 0 0 0 0 0 0 0 - ... r epeat patter n 1...4 until n rc - 1, truncate if neces s ary 1* nrc+0 a ct 0 0 1 1 0 0 00 0 0 f 0 - 1* nrc+1,2 d , d 1 0 0 0 0 0 00 0 0 f 0 - 1* nrc+3,4 d , d 11 1 1 0 0 0 0 0 0 f 0 - ... r epeat patter n nr c + 1,...4 until n rc + nrce - 1, truncate if necessary 1* nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 0011 0011 ... r epeat patter n nr c + 1,...4 until n rc + nras - 1 , truncate if ne cessar y 1* nrc+nras pre 0 0 1 0 0 0 0 0 0 0 f 0 - ... r epea t patter n n r c + 1,...4 until *2 n rc - 1, trunca t e if n e cessa ry 1 2 * n rc repea t su b-loop 0, use ba[2:0] = 1 in stead 2 4 * n rc repea t su b-loop 0, use ba[2:0] = 2 in stead 3 6 * n rc repea t su b-loop 0, use ba[2:0] = 3 in stead 4 8 * n rc repea t su b-loop 0, use ba[2:0] = 4 in stead 5 1 0 * nrc r epea t sub-loop 0, use ba[2:0] = 5 instead 6 1 2 * nrc r epea t sub-loop 0, use ba[2:0] = 6 instead 7 1 4 * nrc r epea t sub-loop 0, use ba[2:0] = 7 instead
rev. 1.1 / may. 2012 20 tab l e 5 - idd2n and idd3n measurement- loop pattern a) a) dm must be driven low all the time. dqs, dqs ar e m i d- lev e l. b) dq s i g n als a r e mid - level . tab l e 6 - idd2nt and iddq2n t measurement-loop pattern a) a ) dm m u s t b e d r ive n l o w a l l th e ti me . dqs , dqs ar e m i d- lev e l. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling static high 0 0 d1 0 0 0 0 0 0 0 0 0 0 - 1d 1 0 0 0 0 0 0 0 0 0 0 - 2d 11 1 1 0 0 0 0 0 f 0 - 3d 11 1 1 0 0 0 0 0 f 0 - 1 4 -7 repea t su b-loop 0, use ba[2:0] = 1 in stead 2 8 -11 r epea t sub-loop 0, use ba[2:0] = 2 instead 3 12 - 15 repea t su b-loop 0, use ba[2:0] = 3 in stead 4 16 - 19 repea t su b-loop 0, use ba[2:0] = 4 in stead 5 20 - 23 repea t su b-loop 0, use ba[2:0] = 5 in stead 6 24 - 17 repea t su b-loop 0, use ba[2:0] = 6 in stead 7 28 - 31 repea t su b-loop 0, use ba[2:0] = 7 in stead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling sta tic high 0 0 d1 0 0 0 0 0 0 0 0 0 0 - 1d 1 0 0 0 0 0 0 0 0 0 0 - 2d 11 1 1 0 0 0 0 0 f 0 - 3d 11 1 1 0 0 0 0 0 f 0 - 1 4 -7 repea t sub-loop 0, but od t = 0 and ba [2:0 ] = 1 2 8 -11 r epea t sub-loop 0, bu t odt = 1 and ba [2:0] = 2 3 1 2- 15 r e p e at s u b - l o o p 0 , b u t odt = 1 a n d b a [ 2 : 0 ] = 3 4 16 - 1 9 repea t sub-loop 0, but od t = 0 and ba [2:0 ] = 4 5 20 - 2 3 repea t sub-loop 0, but od t = 0 and ba [2:0 ] = 5 6 2 4- 17 r e p e at s u b - l o o p 0 , b u t odt = 1 a n d b a [ 2 : 0 ] = 6 7 2 8- 31 r e p e at s u b - l o o p 0 , b u t odt = 1 a n d b a [ 2 : 0 ] = 7
rev. 1.1 / may. 2012 21 tab l e 7 - i dd4 r and i d d q 4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs ar e us ed ac cor din g to rd co mman ds, o t herwise m i d- lev e l. b) burs t sequ ence driv en on ea ch d q signa l b y r ea d co m m an d. ou tside bu rst oper ation , dq sign als ar e m i d- lev e l. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00 00000 0 1d 1 0 0 0 0 0 0 0 0 0 0 0 - 2, 3 d ,d 11 1 1 0 0 0 0 0 0 0 0 - 4 r d 0 1 0 1 0 0 00 0 0 f 0 00 11001 1 5d 1 0 0 0 0 0 0 0 0 0 f 0 - 6, 7 d ,d 11 1 1 0 0 0 0 0 0 f 0 - 1 8-15 repe a t sub-loop 0, but ba[2:0] = 1 2 1 6-2 3 repe at sub-loop 0, but ba[2:0] = 2 3 2 4-3 1 repe at sub-loop 0, but ba[2:0] = 3 4 3 2-3 9 repe at sub-loop 0, but ba[2:0] = 4 5 4 0-4 7 repe at sub-loop 0, but ba[2:0] = 5 6 4 8-5 5 repe at sub-loop 0, but ba[2:0] = 6 7 5 6-6 3 repe at sub-loop 0, but ba[2:0] = 7
rev. 1.1 / may. 2012 22 ta bl e 8 - id d 4 w m e a s u r e m en t-loop pa tt er n a) a) dm must be driven low all the time. dqs, dqs ar e us ed ac cor d in g to wr comm ands , othe rwise mid - l e vel . b) bur s t sequence driv en on ea ch d q signa l b y w r ite co mm and . ou tsid e bu rst oper ation , d q signa l s ar e m i d- lev e l. table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 0000 0000 1d 1 0 0 0 1 0 0 0 0 0 0 0 - 2, 3 d ,d 11 1 1 1 0 0 0 0 0 0 0 - 4 w r 0 1 0 0 1 0 00 0 0 f 0 0011 0011 5d 1 0 0 0 1 0 0 0 0 0 f 0 - 6, 7 d ,d 11 1 1 1 0 0 0 0 0 f 0 - 1 8 -15 r epe a t sub-loop 0, but ba[2:0] = 1 2 1 6-2 3 repe at sub-loop 0, but ba[2:0] = 2 3 2 4-3 1 repe at sub-loop 0, but ba[2:0] = 3 4 3 2-3 9 repe at sub-loop 0, but ba[2:0] = 4 5 4 0-4 7 repe at sub-loop 0, but ba[2:0] = 5 6 4 8-5 5 repe at sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling sta t ic hi gh 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11 . 2 d , d 1 0 0 0 0 0 0 0 0 0 0 0 - 3,4 d , d 11 1 1 0 0 0 0 0 0 f 0 - 5... 8 r epeat cycles 1. .. 4, bu t ba[2:0] = 1 9... 12 repeat cycles 1. .. 4, bu t ba[2:0] = 2 13 ...1 6 r epea t cycles 1 . ..4 , b u t ba[2:0] = 3 17 ...2 0 r epea t cycles 1 . ..4 , b u t ba[2:0] = 4 21 ...2 4 r epea t cycles 1 . ..4 , b u t ba[2:0] = 5 25 ...2 8 r epea t cycles 1 . ..4 , b u t ba[2:0] = 6 29 ...3 2 r epea t cycles 1 . ..4 , b u t ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 1.1 / may. 2012 23 table 10 - idd7 meas urement-loop pattern a) a t tention! sub-loops 10-1 9 ha v e in v e rse a[6:3] p a t t ern and da ta p a ttern than sub-lo ops 0-9 a) dm must be driven low all the time. dqs, dqs ar e us ed ac cor din g to rd co mman ds, o t herwise m i d- lev e l. b) burs t sequ ence driv en on ea ch d q signa l b y r ea d co m m an d. ou tside bu rst oper ation , dq sign als ar e m i d- lev e l. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] da ta b) toggling static high 0 0 ac t 0 0 1 1 0 0 0 0 0 0 0 0 - 1 r da 0 1 0 1 0 0 00 1 0 0 0 0 00000 00 2d 1 0 0 0 0 0 0 0 0 0 0 0 - ... repe at ab ov e d comma nd u n til nrrd - 1 1 nrrd a c t 0 0 1 1 0 1 0 0 0 0 f 0 - n rrd+1 rda 0 1 0 1 0 1 0 0 1 0 f 0 0 01100 11 nrrd+2 d 1 0 0 0 0 1 0 0 0 0 f 0 - ... repe at ab ov e d comma nd u n til 2* n rrd - 1 2 2 *nrrd repe at sub-loop 0, but ba[2:0] = 2 3 3 *nrrd repe at sub-loop 1, but ba[2:0] = 3 4 4 * nrrd d1 0 0 0 0 3 0 0 0 0 f 0 - asse rt and repea t above d comma nd until nfaw - 1, if ne cessa ry 5 n faw r epe a t sub-loop 0, but ba[2:0] = 4 6 n faw+nrrd repe at sub-loop 1, but ba[2:0] = 5 7 n faw+2*n r r d r epe a t sub-loop 0, but ba[2:0] = 6 8 n faw+3*n r r d r epe a t sub-loop 1, but ba[2:0] = 7 9 n f aw+4*n r r d d1 0 0 0 0 7 0 0 0 0 f 0 - asse rt and repea t above d comma nd until 2* nfaw - 1 , if neces s ary 10 2* n f a w +0 ac t 0 0 1 1 0 0 0 0 0 0 f 0 - 2 * nfaw+1 rda 0 1 0 1 0 0 0 0 1 0 f 0 0 01100 11 2& n f a w +2 d1 0 0 0 0 0 0 0 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2* n f a w +nr r d a c t 0 0 1 1 0 1 0 0 0 0 0 0 - 2 * nfaw+n r r d + 1 r da 0 1 0 1 0 1 00 1 0 0 0 0 00000 00 2 &nfaw+nrrd+ 2 d1 0 0 0 0 1 0 0 0 0 0 0 - repea t above d comma nd u n til 2* n f aw + 2* n rrd - 1 12 2 * nfaw+2* n rrd repe at sub-loop 10, but ba[2:0] = 2 13 2 * nfaw+3* n rrd repe at sub-loop 11, but ba[2:0] = 3 1 4 2* n f a w +4 *n r r d d1 0 0 0 0 3 0 0 0 0 0 0 - asse rt and repea t above d comma nd until 3* nfaw - 1 , if neces s ary 15 3 * nfaw repe at sub-loop 10, but ba[2:0] = 4 16 3 * nfaw+n r r d r epe a t sub-loop 11, but ba[2:0] = 5 17 3 * nfaw+2* n rrd repe at sub-loop 10, but ba[2:0] = 6 18 3 * nfaw+3* n rrd repe at sub-loop 11, but ba[2:0] = 7 1 9 3* n f a w +4 *n r r d d1 0 0 0 0 7 0 0 0 0 0 0 - asse rt and repea t above d comma nd until 4* nfaw - 1 , if neces s ary
rev. 1.1 / may. 2012 24 idd specifications idd v a lues ar e f o r f u ll oper at ing r a nge of v o ltage and te mper atur e unless ot herwise note d. i dd specifi c ation no tes: 1. applicable f o r mr2 set t ing s a6=0 a n d a 7 =0. t emper atu r e r a nge f o r id d6 is 0 - 85 o c. 2. applicable fo r mr2 set t ing s a6=0 a n d a 7 =1. t e mper atu r e r a nge f o r id d6 et is 0 - 95 o c. s p eed grade bin symbol ddr3 - 1066 7-7-7 ddr3 - 1333 9-9-9 ddr3 - 1600 11-11-11 ddr3 - 1866 13-13-13 ddr3 - 2133 14-14-14 unit notes max. max. max. max. max. i dd0 50 55 55 60 6 5 m a x8 50 55 55 60 6 5 m a x1 6 i dd 01 60 65 70 75 8 0 m a x8 60 65 70 75 8 0 m a x1 6 i dd 2p0 12 12 12 12 1 2 m a x8 /1 6 i dd 2p1 15 15 20 20 2 0 m a x8 15 15 20 20 2 0 m a x1 6 i dd2 n 25 25 30 30 3 5 m a x8 /1 6 i dd2 nt 25 25 30 30 3 5 m a x8 35 40 40 40 4 5 m a x1 6 i dd2q 25 25 30 30 3 5 m a x8 /1 6 i dd3 p 20 20 20 20 2 5 m a x8 20 20 20 20 2 5 m a x1 6 i dd3 n 30 30 35 35 4 0 m a x8 30 30 35 35 4 0 m a x1 6 i dd4 r 12 0 14 0 16 5 18 5 21 0 m a x 8 12 0 14 0 16 5 18 5 21 0 m a x 1 6 i dd 4 w 11 5 13 5 15 5 17 0 19 0 m a x 8 11 5 13 5 15 5 17 0 19 0 m a x 1 6 i dd5b 10 5 11 0 12 0 12 5 13 0 m a x 8 10 5 11 0 12 0 12 5 13 0 m a x 1 6 i dd6 n o r m a l 12 12 12 12 1 2 m a x8 /1 6 lo w power 6.5 6 .5 6.5 6 .5 6.5 m a x8 6.5 6 .5 6.5 6 .5 6.5 m a x 16 i dd 6 e t 14 14 14 1 4 1 4 m a x8 /1 6 i dd7 21 5 22 5 23 5 25 5 28 0 m a x 8 21 5 22 5 23 5 25 5 28 0 m a x 1 6
rev. 1.1 / may. 2012 25 input/output capacitance parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 units notes min max min max min max min max min max min ma x i n put/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io 1.5 3 .0 1.5 2 . 7 1 . 5 2 .5 1.5 2 .3 1.4 2 .2 1.4 2 .1 pf 1,2,3 i n put capa citance, ck a n d ck c ck 0.8 1 .6 0.8 1 .6 0 . 8 1 .4 0.8 1 .4 0.8 1 .3 0.8 1 .3 pf 2,3 i n put ca pacita nce d e lta ck and ck c dck 0 0 . 1 5 0 0 . 15 0 0 .1 5 0 0. 1 5 0 0 .1 5 0 0. 15 p f 2,3,4 i n put ca pacita nce d e lta , dqs and dqs c ddqs 0 0.20 0 0.20 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,5 i n put ca pacita nce ( a ll o t her in put - on ly pi ns) c i 0. 75 1.4 0 . 7 5 1 .3 5 0 . 7 5 1 .3 0. 75 1.3 0 . 7 5 1 .2 0. 75 1.2 p f 2 ,3,6 i n put ca pacita nce d e lta (al l ctrl input - only pi ns) c di_ctr l -0 .5 0.3 - 0.5 0 .3 -0.4 0.2 - 0.4 0 .2 -0.4 0.2 - 0 . 4 0 .2 pf 2,3 , 7 , 8 i n put ca pacita nce d e lta (al l add/cm d input - on ly pi ns ) c di _add _cmd -0 .5 0.5 - 0.5 0 .5 -0.4 0.4 - 0.4 0 .4 -0.4 0.4 - 0 . 4 0 .4 pf 2,3,9 , 10 i n put/output capacitance de l t a (d q , d m , dqs , dqs ) c di o -0 .5 0.3 - 0.5 0 .3 -0.5 0.3 - 0.5 0 .3 -0.5 0.3 - 0 . 5 0 .3 pf 2,3,11 i n put/output capacitance of zq pin c zq - 3 - 3 - 3 - 3 - 3 - 3 pf 2,3,12 no tes: 1. although the dm , t d qs an d td qs pin s h a v e dif f e r e nt f u nction s, the loading match e s dq and dqs . 2. this par a meter is not subject to pr od uction tes t . it is v e rified b y de sig n and char acterizati on. the capaci tance i s mea s ur ed a ccor d in g to jep 147 (?p r oced ure for mea s uring input cap a cit a n ce using a vect or netwo r k anal yz er(vna)?) with vdd , vd dq , vs s , vs sq applie d an d all othe r pins f l oa ting (e x c ept the pin unde r test, cke, reset and odt a s ne cessa ry). v d d = vd dq=1.5v , vbia s=v d d / 2 and on -d ie termination of f . 3 . this pa r a meter a pplie s to monolithic devices on ly ; stack e d/dual-d ie devices ar e not co v e r e d her e 4 . absolute v a lue of c ck -c ck . 5 . ab solute value of c io (dqs)-c io (dqs ). 6. c i applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 7. c di _ctr applies to odt, cs an d cke. 8. c di _ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk )) 9. c di _add_ cmd applies to a0-a15, ba0-ba2, ras , cas and we . 10 . c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk )) 11 . c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs )) 1 2 . maximum external load capacitance an zq pin: 5 pf.
rev. 1.1 / may. 2012 26 standard speed bins ddr3l sdram st andard spe e d bins include t c k, trcd , trp , tras and trc f o r each c o rr espond ing bin. ddr3-80 0 speed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal r e ad command to first data t aa 15 2 0 ns act to inter n al read or wri t e delay ti m e t rcd 15 ? n s pre comma nd period t rp 15 ? n s act to act or ref comma nd pe riod t rc 52.5 ? n s act to pre comma nd pe riod t ras 37.5 9 * trefi n s cl = 5 c wl = 5 t ck(avg) 3.0 3 .3 n s 1, 2, 3, 4, 11 cl = 6 c wl = 5 t ck(avg) 2.5 3 .3 n s 1 , 2, 3 su ppor t ed cl settings 5, 6 n ck 11 supported cwl settings 5 n ck
rev. 1.1 / may. 2012 27 d d r3-1066 sp eed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13 . 1 2 5 20 ns act to internal read or write delay time t rcd 13 . 12 5 ? n s p re com m and period t rp 13 . 12 5 ? n s act to act or ref command per i od t rc 50 . 62 5 ? n s act to pre command per i od t ras 37.5 9 * tr efi n s cl = 5 cwl = 5 t ck(avg) 3.0 3 .3 n s 1 , 2 , 3 , 4 , 6, 11 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3 .3 n s 1, 2 , 3 , 6 cwl = 6 t ck(avg) reserv ed n s 1, 2 , 3 , 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1. 87 5 < 2 . 5 n s 1 , 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1. 87 5 < 2 . 5 n s 1 , 2, 3 su pported cl setting s 5 , 6 , 7 , 8 n ck 11 supported cwl settings 5 , 6 n ck
rev. 1.1 / may. 2012 28 d d r3-1333 sp eed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 11 20 n s act to i n ternal read or write del a y time t rcd 13.5 (13.125) 11 ?n s pre command per i od t rp 13.5 (13.125) 11 ?n s ac t t o a c t o r r e f comma nd p e riod t rc 49.5 (49.125) 11 ?n s a c t to pre command pe r i o d t ras 36 9 * trefi n s cl = 5 cw l = 5 t ck( a vg) 3.0 3 .3 n s 1 , 2, 3, 4, 7, 1 1 cwl = 6, 7 t ck( a vg) re served ns 4 cl = 6 cw l = 5 t ck( a vg) 2.5 3 .3 n s 1, 2, 3, 7 cw l = 6 t ck( a vg) re serv ed n s 1, 2, 3, 4 , 7 cw l = 7 t ck( a vg) re served ns 4 cl = 7 cw l = 5 t ck( a vg) re served ns 4 cw l = 6 t ck( a vg) 1 . 87 5 < 2.5 n s 1, 2, 3, 4 , 7 (opti o n a l) 11 cw l = 7 t ck( a vg) re serv ed n s 1, 2, 3, 4 cl = 8 cw l = 5 t ck( a vg) re served ns 4 cw l = 6 t ck( a vg) 1 . 87 5 < 2.5 n s 1 , 2, 3, 7 cw l = 7 t ck( a vg) re serv ed n s 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck( a vg) re served ns 4 cw l = 7 t ck( a vg) 1.5 < 1.875 n s 1, 2 , 3, 4 cl = 10 cwl = 5, 6 t ck( a vg) re served ns 4 cw l = 7 t ck( a vg) 1.5 < 1.875 n s 1, 2, 3 ( o ptional) ns 5 su pported cl se ttin gs 5 , 6 , 8, (7), 9 , (10) n ck supporte d cwl settings 5 , 6, 7 n ck
rev. 1.1 / may. 2012 29 d d r3-1600 sp eed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13 . 12 5) 11 20 ns act to i n ternal read or write del a y time t rcd 13.75 (13 . 12 5) 11 ?n s pre command per i od t rp 13.75 (13 . 12 5) 11 ?n s ac t t o a c t o r r e f comma nd p e riod t rc 48.75 (48 . 12 5) 11 ?n s a c t to pre command pe r i o d t ras 3 5 9 * trefi n s cl = 5 cw l = 5 t ck( a vg) 3.0 3 .3 ns 1, 2, 3, 4, 8, 11 cwl = 6, 7 t ck( a vg) rese rved ns 4 cl = 6 cw l = 5 t ck( a vg) 2.5 3 .3 ns 1, 2 , 3 , 8 cw l = 6 t ck( a vg) rese rved ns 1, 2, 3 , 4 , 8 cw l = 7 t ck( a vg) rese rved ns 4 cl = 7 cw l = 5 t ck( a vg) rese rved ns 4 cw l = 6 t ck( a vg) 1.875 < 2.5 ns 1, 2, 3 , 4 , 8 (opti o na l) 5 cw l = 7 t ck( a vg) rese rved ns 1, 2, 3 , 4 , 8 cw l = 8 t ck( a vg) rese rved ns 4 cl = 8 cw l = 5 t ck( a vg) rese rved ns 4 cw l = 6 t ck( a vg) 1.875 < 2.5 n s 1 , 2 , 3 , 8 cw l = 7 t ck( a vg) rese rved ns 1, 2, 3 , 4 , 8 cw l = 8 t ck( a vg) rese rved ns 1, 2 , 3 , 4 cl = 9 cwl = 5, 6 t ck( a vg) rese rved ns 4 cw l = 7 t ck( a vg) 1.5 < 1.875 ns 1, 2, 3 , 4 , 8 (opti o na l) 5 cw l = 8 t ck( a vg) rese rved ns 1, 2 , 3 , 4 cl = 10 cwl = 5, 6 t ck( a vg) rese rved ns 4 cw l = 7 t ck( a vg) 1.5 < 1.875 ns 1, 2 , 3 , 8 cw l = 8 t ck( a vg) rese rved ns 1, 2 , 3 , 4 cl = 11 cwl = 5, 6,7 t ck( a vg) rese rved ns 4 cw l = 8 t ck( a vg) 1.25 <1.5 ns 1, 2 , 3 su ppo rted cl se ttin g s 5 , 6, (7), 8, (9), 10, 11 n ck sup p orte d cwl settings 5 , 6, 7, 8 n ck
rev. 1.1 / may. 2012 30 d d r3-1866 sp eed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-1866m unit note cl - nrcd - nrp 13-13-13 parameter symbol min max internal read command to first data t aa 13 .9 1 (13.125) 13 20 n s act to inter n al read or write del a y time t rcd 13 .9 1 (13.125) 13 ?n s pre command period t rp 13 .9 1 (13.125) 13 ?n s act to pre comma nd pe riod t ra s 34 9 * trefi n s act to act or pre comma nd pe riod t rc 47 .9 1 (47.125) 13 -n s cl = 5 cwl = 5 t ck(avg) 3 . 0 3 .3 n s 1, 2, 3, 4, 9 cwl = 6,7,8,9 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2 . 5 3 .3 n s 1, 2, 3, 9 cwl = 6 t ck(avg) reserv ed n s 1, 2, 3, 4, 9 c w l = 7, 8, 9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.87 5 < 2.5 n s 1 , 2, 3, 4, 9 c w l = 7, 8, 9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.87 5 < 2.5 n s 1 , 2, 3, 9 cwl = 7 t ck(avg) reserv ed n s 1, 2, 3, 4, 9 cwl = 8,9 t ck(avg) reserved ns 4 cl = 9 cwl = 5 , 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1 . 5 < 1.875 n s 1, 2, 3, 4, 9 cwl = 8 t ck(avg) reserv ed n s 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5 , 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1 . 5 < 1.875 n s 1, 2, 3, 9 cwl = 8 t ck(avg) reserv ed n s 1, 2, 3, 4, 9 cl = 11 c w l = 5, 6, 7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1 . 25 <1 .5 n s 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserv ed n s 1, 2, 3, 4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserv ed n s 1,2,3 , 4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1 . 07 <1.25 n s 1 , 2, 3 supported cl settings 5 , 6 , 7 , 8 , 9, 10 , 1 1 , 13 n ck su pported cwl setting s 5 , 6, 7, 8, 9 n ck
rev. 1.1 / may. 2012 31 d d r3-2133 sp eed bins for specific notes see "speed bin table notes" on page 32. speed bin ddr3-2133n unit note cl - nrcd - nrp 14-14-14 parameter symbol min max internal read c o mmand t o first data t aa 13.09 20.0 n s act to internal read or wri t e delay time t rcd 13.09 ? n s pre command period t rp 13.09 ? n s act to pre command pe riod t ras 33.0 9 * trefi n s ac t t o a c t o r p r e comma nd pe riod t rc 46.09 - n s cl = 5 cwl = 5 t ck(avg) res erved ns 1, 2, 3, 4, 10 cwl = 6,7,8,9,1 0 t ck(avg) res erved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3 .3 ns 1, 2, 3, 10 cwl = 6 t ck(avg) res erved ns 1, 2, 3, 4, 10 cwl = 7,8,9 1 0 t ck(avg) res erved ns 4 cl = 7 cwl = 5 t ck(avg) res erved ns 4 cwl = 6 t ck(avg) 1.8 7 5 < 2.5 n s 1 , 2, 3, 10 cwl = 7 t ck(avg) res erved ns 1, 2, 3, 4, 10 c w l = 8,9,10 t ck(avg) res erved ns 4 cl = 8 cwl = 5 t ck(avg) res erved ns 4 cwl = 6 t ck(avg) 1.8 7 5 < 2.5 n s 1 , 2, 3, 10 cwl = 7 t ck(avg) res erved ns 1, 2, 3, 4, 10 c w l = 8,9,10 t ck(avg) res erved ns 4 cl = 9 cwl = 5, 6 t ck(avg) res erved ns 4 cwl = 7 t ck(avg) 1.5 < 1 . 87 5 n s 1 , 2, 3, 10 cwl = 8 t ck(avg) res erved ns 1, 2, 3, 4, 10 cwl = 9 , 10 t ck(avg) res erved ns 4 cl = 10 cwl = 5, 6 t ck(avg) res erved ns 4 cwl = 7 t ck(avg) 1.5 < 1 . 87 5 n s 1 , 2, 3, 9 cwl = 8 t ck(avg) res erved ns 1, 2, 3, 4, 9 cwl = 9 t ck(avg) res erved ns 4 cwl = 10 t ck(avg) res erved ns 4 cl = 11 cwl = 5,6,7 t ck(avg) res erved ns 4 cwl = 8 t ck(avg) 1.2 5 <1.5 ns 1, 2, 3, 10 cwl = 9 t ck(avg) res erved ns 1, 2, 3, 4, 10 cwl = 10 t ck(avg) res erved ns 1, 2, 3, 4 cl = 12 c w l = 5 , 6, 7, 8 t ck(avg) res erved ns 4 cwl = 9 t ck(avg) res erved ns 1,2 , 3,4, 10 cwl = 10 t ck(avg) res erved ns 4 cl = 13 c w l = 5 , 6, 7, 8 t ck(avg) res erved ns 4 cwl = 9 t ck(avg) 1.0 7 <1.2 5 n s 1, 2, 3, 10 cwl = 10 t ck(avg) res erved 1, 2, 3, 4 cl = 14 cwl = 5,6,7,8,9 t ck(avg) res erved ns 4 cwl = 10 t ck(avg) 0.9 3 5 < 1.0 7 ns 1, 2, 3 su ppo rted cl settings 5 , 6 , 7 , 8, 9, 10 , 11 , 1 2 , 13, 14 n ck supp orted cwl settings 5 , 6, 7, 8, 9 , 1 0 n ck
rev. 1.1 / may. 2012 32 speed bin table notes ab solute specification (t op er ; v dd q = v dd = 1.5v +/- 0.075 v); 1. the cl set t ing and cwl set t ing r e sul t i n t c k( a v g ).min a n d tck( a v g ).ma x re quir ements. when making a selection of tck(av g), b o th need to be f u lfilled: r equir em ents f r om cl se t t in g as well as re quir emen ts f r om cwl s e t t ing. 2. tck(avg).min limi ts: since cas l a tency is not pur e ly a n alog - da ta and s t robe output ar e synchr onized b y the dll - a l l possible inte rmediate f r eque ncies m a y not be gua r a n teed . an applica t ion shou ld use the next s m aller je dec sta n - da rd tck ( a v g) v a lu e (3 .0 , 2.5, 1.8 75, 1.5 , or 1.25 ns ) wh en calculatin g cl [n ck] = taa [ns] / tck( a v g) [n s], r o und in g up to t h e next ?supported cl? , wher e tck(a v g) = 3. 0 n s sh ou ld on ly be u s ed f o r cl = 5 ca lcu l a t ion. 3. tck(avg).max l i mits: calculate tck(a v g) = taa. m a x / cl selected and r o und th e re sulting tck(a v g) down to the next v a lid speed bin (i.e. 3.3n s or 2 . 5n s or 1.875 ns or 1.25 ns ). th is r esu lt is tck(a v g).ma x corre sponding to cl selecte d . 4 . ?r e s erv ed? s et t ings ar e not a l lowed. user must pr ogr a m a dif f e r e n t v a lue. 5. ?optional? set t ings al lo w certain devices in t h e i n dustry to s u p p o r t t h i s s e t t i n g , h o w e v e r , i t i s n o t a m a n d a t o r y f e a - tur e . r e f e r t o sk hyni x dimm data s h ee t and/ or the dimm sp d in f o r m at i o n if an d ho w this se t t ing is supported. 6. an y ddr3-106 6 spee d bin a l s o s u pports f u nction al op er a t ion at lowe r f r eque ncies a s sho w n in the ta ble which a r e not subject to pr oduction tests but v e rif i e d by design/char a cterization. 7 . an y ddr3-133 3 spee d bin a l s o s u pports f u nction al op er a t ion at lowe r f r eque ncies a s sho w n in the ta ble which a r e not subject to pr oduction tests but v e rif i e d by design/char a cterization. 8. an y ddr3-160 0 spee d bin a l s o s u pports f u nction al op er a t ion at lowe r f r eque ncies a s sho w n in the ta ble which a r e not subject to pr oduction tests but v e rif i e d by design/char a cterization. 9. an y ddr3-186 6 spee d bin a l s o s u pports f u nction al op er a t ion at lowe r f r eque ncies a s sho w n in the ta ble which a r e not subject to pr oduction tests but v e rif i e d by design/char a cterization. 10. an y ddr3-213 3 spee d bin a l s o s u pports f u nction al op er a t io n at lowe r f r eque ncies a s sho w n in the ta ble which a r e not subject to pr oduction tests but v e rif i e d by design/char a cterization 11. sk hy nix dd r3 sdr a m dev i ce s s u pporting optional d o wn bi nning to cl=7 and cl=9, and ta a/tr cd/trp must be 13 .12 5 n s or lower . spd set t ing s mu st be pr ogr a m m ed to ma tc h . f o r exa mple, ddr 3-1 333h de vices supp orting down bin- n i n g to ddr3-106 6f sh ou ld pr ogr a m 13.125 n s in sp d b y te s f o r taam in (by t e 16), tr cdmin (byte 1 8), and trp m in (by t e 20). ddr3 - 16 00k de vices sup por tin g down b i n n in g to ddr3-1333 h or d d r3-1600f should pr ogr a m 13.125 n s in spd byte s f o r taamin (byte 16), tr cdmin (byte 18), and tr pmin (byte 2 0 ). once trp (by t e 20) is pr og r a mmed to 13 .12 5 ns, tr cmin (byte 21,23) also should be p r ogr a mme d ac cor d ingly . f o r examp l e , 49 .12 5 ns (tr a smin + trp min = 36 ns + 1 3 .1 25 n s) f o r dd r3-1333h an d 48.125 ns (tr a smin + trpmin = 35 ns + 13.125 n s) f o r d d r3-1600k . 12. f o r cl5 support, re f e r to dimm spd inf o rm a t ion. dr am is r e quir ed to supp ort cl5 . cl5 is no t ma nda t ory in s pd co ding. 13 . sk hynix dd r3 sdr a m devices s u pporting optional down bi nning to cl=11, cl=9 and cl=7 , taa/tr cd/ trpmin must be 13.125n s. spd se t t in g mu st be p r ogr a me d to match. f o r exam ple , dd r3-1866m devices supp orting down binnin g to ddr 3-1600 k or ddr3 - 1 333h or 1066f shou ld p r ogr a m 13.125n s in spd byte s f o r taamin (b yt e 1 6 ), tr cdmin(by te 18) a n d trpm in (b yte 20) is pr ogr a m m ed to 13.125 ns, trcm in (b yte 2 1 ,2 3) also should be pr og r a mmed a ccor d in gly . f o r example, 47 .12 5 ns (tr a smin + trpmin = 3 4 ns + 13.125n s)
rev. 1.1 / may. 2012 33 package dimensions package dimension(x8): 78ball fi ne pitch ball grid array outline
rev. 1.1 / may. 2012 34 package dimension(x16): 96ball fi ne pitch ball grid array outline

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