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pci 9030 data book

pci 9030 data book version 1.4 may 2002 website : http://www.plxtech.com email : apps@plxtech.com phone : 408 774-9060 800 759-3735 fax : 408 774-2169
? 2002 plx technology, inc. all rights reserved. plx technology, inc. retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx products. plx technology and the plx logo are registered trademarks and plxmon and smartarget are trademarks of plx technology, inc. other brands and names are the property of their respective owners. order number: 9030-sil-db-p1-1.4 printed in the usa, may 2002
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. v contents figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii supplemental documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii terms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii feature summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1. company and product background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1. pci 9030 smartarget i/o accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.2. smartarget technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.3. pci 9030 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.3.1. high-performance pci target interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.3.2. high-performance compactpci adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.3.3. pmc adapter cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.4. pci 9030 smartarget features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.4.1. performance features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.4.2. flexibility features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.4.3. additional features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.5. plx chip compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.5.1. pin compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.5.2. register compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.6. pci 9030 comparison with other plx chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2. pci and local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1. pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1. pci bus interface and bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1.1. pci target command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1.2. wait states?pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1.3. pci bus little endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1.4. pci prefetchable memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1.5. pci target accesses to an 8-or 16-bit local bus device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1.1. transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1.2. basic bus states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.2. local bus signals used in timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3. local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3.1. clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3.2. address/data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3.2.1. multiplexed mode (mode=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
contents pci 9030 data book version 1.4 vi ? 2002 plx technology, inc. all rights reserved. 2.2.3.2.1.1. la[27:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3.2.1.2. lad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3.2.2. non-multiplexed mode (mode=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.2.2.1. la[27:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.2.2.2. ld[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3. control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.1. ads#, ale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.2. lbe[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.3. llocko# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.4. lw/r# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.5. rd# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.3.6. ready# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.3.7. waito# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.3.8. wr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.4. local bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.4.1. lgnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.4.2. lreq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3.4.3. arbitration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4. local bus interface and bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4.1. bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4.2. wait state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4.2.1. internal wait state generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4.2.2. ready signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4.3. burst mode and continuous burst mode (bterm ? burst terminate ? mode) . . . . . . . . . . . . . . . . . . . 2-9 2.2.4.3.1. burst and bterm modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.4.3.2. burst-4 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.4.3.3. continuous burst mode (bterm ? burst terminate ? mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.2.4.3.4. partial lword accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4.4. recovery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4.5. local bus read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4.6. local bus write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.5. local bus big/little endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.5.1. 32-bit local bus ? big endian mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.5.2. 16-bit local bus ? big endian mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.5.3. 8-bit local bus ? big endian mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 3. serial eeprom reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2.1. pci bus rst# input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2.2. software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2.3. local bus output lreseto# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3. serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3.1. serial eeprom load sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3.1.1. serial eeprom load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3.1.2. recommended serial eeproms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4. internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1. pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.2. pci bus access to internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5. new capabilities function support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.6. serial eeprom and configuration initialization timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 4. pci target (direct slave) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2. direct data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1. pci target operation (pci master-to-local bus access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1.1. pci target lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
contents pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. vii 4.2.1.2. pci r2.2 features enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.2.1. pci target delayed read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.2.2. 2 15 pci clock timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.2.3. pci r2.2 16- and 8-clock rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.3. local bus prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.4. pci target read ahead mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.5. pci target delayed write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.6. pci target local bus ready# timeout mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.7. pci target transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.1.8. pci target pci-to-local address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.1.8.1. pci target local bus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.1.8.2. pci target initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.1.8.3. pci target example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.1.8.4. pci target byte enables (multiplexed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.1.8.5. pci target byte enables (non-multiplexed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -7 4.3. response to fifo full or empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4. pci target (direct slave) operation timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.1. serial eeprom and configuration initialization timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -13 4.4.2. multiplexed and non-multiplexed modes timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.2.1. multiplexed mode only timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 4.4.2.2. non-multiplexed mode only timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 5. local chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. chip select base address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3. procedure for using chip select base address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1. chip select base address register programming example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4. chip select timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 6. interrupts and general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2. interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2.1. pci interrupts (inta#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2.2. local interrupt input (linti[2:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2.3. local power management interrupt (lpmint#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2.4. local power management enumerator set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2.5. all modes pci serr# (pci nmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3. general purpose i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.4. interrupts and general purpose i/o timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 7. pci power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2. pci power management functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2.1. power management data_select, data_scale, and power data utilization . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.2. reading hidden data example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3. system changes power mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.4. wake-up request example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 8. compactpci hot swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2. controlling connection processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2.1. connection control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2.1.1. board slot control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2.1.2. board healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.1.3. platform reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
contents pci 9030 data book version 1.4 viii ? 2002 plx technology, inc. all rights reserved. 8.2.2. software connection control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.2.1. ejector switch and blue led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.2.2. enum# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.2.3. hot swap control/status register (hs_csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.2.4. hot swap capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9. pci vital product data (vpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2. vpd capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3. vpd serial eeprom partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.4. sequential read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.5. random access read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 10. registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1. new register definitions summary (as compared to the pci 9050 and pci 9052) . . . . . . . . . . . . . . . . . 10-1 10.2. register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3. pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4. local configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.5. chip select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.6. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 11. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. pull-up and pull-down resistor recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.1. input pins (pin type i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.2. output pins (pin type o). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.2.1. three-state output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.2.2. totem-pole output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.2.3. open-drain output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.3. i/o pins (pin type i/o). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3. pinout common to all bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4. multiplexed local bus mode pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.5. non-multiplexed local bus mode pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.6. debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.6.1. ieee 1149.1 test access port (jtag debug port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.6.2. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.6.3. jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 12. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1. general electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. local inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3. local outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 13. physical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1. 176-pin pqfp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. 180-pin bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 a. general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1. ordering instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2. united states and international representatives, and distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.3. technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index-1
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. ix figures pci 9030 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix 1-1 typical pci target adapter card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 high-performance compactpci adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-3 typical pmc adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-1 local bus block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 pci 9030 single cycle write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-3 pci 9030 single cycle read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-4 wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-5 big/little endian ? 32-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-6 big/little endian ? 16-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-7 big/little endian ? 8-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 3-1 serial eeprom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 pci 9030 internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4-1 pci target delayed read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2 pci target read ahead mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-3 pci target write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-4 pci target read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-5 local bus pci target access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 5-1 chip select base address and range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 6-1 interrupt and error sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 8-1 redirection of bd_sel# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-2 board healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-3 pci reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-4 hot swap capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9-1 vpd capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 12-1 pci 9030 local input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-2 pci 9030 local output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12-3 pci 9030 ale output delay (min/max) to the local clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 13-1 176-pin pqfp package mechanical dimensions ? topside and cross-section views . . . . . . . . . . . . . . . . . . . . . 13-1 13-2 176-pin pqfp pcb layout suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-3 176-pin pqfp pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13-4 180-pin bga package mechanical dimensions ? topside, underside, and cross-section views . . . . . . . . . . . . 13-4 13-5 180-pin bga pcb layout suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13-6 180-pin bga physical layout with pinout ? topside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13-7 180-pin bga six-layer board routing example (four routing layers) ? component side . . . . . . . . . . . . . . . . 13-8 13-8 180-pin bga six-layer board routing example (four routing layers) ? first inside layer . . . . . . . . . . . . . . . . 13-8 13-9 180-pin bga six-layer board routing example (four routing layers) ? second inside layer . . . . . . . . . . . . . 13-8 13-10 180-pin bga six-layer board routing example (four routing layers) ? solder side. . . . . . . . . . . . . . . . . . . . 13-8
pci 9030 data book version 1.4 x ? 2002 plx technology, inc. all rights reserved.
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. xi tables 1-1 fifo depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-2 pci 9030, pci 9050, and pci 9052 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2-1 pci target command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 pci bus little endian byte lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-3 ready# data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-4 mode pin-to-bus mode cross-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-5 local address space bus region descriptor internal wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-6 burst and bterm on the local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-7 burst-4 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-8 pci target single and burst reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2-9 byte number and lane cross-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-10 lword lane transfer ? 32-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-11 upper word lane transfer ? 16-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-12 lower word lane transfer ? 16-bit local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-13 upper byte lane transfer ? 8-bit local bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-14 lower byte lane transfer ? 8-bit local bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 3-1 serial eeprom guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 serial eeprom register load sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-3 new capabilities function support features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 4-1 response to fifo full or empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 5-1 chip select base address register signal programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 8-1 hot swap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 10-1 new registers definitions summary (as compared to the pci 9050 and pci 9052) . . . . . . . . . . . . . . . . . . . . . . 10-1 10-2 pci configuration register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10-3 local configuration register address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-4 chip select register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-5 control register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11-1 pin type abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-2 input pin pull-up and pull-down resistor requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-3 output pin pull-up and pull-down resistor requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11-4 i/o pin pull-up and pull-down resistor requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11-5 power and ground pins (176-pin pqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-6 power, ground, and no connect pins (180-pin bga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-7 serial eeprom interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-8 test and debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11-9 pci system bus interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-10 local bus mode independent interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-11 multiplexed bus mode interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-12 non-multiplexed bus mode interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-13 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 12-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-3 capacitance (sample tested only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-4 package thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-5 electrical characteristics over operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-6 ac electrical characteristics (local inputs) over operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
tables pci 9030 data book version 1.4 xii ? 2002 plx technology, inc. all rights reserved. 12-7 ac electrical characteristics (local outputs) over operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 13-1 176-pin pqfp package mechanical dimensions (legend for figure 13-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2 symbol definitions ? pqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-3 180-pin bga package mechanical dimensions (legend for figure 13-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13-4 symbol definitions ? bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13-5 180-pin bga six-layer board routing example (four routing layers) ? sample parameters . . . . . . . . . . . . . . 13-7 a-1 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. xiii registers 10-1 (pciidr; pci:00h) pci configuration id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-2 (pcicr; pci:04h) pci command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-3 (pcisr; pci:06h) pci status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-4 (pcirev; pci:08h) pci revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-5 (pciccr; pci:09-0bh) pci class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-6 (pciclsr; pci:0ch) pci cache line size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-7 (pciltr; pci:0dh) pci bus latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-8 (pcihtr; pci:0eh) pci header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-9 (pcibistr; pci:0fh) pci built-in self test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-10 (pcibar0; pci:10h) pci base address 0 for memory accesses to local configuration registers . . . . . . . . . . . 10-7 10-11 (pcibar1; pci:14h) pci base address 1 for i/o accesses to local configuration registers . . . . . . . . . . . . . . . 10-7 10-12 (pcibar2; pci:18h) pci base address 2 for accesses to local address space 0 . . . . . . . . . . . . . . . . . . . . . . . 10-8 10-13 (pcibar3; pci:1ch) pci base address 3 for accesses to local address space 1. . . . . . . . . . . . . . . . . . . . . . . 10-8 10-14 (pcibar4; pci:20h) pci base address 4 for accesses to local address space 2 . . . . . . . . . . . . . . . . . . . . . . . 10-9 10-15 (pcibar5; pci:24h) pci base address 5 for accesses to local address space 3 . . . . . . . . . . . . . . . . . . . . . . 10-9 10-16 (pcicis; pci:28h) pci cardbus information structure pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-17 (pcisvid; pci:2ch) pci subsystem vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-18 (pcisid; pci:2eh) pci subsystem id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-19 (pcierbar; pci:30h) pci expansion rom base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-20 (cap_ptr; pci:34h) new capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-21 (pciilr; pci:3ch) pci interrupt line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-22 (pciipr; pci:3dh) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-23 (pcimgr; pci:3eh) pci minimum grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-24 (pcimlr; pci:3fh) pci maximum latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-25 (pmcapid; pci:40h) power management capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-26 (pmnext; pci:41h) power management next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-27 (pmc; pci:42h) power management capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-28 (pmcsr; pci:44h) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-29 (pmcsr_bse; pci:46h) pmcsr bridge support extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-30 (pmdata; pci:47h) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-31 (hs_cntl; pci:48h) hot swap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-32 (hs_next; pci:49h) hot swap next capability pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-33 (hs_csr; pci:4ah) hot swap control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-34 (pvpdcntl; pci:4ch) pci vital product data control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-35 (pvpd_next; pci:4dh) pci vital product data next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-36 (pvpdad; pci:4eh) pci vital product data address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-37 (pvpdata; pci:50h) pci vpd data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-38 (las0rr; 00h) local address space 0 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-39 (las1rr; 04h) local address space 1 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-40 (las2rr; 08h) local address space 2 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10-41 (las3rr; 0ch) local address space 3 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10-42 (eromrr; 10h) expansion rom range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
registers pci 9030 data book version 1.4 xiv ? 2002 plx technology, inc. all rights reserved. 10-43 (las0ba; 14h) local address space 0 local base address (remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10-44 (las1ba; 18h) local address space 1 local base address (remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10-45 (las2ba; 1ch) local address space 2 local base address (remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-46 (las3ba; 20h) local address space 3 local base address (remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-47 (eromba; 24h) expansion rom local base address (remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-48 (las0brd; 28h) local address space 0 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10-49 (las1brd; 2ch) local address space 1 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10-50 (las2brd; 30h) local address space 2 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10-51 (las3brd; 34h) local address space 3 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10-52 (erombrd; 38h) expansion rom bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10-53 (cs0base; 3ch) chip select 0 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10-54 (cs1base; 40h) chip select 1 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10-55 (cs2base; 44h) chip select 2 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10-56 (cs3base; 48h) chip select 3 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10-57 (intcsr; 4ch) interrupt control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10-58 (prot_area; 4eh) serial eeprom write-protected address boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10-59 (cntrl; 50h) pci target response, serial eeprom, and initialization control . . . . . . . . . . . . . . . . . . . . . . 10-34 10-60 (gpioc; 54h) general purpose i/o control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36 10-61 (pmdatasel; 70h) hidden 1 power management data select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10-62 (pmdatascale; 74h) hidden 2 power management data scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. xv timing diagrams 2-1 local bus arbitration from the pci 9030 by another local bus initiator (lreq and lgnt). . . . . . . . . . . . . . . . . . . . 2-6 3-1 initialization from serial eeprom (2k or 4k bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-2 pci configuration write to pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-3 pci configuration read from pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-4 pci memory write to local configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-5 pci memory read from local configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 4-1 local bus arbitration from the pci 9030 by another local bus initiator (lreq and lgnt). . . . . . . . . . . . . . . . . . . . 4-9 4-2 local level-triggered interrupt asserting pci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-3 local edge-triggered interrupt asserting pci interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-4 gpio[8:0] as outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-5 chip select [3:0]# (32-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-6 initialization from serial eeprom (2k or 4k bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4-7 pci configuration write to pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-8 pci configuration read from pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-9 pci memory write to local configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-10 pci memory read from local configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-11 pci target burst write with delayed write and chip select enabled (32-bit local bus) . . . . . . . . . . . . . . . . . . . . 4-16 4-12 pci target burst write (32-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4-13 pci target burst write (16-bit local bus), no wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4-14 pci target burst write (16-bit local bus), one data-to-data wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-15 pci target burst writes (8-bit local bus), one data-to-data wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-16 pci target single writes (16-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4-17 pci target burst write (8-bit local bus), no wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4-18 pci target back-to-back single writes (32-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4-19 pci target back-to-back burst write followed by read (16-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4-20 pci target back-to-back burst read followed by write (16-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4-21 pci target back-to-back burst reads (16-bit local bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4-22 pci target single write (32-bit local bus), multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 4-23 pci target single read (32-bit local bus), multiplexed mode only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4-24 pci target burst write with bterm enabled (32-bit local bus), multiplexed mode only . . . . . . . . . . . . . . . . . . . . 4-29 4-25 pci target burst read with prefetch enabled (32-bit local bus), prefetch counter set to 8, multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4-26 pci target non-burst write (8-bit local bus), multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4-27 pci target single write (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4-28 pci target single read (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 4-29 pci target single read with one wait state using ready# input (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4-30 pci target single read with one wait state using internal wait state (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 4-31 pci target non-burst write (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4-32 pci target non-burst read, non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 4-33 pci target burst write with bterm enabled (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . 4-3 8 4-34 pci target burst write with bterm disabled (32-bit local bus), non-multiplexed mode only . . . . . . . . . . . . . . . . 4-3 9
timing diagrams pci 9030 data book version 1.4 xvi ? 2002 plx technology, inc. all rights reserved. 4-35 pci target burst read with prefetch counter set to 8 (32-bit local bus), non-multiplexed mode only . . . . . . . . 4-40 4-36 pci target burst write (32-bit local bus), non-multiplexed mode only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4-37 pci r2.2 features enable, non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4-38 pci target read no flush mode (read ahead mode), prefetch enabled, prefetch count disabled, burst enabled, non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 3 4-39 locked pci target read followed by write and release (llocko#), non-multiplexed mode only . . . . . . . . . . . 4-44 4-40 pci target write to local target in bigend mode, non-multiplexed mode only . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 5-1 chip select [3:0]# (32-bit local bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-2 pci target burst write with delayed write and chip select enabled (32-bit local bus) . . . . . . . . . . . . . . . . . . . . . . 5-4 6-1 local level-triggered interrupt asserting pci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-2 local edge-triggered interrupt asserting pci interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-3 gpio[8:0] as outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. xvii preface the information contained in this document is subject to change without notice. although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein. supplemental documentation the following is a list of additional documentation to provide the reader with further information regarding the pci 9030 and related subjects: pci local bus specification, revision 2.1 , june 1, 1995 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com pci local bus specification, revision 2.2 , december 18, 1998 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com pci hot-plug specification, revision 1.1 , june 20, 2001 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com pci bus power management interface specification , revision 1.1 , december 18, 1998 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 291-2569, fax: 503 297-1090, http://www.pcisig.com picmg 2.1, r2.0, compactpci hot swap specification , january 17, 2001 pci industrial computer manufacturers group (picmg) c/o virtual inc., 401 edgewater place, suite 500, wakefield, ma 01880, usa tel: 781 246-9318, fax: 781 224-1239, http://www.picmg.org ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture , 1990 the institute of electrical and electronics engineers, inc. 445 hoes lane, po box 1331, piscataway, nj 08855-1331, usa tel: 800 678-4333 (domestic) or 732 981-0060, fax: 732 981-1721, http://www.ieee.org note: in this data book, shortened titles are given to the works listed above. the following table lists these abbreviations. supplemental documentation abbreviations abbreviation document pci r2.1 pci local bus specification, revision 2.1 pci r2.2 pci local bus specification, revision 2.2 hot-plug r1.1 pci hot-plug specification, revision 1.1 pci power mgmt. r1.1 pci bus power management interface specification , revision 1.1 picmg 2.1, r2.0 picmg 2.1, r2.0, compactpci hot swap specification ieee standard 1149.1-1990 ieee standard test access port and boundary-scan architecture
preface pci 9030 data book version 1.4 xviii ? 2002 plx technology, inc. all rights reserved. terms and definitions pci target (direct slave) external pci bus initiator initiates data write/read to/from the local bus revision history data assignment conventions data width pci 9030 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) lword date version comment 3/1999 0.90 new release pci 9030 preliminary data book, version 0.9. 8/1999 0.90 update. 10/1999 0.90 initial release red book. 10/1999 0.91 update. 11/1999 0.92 update. 12/1999 0.93 initial release blue book. 4/2000 1.0 production release. 1/31/2001 1.1 incorporated 1/31/2001 addendum changes, including past design notes. 12/2001 1.2 released version 1.2. updated hot-plug support from revision 1.0 to revision 1.1. updated picmg 2.1 hot swap support from revision 1.0 to revision 2.0. corrected table 2-1 for pci command code response. renamed section 2.2.2 from ? local signals ? to ? local bus signals used in timing diagrams. ? revised section 2.2.4.2.1 local bus wait state content and added figures 2-1 and 2-2 to illustrate wait state definitions. revised sections 2.2.4.3.1 through 2.2.4.3.2.1 to clarify local bus bursting, bterm mode, and bterm# input. corrected lint[1:2] polarity in timing diagram 4-8. updated section 10 pcibar x , eromrr, las x rr, erombrd, and las x brd register bit descriptions. replaced the pmdatasel register description (missing in version 1.1). corrected las x brd[25] descriptions for big endian byte lane mode to indicate this bit is functional only in big endian mode. updated the pmc register description to match pci power mgmt. r1.0. (refer to pci 9030 design notes #1 for a revised pmc register description compliant with pci power mgmt. r1.1 ). added pull-down recommendation to trst# pin description and changed ready# wait state generator- related information in section 11. documented additional reset behavior in section 11.1. updated ale timing illustration, figure 12-3. figure 13-2 modified to remove non-metric measurements. replaced figure 13-6, ? 180-pin bga package layout ? underside view ? and table 13-3, ? 180-pin bga pci 9030 pinout ? with new figure 13-6, ? 180-pin bga physical layout with pinout. ? updated package mechanical drawings for changed marking content, which affects inspection, pattern recognition, and tray and board loading equipment. 01/2002 1.3 revised and clarified figures 13-4 and 13-6. updated section 10 erombrd[19:15] and las x brd[19:15] register bit descriptions, and associated text that appears elsewhere in the data book, to include ld signal. corrected section 10 erombrd[5] and las x brd[5] register bit descriptions regarding ? when set to 0 ? . 05/2002 1.4 corrected fiducial locations and pad pitch measurement in figure 13-2. only affected pages list the revision and date change.
pci smartarget i/o accelerator may 2002 compactpci hot swap ready version 1.4 for adapters and embedded systems pci 9030 pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. xix feature summary feature summary pci local bus specification r2.2 -compliant 32-bit, 33 mhz bus target interface device enabling pci burst transfers up to 132 mb/s pci bus power management interface specification r1.1 compliant pci local bus specification r2.2 vital product data (vpd) configuration support picmg 2.1, r2.0, compactpci hot swap specification , hot swap silicon programming interface 0 (pi = 0) precharge bias voltage support early power support pci target programmable burst management pci target read ahead mode pci target delayed read mode pci target delayed write mode programmable interrupt generator/controller two programmable fifos for zero wait state burst operation flexible local bus runs up to 60 mhz 3.3/5v tolerant pci and local signaling supports universal pci adapter designs flexible local bus provides 32-bit multiplexed or non-multiplexed protocol for 8-, 16-, or 32-bit peripheral and memory devices serial eeprom interface nine programmable general purpose i/o (gpios) five programmable local address spaces four programmable independent chip selects programmable local bus wait states programmable local read prefetch mechanism local bus can run asynchronously to the pci bus two programmable local-to-pci interrupts endian byte swapping 3.3v core, low-power cmos in 176-pin pqfp or 180-pin bga industrial temp range operation pci 9030 internal block diagram 32-bit, 33 mhz pci bus 32-bit, 60 mhz local bus endian control logic local bus control logic multiplexed/ non-multiplexed control logic local bus interface control logic pci bus control logic hot swap control logic pci bus interface control logic read fifo write fifo fifo control logic local configuration register pci configuration register serial eeprom controller dynamic data bus width control logic

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 1-1 1?introduction 1 introduction 1.1 company and product background plx technology, inc., is the leading supplier of high-speed, interconnect silicon and software solutions for the networking and communications industry. these include high-speed silicon, reference design tools that minimize design risk, and software for managing data throughout the pci bus, as well as third-party development tool support through the plx partner program, further extending our complete solution. the plx solution enables hardware designers and software developers to maximize system input/output (i/o), lower development costs, minimize system design risk, and accelerate time to market. plx pci i/o accelerator chips and i/o processor devices are designed in a wide variety of embedded pci communication systems, including switches, routers, media gateways, base stations, access multiplexors, and remote access concentrators. plx customers include many of the leading communications equipment companies?3com, cisco systems, compaq computer, ericsson, hewlett- packard, intel, ibm, lucent technologies, marconi, nortel networks, and siemens. founded in 1986, plx has developed products based on the pci industry standard since 1994. plx is publicly traded (nasdaq: plxt) and headquartered in sunnyvale, california, usa, with operations in the united kingdom, japan, and china. 1.1.1 pci 9030 smartarget i/o accelerator the pci 9030, a 32-bit, 33-mhz pci bus target interface chip with smartarget? technology, is the most advanced general-purpose pci target device available. it offers complete pci r2.2 implementation, enabling burst transfers up to 132 mb/s, and is the industry?s first compactpci hot swap picmg 2.1, r1.0 -compatible ready target device. the pci 9030 is the perfect solution for migrating legacy designs to pci while adding new features that enhance next generation target designs. the pci 9030 smartarget i/o accelerator brings plx?s industry- leading experience in the pci design world to the customer in a way that is simple and convenient to use. 1.1.2 smartarget technology many pci chip and core designs implement only basic pci r2.2 bus interface signaling, leaving the difficult performance and compatibility issues to the designer. the pci 9030, with smartarget technology, incorporates features which simplify design implementation. these features go far beyond the minimum to provide the highest possible design performance and flexibility. smartarget technology performance features: pci r2.2 compliant, 32-bit, 33 mhz target interface, enabling pci burst transfers up to 132 mb/s up to 60 mhz local bus operation, enabling burst transfers up to 240 mb/s pci target read ahead mode pci target programmable burst pci target delayed write mode posted memory writes smartarget technology flexibility features: programmable 32-bit local bus operates up to 60 mhz supports five pci-to-local address spaces nine programmable general purpose i/os (gpios) four programmable chip selects picmg 2.1, r2.0 , hot swap silicon, including support for programming interface 0 (pi = 0) precharge bias voltage early power big/little endian byte conversion interrupt generator/controller pci r2.2 vital product data (vpd) ? pci power mgmt. r1.1 3.3/5v tolerant pci signaling 3.3v cmos device in 176-pqfp or 180-pin bga programmable read and write strobe timing on the local bus
section 1 introduction company and product background pci 9030 data book version 1.4 1-2 ? 2002 plx technology, inc. all rights reserved. 1.1.3 pci 9030 applications the pci 9030 can be used in a wide variety of networking, telecom, imaging, industrial and storage applications. the pci 9030 simplifies legacy design migration to pci by providing a convenient off-the-shelf solution that enables prototypes to be operational in a short time period. 1.1.3.1 high-performance pci target interface the pci 9030 ? s built-in smartarget performance features ( such as 3.3/5v tolerant i/o buffers and local bus operation up to 60 mhz), enable designers to connect a wide variety of memory and i/o devices. with smartarget in action, pci target adapter designs have never been simpler to implement. figure 1-1 illustrates a typical pci target adapter card. figure 1-1. typical pci target adapter card 1.1.3.2 high-performance compactpci adapter card the pci 9030 has integrated key features to enable live insertion of hot swap compactpci adapters. the pci 9030 hot swap silicon includes the following features: compliant with pci r2.2 tolerant of v cc from early power, including support for pin bounce, i/o cell stability within 4 ms, and low current drain during insertion tolerant of asynchronous reset tolerant of precharge bias voltage i/o buffers meet modified v/i requirements in picmg 2.1, r2.0 limited i/o pin leakage at precharge bias voltage incorporates the hot swap control/status register (hs_csr) incorporates an extended capability pointer (ecp) to the hot swap control/status register incorporates added resources for software control of the ejector switch, enum#, and the blue ? status ? led which indicates insertion and removal to the user precharge bias voltage support with integrated 10k-ohm precharge resistors eliminates the need for an external resistor network early power support allows transition between the operating and powered down states without external circuitry programming interface 0 (pi = 0) figure 1-2 illustrates a typical compactpci adapter card. figure 1-2. high-performance compactpci adapter card 1.1.3.3 pmc adapter cards in the real estate-conscious world of pmc cards, the pci 9030 offers an attractive packaging option with the dime-size 180-pin bga. smartarget flexibility features, such as gpios and programmable chip selects, save additional valuable board space. the pci 9030 enables a new generation of mini form factor pci cards. 32-bit 60 mhz local bus 32-bit 33 mhz system pci bus memory pci 9030 smartarget device i/o i/o i/o i/o ? 32-bit 60 mhz local bus i/o memory 32-bit 33 mhz compactpci bus i/o pci 9030 smartarget device ? enum# led
section 1 company and product background introduction pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 1-3 1 ? introduction figure 1-3 illustrates a typical pmc adapter card. figure 1-3. typical pmc adapter card 1.1.4 pci 9030 smartarget features 1.1.4.1 performance features pci r2.2 compliant. this 32-bit, 33 mhz target interface chip enables pci burst transfers up to 132 mb/s. up to 60 mhz local bus operation. enables burst transfers up to 240 mb/s. pci target read ahead mode. prefetches a programmable amount of data from the local bus. this data can then be burst-transferred onto the pci bus from the pci 9030 internal pci target read fifo. the prefetch size can be programmed to match the pci master burst length or can be used in the pci target read ahead mode data. this feature also allows for increased bandwidth and reduced read latency. pci target programmable burst . the pci 9030 may be programmed for several burst lengths, including unlimited burst. this allows for maximum transfer rates on both the pci and local buses. pci target delayed write mode. the pci target write data accumulates in the pci target write fifo to allow uninterrupted burst transactions on the local bus. this allows for a higher throughput for conditions in which the pci clock frequency is slower than the local clock frequency. posted memory writes. a pci memory write is posted to the pci 9030 for later transfer to the local bus. this allows for maximum pci performance and avoids potential deadlock situations. 1.1.4.2 flexibility features programmable local bus. operates up to 60 mhz and supports both multiplexed and non-multiplexed 32-bit address/data protocol, and dynamic local bus width control allowing slave accesses to 8-, 16- or 32-bit devices. pci-to-local address spaces . supports five pci-to- local address spaces. spaces 0, 1, 2, 3, and the expansion rom all allow a pci bus master to access the local memory spaces with individually programmable wait states, bus width, and burst capabilities. gpios. the pci 9030 has nine programmable general purpose i/o pins, which may be used for generic interface purposes. four programmable chip selects. eliminates decode logic, which improves performance. picmg 2.1, r2.0 hot swap silicon. compliant with picmg 2.1, r2.0 , including support for programming interface 0 (pi = 0), precharge bias voltage, and early power. big/little endian conversion. supports automatic on-the-fly big endian and little endian conversion for all operations and bus widths. interrupt generator/controller. can assert pci interrupts from external and internal sources. vpd support. fully supports the pci r2.2 vital product data (vpd) extension, including the new capabilities structure. provides an alternate access method for user- or system-defined parameters or configuration data. pci power management. supports d 0 and d 3hot power states. two programmable fifos for zero wait state burst operation. the following table describes the fifo depth. 3.3/5v tolerant pci signaling. enables universal pci adapters. 3.3v cmos device in 176-pin pqfp or 180-pin bga. 32-bit 60 mhz local bus 32-bit 33 mhz pci bus i/o memory pci 9030 smartarget device ( bga) ? table 1-1. fifo depth fifo depth pci target read 16 lwords pci target write 32 lwords
section 1 introduction company and product background pci 9030 data book version 1.4 1-4 ? 2002 plx technology, inc. all rights reserved. 1.1.4.3 additional features 5v tolerant operation. the pci 9030 requires a 3.3v supply. it provides 3.3v signaling with 5v i/o tolerance on both the pci and local buses. serial eeprom interface. the pci 9030 contains a three-wire serial eeprom interface that provides the option of loading configuration information from a serial eeprom device. clocks. the local bus interface runs from a local bus clock, which runs asynchronously to the pci clock. in addition, the pci 9030 provides a buffered pci clock output, which can be used as a local bus clock input. rst# timing. supports response to first configuration accesses after de-assertion of pci rst# in less than 2 25 clocks. subsystem and subsystem vendor ids. contains subsystem id and subsystem vendor id in the pci configuration register space, in addition to device and vendor ids. silicon revision id. contains the pci 9030 silicon revision id, which is programmable by way of the serial eeprom. 1.1.5 plx chip compatibility 1.1.5.1 pin compatibility the pci 9030 is not pin compatible with the pci 9050, pci 9052, pci 9054, nor the pci 9080. 1.1.5.2 register compatibility all registers implemented in the pci 9050 and 9052 are implemented in the pci 9030. the pci 9030 includes many new bit definitions and several new registers. refer to table 1-2 for details. the pci 9030 is not register-compatible with the pci 9080 nor the pci 9054.
section 1 company and product background introduction pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 1-5 1 ? introduction 1.1.6 pci 9030 comparison with other plx chips table 1-2. pci 9030, pci 9050, and pci 9052 comparison feature pci 9030 pci 9050 pci 9052 pin count and type 176 pqfp/180 bga 160 pqfp 160 pqfp package size 27 x 27 mm 31 x 31 mm 31 x 31 mm local address spaces 555 pci initiator mode no no no number of fifos 222 fifo depth ? pci target write 32 lwords (128 bytes) 16 lwords (64 bytes) 16 lwords (64 bytes) fifo depth ? pci target read 16 lwords (64 bytes) 8 lwords (32 bytes) 8 lwords (32 bytes) llocko# pin for lock cycles yes yes yes waito# pin for wait state generation yes yes yes bclko (bclko) pin; buffered pci clock yes yes yes isa bus interface no no yes register addresses identical to the pci 9050 and pci 9052, but contains additional registers for increased functionality ?? big endian ! little endian conversion yes yes yes pci target delayed read transactions yes yes yes pci target delayed write transactions yes no no pci bus power management interface r1.1 yes no no pci r2.2 vpd support yes no no programmable prefetch counter yes yes yes programmable wait states yes yes yes programmable local bus ready# timeout yes no no programmable gpios 944 additional device and vendor id registers yes yes yes core and local bus v cc 3.3v 5v 5v pci bus v cc 3.3v 5v 5v 3.3v pci bus and local bus signaling yes no no 5v tolerant pci bus and local bus signaling yes yes yes serial eeprom support 2k, 4k bit devices 1k bit devices 1k bit devices serial eeprom read control reads allowed via vpd function (refer to section 9) and serial eeprom control register (cntrl) reads allowed via serial eeprom control register (cntrl) reads allowed via serial eeprom control register (cntrl) pci target read ahead mode yes yes yes compactpci hot swap capability ready capable capable

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-1 2 ? pci & local bus 2 pci and local bus this section discusses pci and local bus operation. 2.1 pci bus 2.1.1 pci bus interface and bus cycles the pci 9030 is pci r2.2 -compliant. refer to pci r2.2 for specific pci bus functions as a pci target interface chip. 2.1.1.1 pci target command codes as a target, the pci 9030 allows access to the pci 9030 internal registers and the local bus, using the commands listed in table 2-1. all read or write accesses to the pci 9030 can be byte, word, or lword (32-bit data). all memory commands are aliased to basic memory commands. all pci 9030 i/o accesses are decoded to an lword boundary. byte enables are used to determine which bytes are read or written. an i/o access with illegal byte enable combinations is terminated with a target abort. 2.1.1.2 wait states ? pci bus the pci bus master throttles irdy# and the pci bus slave throttles trdy# to assert pci bus wait state(s). 2.1.1.3 pci bus little endian mode the pci bus is a little endian bus ( that is , the address is invariant and data is lword-aligned to the lowermost byte lane). 2.1.1.4 pci prefetchable memory mapping pci memory address spaces assigned to the pci 9030 for its local address spaces can be mapped as either prefetchable or non-prefetchable memory within the system. configuration software (pci bios) checks the pci 9030 configuration register prefetchable bit(s) (pcibar x [3], where x is the pci base address register number) to determine whether the target memory is prefetchable. the value of the pcibar x [3] bit(s) is set according to local configuration register settings (as configured by serial eeprom values) at boot time. when set to 1, the pcibar x [3] bit(s) signals that the memory space can operate under a prefetching protocol, for improved performance. if a pci master initiates a read to a location that is mapped in the prefetchable address range, a host-to-pci or pci-to-pci bridge is permitted to extend the read transaction burst length in anticipation of the master consuming the additional data. pcibar x [3] should normally be set if all the following conditions are met: multiple memory reads of an lword result in the same data if read data is discarded by the pci master, no negative side effects occur address space is not mapped as i/o local target must be able to operate with byte merging table 2-1. pci target command codes command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) memory read 0110 (6h) memory write 0111 (7h) configuration read 1010 (ah) configuration write 1011 (bh) memory read multiple 1100 (ch) memory read line 1110 (eh) memory write and invalidate 1111 (fh) table 2-2. pci bus little endian byte lanes byte number byte lane 0 ad[7:0] 1 ad[15:8] 2 ad[23:16] 3 ad[31:24]
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-2 ? 2002 plx technology, inc. all rights reserved. byte merging is an optional function of a host-to-pci or pci-to-pci bridge in which bytes or combinations of bytes written in any order by multiple individual memory write cycles to one lword address can be merged within the bridge ? s posted memory write buffer into a single lword write cycle. byte merging is possible when any of the bytes to be merged are written only once, and the prefetchable bit(s) is set to 1 (pcibar x [3]=1). the prefetchable bit(s) setting has no effect on prefetching initiated by the pci 9030. pci 9030 prefetching is disabled, by default, in the local configuration registers, and should be enabled to support highest performance with pci target burst reads and pci target read ahead mode. (refer to section 4.2.1.4.) 2.1.1.5 pci target accesses to an 8-or 16-bit local bus device direct pci access to an 8- or 16-bit local bus device results in the pci bus lword being broken into multiple local bus transfers. for each 8-bit transfer, byte enables are encoded to provide local address bits la[1:0]. for each 16-bit transfer, byte enables are encoded to provide ble#, bhe#, and la1. 2.2 local bus 2.2.1 introduction the local bus provides a data path between the pci bus and non-pci devices, including memory devices and peripherals. the local bus is a 32-bit multiplexed or non-multiplexed bus, with bus memory regions that can be programmed for 8-, 16-, or 32-bit widths. the pci 9030 local bus is signal-compatible with popular risc and bridge architecture, including the i960cx, i960jx, and ppc401 gf. in addition, the local bus can directly connect to texas instruments dsp devices ( such as the tms320c6202 and tms320c54x). the pci 9030 is the local bus master. the pci 9030 can transfer data between the local bus, internal registers and fifos. burst lengths are not limited. the bus width depends upon the local address space register setting. there are four address spaces and one default space (the expansion rom that can be used as another address space). each space contains a set of configuration registers that determine all local bus characteristics when that space is accessed. figure 2-1. local bus block diagram pci target fifos local address/ data bus local master controller local arbiter configuration registers local control feature control address/data data local/data control la[27:2] lad/ld[31:0] from pci to pci config data_inbound config data_outbound data to pci address/data from pci from pci pci control
section 2 local bus pci and local bus pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-3 2 ? pci & local bus 2.2.1.1 transactions four types of transactions can occur on a local bus: read write read burst write burst a bus access is a transaction which is bounded by the assertion of ads# at the beginning and de-assertion of blast# at the end. a bus access consists of an address cycle followed by one or more data transfers. during each clock cycle of an access, the local bus is in one of four basic states defined in section 2.2.1.2. a clock cycle consists of one local bus clock period. 2.2.1.2 basic bus states the four basic bus states are idle, address, data/wait, and recovery. once the local bus master owns the bus and needs to start a bus access, the address state is entered, ads# or ale is asserted, and a valid address is presented on the address/data bus. data is then transferred while in a data/wait state. ready# or the internal wait state generator is used to insert wait states. blast# is asserted during the last data/wait state to signify the last transfer of the access. after all data is transferred, the bus enters the recovery state to allow the bus devices to recover. the bus then enters the idle state and waits for another access. 2.2.2 local bus signals used in timing diagrams the key local bus control signals listed in most timing diagram examples are as follows: ads# or ale indicates the start of an access ready#, waito#, and bterm# are used to insert wait states and terminate burst cycles during data transfers lw/r# indicates the data transfer direction blast# and bterm# indicate the end of an access the key data signals are: la address bus lad address, data bus lbe[3:0]# local byte enables, indicating valid byte lanes 2.2.3 local bus signals there are four groups of local bus signals: clock address/data control/status arbitration signal usage varies upon application. 2.2.3.1 clock lclk, the local bus clock, operates at frequencies up to 60 mhz, and is asynchronous to the pci bus clock. most local bus signals are driven and sampled on the rising edge of lclk. setup and hold times, with respect to lclk, must be observed. (refer to section 12.2, ? local inputs, ? on page 12-3 for setup and hold timing requirements.) 2.2.3.2 address/data 2.2.3.2.1 multiplexed mode (mode=1) 2.2.3.2.1.1 la[27:2] la[27:2] contains the transfer address. the address remains valid during the transfer, and increments with successive data during burst cycles. 2.2.3.2.1.2 lad[31:0] the lad[31:0] bus is a 32-bit multiplexed address/ data bus. during an address phase, lad[27:0] contains the transfer address, with lad[1:0] having the same state as lbe[1:0]# pins. during data phases, lad[31:0], lad[15:0], or lad[7:0] contain transfer data for a 32-, 16-, or 8-bit bus, respectively. if the bus is 8 or 16 bits wide, the data supplied by the pci 9030 is replicated across the entire 32-bit-wide bus.
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-4 ? 2002 plx technology, inc. all rights reserved. 2.2.3.2.2 non-multiplexed mode (mode=0) 2.2.3.2.2.1 la[27:2] la[27:2] contains the transfer address. the address remains valid during the transfer, and increments with successive data during burst cycles. 2.2.3.2.2.2 ld[31:0] the ld[31:0] bus is a 32-bit non-multiplexed data bus. during data phases, ld[31:0], ld[15:0], or ld[7:0] contain transfer data for a 32-, 16-, or 8-bit bus, respectively. if the bus is 8 or 16 bits wide, the data supplied by the pci 9030 is replicated across the entire 32-bit-wide bus. 2.2.3.3 control/status the control/status signals control the address latches and flow of data across the local bus. 2.2.3.3.1 ads#, ale a local bus access starts when ads# (address strobe) is asserted during an address state by the pci 9030 as the local bus master. ale is used to strobe the la/lad bus into an external address latch. when bterm# input is enabled for a local address space in the corresponding bus region descriptor register, bterm# can be used to complete an access in place of lrdyi#. when bterm# is enabled and asserted, lrdyi# is ignored. (refer to figure 12-3 on page 12-5 for ale timing specifications, and to section 2.2.4.3 for further information regarding bterm#.) 2.2.3.3.2 lbe[3:0]# during an address phase, the lbe[3:0]# local byte enables denote which byte lanes are being used during access of a 32-bit bus. they remain asserted until the end of the data transfer. 2.2.3.3.3 llocko# when the pci 9030 owns the local bus, llocko# is asserted to indicate that an atomic operation for a pci target access may require multiple transactions to complete. llocko# is asserted during the address phase of the first transaction of the atomic operation, and de-asserted one clock after the last transaction of the atomic operation completes. if enabled, the local bus arbiter does not grant the bus to another master until the atomic operation completes. 2.2.3.3.4 lw/r# during an address phase, lw/r# is driven to a valid state, and signifies direction of the data transfer. since the pci 9030 is the local bus master, lw/r# is driven high when the pci 9030 is writing data to a local bus, and low when it is reading the bus. 2.2.3.3.5 rd# rd# is a general purpose read output strobe. the timing is controlled by the current bus region descriptor register. the rd# strobe is asserted during the entire data transfer. normally, rd# is also asserted during nrad wait states, unless read strobe delay clocks are programmed the bus region descriptor register(s) (las x brd[27:26] and/or erombrd[27:26], where x is the local address space number). (refer to table 2-5 and figure 2-3.) rd# remains asserted throughout burst and nrdd wait states.
section 2 local bus pci and local bus pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-5 2 ? pci & local bus 2.2.3.3.6 ready# the ready# input pin has a corresponding enable bit in the bus region descriptor register(s) (las x brd[1] and/or erombrd[1]). if ready# is enabled, this indicates that write data is being accepted or read data is being provided by the bus slave. if a bus slave needs to insert wait states, it can de-assert ready# until it is ready to accept or provide data. if ready# is disabled, then the local bus transfer length can be determined by internal wait state generators. (refer to table 2-3.) 2.2.3.3.7 waito# waito# is an output that provides status of the internal wait state generators. it is asserted while internal wait states are being inserted. ready# input is not sampled until waito# is de-asserted. 2.2.3.3.8 wr# wr# is a general purpose write output strobe. the timing is controlled by the current bus region descriptor register. the wr# strobe is asserted during the entire data transfer. wr# is normally asserted during address-to-data wait states (nwad), unless write strobe delay clocks are programmed in the bus region descriptor register(s) (las x brd[29:28] and/or erombrd[29:28]). wr# remains asserted throughout burst and data-to-data wait states (nwdd). the lad/ld data bus valid time can be extended beyond wr# de-assertion if write cycle hold clocks are programmed in the bus region descriptor register(s) (las x brd[31:30] and/or erombrd[31:30]). 2.2.3.4 local bus arbitration the pci 9030 is the local bus master. when the pci bus initiates a new transfer request, the pci 9030 takes local bus control. another device can gain local bus control by asserting lreq. if the pci 9030 has no cycles to run, it asserts lgnt, transferring control to the external master. if the pci 9030 requires the local bus for a pending pci target transaction before the external master completes, and the pci 9030 local bus arbiter is configured to give priority to pci target accesses over external master ownership of the local bus (cntrl[7]=0), the local bus arbiter de-asserts lgnt regardless of lreq pin state (default preempt condition). if instead, priority is given to the external master (cntrl[7]=1), the local bus arbiter continues to assert lgnt output until the local bus master releases the bus by de-asserting lreq. lreq can be pulled low or grounded to provide permanent local bus ownership to the pci 9030. 2.2.3.4.1 lgnt lgnt is asserted by the pci 9030 to grant local bus control to a local bus master. when the pci 9030 requires the local bus, it can signal a preempt by de-asserting lgnt, if configured to do so in the local arbiter lgnt signal select enable bit (cntrl[7]=0). 2.2.3.4.2 lreq lreq is asserted by a local bus master to request local bus use. the pci 9030 can be made master of the local bus by pulling lreq low (or by grounding lreq). table 2-3. ready# data transfers slave device ready# description input enable signal address spaces 0 ignored ready# is not sampled by the pci 9030. data transfers determined by the internal wait state generator. ready# is ignored and the data transfer takes place after the internal wait state counter expires. 1 sampled ready# is sampled by the pci 9030. data transfers are determined by an external device, which asserts ready# to indicate a data transfer is taking place.
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-6 ? 2002 plx technology, inc. all rights reserved. 2.2.3.4.3 arbitration timing diagram timing diagram 2-1. local bus arbitration from the pci 9030 by another local bus initiator (lreq and lgnt) 2.2.4 local bus interface and bus cycles the pci 9030 is the local bus master. the pci 9030 interfaces a pci host bus to a multiplexed or non-multiplexed local bus, selected by the mode[1:0] pins, as listed in table 2-4. notes: no pci initiator capability. internal registers are not readable/writable from the local bus. the internal registers are accessible from the host cpu on the pci bus or from the serial eeprom. 2.2.4.1 bus cycles in both non-multiplexed and multiplexed modes, the la[27:2] address bus drives an access address valid beginning one clock prior to ads# assertion (which signals the start of the bus cycle) and continues until the cycle ends (signaled by blast# de-assertion). in multiplexed mode (mode=1), the lad/ld[31:0] multiplexed address/data bus also drives the access address valid onto lad/ld[27:0], beginning one clock prior to ads# assertion and continuing until ads# de- assertion one clock later, after which data is driven. the lad/ld[31:0] data bus drives write data valid one clock after ads# assertion when ads# de-asserts, and continues until the cycle ends or until data-to-address wait states (or data-to-data wait states if burst is enabled) begin, if programmed. blast# assertion indicates the last data cycle of an access. (refer to figure 2-2 and figure 2-3.) write cycle data valid time and read cycle data time can be extended with internally generated address-to- data wait states and/or by delaying ready# ready input assertion if ready# input is enabled for the space. when enabled, ready# input assertion indicates to the pci 9030 that read data on the bus is valid to accept or a write data transfer has completed. ready# input is not sampled until address-to-data wait states (and/or data-to-data wait states with burst), which are signaled by waito# assertion, expire (waito# de-asserted). ready# is ignored during the address cycle (ads# assertion), internally generated data-to-address wait states, and idle cycles between transfers. bterm# input, if enabled, is used to break up a burst access and also serves as a ready input. (refer to section 2.2.4.3.) rd# and wr# strobes can be independently programmed for each local address space. rd# and/ or wr# strobe assertion can be optionally delayed during address-to-data wait states. write cycle hold clocks can be selectively programmed to extend data valid time and blast# assertion, beyond wr# strobe de-assertion. recovery (idle) cycles can be optionally programmed for each space, using data-to-address wait states (nxda) to extend time between local bus accesses to allow sufficient time for an external device to float its data pins after a read request. 1 another local initiator drives bus pci 9030 grants the local bus to another local initiator; otherwise, remains low. local bus is requested by another local initiator. de-asserted if pci 9030 needs to use a local bus and cntrl[7]=0; otherwise, remains high until the local initiator is done. 0ns 250ns 500ns lclk lreq lgnt local bus table 2-4. mode pin-to-bus mode cross-reference mode pin mode bus width 1 multiplexed 32-, 16, or 8-bit 0 non-multiplexed
section 2 local bus pci and local bus pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-7 2 ? pci & local bus figure 2-2. pci 9030 single cycle write note: nwdd is relevant only in a burst cycle, where it determines the wait state between successive data cycles. figure 2-3. pci 9030 single cycle read note: nrdd is relevant only in a burst cycle, where it determines the wait state between successive data cycles. write cycle hold, example=3 write strobe delay, example=1 nwad, example=2 nxda, example=2 addr data addr data data transferred 0ns 250ns 500ns lclk ads# blast# la[27:2] ld[31:0] waito# wr# lw/r# ready# addr data addr data 0ns 100ns 200ns 300ns 400ns lclk ads# blast# la[27:2] ld[31:0] waito# rd# lw/r# ready# nxda, example=2 read strobe delay, example=1 nrad, example=2 data transferred
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-8 ? 2002 plx technology, inc. all rights reserved. 2.2.4.2 wait state control the pci 9030 as a local bus master signals internal wait states with the waito# signal. local bus devices can insert external wait states by delaying ready# assertion. (refer to figure 2-2 and figure 2-3.) the following figure illustrates wait state control. figure 2-4. wait states note: the figure represents a sequence of bus cycles. 2.2.4.2.1 internal wait state generator the local address space bus region descriptor can be used to program the number of wait states (if any) generated by the internal wait state generator. (refer to table 2-5.) nxda wait states are inserted only after the last data transfer of a bus request. for example , for a pci target single cycle access to an 8-bit burst local bus, nxda wait states are inserted only after the fourth byte, rather than after every byte. 2.2.4.2.2 ready signaling if ready# mode is disabled, the external ready# input signal has no effect on wait states for a local access. wait states between data cycles are inserted internally by a wait state counter. the wait state counter is initialized with its configuration register value at the start of each data access. if ready# mode is enabled and the internal wait state counter is zero (default value), the ready# input controls the number of additional wait states. if ready# mode is enabled and the internal wait state counter is programmed to a non-zero value, ready# has no effect until the wait state counter reaches 0. when it reaches 0, the ready# input controls the number of additional wait states. bterm# input can also be used as a ready input. (refer to section 2.2.4.3.) if the internal wait state counter is programmed to a non-zero value and bterm# is enabled, bterm# input is not sampled until the wait state counter reaches 0. pci 9030 accessing pci 9030 from pci bus pci 9030 de-asserts trdy# when waiting on the local bus pci bus de-asserts irdy# for wait states or simply ends the cycle when it is not ready pci 9030 accessing local bus pci 9030 generates wait states with waito# (programmable) local bus can respond to pci 9030 requests with ready# pci bus local bus table 2-5. local address space bus region descriptor internal wait states wait state bits description nrad las x brd[10:6] erombrd[10:6] n umber of r ead a ddress-to- d ata wait states (0-31). (wait states between the address cycle and first read data cycle.) nrdd las x brd[12:11] erombrd[12:11] n umber of r ead d ata-to- d ata wait states (0-3). (wait states between consecutive data cycles of a burst read.) nxda las x brd[14:13] erombrd[14:13] n umber of r ead/ w rite d ata-to- a ddress wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) nwad las x brd[19:15] erombrd[19:15] n umber of w rite a ddress-to- d ata wait states (0-31). lad/ ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) nwdd las x brd[21:20] erombrd[21:20] n umber of w rite d ata-to- d ata wait states (0-3). (wait states between consecutive data cycles of a burst write.) note: x is the local address space number.
section 2 local bus pci and local bus pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-9 2 ? pci & local bus 2.2.4.3 burst mode and continuous burst mode (bterm ? burst terminate ? mode) note: in the following sections, bterm refers to the pci 9030 internal register bit and bterm# refers to the pci 9030 external signal. 2.2.4.3.1 burst and bterm modes as an input, bterm# is asserted by external logic. it instructs the pci 9030 to break up a burst cycle. on the local bus, blast# and bterm# perform the following: if local bus bursting is enabled for a local address space (las x brd[0]=1 and/or erombrd[0]=1), but bterm mode (continuous burst) and bterm# input are disabled (las x brd[2]=0 and/or erombrd[2]=0), the pci 9030 bursts up to four data phases or to the next 16-byte boundary, whichever occurs first. blast# is asserted at the beginning of the last data phase and a new ads# is asserted at the first lword-aligned address (la[3:2]=00) for the next burst. if bterm mode and bterm# input are enabled (las x brd[2]=1 and/or erombrd[2]=1) and asserted, the pci 9030 terminates the burst cycle at the end of the current data phase without generating blast#. the pci 9030 generates a new burst transfer, starting with a new ads#, and terminating it normally using blast#. bterm# input is valid only when the pci 9030 is performing a pci target transaction. bterm# is used to indicate a memory access is crossing a page boundary or requires a new address cycle. if the internal wait state counter is programmed to a non-zero value and bterm mode and the bterm# input are enabled (las x brd[2]=1 and/or erombrd[2]=1), bterm# input is not sampled until the wait state counter reaches 0. bterm# always overrides ready#, even if both signals are asserted. bterm# executes the ongoing transaction and causes the pci 9030 to initiate a new address/data cycle for burst transactions. note: if bterm mode (continuous burst) and bterm# input are disabled (lasxbrd[2]=0 and/or erombrd[2]=0), the pci 9030 performs the following: 32-bit local bus ? bursts up to four lwords 16-bit local bus ? bursts up to two lwords 8-bit local bus ? bursts up to one lword in every case, it performs four data beats. 2.2.4.3.2 burst-4 mode if bterm mode (continuous burst) and bterm# input are disabled, and local bus bursting is enabled for a local address space (lasxbrd[2, 0]=01 and/or erombrd[2, 0]=01, respectively), bursting can start on any lword boundary and continue up to a 16-byte address boundary. after data up to the boundary is transferred, the pci 9030 asserts a new address cycle (ads#). 2.2.4.3.3 continuous burst mode (bterm ? burst terminate ? mode) if bterm mode and bterm# input are enabled, and local bus bursting for a local address space is enabled (las x brd[2, 0]=11 and/or erombrd[2, 0] =11, respectively), the pci 9030 can operate beyond burst-4 mode. bterm mode enables the pci 9030 to perform long bursts to devices that can accept bursts of longer than four data. the pci 9030 asserts one address cycle and continues to burst data. if a device requires a new address cycle (ads#), it can assert bterm# input to cause the pci 9030 to assert a new address cycle. the bterm# input acknowledges the current data transfer (replacing ready#) and requests that a new address cycle be asserted (ads#). the new address is for the next data transfer. if bterm mode and table 2-6. burst and bterm on the local bus mode burst bterm result single cycle 00 one ads# per data (default) 01 one ads# per data burst-4 10 one ads# per four data continuous burst 11 one ads# per bterm# (refer to section 2.2.4.3.3) table 2-7. burst-4 mode bus width burst 32 bit four lwords or up to a quad lword boundary (la[3:2]=11) 16 bit four words or up to a quad word boundary (la[2:1]=11) 8 bit four bytes or up to a quad byte boundary (la[1:0]=11)
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-10 ? 2002 plx technology, inc. all rights reserved. the bterm# input are enabled (las x brd[2]=1 and/ or erombrd[2]=1) and the bterm# signal is asserted, the pci 9030 asserts blast# only if its read fifo is full, its write fifo is empty, or a transfer completes. 2.2.4.3.4 partial lword accesses partial lword accesses are lword accesses in which not all byte enables are asserted. pci target writes always pass the pci byte enables (c/be[3:0]#) to the local byte enables (lbe[3:0]#). pci target single reads always pass the byte enables. pci target burst reads ignore the byte enables and return all 32-bit data. (refer to table 2-8.) local bus burst start addresses can be any lword boundary. if the burst start address in a pci target transfer is not aligned to an lword boundary, the pci 9030 first performs a single cycle. it then starts to burst on the lword boundary. 2.2.4.4 recovery states in multiplexed mode, the pci 9030 inserts a minimum of one recovery state between the last data transfer and the next address cycle. add recovery states by programming values greater than 1 into the nxda bits of the bus region descriptor register(s) (las x brd[14:13] and/or erombrd[14:13]). in non-multiplexed mode, the pci 9030 uses the nxda (data-to-address wait states) value in the bus region descriptor register(s) (las x brd[14:13] and/or erombrd[14:13]) to determine the number of recovery states to insert between the last data transfer and next address cycle. this value can be programmed between 0 and 3 clock cycles (default value is 0). note: the pci 9030 does not support the i960j function that uses the ready# input to add recovery states. no additional recovery states are added if the ready# input remains asserted during the last data cycle. 2.2.4.5 local bus read accesses for all single cycle local bus read accesses, the pci 9030 reads only bytes corresponding to byte enables requested by a pci initiator. for all burst read cycles, the pci 9030 can be programmed to: perform pci target delayed reads perform pci target read ahead generate internal wait states enable external wait control (ready# input) enable type of burst mode to perform 2.2.4.6 local bus write accesses for local bus writes, only bytes specified by a pci bus master are written. for all burst write cycles, the pci 9030 can be programmed to: perform pci target delayed writes generate internal wait states enable external wait control (ready# input) 2.2.5 local bus big/little endian mode for each of the following transfer types, the pci 9030 local bus can be independently programmed to operate in little endian or big endian mode for pci target accesses to local address spaces 0, 1, 2, and 3, and expansion rom. notes: the pci bus is always little endian. only byte lanes are swapped, not individual bits. the pci 9030 local bus can be programmed to operate in big or little endian mode, as listed in table 2-9. big/little endian control bits are as follows: las0brd[24] ? space 0 las1brd[24] ? space 1 las2brd[24] ? space 2 las3brd[24] ? space 3 erombrd[24] ? expansion rom in big endian mode, the pci 9030 transposes data byte lanes. data is transferred as listed in table 2-10 through table 2-14. table 2-8. pci target single and burst reads bus pci target single reads pci target burst reads 32-, 16-, or 8-bit local bus passes the byte enables ignores the byte enables and all 32-bit data is passed
section 2 local bus pci and local bus pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 2-11 2 ? pci & local bus 2.2.5.1 32-bit local bus ? big endian mode data is lword aligned to the uppermost byte lane (address invariance). figure 2-5. big/little endian ? 32-bit local bus 2.2.5.2 16-bit local bus ? big endian mode for a 16-bit local bus, the pci 9030 can be programmed to use upper or lower word lanes. figure 2-6. big/little endian ? 16-bit local bus table 2-9. byte number and lane cross-reference byte number byte lane big endian little endian multiplexed mode non-multiplexed mode 3 0 lad[7:0] ld[7:0] 2 1 lad[15:8] ld[15:8] 1 2 lad[23:16] ld[23:16] 0 3 lad[31:24] ld[31:24] table 2-10. lword lane transfer ? 32-bit local bus burst order byte lane first transfer pci byte 0 appears on local data [31:24] pci byte 1 appears on local data [23:16] pci byte 2 appears on local data [15:8] pci byte 3 appears on local data [7:0] little endian big endian byte 3 byte 0 byte 2 byte 1 byte 1 byte 2 byte 0 byte 3 31 0 0 31 table 2-11. upper word lane transfer ? 16-bit local bus burst order byte lane first transfer byte 0 appears on local data [31:24] byte 1 appears on local data [23:16] second transfer byte 2 appears on local data [31:24] byte 3 appears on local data [23:16] table 2-12. lower word lane transfer ? 16-bit local bus burst order byte lane first transfer byte 0 appears on local data [15:8] byte 1 appears on local data [7:0] second transfer byte 2 appears on local data [15:8] byte 3 appears on local data [7:0] little endian big endian big endian byte 3 byte 2 byte 0 byte 1 byte 1 byte 0 byte 0 byte 1 31 0 first cycle second cycle 15 0 15 0 31 15 0 16
section 2 pci and local bus local bus pci 9030 data book version 1.4 2-12 ? 2002 plx technology, inc. all rights reserved. 2.2.5.3 8-bit local bus ? big endian mode for an 8-bit local bus, the pci 9030 can be programmed to use upper or lower byte lanes. figure 2-7. big/little endian ? 8-bit local bus table 2-13. upper byte lane transfer ? 8-bit local bus burst order byte lane first transfer byte 0 appears on local data [31:24] second transfer byte 1 appears on local data [31:24] third transfer byte 2 appears on local data [31:24] fourth transfer byte 3 appears on local data [31:24] table 2-14. lower byte lane transfer ? 8-bit local bus burst order byte lane first transfer byte 0 appears on local data [7:0] second transfer byte 1 appears on local data [7:0] third transfer byte 2 appears on local data [7:0] fourth transfer byte 3 appears on local data [7:0] little endian big endian byte 3 byte 2 byte 0 byte 0 byte 1 byte 0 byte 0 byte 0 31 0 first cycle second cycle third cycle fourth cycle 70 70 70 70 15 8 7 0 23 16 31 24
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 3-1 3 ? serial eeprom 3 serial eeprom reset and initialization 3.1 initialization during power-on, the pci rst# signal resets the default values of the pci 9030 internal registers. in return, the pci 9030 outputs the local lreseto# signal and checks for a serial eeprom. if a serial eeprom exists, and the first 33 bits are not all ones (1), the pci 9030 loads the internal registers from the serial eeprom. otherwise, default values are used. the pci 9030 configuration registers can be written only by the optional serial eeprom or pci host processor. during serial eeprom initialization, the pci 9030 response to direct slave accesses is retrys. 3.2 reset 3.2.1 pci bus rst# input pci bus rst# input assertion causes all pci bus outputs to float, asserts both local reset outputs lreseto# and ledon#, and floats all other local bus output and i/o pins, except bclko, eecs, eedi, eesk, enum#, lgnt, lpmint#, multiplexed i/o pins la[27:24]/gpio[4:7], and the local data bus signals. the la[27:24]/gpio[4:7] multiplexed i/o pins, and the non-multiplexed mode ld[31:0] data or multiplexed mode lad[31:0] address/data i/o pins, are driven low during pci reset. (refer to pci 9030 errata #4 .) 3.2.2 software reset a pci host can set the pci adapter software reset bit (cntrl[30]=1) to reset the pci 9030 and assert lreseto#. the pci and local configuration register contents are not reset as a result. when the software reset bit is set, the pci 9030 responds only to configuration register accesses, and not to local bus accesses. the pci 9030 remains in this reset condition until the pci host clears the bit (cntrl[30]=0). the pci interface is not reset. note: if pci target read ahead mode is enabled (cntrl[16]=1), disable it prior to a software reset, or if following a software reset, perform a pci target read of any valid local bus address, except the next sequential lword referenced from the last pci target read, to flush the pci target read fifo. 3.2.3 local bus output lreseto# lreseto# is asserted when the pci bus rst# input is asserted or the pci adapter software reset bit is set (cntrl[30]=1). 3.3 serial eeprom after reset, the pci 9030 attempts to read the serial eeprom to determine its presence. an active start bit set to 0 indicates a serial eeprom is present. the pci 9030 supports 93cs56l (2k bit) or 93cs66l (4k bit). (refer to manufacturer ? s data sheet for the particular serial eeprom being used.) the first 33 bits are then checked to verify that the serial eeprom is programmed. if the first 33 bits are all ones (1), a blank serial eeprom is present. for blank serial eeprom conditions, the pci 9030 reverts to the default values. (refer to table 3-1.) when the serial eeprom valid bit is set to 1 (cntrl[28]=1), if programmed, real or random data is detected in the serial eeprom. an active start bit set to 1 indicates that a serial eeprom is not present. for missing serial eeprom conditions, the pci 9030 stops the serial eeprom load and reverts to the default values within 13 serial eeprom clocks (eesk). the 3.3v serial eeprom clock is derived from the pci clock, generated by the pci 9030 by internally dividing the pci clock by 132. the serial eeprom can be read or written from the pci bus. the serial eeprom control register bits (cntrl[28:24]) control the pci 9030 pins that enable reading or writing of serial eeprom data bits. (refer to manufacturer ? s data sheet for the particular serial eeprom being used.) to reload serial eeprom data into the pci 9030 internal registers, write 1 to the reload configuration registers bit (cntrl[29]=1). the serial eeprom can also be read or written, using the vpd function. (refer to section 9.) the pci 9030 loads 34 lwords from the serial eeprom.
section 3 serial eeprom reset and initialization serial eeprom pci 9030 data book version 1.4 3-2 ? 2002 plx technology, inc. all rights reserved. 3.3.1 serial eeprom load sequence the serial eeprom load sequence, listed in table 3-2, uses the following abbreviations: msw = most significant word bits [31:16] lsw = least significant word bits [15:0] 3.3.1.1 serial eeprom load the registers listed in table 3-2 are loaded from the serial eeprom after a pci reset is de-asserted. the serial eeprom is organized in words (16 bit). the pci 9030 first loads the most significant word bits (msw[31:16]), starting from the most significant bit ([31]). the pci 9030 then loads the least significant word bits (lsw[15:0]), starting again from the most significant bit ([15]). therefore, the pci 9030 loads the device id, vendor id, class code, and so forth. the serial eeprom values can be programmed using a serial eeprom programmer or plxmon ? software. the values can be programmed using the pci 9030 vpd function (refer to section 9) or through the serial eeprom control register (cntrl). the cntrl register allows programming of the serial eeprom, one bit at a time. to read back the value from the serial eeprom, the vital product data (vpd) function can be utilized. with full utilization of vpd, the designer can perform reads and writes from/to the serial eeprom, 32 bits at a time. values should be programmed in the order listed in table 3-2. the 68, 16-bit words listed in the table are stored sequentially in the serial eeprom. 3.3.1.2 recommended serial eeproms the pci 9030 is designed to use serial eeproms with a three-wire serial interface, powered at 3.3v, and that support 250 khz clocking and sequential reads. for specific eeprom recommendations, refer to the eeprom guidelines posted on the plx website, http://www.plxtech.com/products/default.htm. figure 3-1. serial eeprom memory map table 3-1. serial eeprom guidelines serial eeprom pci 9030 system boot condition none uses default values (start bit is 1). programmed boots with serial eeprom values (start bit is 0). blank detects a blank device and reverts to default values (start bit is 0). load data vpd 00 4096 2048 1088 44h 1536 60h (prot_area register default) 80h 100h # of bits empty # of words (16-bit data)
section 3 serial eeprom serial eeprom reset and initialization pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 3-3 3 ? serial eeprom table 3-2. serial eeprom register load sequence serial eeprom offset register offset register description register bits affected 00h pci 02h device id pciidr[31:16] 02h pci 00h vendor id pciidr[15:0] 04h pci 06h pci status pcisr[15:0] 06h pci 04h pci command reserved 08h pci 0ah class code pciccr[15:0] 0ah pci 08h class code / revision pciccr[7:0] / pcirev[7:0] 0ch pci 2eh subsystem id pcisid[15:0] 0eh pci 2ch subsystem vendor id pcisvid[15:0] 10h pci 36h msb new capability pointer reserved 12h pci 34h lsb new capability pointer cap_ptr[7:0] 14h pci 3eh (maximum latency and minimum grant are not loadable) reserved 16h pci 3ch interrupt pin (interrupt line routing is not loadable) pciipr[7:0] / pciilr [7:0] 18h pci 42h msw of power management capabilities pmc[15:11, 5, 3:0] 1ah pci 40h lsw of power management next capability pointer / power management capability id pmnext[7:0] / pmcapid[7:0] 1ch pci 46h msw of power management data / pmcsr bridge support extension reserved 1eh pci 44h lsw of power management control/status pmcsr[14:8] 20h pci 4ah msw of hot swap control/status reserved 22h pci 48h lsw of hot swap next capability pointer / hot swap control hs_next[7:0] / hs_cntl[7:0] 24h pci 4eh pci vital product data address reserved 26h pci 4ch pci vital product data next capability pointer / pci vital product data control pvpd_next[7:0] / pvpdcntl[7:0] 28h local 02h msw of local address space 0 range las0rr[31:16] 2ah local 00h lsw of local address space 0 range las0rr[15:0] 2ch local 06h msw of local address space 1 range las1rr[31:16] 2eh local 04h lsw of local address space 1 range las1rr[15:0] 30h local 0ah msw of local address space 2 range las2rr[31:16] 32h local 08h lsw of local address space 2 range las2rr[15:0] 34h local 0eh msw of local address space 3 range las3rr[31:16] 36h local 0ch lsw of local address space 3 range las3rr[15:0] 38h local 12h msw of expansion rom range eromrr[31:16] 3ah local 10h lsw of expansion rom range eromrr[15:0] 3ch local 16h msw of local address space 0 local base address (remap) las0ba[31:16] 3eh local 14h lsw of local address space 0 local base address (remap) las0ba[15:0]
section 3 serial eeprom reset and initialization serial eeprom pci 9030 data book version 1.4 3-4 ? 2002 plx technology, inc. all rights reserved. 40h local 1ah msw of local address space 1 local base address (remap) las1ba[31:16] 42h local 18h lsw of local address space 1 local base address (remap) las1ba[15:0] 44h local 1eh msw of local address space 2 local base address (remap) las2ba[31:16] 46h local 1ch lsw of local address space 2 local base address (remap) las2ba[15:0] 48h local 22h msw of local address space 3 local base address (remap) las3ba[31:16] 4ah local 20h lsw of local address space 3 local base address (remap) las3ba[15:0] 4ch local 26h msw of expansion rom local base address (remap) eromba[31:16] 4eh local 24h lsw of expansion rom local base address (remap) eromba[15:0] 50h local 2ah msw of local address space 0 bus region descriptor las0brd[31:16] 52h local 28h lsw of local address space 0 bus region descriptor las0brd[15:0] 54h local 2eh msw of local address space 1 bus region descriptor las1brd[31:16] 56h local 2ch lsw of local address space 1 bus region descriptor las1brd[15:0] 58h local 32h msw of local address space 2 bus region descriptor las2brd[31:16] 5ah local 30h lsw of local address space 2 bus region descriptor las2brd[15:0] 5ch local 36h msw of local address space 3 bus region descriptor las3brd[31:16] 5eh local 34h lsw of local address space 3 bus region descriptor las3brd[15:0] 60h local 3ah msw of expansion rom bus region descriptor erombrd[31:16] 62h local 38h lsw of expansion rom bus region descriptor erombrd[15:0] 64h local 3eh msw of chip select 0 base address cs0base[31:16] 66h local 3ch lsw of chip select 0 base address cs0base[15:0] 68h local 42h msw of chip select 1 base address cs1base[31:16] 6ah local 40h lsw of chip select 1 base address cs1base[15:0] 6ch local 46h msw of chip select 2 base address cs2base[31:16] 6eh local 44h lsw of chip select 2 base address cs2base[15:0] 70h local 4ah msw of chip select 3 base address cs3base[31:16] 72h local 48h lsw of chip select 3 base address cs3base[15:0] 74h local 4eh serial eeprom write-protected address boundary prot_area[7:0] 76h local 4ch lsw of interrupt control/status intcsr[15:0] 78h local 52h msw of pci target response, serial eeprom, and initialization control cntrl[31:16] 7ah local 50h lsw of pci target response, serial eeprom, and initialization control cntrl[15:0] 7ch local 56h msw of general purpose i/o control gpioc[31:16] 7eh local 54h lsw of general purpose i/o control gpioc[15:0] table 3-2. serial eeprom register load sequence (continued) serial eeprom offset register offset register description register bits affected
section 3 serial eeprom serial eeprom reset and initialization pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 3-5 3 ? serial eeprom 80h local 72h msw of hidden 1 power management data select (refer to section 7.2.1) pmdata[7:0] hidden, d 0 and d 3hot power dissipated 82h local 70h lsw of hidden 1 power management data select (refer to section 7.2.1) pmdata[7:0] hidden, d 0 and d 3hot power consumed 84h local 76h msw of hidden 2 power management data scale (refer to section 7.2.1) reserved 86h local 74h lsw of hidden 2 power management data scale (refer to section 7.2.1) pmcsr[14:13] hidden, bits [7:0] are used as follows: [7:6] d 3hot power dissipated, [5:4] d 0 power dissipated, [3:2] d 3hot power consumed, [1:0] d 0 power consumed table 3-2. serial eeprom register load sequence (continued) serial eeprom offset register offset register description register bits affected
section 3 serial eeprom reset and initialization internal register access pci 9030 data book version 1.4 3-6 ? 2002 plx technology, inc. all rights reserved. 3.4 internal register access the pci 9030 provides several internal registers, which allow for maximum flexibility in the bus-interface design and performance. these registers are accessible from the pci and local buses (refer to figure 3-2) and include the following: pci configuration local configuration power management hot swap vpd figure 3-2. pci 9030 internal register access note: local configuration register access can be limited to memory- or i/o-mapped. access can be disabled by way of the pcibar1 and pcibar0 enable bits (cntrl[13:12]). these bits should not be disabled for the pc platform. 3.4.1 pci configuration registers device and vendor ids. there are two sets of device and vendor ids. the device id and vendor id are located at offset 00h of the pci configuration registers (pciidr[31:16] and pciidr[15:0], respectively). the subsystem id and subsystem vendor id are located at offsets 2eh and 2ch, respectively, of the pci configuration registers (pcisid[15:0] and pcisvid [15:0], respectively). the device id and vendor id identify the particular device and its manufacturer. the subsystem vendor id and subsystem id provide a way to distinguish between pci interface chip vendors and add-in board manufacturers, using a pci chip. status. this register contains pci bus-related events information. command. this register controls the ability of a device to respond to pci accesses. it controls whether the device responds to i/o or memory space accesses. class code. this register identifies the general function of the device. (refer to pci r2.2 for further details.) revision id. the value read from this register represents the pci 9030 current silicon revision. header type. this register defines the device configuration header format and whether the device is single function or multi-function. note: multiple functions are not supported. cache line size. this register defines the system cache line size in units of 32-bit lwords. pci base address for memory accesses to local configuration registers. the system bios uses this register to assign a pci address space segment for memory accesses to the pci 9030 local configuration registers. the pci address range occupied by these configuration registers is fixed at 128 bytes. during initialization, the host writes ffffffff to this register, then reads back ffffff80, determining the required memory space of 128 bytes. the host then writes the base address to pcibar0[31:7]. pci base address for i/o accesses to local configuration registers. the system bios uses this register to assign a pci address space segment for i/o accesses to the pci 9030 local configuration registers. the pci address range occupied by these configuration registers is fixed at 128 bytes. during initialization, the host writes ffffffff to this register, then reads back ffffff81, determining a required 128 bytes of i/o space. the host then writes the base address to pcibar1[31:7]. local bus master pci bus master local configuration registers pci configuration registers pci 9030 pci interrupt local interrupt power management registers hot swap registers vpd registers
section 3 new capabilities function support serial eeprom reset and initialization pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 3-7 3 ? serial eeprom pci base address for accesses to local address spaces 0, 1, 2, and 3. the system bios uses these registers to assign a pci address space segment for accesses to local address space 0, 1, 2, and 3. the pci address range occupied by this space is determined by the local address space range registers. during initialization, the host writes ffffffff to these registers, then reads back a value determined by the range. the host then writes the base address to the upper bits of these registers. pci expansion rom base address. the system bios uses this register to assign a pci address space segment for accesses to the expansion rom. the pci address range occupied by this space is determined by the expansion rom range register. during initialization, the host writes ffffffff to this register, then reads back a value determined by the range. the host then writes the base address to the upper bits of this register. pci interrupt line . indicates to which system interrupt controller(s) input the interrupt line is connected. the pci 9030 does not use this value, rather the value is used by device drivers and operating systems for priority and vector information. values in this register are system-architecture specific. pci interrupt pin. this register specifies the interrupt request pin (if any) to be used. the pci 9030 supports inta#, but not intb#, intc#, nor intd#. 3.4.2 pci bus access to internal registers the pci 9030 pci configuration registers can be accessed from the pci bus with a type 0 configuration cycle. all other pci 9030 internal registers can be accessed by a memory cycle, with the pci bus address that matches the base address specified in pci base address 0 (pcibar0[31:4]) for the pci 9030 memory- mapped configuration register. these registers can also be accessed by an i/o cycle, with the pci bus address matching the base address specified in pci base address 1 (pcibar1[31:2] for the pci 9030 i/o-mapped configuration register. all pci read or write accesses to the pci 9030 registers can be byte, word, or lword accesses. all pci memory accesses to the pci 9030 registers can be burst or non-burst accesses. the pci 9030 responds with a pci bus disconnect for all burst i/o accesses (pcibar1[31:2]) to the pci 9030 internal registers. 3.5 new capabilities function support the new capabilities function support includes pci power management, hot swap, and vpd features, as listed in the following table. [for further information on these features, refer to section 7, ? pci power management, ? section 8, ? compactpci hot swap, ? and section 9, ? pci vital product data (vpd). ? ] table 3-3. new capabilities function support features new capability function pci register offset location first (power management) 40h, which is pointed to, from cap_ptr [7:0]. second hot swap) 48h, which is pointed to, from pmnext[7:0]. third (vpd) 4ch, which is pointed to, from hs_next[7:0]. because pvpd_next[7:0] defaults to zero (0), this indicates that vpd is the last pci 9030 new capability function support feature.
section 3 serial eeprom reset and initialization serial eeprom and configuration initialization timing diagrams pci 9030 data book version 1.4 3-8 ? 2002 plx technology, inc. all rights reserved. 3.6 serial eeprom and configuration initialization timing diagrams note: serial eeprom initialization completes in approximately 4.35 ms with a 33.3 mhz pci clock. timing diagram 3-1. initialization from serial eeprom (2k or 4k bit) 1 1 0 a7a6a5a4a3 0 d15d14d13d12d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 a2 d15d14d13 d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 device id (pciidr[31:16]) vendor id (pciicr[15:0]) d14d13d12d11 d10 d9 d8 d7 d6 d5 d4 d3 pci status (pcisr[15:0]) continues d15d14d13d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 start bit 0 indicates serial eeprom present ----| last word (pmdatascale[7:0]) eesk, eedo, eecs status from configuration registers after completion of read continues a0 a1 d0 d2 d1 d0 0us 40us 80us 120us eesk lreseto# eecs eedi eedo eesk eedo eesk (continues) eecs eedo
section 3 serial eeprom and configuration initialization timing diagrams serial eeprom reset and initialization pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 3-9 3 ? serial eeprom 1 ? introduction timing diagram 3-2. pci configuration write to pci configuration register timing diagram 3-3. pci configuration read from pci configuration register 1 2 3 addr 5 6 7 cmd=b 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# 1 2 3 addr 5 6 7 cmd=a 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns 300 n clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy#
section 3 serial eeprom reset and initialization serial eeprom and configuration initialization timing diagrams pci 9030 data book version 1.4 3-10 ? 2002 plx technology, inc. all rights reserved. timing diagram 3-4. pci memory write to local configuration register timing diagram 3-5. pci memory read from local configuration register 1 2 3 addr 5 6 7 cmd=7 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# 1 2 3 addr 5 6 7 cmd=6 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy#
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-1 4 ? pci target 4 pci target (direct slave) operation functional operation described can be modified through the pci 9030 programmable internal registers. 4.1 overview pci target (direct slave) operations originate on the pci bus, go through the pci 9030, and finally access the local bus. the pci 9030 is a pci bus target and a local bus master. 4.2 direct data transfer mode the pci 9030 supports pci target accesses to local memory or i/o transfer mode. 4.2.1 pci target operation (pci master-to-local bus access) the pci 9030 supports burst memory-mapped transfer accesses and i/o-mapped, single-transfer accesses to the local bus from the pci bus through a 16-lword (64-byte) pci target read fifo and a 32-lword (128-byte) pci target write fifo. the pci base address registers are provided to set up the adapter location in the pci memory and i/o space. in addition, local mapping registers allow address translation from the pci address space to the local address space. five spaces are available: space 0 space 1 space 2 space 3 expansion rom expansion rom is intended to support a bootable rom device for the host. for single cycle pci target reads, the pci 9030 reads a single local bus lword or partial lword. the pci 9030 disconnects after one transfer for all pci target i/o accesses. for highest data-transfer rates, the pci 9030 supports posted writes. memory-mapped address spaces can be selectively enabled to prefetch data to support pci burst reads. a prefetch counter for each local address space controls whether prefetch is enabled and continuous, or limited to a finite number of accesses. (refer to section 4.2.1.3.) if prefetch is enabled for a local address space, the pci 9030 can also be programmed to support pci target read ahead mode. (refer to section 4.2.1.4.) each local space can be programmed to operate in an 8-, 16-, or 32-bit local bus width. the pci 9030 contains an internal wait state generator and external wait state input, ready#. ready# can be selectively enabled or disabled for each local address space in the corresponding las x brd and/or erombrd registers. with or without wait state(s), the local bus, independent of the pci bus, can: burst as long as data is available (continuous burst mode) burst four data at a time (burst-4 mode) perform continuous single cycles 4.2.1.1 pci target lock the pci 9030 supports direct pci-to-local-bus exclusive accesses (locked atomic operations). a pci-locked operation to the local bus results in the entire address spaces 0, 1, 2, and 3, and expansion rom being locked until they are released by the pci bus master. locked operations are enabled or disabled with the pci target lock# enable bit (cntrl[23]) for pci-to-local accesses. it is the responsibility of external arbitration logic to monitor the llocko# pin and enforce the meaning for an atomic operation. for example , if a local master initiates a locked operation, the local bus arbiter may choose to not grant use of the local bus to other masters until the locked operation completes.
section 4 pci target (direct slave) operation direct data transfer mode pci 9030 data book version 1.4 4-2 ? 2002 plx technology, inc. all rights reserved. 4.2.1.2 pci r2.2 features enable the pci 9030 can be programmed through the pci r2.2 features enable bit (cntrl[14]) to perform all pci read/write transactions in compliance with pci r2.2 . the following pci 9030 behavior occurs when cntrl[14]=1. 4.2.1.2.1 pci target delayed read mode pci bus single cycle aligned or unaligned pci target read transactions always result in a one-lword single cycle transfer on the local bus, with corresponding local byte enables (lbe[3:0]#), asserted to reflect pci byte enables (c/be[3:0]#), unless the pci read no flush mode bit is enabled (cntrl[16]=1). (refer to section 4.2.1.4.) this causes the pci 9030 to retry all pci bus read requests that follow, until the original pci address and pci byte enables (c/be[3:0]#) are matched. (refer to figure 4-1.) figure 4-1. pci target delayed read mode note: the figure represents a sequence of bus cycles. 4.2.1.2.2 2 15 pci clock timeout if the pci master does not complete the originally requested pci target delayed read transfer, the pci 9030 flushes the pci target read fifo after 2 15 pci clocks and grants an access to a new pci target read access. the pci 9030 retries all other pci target read accesses that occur before the 2 15 pci clock timeout, provided the disconnect with flush read fifo bit is disabled (cntrl[31]=0, default). if enabled (cntrl[31]=1), a new pci target read access flushes any pending delayed reads from the read fifo and the new read request is granted. 4.2.1.2.3 pci r2.2 16- and 8-clock rule the pci 9030 guarantees that if the first pci target write data cannot be accepted by the pci 9030 and/or the first pci target read data cannot be returned by the pci 9030 within 16 pci clocks from the beginning of the pci target cycle (frame# asserted), the pci 9030 issues a retry (stop# asserted) to the pci bus. during successful pci target read and/or write accesses, the subsequent data after the first access is accepted for writes or returned for reads in eight pci clocks (trdy# asserted). otherwise, the pci 9030 issues a pci disconnect (stop# asserted) to the pci master. in addition, setting the pci r2.2 features enable bit [cntrl[14]=1) allows optional enabling of the following pci r2.2 functions: no write while a delayed read is pending (pci retries for writes) (cntrl[17]) write and flush pending delayed read (cntrl[15]) pci r2.2 features enable bit set in internal registers data is stored in 16-lword internal fifo pci 9030 returns prefetched data immediately pci bus local bus pci read request pci 9030 instructs pci host to ? retry ? read cycle later pci bus is free to perform other cycles during this time pci host returns to fetch read data again read data is now ready for host pci 9030 requests read data from local bus local memory returns requested data to pci 9030 pci 9030
section 4 direct data transfer mode pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-3 4 ? pci target 4.2.1.3 local bus prefetch memory-mapped pci 9030 local address spaces can be selectively programmed to enable a local bus prefetch (enabled by default in las x brd[5:3]). a prefetch counter for each space controls the number of prefetches to perform in conjunction with each pci target read. when the prefetch counter is enabled (las x brd[5]=1), the prefetch count (las x brd[4:3]) can be set to 0 (disabling prefetch), or to 4, 8 or 16 lwords (independent of local bus width). if the prefetch counter is disabled (las x brd[5]=0), the pci 9030 performs continuous prefetches. when a pci target read is performed and a local bus prefetch is enabled for the local address space, the pci 9030 fetches the requested data and continues to read data from sequential addresses (anticipating the pci master eventually consuming the additional data). when the pci 9030 prefetches, if the prefetch counter is enabled, the pci 9030 stops reading from the local bus read after reaching the prefetch count limit. in continuous prefetch mode, if pci target read ahead mode is disabled (cntrl[16]=0) (refer to section 4.2.1.4), the pci 9030 prefetches as long as space is available in its fifo, and stops prefetching a few pci clocks after the pci master completes its read. if both continuous prefetch and pci target read ahead modes are enabled, the pci 9030 continues to prefetch until the read fifo is full. if prefetch is disabled (las x brd[5:3]=100), or the address space is mapped as i/o, the pci 9030 stops after one read transfer. local prefetch must be enabled if pci burst reads and read ahead mode are utilized. refer to section 2.1.1.4 regarding mapping of pci 9030 address spaces into an upstream bridge ? s prefetchable base and limit registers. 4.2.1.4 pci target read ahead mode the pci 9030 also supports pci target read ahead mode (cntrl[16]), where prefetched data can be read from the pci 9030 internal fifo instead of the local bus. the address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). the pci target read ahead mode functions can be used with or without pci target delayed read mode. (refer to figure 4-2.) read ahead mode requires that prefetch be enabled in the las x brd and/or erombrd registers for the memory-mapped spaces that use read ahead mode. the pci 9030 flushes its read fifo for each i/o- mapped access. figure 4-2. pci target read ahead mode note: the figure represents a sequence of bus cycles. 4.2.1.5 pci target delayed write mode the pci 9030 supports pci target delayed write mode transactions, where posted write data accumulates in the pci target write fifo before the pci 9030 requests a write transaction (ads# and/or ale assertion) to be performed on the local bus. pci target delayed write mode is programmable to delay the ads# and ale assertion for the amount of local clocks selected in cntrl[11:10]. this feature is useful for gaining higher throughput during pci target write burst transactions for conditions in which the pci clock frequency is slower than the local clock frequency. 4.2.1.6 pci target local bus ready# timeout mode the pci 9030 supports pci target local bus ready# timeout mode transactions, where the pci 9030 asserts an internal ready# signal to recover from stalling the local and pci buses. the pci target local bus ready# timeout mode transaction is programmable to select the amount of local clocks before ready# times out (cntrl[9:8]). if a local target stalls with a ready# assertion pci 9030 pci bus local bus pci read request read data read data pci bus master read returns with ? sequential address ? pci 9030 prefetches data from local bus device pci target read ahead mode is set in internal registers prefetched data is stored in the internal fifo pci 9030 returns prefetched data immediately from internal fifo without reading again from the local bus pci 9030 prefetches more data if fifo space is available pci 9030 prefetches more data from local memory
section 4 pci target (direct slave) operation direct data transfer mode pci 9030 data book version 1.4 4-4 ? 2002 plx technology, inc. all rights reserved. during pci target write transactions, the pci 9030 empties the write fifo by dumping the data into the local bus and does not pass an error condition to the pci bus initiator. during pci target read transactions, the pci 9030 issues a pci target abort to the pci bus initiator every time the pci target local bus ready# timeout is detected. 4.2.1.7 pci target transfer a pci bus master addressing the memory space decoded for the local bus initiates transactions. upon a pci read/write, the pci 9030 being a local bus master executes a transfer, at which time it reads data into the pci target read fifo or writes data to the local bus. for a pci direct access to the local bus, the pci 9030 has a 32-lword (128-byte) write fifo and an 16-lword (64-byte) read fifo. the fifos enable the local bus to operate independently of the pci bus. for write transfers, if the write fifo becomes full, the pci 9030 is programmable to disconnect, or retain the pci bus while generating wait states (trdy# de-asserted) (cntrl[18]). for pci read transactions from the local bus, the pci 9030 holds off trdy# while gathering data from the local bus. for read accesses mapped to pci memory space, the pci 9030 prefetches up to 16 lwords (in continuous prefetch mode) from the local bus. unused read data is flushed from the fifo. for read accesses mapped to pci i/o space, the pci 9030 does not prefetch read data. rather, it breaks each read of a burst cycle into a single address/data cycle on the local bus. the pci target retry delay clocks bits (cntrl[22:19]) can be used to program the period of time in which the pci 9030 holds off trdy#. the pci 9030 issues a retry to the pci bus transaction master when the programmed time period expires. this occurs when the pci 9030 cannot gain local bus control and return trdy# within the programmed time period or the local bus is slowly emptying the write fifo, and filling the read fifo. the pci 9030 supports on-the-fly endian conversion for spaces 0, 1, 2, and 3, and expansion rom. the local bus can be big/little endian by using the programmable internal register configuration. note: the pci bus is always little endian. figure 4-3. pci target write figure 4-4. pci target read note: the figures represent a sequence of bus cycles. 4.2.1.8 pci target pci-to-local address mapping five local address spaces ? spaces 0, 1, 2, and 3, and expansion rom ? are accessible from the pci bus. each is defined by a set of three registers: local address range (las x rr and/or eromrr, where x is the local address space number) local base address (las x ba and/or eromba) pci base address (pcibar2, pcibar3, pcibar4, pcibar5, and/or pcierbar) pci 9030 la, ads#, lw/r# irdy#, ad (data) pci bus local bus lrdyi# devsel#, trdy# frame#, c/be#, ad (addr) slave master master slave lad, blast# pci 9030 la, ads#, lw/r#, blast# trdy#, ad (data) pci bus lrdyi#, lad devsel# frame#, c/be#, ad (addr) irdy# slave master master slave pci bus local bus
section 4 direct data transfer mode pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-5 4 ? pci target a fourth register, the bus region descriptor registers (las x brd and/or erombrd), defines the local bus characteristics for the pci target regions. (refer to figure 4-5.) each pci-to-local address space is defined as part of reset initialization. (refer to section 4.2.1.8.1.) these local bus characteristics can be modified at any time before actual data transactions. 4.2.1.8.1 pci target local bus initialization range ? specifies the pci address bits to use for decoding a pci access to local bus space. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits required to be included in decode, and 0 to all others. remap pci-to-local addresses into a local address space ? bits in this register remap (replace) the pci address bits used in decode as the local address bits. local bus region descriptor ? specifies the local bus characteristics. 4.2.1.8.2 pci target initialization after a pci reset and serial eeprom load, the software determines the amount of required address space by writing all ones (1) to a pci base address register and then reading back the value. the pci 9030 returns zeros (0) in the don ? t care address bits, effectively specifying the address space required, at which time the pci software maps the local address space into the pci address space by programming the pci base address register. (refer to figure 4-5.)
section 4 pci target (direct slave) operation direct data transfer mode pci 9030 data book version 1.4 4-6 ? 2002 plx technology, inc. all rights reserved. figure 4-5. local bus pci target access serial eeprom fifos 32-lword deep write 16-lword deep read local address space 0, 1, 2, and 3 ranges local address space 0, 1, 2, and 3 local base addresses (remap) local address space 0, 1, 2, and 3 bus region descriptors expansion rom range expansion rom local base address (remap) pci base addresses for accesses to local address space 0, 1, 2, and 3 expansion rom bus region descriptor pci expansion rom base address 1 initialize local direct access registers pci address space pci base address local bus access local memory local base address range pci bus access local bus hardware characteristics 3 4 pci bus master initialize pci base address registers 2
section 4 direct data transfer mode pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-7 4 ? pci target 4.2.1.8.3 pci target example a 1 mb prefetchable local address space encompassing local bus addresses 01200000h through 012fffffh is to be configured for local address space 0. assume the bios system resource manager allocates 1 mb with a pci base address of 34500000h. the local memory is then accessible at pci addresses 34500000h through 345fffffh. a. program the serial eeprom as follows: range ? fff00008h [1 mb, decode the upper 12 pci address bits, and set the prefetchable bit (las0rr[3]=1)]. local base address (remap) ? 01200001h (local base address for pci-to-local accesses). bit 0 must be set to enable address decoding (las0ba[0]=1). b. pci initialization software writes all ones (1) to the pci base address register, then reads it back. the pci 9030 returns a value of fff00008h, after which the pci software writes the base address it assigned into the pci base address register(s). pci base address ? 34500008h (pci base address for access to local address space 0 register, pcibar2). the pci base address is always aligned on a boundary determined by address space size. the prefetchable bit is set (pcibar2[3]=1). 4.2.1.8.4 pci target byte enables (multiplexed mode) during a pci target transfer, each of five spaces ? spaces 0, 1, 2, and 3, and expansion rom ? can be programmed to operate in an 8-, 16-, or 32-bit local bus width by encoding the local byte enables (lbe[3:0]#). lbe[3:0]# (pqfp ? pins 55, 58-60, respectively; bga ? pins m5, p5, m6, n6, respectively) are encoded, based on the configured bus width, as follows. 32-bit bus ? the four byte enables indicate which of the four bytes are active during a data cycle: lbe3# byte enable 3 ? lad[31:24] lbe2# byte enable 2 ? lad[23:16] lbe1# byte enable 1 ? lad[15:8] lbe0# byte enable 0 ? lad[7:0] 16-bit bus ? lbe[3, 1:0]# are encoded to provide bhe#, lad1, and ble#, respectively: lbe3# byte high enable (bhe#) ? lad[15:8] lbe2# not used lbe1# address bit 1 (lad1) lbe0# byte low enable (ble#) ? lad[7:0] 8-bit bus ? lbe[1:0]# are encoded to provide lad[1:0], respectively: lbe3# not used lbe2# not used lbe1# address bit 1 (lad1) lbe0# address bit 0 (lad0) during the address phase, lad[1:0] are valid address bits with the same value as lbe[1:0]#. 4.2.1.8.5 pci target byte enables (non-multiplexed mode) during a pci target transfer, each of five spaces ? spaces 0, 1, 2, and 3, and expansion rom ? can be programmed to operate in an 8-, 16-, or 32-bit local bus width by encoding the local byte enables (lbe[3:0]#). lbe[3:0]# (pqfp ? pins 55, 58-60, respectively; bga ? pins m5, p5, m6, n6, respectively) are encoded, based on the configured bus width, as follows. 32-bit bus ? the four byte enables indicate which of the four bytes are active during a data cycle: lbe3# byte enable 3 ? ld[31:24] lbe2# byte enable 2 ? ld[23:16] lbe1# byte enable 1 ? ld[15:8] lbe0# byte enable 0 ? ld[7:0] 16-bit bus ? lbe[3, 1:0]# are encoded to provide bhe#, la1, and ble#, respectively: lbe3# byte high enable (bhe#) ? ld[15:8] lbe2# not used lbe1# address bit 1 (la1) lbe0# byte low enable (ble#) ? ld[7:0] 8-bit bus ? lbe[1:0]# are encoded to provide la[1:0], respectively: lbe3# not used lbe2# not used lbe1# address bit 1 (la1) lbe0# address bit 0 (la0)
section 4 pci target (direct slave) operation response to fifo full or empty pci 9030 data book version 1.4 4-8 ? 2002 plx technology, inc. all rights reserved. 4.3 response to fifo full or empty table 4-1 lists the pci 9030 response to full or empty fifos. table 4-1. response to fifo full or empty mode direction fifo pci bus local bus pci target write pci-to-local full disconnect or throttle trdy# 1 1. throttle trdy# depends on the pci target retry delay clocks (cntrl[22:19]). if cntrl[31]=0 (default preempt condition), de-assert lgnt if the local bus is busy. in either case, wait for lreq to be de-asserted by the local bus master. empty normal normal, assert blast#. pci target read local-to-pci full normal normal, assert blast#. empty disconnect or throttle trdy# 1 normal.
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-9 4 ? pci target 4.4 pci target (direct slave) operation timing diagrams timing diagram 4-1. local bus arbitration from the pci 9030 by another local bus initiator (lreq and lgnt) 1 another local initiator drives bus pci 9030 grants the local bus to another local initiator; otherwise, remains low. local bus is requested by another local initiator. de-asserted if pci 9030 needs to use a local bus and cntrl[7]=0; otherwise, remains high until the local initiator is done. 0ns 250ns 500ns lclk lreq lgnt local bus
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-10 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-2. local level-triggered interrupt asserting pci interrupt timing diagram 4-3. local edge-triggered interrupt asserting pci interrupt 2 1 cmd be addr inta# assertion is asynchronous to both pci and local clocks. data 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# inta# lclk linti[2:1] 2 1 cmd be addr inta# assertion is asynchronous to both pci and local clocks. data cleared by configuration register 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# inta# lclk linti[2:1]
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-11 4 ? pci target note: gpio pins configured as outputs are driven only when the pci 9030 owns the local bus. (refer to pci 9030 errata #2 .) timing diagram 4-4. gpio[8:0] as outputs cmd be ad d cmd be a cmd be bit[2]=0 a cmd be bit[2]=1 a gpio0 set as output gpio[8:0] pins are outputs data data 0ns 250ns 500ns 750ns 1000ns 1250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# la[27:2] lad[31:0] ready# gpio[8:0]
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-12 ? 2002 plx technology, inc. all rights reserved. note: cs[3:0]# base address is in the range of local address spaces 3 through 0. timing diagram 4-5. chip select [3:0]# (32-bit local bus) cmd be addr d0 d1 d2 d3 addr +4 +8 +12 d0 d1 d2 d3 lbe 0ns 100ns 200ns 300ns 400ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# la[27:2] ld[31:0] ready# cs[3:0]# lbe[3:0]# wr# rd# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-13 4 ? pci target 4.4.1 serial eeprom and configuration initialization timing diagrams note: serial eeprom initialization completes in approximately 4.35 ms with a 33.3 mhz pci clock. timing diagram 4-6. initialization from serial eeprom (2k or 4k bit) 1 1 0 a7a6a5a4a3 0 d15d14d13d12d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 a2 d15d14d13 d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 device id (pciidr[31:16]) vendor id (pciicr[15:0]) d14d13d12d11 d10 d9 d8 d7 d6 d5 d4 d3 pci status (pcisr[15:0]) continues d15d14d13d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 start bit 0 indicates serial eeprom present ----| last word (pmdatascale[7:0]) eesk, eedo, eecs status from configuration registers after completion of read continues a0 a1 d0 d2 d1 d0 0us 40us 80us 120us eesk lreseto# eecs eedi eedo eesk eedo eesk (continues) eecs eedo
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-14 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-7. pci configuration write to pci configuration register timing diagram 4-8. pci configuration read from pci configuration register 1 2 3 addr 5 6 7 cmd=b 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# 1 2 3 addr 5 6 7 cmd=a 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns 300 n clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-15 4 ? pci target timing diagram 4-9. pci memory write to local configuration register timing diagram 4-10. pci memory read from local configuration register 1 2 3 addr 5 6 7 cmd=7 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# 1 2 3 addr 5 6 7 cmd=6 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-16 ? 2002 plx technology, inc. all rights reserved. 4.4.2 multiplexed and non-multiplexed modes timing diagrams timing diagram 4-11. pci target burst write with delayed write and chip select enabled (32-bit local bus) d0 d1 d2 d3 d4 d5 7 d4 d3 d2 d1 d0 ad be ad be ad +4 +8 +c +10 +14 d5 note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 100ns 200ns 300ns 400ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r# cs[1:0]#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-17 4 ? pci target timing diagram 4-12. pci target burst write (32-bit local bus) ad d0 d1 d2 d3 70 ad ad d0 d1 d2 d3 f0f note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. five address-to-data wait states; one data-to-data wait state; three write strobe delay clocks; two write cycle hold clocks. 0ns 250ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-18 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-13. pci target burst write (16-bit local bus), no wait states 7 0 f 4 6 4 6 4 6 4 6 4 6 4 6 ad d0 d1 d2 d3 d4 d5 ad ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-19 4 ? pci target timing diagram 4-14. pci target burst write (16-bit local bus), one data-to-data wait state ad d0 1 2 3 4 5 7 0 ad f 4 6 4 6 4 6 4 6 4 6 4 6 ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-20 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-15. pci target burst writes (8-bit local bus), one data-to-data wait state be c d e f c d e f c d e f ad d0 d1 d2 7 ad ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-21 4 ? pci target timing diagram 4-16. pci target single writes (16-bit local bus) 0 f 4 6 4 6 4 6 4 6 4 6 4 6 f 7 ad d0 d1 d2 d3 d4 d5 ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns 750n s pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-22 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-17. pci target burst write (8-bit local bus), no wait states d0 d1 d2 7 c d e f c d e f c d e f ad ad ad d0 note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-23 4 ? pci target timing diagram 4-18. pci target back-to-back single writes (32-bit local bus) ad d0 ad d1 7 0 7 0 ad ad d0 d1 f 0 0 f ad ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-24 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-19. pci target back-to-back burst write followed by read (16-bit local bus) ad d0 ad 7 0 6 0 d0 ad ad d0 ad d0 f 0 8 0 f ad note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-25 4 ? pci target timing diagram 4-20. pci target back-to-back burst read followed by write (16-bit local bus) ad d0 ad d1 6 0 7 ad ad ad d0 ad d0 f 0 f 0 f 0 note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns 750n s pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-26 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-21. pci target back-to-back burst reads (16-bit local bus) ad d0 ad d1 6 0 6 ad ad 0 ad ad 0 f 0 f 0 f note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 250ns 500ns 750ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# lw/r#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-27 4 ? pci target 4.4.2.1 multiplexed mode only timing diagrams timing diagram 4-22. pci target single write (32-bit local bus), multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 4 be data a data lbe 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# ale blast# lbe[3:0]# lw/r# lad[31:0] ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-28 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-23. pci target single read (32-bit local bus), multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 be a 14 data 4 data lbe 0ns 100ns 200ns 300ns 400ns 500n s clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# ale blast# lw/r# lbe[3:0]# lad[31:0] ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-29 4 ? pci target timing diagram 4-24. pci target burst write with bterm enabled (32-bit local bus), multiplexed mode only a does not change, unaligned has own cycle with ads# d0 d1 d7 d2 d3 d4 a+14 d5 d6 eight lword burst, no wait states, bterm# (input) enabled, burst enabled, 32-bit local bus. note: if bterm# (input) is disabled, a new ads# cycle starts every quad-lword boundary. bterm# (input) replaces ready# (input) when asserted. 0ns 250ns 500ns lclk lreq lgnt ads# ale blast# lbe[3:0]# lw/r# lad[31:0] bterm# (input) ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-30 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-25. pci target burst read with prefetch enabled (32-bit local bus), prefetch counter set to 8, multiplexed mode only cmd be a addr lbe d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6 d7 d0 d7 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# ale blast# lad[31:0] lbe[3:0]# lw/r# ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-31 4 ? pci target timing diagram 4-26. pci target non-burst write (8-bit local bus), multiplexed mode only d0 d1 be c d e f c d e f ad ad ad ad ad ad ad ad ad ad ad ad ad ad ad notes: for multiplexed mode, use the lad[31:0] signal for address. in multiplexed mode, the pci 9030 inserts one recovery state between the last data and the next address cycle. 0ns 250ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r#
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-32 ? 2002 plx technology, inc. all rights reserved. 4.4.2.2 non-multiplexed mode only timing diagrams timing diagram 4-27. pci target single write (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 4 be data addr data lbe 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-33 4 ? pci target timing diagram 4-28. pci target single read (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 be addr data data 4 9 10 11 12 13 14 0ns 250ns 500n s clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-34 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-29. pci target single read with one wait state using ready# input (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 be addr data data 4 9 10 11 13 12 14 lbe 0ns 250ns 500n s clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-35 4 ? pci target timing diagram 4-30. pci target single read with one wait state using internal wait state (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 be addr data data 4 9 10 11 13 12 14 lbe * * note: the pci 9030 and local memory will have one wait state without the ready# signal provided. 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0]
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-36 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-31. pci target non-burst write (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 4 be d0 addr d0 d1 +4 +8 d2 d1 d2 lbe 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] bterm# (input) ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-37 4 ? pci target timing diagram 4-32. pci target non-burst read, non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 4 be d0 addr d0 d1 +4 +8 d2 d1 d2 lbe 14 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] bterm# (input) ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-38 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-33. pci target burst write with bterm enabled (32-bit local bus), non-multiplexed mode only d0 d1 d10 d2 d3 d4 d8 d9 a+20 a a+4 a+8 a+c a+10 a+24 a+28 d5 d6 d7 a+14 a+18 a+1c bterm forces new ads# --> lbe eight lword burst, no wait states, bterm enabled, burst enabled, 32-bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad-lword boundary. 0ns 250ns 500ns lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] bterm# (input) ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-39 4 ? pci target timing diagram 4-34. pci target burst write with bterm disabled (32-bit local bus), non-multiplexed mode only 0001 d2 d6 addr a+4 a+8 a+c d4 a+10 d0 d1 d3 d5 d7 d8 a+14 a+18 a+1c a+20 lbe = 0 no wait states, bterm disabled, burst enabled, 32-bit local bus. unaligned transfer results in new ads#. note: not all byte enables asserted on a quad boundary la[3:2]=11 results in a new ads#. 0ns 250ns 500ns lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] bterm# (input) ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-40 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-35. pci target burst read with prefetch counter set to 8 (32-bit local bus), non-multiplexed mode only cmd be addr d0 d1 d2 d3 d4 +4 +8 +16 d0 d1 d2 d3 +12 d4 addr +20 +24 +28 d5 d6 d7 lbe 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-41 4 ? pci target timing diagram 4-36. pci target burst write (32-bit local bus), non-multiplexed mode only 1 2 3 addr 5 6 7 cmd 8 4 +4 be do d1 d3 d4 +8 +c +10 d1 d2 d3 d4 d0 a five lwords, one external wait state, bterm enabled, burst enabled. lbe 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-42 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-37. pci r2.2 features enable , non-multiplexed mode only cmd be addr aa lbe retry a cmd cmd be write is not allowed during delayed read retry delayed read retries d0 d1 d2 d3 d4 d5 d6 d7 d8 reads data +4 +8 +c +10+14+18+1c d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10d11d12d13d14d15 +20+24+28+2c+30+34+38+3c addr cmd d0 be write retries and completes 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# stop# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input) disconnect immediately for a read. does not affect pending reads when a write cycle occurs, nor flush the read fifo if the pci read cycle completes. when a read is pending, force retry on a write. de-assert trdy# until space is available in the
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-43 4 ? pci target timing diagram 4-38. pci target read no flush mode (read ahead mode), prefetch enabled, prefetch count disabled, burst enabled, non-multiplexed mode only cmd be addr addr lbe cmd be d1 d2 d3 d4 d5 d6 +4 +8 +c +10 +14 +18 +1c d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 +20 +24 +28 +2c +30 +34 +38 +3c +40 d16 d0 addr addr d0 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)
section 4 pci target (direct slave) operation pci target (direct slave) operation timing diagrams pci 9030 data book version 1.4 4-44 ? 2002 plx technology, inc. all rights reserved. timing diagram 4-39. locked pci target read followed by write and release (llocko#), non-multiplexed mode only addr r byte enables d0 d1 w-a w be w-data <-- can be de-asserted after last data d0 addr d1 d2 d3 d4 +4 +8 +12 +16 +20 d5 d6 d7 +24 +28 d8 +32 w-data w-addr de-asserted after detecting pci unlock ---> lbe lbe 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lock# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input) llocko#
section 4 pci target (direct slave) operation timing diagrams pci target (direct slave) operation pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 4-45 4 ? pci target timing diagram 4-40. pci target write to local target in bigend mode, non-multiplexed mode only 1 23 addr 567 cmd 8 4 be data= aabbccdd addr ddccbbaa 01234567 67452301 lbe 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# lbe[3:0]# lw/r# la[27:2] ld[31:0] ready# (input)

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 5-1 5 ? chip selects 5 local chip selects 5.1 overview the pci 9030 provides four chip select outputs to selectively enable devices on its local bus. each active-low chip select is programmable and independent of any local address space. without this feature, external address decoding logic is required to implement chip selects. 5.2 chip select base address registers there are four chip select base address registers. these registers control the four chip select pins on the pci 9030. [ for example , chip select 0 base address register (cs0base) controls cs0#, chip select 1 base address register (cs1base) controls cs1#, and so forth.] the chip select base address registers serve three purposes: 1. to enable or disable chip select functions within the pci 9030. if enabled, the chip select signal is active if the local bus address falls within the address specified by the range and base address. if disabled, the chip select signal is not active. 2. to set the range of the local bus addresses for which the chip select signal(s) is active. 3. to set the local base address, at which the range starts. the three rules used to program the chip select base address registers are as follows: 1. range must be a power of 2 (only the most significant bit is 1). 2. base address must be a multiple of the range or 0. 3. address range must be encompassed by one or more local address spaces. otherwise, the chip select decoder does not see addresses which have not been claimed by the pci 9030 on behalf of a local address space, and a chip select is not asserted. chip selects are not bound to any particular local address space unless programmed accordingly in the cs x base, las x rr, and las x ba registers (where x is the chip select number or local address space number, as appropriate). each 28-bit chip select base address register is programmed, as listed in the following table. the y bit (bit 0) enables or disables the chip select signal. x bits are used to determine the range and base address of where the cs# pin is asserted. to program the base and range, the x bits are set as follows: device length or range is specified by the first bit set above the y bit. determined by setting a bit in the register, calculated by shifting the range value (a power of 2) one bit to the right (range divided by 2). base address is determined by the bit(s) set above the range bit. the address is not shifted from its original value. the base address uses all bits in the register above (to the left of) the range bit, and none of the bits in the register at or below (to the right of) the range bit. figure 5-1. chip select base address and range table 5-1. chip select base address register signal programming msb=27 lsb=0 xxxx xxxx xxxx xxxx xxxx xxxx xxxy base address fffffffh 0 { range ? address at which cs x # is asserted (where x is the chip select number)
section 5 local chip selects procedure for using chip select base address registers pci 9030 data book version 1.4 5-2 ? 2002 plx technology, inc. all rights reserved. 5.3 procedure for using chip select base address registers the following describes the procedure for using the chip select base address registers. 1. determine the range in hex. the range must be a power of 2 (only the highest order bit is set). 2. set a bit in the chip select base address register to specify the range. calculate this value by shifting the range value one bit to the right (range divided by 2). only one bit may be set to encode the range. 3. determine the base address. the base address must be a multiple of the range [the base address cannot contain ones (1) at or below (to the right of) the encoded range bit]. set the base address directly into the bits above the range bit. the base address is not shifted from its original value. 4. set the enable bit (bit 0) in the chip select base address register to 1. 5.3.1 chip select base address register programming example a 16k chip select device is attached to the local bus and a chip select is provided. the base address is specified to be 24000h. the following figure illustrates this example. figure 5-2. memory map example 1. determine the range in hex and divide the value by 2 ( for example , 16k is equivalent to 4000h, leaving the range encoding at 2000h). 2. determine the base address ( for example , 24000h). verify that the base address does not overwrite the range bit or any lower bits. 3. set the base address into the bits above the range encoding. the base address is not shifted from its original value. 4. set the enable bit (bit 0). the following is a complete example of setting the chip select base address register with a range of 4000h, a base address of 24000h, and enabled: msb=27 lsb=0 0000 0000 0010 0110 0000 0000 0001 24000h fffffffh 0 27fffh
section 5 chip select timing diagrams local chip selects pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 5-3 5 ? chip selects 5.4 chip select timing diagrams note: cs[3:0]# base address is in the range of local address spaces 3 through 0. timing diagram 5-1. chip select [3:0]# (32-bit local bus) cmd be addr d0 d1 d2 d3 addr +4 +8 +12 d0 d1 d2 d3 lbe 0ns 100ns 200ns 300ns 400ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# la[27:2] ld[31:0] ready# cs[3:0]# lbe[3:0]# wr# rd# lw/r#
section 5 local chip selects chip select timing diagrams pci 9030 data book version 1.4 5-4 ? 2002 plx technology, inc. all rights reserved. timing diagram 5-2. pci target burst write with delayed write and chip select enabled (32-bit local bus) d0 d1 d2 d3 d4 d5 7 d4 d3 d2 d1 d0 ad be ad be ad +4 +8 +c +10 +14 d5 note: for multiplexed mode, use the lad[31:0] signal for address. for non-multiplexed mode, use the la[27:2] signal for address. 0ns 100ns 200ns 300ns 400ns 500ns pclk frame# ad[31:0] cbe[3:0]# irdy# trdy# devsel# lclk lreq lgnt ads# la[27:2] lad/ld[31:0] lbe[3:0]# blast# ready# wr# rd# lw/r# cs[1:0]#
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 6-1 6 ? interrupts, i/o 6 interrupts and general purpose i/o 6.1 overview the pci 9030 provides two local interrupt input pins (linti[2:1]) and a register bit in the interrupt control/status register (intcsr[7]) that can optionally trigger pci interrupt inta# output. the interrupt input pins have an associated register bit to enable or disable the pin (intcsr[3, 0], respectively), and each has a status bit to indicate whether an interrupt source is active (intcsr[5, 2], respectively). the linti[2:1] pins are programmable for active-low or active-high polarity in the default level-sensitive mode. they can be optionally configured as a rising edge-triggered interrupt ( such as , for isa compatibility). level-sensitive interrupts are cleared when the interrupt source is no longer active, or the interrupt input pin is disabled. edge-triggered (latched) interrupts remain active until cleared by a software write, which either asserts the associated local edge triggerable interrupt clear bit(s) (intcsr[11:10], respectively), or disables the interrupt input pin. inta# output can also be de-asserted by clearing the pci interrupt enable bit (intcsr[6]=0). 6.2 interrupts figure 6-1. interrupt and error sources 6.2.1 pci interrupts (inta#) a pci 9030 pci interrupt (inta#) can be asserted by local interrupt input 2 or 1 (linti[2:1]), which are described in the next section. inta# can also be asserted by setting the software interrupt bit (intcsr[7]=1). inta# can be enabled or disabled (default configuration) in the interrupt control/status register (intcsr[6]). if a pci interrupt is required, the pci interrupt pin register (pciipr) must be set to a value of 1 at boot time by the serial eeprom, or chip default value 1 if a blank or no serial eeprom is used, so that bios can route inta# to an interrupt controller interrupt request (irq) input. bios writes the assigned irq number to the pci interrupt line register (pciilr). pciilr register bit values are system- architecture specific. an inta# assertion generated from either linti[2:1] input, configured as level-sensitive interrupts, is cleared when one of the following occurs: interrupt source is no longer active interrupt input pin is disabled pci interrupts are disabled (intcsr[6]=0) subsequent to disabling interrupts, if the local interrupt input remains asserted and interrupts are re-enabled, another interrupt is generated. an inta# assertion generated from either linti[2:1] input, configured as edge-triggered interrupts, remains active regardless of the linti[2:1] input pin state, until the interrupt is cleared with a software write that performs one of the following: asserts the associated local edge triggerable interrupt clear bit(s) (intcsr[11:10], respectively) disables the interrupt input pin disables pci interrupts (intcsr[6]=0) subsequent to disabling interrupts, if interrupts are re-enabled, another interrupt is not generated (although the linti[2:1] input state remains high) until the next low-to-high transition on the linti[2:1] input pin occurs. a software interrupt can be enabled by setting the software interrupt bit (intcsr[7]=1). inta# is asserted if the pci interrupt enable bit is also set (intcsr[6]=1). inta# output is subsequently de-asserted when the software interrupt or pci interrupt enable bit is cleared (intcsr[7 or 6]=0, respectively). or inta# linti1 linti2 software interrupt intcsr[7]
section 6 interrupts and general purpose i/o interrupts pci 9030 data book version 1.4 6-2 ? 2002 plx technology, inc. all rights reserved. inta# is a level output. if inta# is asserted or de-asserted in response to linti[2:1] input, inta# output timing is asynchronous to the pci and local clocks. if inta# is asserted or de-asserted by software, inta# output timing is referenced to a rising edge of the pci clock. note: regarding plxmon, if pci interrupts are enabled and the pci 9030 generates an inta#, the interrupt status displayed in plxmon does not show the bit in the intcsr control register as ? active. ? this occurs because the pci 9030 driver responds to the pci interrupt and clears it. to test a pci interrupt assertion and view active status with plxmon, disable the pci interrupt enable bit (intcsr[6]=0), while keeping all other bit(s) required to generate the interrupt active. then the driver does not see an inta# assertion. after the screen is refreshed, following interrupt assertion, the active status can be seen in plxmon. 6.2.2 local interrupt input (linti[2:1]) the pci 9030 provides two local interrupt input pins linti[2:1]. the local interrupts can be used to generate a pci interrupt, and/or software can poll the interrupt status bits (intcsr[5,2]). linti[2:1] are programmable for active-low or active-high polarity (intcsr[4, 1], respectively) in the default level- sensitive mode (intcsr[9, 8]=00). each pin can be optionally configured as a rising edge-triggered interrupt (intcsr[8, 1, 0]=111 and intcsr[9, 4, 3] =111), such as , for isa compatibility. level-sensitive interrupts are cleared when the interrupt source is no longer active, or the interrupt input pin is disabled. edge-triggered (latched) interrupts remain active until cleared by a software write, which asserts the associated interrupt clear register bit(s) (intcsr[11, 10]=11), or disables the interrupt input pin (intcsr[3, 0]=00). if the pci interrupt enable bit is set (intcsr[6]=1) and inta# is asserted for a local interrupt input assertion, inta# can be de-asserted by clearing the pci interrupt enable bit (intcsr[6]=0). pci 9030 sampling of enabled linti[2:1] inputs, and inta# output state changes (if pci interrupts are enabled) in response to enabled lint[2:1] input, are asynchronous to the pci and local clocks. 6.2.3 local power management interrupt (lpmint#) the pci 9030 is a pci target device only; therefore, there is no access to the internal registers from the local bus. the local power management interrupt output (lpmint#) is included to accommodate the pci bus power management interface to a local bus. the pci 9030 asserts lpmint# to request a power state change to the local bus when the power state bit(s) change (pmcsr[1:0]). the lpmint# interrupt is synchronous to the local clock. when asserted, it is a one clock-wide pulse. external glue logic is needed to latch the power state change and to retain the previous power state history for further evaluation by the external local bus initiator. 6.2.4 local power management enumerator set the local power management enumerator set interrupt input (lpmeset) is included to accommodate the pci bus power management interface to a local bus. the external local bus initiator can assert lpmeset to the pci 9030 power management control/status register (pmcsr[15]) to set the pme# status and assert the pme# signal to the pci bus in case of a wake-up request event. 6.2.5 all modes pci serr# (pci nmi) the pci 9030 asserts a serr# pulse if parity checking is enabled (pcicr[6]=1) and it detects an address parity error. the serr# output can be enabled or disabled with the serr# enable bit (pcicr[8]).
section 6 general purpose i/o interrupts and general purpose i/o pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 6-3 6 ? interrupts, i/o 6.3 general purpose i/o the pci 9030 supports nine general purpose input and output pins, multiplexed gpio0/waito#, gpio1/ llocko#, gpio2/cs2#, gpio3/cs3#, gpio4/la27, gpio5/la26, gpio6/la25, and gpio7/la24, and gpio8. the pci 9030 default condition is the general purpose input for gpio[3:0], with local address la[27:24] for gpio[4:7], and general purpose input for gpio8. the general purpose i/o pins and functionality can be enabled and selected in the general purpose i/o control register (gpioc[31:0]). gpio[8:0] pins configured as inputs (gpio[8, 3:0] are inputs with the default gpioc register value) are active regardless of whether the pci 9030 owns the local bus. gpio[8:0] pins configured as outputs are driven only when the pci 9030 owns the local bus. (refer to pci 9030 errata #2 .) it is recommended that unused gpio pins be configured as outputs, rather than inputs (by default, gpio[8, 3:0] are inputs); otherwise, input pins should be pulled to a known state.
section 6 interrupts and general purpose i/o interrupts and general purpose i/o timing diagrams pci 9030 data book version 1.4 6-4 ? 2002 plx technology, inc. all rights reserved. 6.4 interrupts and general purpose i/o timing diagrams timing diagram 6-1. local level-triggered interrupt asserting pci interrupt timing diagram 6-2. local edge-triggered interrupt asserting pci interrupt 2 1 cmd be addr inta# assertion is asynchronous to both pci and local clocks. data 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# inta# lclk linti[2:1] 2 1 cmd be addr inta# assertion is asynchronous to both pci and local clocks . data cleared by configuration register 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# inta# lclk linti[2:1]
section 6 interrupts and general purpose i/o timing diagrams interrupts and general purpose i/o pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 6-5 6 ? interrupts, i/o note: gpio pins configured as outputs are driven only when the pci 9030 owns the local bus. (refer to pci 9030 errata #2 .) timing diagram 6-3. gpio[8:0] as outputs cmd be ad d cmd be a cmd be bit[2]=0 a cmd be bit[2]=1 a gpio0 set as output gpio[8:0] pins are outputs data data 0ns 250ns 500ns 750ns 1000ns 1250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lreq lgnt ads# blast# la[27:2] lad[31:0] ready# gpio[8:0]

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 7-1 7 ? power management 7 pci power management 7.1 overview pci power mgmt. r1.1 provides a standard mechanism for operating systems to control add-in boards for power management. it defines four pci functional power states ? d 0 , d 1 , d 2 , and d 3 . states d 0 and d 3 are required, while states d 1 and d 2 are optional. state d 0 represents the highest power consumption and state d 3 the least. d 0 (uninitialized) ? enters this state from power- on reset or from state d 3hot or d 3cold . supports only pci target transactions. d 0 (active) ? all functions active. d 1 ? uses less power than state d 0 , and more than state d 2 . light sleep state. not supported by the pci 9030. d 2 ? uses very little power. supports pci configuration cycles to function if clock is running (memory, i/o, bus mastering, and interrupts are disabled). it also supports the wake-up event from function, but not standard pci interrupts. not supported by the pci 9030. d 3hot ? uses lower power than any other state. supports pci configuration cycles to function if clock is running. supports wake-up event from function, but not standard pci interrupts. when programmed for state d 0 , an internal soft reset occurs. the pci bus drivers must be disabled. pme# context must be retained during this soft reset. d 3cold ? no power. supports only bus reset. all context is lost in this state. from a power management perspective, the pci bus can be characterized at any point in time by one of four power management states ? b 0 , b 1 , b 2 , and b 3 : b 0 (fully on) ? bus is fully usable with full power and clock frequency, pci r2.2 compliant. fully operational bus activity. this is the only power management state in which data transactions can occur. b 1 ? intermediate power management state. full power with clock frequency, pci r2.2 compliant. pme event driven bus activity. v cc is applied to all devices on the bus, and no transactions are allowed to occur on the bus. b 2 ? intermediate power management state. full power clock frequency stopped, pci r2.2 compliant (in the low state). pme event-driven bus activity. v cc is applied to all devices on the bus; however, the clock is stopped and held in the low state. b 3 (off) ? power to the bus is switched off. pme event-driven bus activity. v cc is removed from all devices on the pci bus. all system pci buses have an originating device, which can support one or more power states. in most cases, this creates a bridge ( such as , a host-to-pci bus or a pci-to-pci bridge). function states must be at the same or lower energy state than the bus on which they reside. 7.2 pci power management functional description the pci 9030 passes power management information and has no inherent power-saving feature. the pci 9030 supports d 0 , d 3hot , and d 3cold states (the pci 9030 does not support pme# assertion in the d 3cold state). the pci status register (pcisr) and the new capability pointer register (cap_ptr) indicate whether a new capability (the power management function) is available. the new capability functions support bit (pcisr[4]) enables a pci bios to identify a new capability function support. this bit is executable for writes from the serial eeprom and reads from the pci bus. cap_ptr provides an offset into pci configuration space, the start location of the first item in a new capabilities linked list. the power management capability id register (pmcapid) specifies the power management capability id, 01h, assigned by the pci sig. the power management next capability pointer register (pmnext) points to the first location of the next item in the capabilities linked list. if power management is the last item in the list, then this register should be set to 0h. the default value for the pci 9030 is 48h (hot swap). for the pci 9030 to change the power state and assert pme#, the serial eeprom or pci host should set the pme_en bit (pmcsr[8]=1). the local host then determines to which power state the backplane
section 7 pci power management pci power management functional description pci 9030 data book version 1.4 7-2 ? 2002 plx technology, inc. all rights reserved. should change by monitoring the power_state bits (pmcsr[1:0]), by way of the lpmint# interrupt signal. the pci 9030 is a pci target device only; therefore, there is no access to the internal registers from the local bus. the local power management interrupt output (lpmint#) is included to accommodate the pci power management interface to a local bus. the pci 9030 asserts lpmint# to request a power state change to an external local bus initiator when the power management control/status register (pmcsr[1:0]) changes. the lpmint# interrupt is synchronous to the local clock. when asserted, it is one clock-wide pulse. external local glue logic is needed to latch the power state change and to retain the previous power state history for further evaluation by the external local bus initiator. the pci 9030 uses the pme_support bits (pmc[15:11]) to identify the pme# support corresponding to a specific power state (pmcsr[1:0]). pmc[15:11] are configured by way of the serial eeprom. the local host then sets the pme_status bit (pmcsr[15]=1), by way of lpmeset, and the pci 9030 asserts pme#. to clear the pme_status bit, the pci host must write 1 to the status bit (pmcsr[15]=1). to disable the pme# interrupt signal, either the pci host or serial eeprom can write 0 to the pme_en bit (pmcsr[8]=0). the local power management enumerator set interrupt input (lpmeset) is included to accommodate the pci power management interface to a local bus. the external local bus initiator can assert lpmeset to the pci 9030 power management control/status register (pmcsr[15]) to set the pme# status and assert the pme# signal in the case of a wake-up request event to the pci bus. lpmint# output is asserted every time the power state in the pmcsr register changes. transition from state 11 (d 3hot ) to state 00 (d 0 ) causes a soft reset and serial eeprom reload. during a soft reset, the local bus interface is in reset mode. the pci 9030 issues lreseto# and resets the local bus and all its local internal registers to their default values. in state d 3hot , pci memory and i/o accesses are disabled, as well as pci interrupts, and only configuration is allowed. 7.2.1 power management data_select, data_scale, and power data utilization the data_scale bits (pmcsr[14:13]) indicate the scaling factor to use when interpreting the value of the power management data bits (pmdata[7:0]). the value and meaning of the bits depend upon the data value specified in the data_select bits (pmcsr[12:9]). the data_scale bit value is unique for each data_select bit. for data_select values from 8 to 15, the data_scale bits always return a 0 (pmcsr[14:13]=0). to accommodate the pci power management interface to a local bus, two hidden registers (loadable by the serial eeprom) are available to store all necessary information for the power management data and data_scale register bits ? (pmdatasel; pci:70h) for pmdata[7:0] and (pmdatascale; pci:74h) for pmcsr[14:13], respectively. the pci 9030 supports only d 0 , d 3hot , and d 3cold . power management states. therefore, the pmdata register, which provides operating data (such as power consumption and/or heat dissipation), retains only four possible power data combinations: 1. d 0 power consumed 2. d 3 power consumed 3. d 0 power dissipated 4. d 3hot power dissipated each power combination field requires an 8-bit register in which to store the data. the pci 9030 provides a 32-bit hidden register, pmdatasel, to store such information. the pmdatasel register can be written only from the serial eeprom and read from pmdata[7:0], with the corresponding value in the data_select bits (pmcsr[12:9]). notes: the pci 9030 complies with pci power mgmt. r1.1; however, the version encoding in power management version bits (pmc[2:0]) indicates compliance with pci power mgmt. r1.0. pmc[2:0] can be programmed in serial eeprom to the value 010 to indicate compliance with pci power mgmt. r1.1. (refer to pci 9030 design notes.) the new capability pointer bits (cap_ptr[7:0]) must always contain the default value 40h. (refer to pci 9030 errata #9.)
section 7 system changes power mode example pci power management pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 7-3 7 ? power management the pmdatasel register loading sequence from the serial eeprom is as follows: bits [31:24] ? data select for d 3hot power dissipated bits [23:16] ? data select for d 0 power dissipated bits [15:8] ? data select for d 3hot power consumed bits [7:0] ? data select for d 0 power consumed the data_scale register bits (pmcsr[14:13]) that provide a scale factor value for the data_select value retains four possible scale factors ? 0, 1, 2, and 3. (refer to pci power mgmt. r1.1 for the scale factor derivative values.) each data_scale field requires a 2-bit register in which to store the data. the pci 9030 provides an 8-bit hidden register, pmdatascale, to store such information. the pmdatascale register can be written only from the serial eeprom and read from the pmcsr[14:13] with the corresponding data_select value in the power management control/ status register bits (pmcsr[12:9]). the loading sequence of the pmdatascale register from the serial eeprom is as follows: bits [7:6] ? data_scale for d 3hot power dissipated bits [5:4] ? data_scale for d 0 power dissipated bits [3:2] ? data_scale for d 3hot power consumed bits [1:0] ? data_scale for d 0 power consumed 7.2.2 reading hidden data example an example of reading hidden data follows: 1. pmcsr[12:9] data_select retains a value of 0h. pmcsr[14:13] provides a scale factor for the d 0 power consumed from the data_scale 0 bits (pmdatascale[1:0]). pmdata[7:0] provides the d 0 power consumed value from the d 0 power consumed bits (pmdatasel[7:0]). 2. pmcsr[12:9] data_select retains a value of 7h. pmcsr[14:13] provides a scale factor for the d 3hot power dissipated from the data_scale 7 bits (pmdatascale[7:6]). pmdata[7:0] provides the d 3hot power dissipated value, from the d 3 power dissipated bits (pmdatasel[31:24]). 7.3 system changes power mode example an example of system changes power mode follows: 1. the host writes to the pci 9030 pmcsr register to change the power states. 2. the pci 9030 sends a local power management interrupt (lpmint# output) to a local cpu (lcpu). 3. the lcpu has 200 s to respond to the power management information change (lpmint#) from the pci 9030 pmcsr register to implement the power saving function. 4. after the lcpu implements the power saving function, the pci 9030 disables all pci target accesses and pci interrupt output (inta#). notes: in power-saving mode, all pci and local configuration cycles are granted. the pci 9030 automatically performs a soft reset to a local bus on d 3 -to-d 0 transitions, then reloads the configuration register values stored in the serial eeprom. 7.4 wake-up request example an example of a wake-up request follows: 1. the add-in board (with a pci 9030 chip installed) is in a powered-down state. 2. the local cpu performs a lpmeset interrupt assertion (pci 9030 pmcsr[15]) to request a wake-up procedure. 3. as soon as the request is detected, the pci 9030 drives pme# out to the pci bus. 4. the pci host accesses the pci 9030 pmcsr register to disable the pme# output signal and restores the pci 9030 to the d 0 power state. 5. the pci 9030 completes the power management task by issuing the local power management interrupt (lpmint# output) to the local cpu, indicating that the power mode has changed.

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 8-1 8 ? hot swap 8 compactpci hot swap the pci 9030 is compliant with picmg 2.1, r2.0 requirements for hot swap silicon, including support for programming interface 0 (pi = 0), precharge bias voltage, and early power. 8.1 overview hot swap is used for many compactpci applications. hot swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. this is done for repair of faulty boards or system reconfiguration. additionally, hot swap provides access to hot swap services, allowing system reconfiguration and fault recovery to occur with no system down time and minimum operator interaction. adapter insertion/removal logic control resides on the individual adapters. the pci 9030 uses four pins ? bd_sel#, cpcisw, enum# and ledon# ? to implement the hardware aspects of hot swap functionality. the pci 9030 uses the hot swap capabilities register to implement the software aspects of hot swap. the pci 9030 supports the following features specified in the picmg 2.1, r2.0 requirements for hot swap silicon: picmg 2.1, r2.0 compliance tolerate v cc from early power tolerate asynchronous reset tolerate precharge bias voltage i/o buffers must meet modified v/i requirements limited i/o pin leakage at precharge bias voltage incorporates hot swap control/status register (hs_csr) ? contained within the configuration space. incorporates an extended capability pointer (ecp) mechanism ? it is required that software retain a standard method of determining whether a specific function is designed in accordance with picmg 2.1, r2.0 . the capabilities pointer is located within standard csr space, in the new capability functions support bit (pcisr[4]). incorporates remaining software connection control resources. provides enum#, hot swap switch, and the blue led. early power support. incorporates a 1v precharge bias voltage to the pci i/o pins ? all pci bus signals are required to be precharged to a 1v bias through a 10k-ohm resistor during the hot swap process. the pci 9030 provides an internal voltage regulator to supply 1v, with a built-in 10k-ohm resistor, to all required pci i/o buffers. other pci signals can be precharged to v io . 8.2 controlling connection processes the following sections are excerpts from picmg 2.1, r2.0 . refer to this specification for more details. 8.2.1 connection control hardware control provides a means for the platform to control the hardware connection process. the signals listed in the following sections must be supported on all hot swap boards for interoperability. implementations on different platforms may vary. 8.2.1.1 board slot control bd_sel#, one of the shortest pins from the compactpci backplane, is driven low to enable power-on. for systems not implementing hardware control, it is grounded on the backplane. systems implementing hardware control radially connect bd_sel# to a hot swap controller (hsc). the controller terminates the signal with a weak pull-down, and can detect board present when the board pull-up overrides the pull-down. hsc can then control the power-on process by driving bd_sel# low. the pci 9030 uses the bd_sel# signal to three-state all local output buffers during the insertion and extraction process. in addition, the pci 9030 uses bd_sel# as a qualifier to dynamically connect 1v and v i/o precharge bias resistors to all required pci i/o buffers. a pull-up resistor must be provided to the bd_sel# pin or add-in card, where the pull-up resistor is connected to an early power power supply, which provides for proper pci 9030 operation. (refer to section 11, ? pin description, ? for precharge connections.)
section 8 compactpci hot swap controlling connection processes pci 9030 data book version 1.4 8-2 ? 2002 plx technology, inc. all rights reserved. figure 8-1. redirection of bd_sel# 8.2.1.2 board healthy a second radial signal is used to acknowledge board health. it signals that a board is suitable to be released from reset and allowed onto the pci bus. minimally, this signal must be connected to the board ? s power controller ? power good ? status line. use of healthy# can be expanded for applications requiring additional conditions to be met for the board to be considered healthy. on platforms that do not use hardware connection control, this line is not monitored. platforms implementing this signaling, route these signals radially to a hot swap controller. figure 8-2. board healthy 8.2.1.3 platform reset reset (pci_rst#), as defined by picmg 2.1, r2.0 , is a bus signal on the backplane, driven by the host. platforms may implement this signal as a radial signal from the hot swap controller to further control the electrical connection process. platforms that maintain function of the bus signal must or the host reset signal with the slot-specific signal. locally, boards must not exit reset until the h1 state is reached (healthy), and they must honor the backplane reset. the local board reset (local_pci_rst#) must be the logical or of these two conditions. local_pci_rst# is connected to the pci 9030 rst# input pin. during a precharge bias voltage and platform reset, in insertion and extraction procedures, all pci i/o buffers must be in a high-impedance state. the pci 9030 supports this condition when the host rst# is asserted. to protect the local board components from early power, the pci 9030 floats the local bus i/os. the bd_sel# pin is used to perform the high-impedance condition on the local bus. with full contact of the add-in card to the backplane, bd_sel# is asserted, which ensures that the pci 9030 asserts the lreseto# signal to complete a local board reset task. figure 8-3. pci reset 8.2.2 software connection control software connection control provides a means to control the software connection process. hot swap board resources facilitate software connection control. access to these resources occurs by way of the bus, using pci protocol transfers (in-band). these resources consist of four elements: enum# driven active indicates the need to change the hot swap board state a switch, tied to the ejector, indicates the intent to remove a board led indicates the software connection process status control/status register allows the software to interact with these resources 8.2.2.1 ejector switch and blue led a microswitch (switch), located in the hot swap compactpci board card-ejector mechanism, is used to signal impending board removal. this signal asserts enum#. when the switch is activated, it is necessary to wait for the led to turn on, indicating it is now okay to remove the board. the pci 9030 implements separate control logic for the microswitch and blue on pwr on present vio on power circuitry bd_sel# vio hsc no hardware control hardware control platform | board platform | board bd_sel# power circuitry healthy vio nc power circuitry hlty power circuitry hsc no hardware control hardware control platform | board platform | board host no hardware control host hsc hardware connection control platform | board healthy# platform | board pci_rst# healthy# local_pci_rst# local_pci_rst# pci_rst#
section 8 controlling connection processes compactpci hot swap pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 8-3 8 ? hot swap led in two different pins (cpcisw and ledon#, respectively). when the ejector is opened or closed, the switch bounces for a time. the pci 9030 uses internal debounce circuitry to clean the signal before the remainder of hot swap logic acknowledges it. the switch state is sampled six times, at 1 ms intervals, before it is determined to be closed or open. the blue ? status ? led, located on the front of the hot swap compactpci board, is turned on when it is permissible to remove a board. the hardware connection layer provides protection for the system during all insertions and extractions. this led indicates the system software is in a state that tolerates board extraction. upon insertion, the led is automatically turned on by the hardware until the hardware connection process completes. the led remains off until the software uses it to indicate extraction is once again permitted. the pci 9030 uses an open-drain output pin to sink the external led. the led state is driven from the led software on/off switch bit (hs_csr[3]). ledon# is also asserted during pci reset (rst# asserted). the cpcisw input signal acknowledges the state ejector handle change to identify when a board is inserted or removed. the appropriate status bits are set (hs_csr[7:6]=1). 8.2.2.2 enum# enum# is provided to notify the host cpu that a board was recently inserted or is about to be removed. this signal informs the cpu that system configuration changed, at which time the cpu performs necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver prior to board extraction. enum# is an open collector bused signal with a pull-up on the host bus. it may drive an interrupt (preferred) or be polled by the system software at regular intervals. the compactpci hot-plug system driver on the system host manages the enum# sensing. full hot swap boards assert enum# until serviced by the hot-plug system driver. when a board is inserted into the system and comes out of reset, the pci 9030 acknowledges the ejector switch state. if this switch is open (ejector handle closed), the pci 9030 asserts the enum# interrupt and sets the enum# status indicator for board insertion bit (hs_csr[7]). once the host cpu installs the proper drivers, it can logically include this board by clearing the interrupt. when a board is about to be removed, the pci 9030 acknowledges the ejector handle is open, asserts the enum# interrupt, and sets the enum# status indicator for the board removal bit (hs_csr[6]). the host then logically removes the board and turns on the led, at which time the board can be removed from the system. 8.2.2.3 hot swap control/status register (hs_csr) the pci 9030 supports hot swap directly, as a control/status register in configuration space. this register is accessed through the pci extended capabilities pointer (ecp) mechanism. the hot swap control/status register (hs_csr) provides status read-back for the hot-plug system software to determine which board is driving enum#. this register is also used to control the hot swap status led on the board front panel, and to de-assert enum#.
section 8 compactpci hot swap controlling connection processes pci 9030 data book version 1.4 8-4 ? 2002 plx technology, inc. all rights reserved. 8.2.2.4 hot swap capabilities register hot swap id. bits [7:0] (hs_cntl[7:0]; pci:48h). these bits are set to a default value of 06h. next_cap pointer. bits [15:8] (hs_next[7:0]; pci:49h). these bits either point to the next new capability structure, or are set to 0h if this is the last capability in the structure. bits [9:8] are reserved by pci r2.2 , and should be set to 00. control. bits [23:16] (hs_csr[7:0]; pci:4ah). this 8-bit control register is defined in table 8-1. 31 24 23 16 15 8 7 0 reserved control next_cap pointer hot swap id (06h) figure 8-4. hot swap capabilities table 8-1. hot swap control bit description 23 enum# status ? insertion (1 = board is inserted). 22 enum# status ? removal (1 = board is being removed). 21:20 programming interface 0 (pi = 0). 19 led state (1 = led on, 0 = led off). 18 not used. 17 enum# interrupt enable (1 = de-assert, 0 = enable interrupt). 16 not used.
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 9-1 9 ? vpd 9 pci vital product data (vpd) 9.1 overview the pci r2.2 vital product data (vpd) function defines a new location and access method. it also defines the read only and read/write bits. currently device id, vendor id, revision id, class code, subsystem id, and subsystem vendor id are required in the configuration space header and for basic device identification and configuration. although this information allows a device to be configured, it is not sufficient to allow a device to be uniquely identified. with the addition of vpd, optional information is provided that allows a device to be uniquely identified and tracked. these additional bits enable current and/ or future support tools and reduces the total cost of ownership of pcs and systems. this provides an alternate access method other than expansion rom for vpd. vpd is stored in an external serial eeprom, which is accessed using the configuration space new capabilities function. the vpd registers ? pvpdcntl, pvpd_next, pvpdad, and pvpdata ? are not accessible for reads from the local bus. the vpd function can be exercised only from the pci bus. 9.2 vpd capabilities register vpd id. bits [7:0] (pvpdcntl[7:0]; pci:4ch). the pci sig assigned these bits a value of 03h. the vpd id is hardwired. next_cap pointer. bits [15:8] (pvpd_next[7:0]; pci:4dh). these bits either point to the next new capability structure, or are set to 0 if this is the last capability in the structure. the pci 9030 defaults to 0h. this value can be overwritten from the serial eeprom. bits [9:8] are reserved by pci r2.2 and should be set to 00. vpd address. bits [24:16] (pvpdad[14:0]; pci:4eh). these bits specify the lword-aligned vpd byte address to be accessed. all accesses are 32-bit wide; bits [17:16] must be 00, with the maximum serial eeprom size being 4k bits. bits [30:25] are ignored. f. bit 31 (pvpdad[15]; pci:4eh). this bit sets a flag to indicate when a serial eeprom data operation completes. for write cycles, the four bytes of data are first written into the vpd data bits, after which the vpd address is written at the same time the f flag is set to 1. the f flag clears when the serial eeprom data transfer completes. for read cycles, the vpd address is written at the same time the f flag is cleared to 0. the f flag is set when four bytes of data are read from the serial eeprom. (refer to pci 9030 errata #1 .) vpd data. bits [31:0] (pvpdata[31:0]; pci:50h). the pvpdata register is not a pure read/write register. the data read from the register depends upon the last read operation performed in pvpdad[15]. vpd data is written or read through this register. least- significant byte corresponding to vpd byte at the address specified by the vpd address register. four bytes are always transferred between the register and the serial eeprom. 9.3 vpd serial eeprom partitioning to support vpd, the serial eeprom is partitioned into read-only and read/write sections. 9.4 sequential read only the first 1088 bits (136 bytes) of the serial eeprom contain read-only information. the read-only portion of the serial eeprom is loaded into the pci 9030, using a sequential read protocol to the serial eeprom and occurs after pci reset. sequential words are read by holding eecs asserted, following issuance of a serial eeprom read command. 31 30 16 15 8 7 0 f vpd address next_cap pointer (0h) vpd id (03h) vpd data figure 9-1. vpd capabilities
section 9 pci vital product data (vpd) random access read and write pci 9030 data book version 1.4 9-2 ? 2002 plx technology, inc. all rights reserved. 9.5 random access read and write the pci 9030 has full access to the read/write portion of the serial eeprom. the serial eeprom, starting at lword boundary for vpd accesses bits (prot_area[6:0]), designates this portion. this register is loaded upon power-on and can be written with a desired value, starting at location 0. this provides the capability of writing the entire serial eeprom. writes to the serial eeprom are comprised of the following commands: write enable write command, followed by the upper 16-bit write data write command, followed by the lower 16-bit write data write disable this is done to ensure against accidental write of the serial eeprom. randomly occurring cycles allow vpd information to be written and read at any time. to perform a simple vpd write to the serial eeprom, the following steps are necessary: 1. change the write-protected serial eeprom address in prot_area[6:0], if required. 00000000h makes the serial eeprom writable from the beginning. 2. write the desired data into the pvpdata register. 3. write the destination serial eeprom address and flag of operation to a value of 1. 4. probe the flag of operation until it changes to a 0 to ensure the write is complete. to perform a simple vpd read from the serial eeprom, the following steps are necessary: 1. write a destination serial eeprom address and flag of operation to a value of 0. 2. probe the flag of operation until it changes to a 1 to ensure the read data is available. 3. read back the pvpdata register to see the requested data.
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-1 10 ? registers 10 registers 10.1 new register definitions summary (as compared to the pci 9050 and pci 9052) refer to the description column in the following tables for a full explanation. table 10-1. new registers definitions summary (as compared to the pci 9050 and pci 9052) pci register address local offset from base address register bits description 34h ? new capability pointer 7:0 provides offset into pci configuration space for the location of the first item in the new capability linked list. 40h ? power management 31:0 provides power management id, power management next capability pointer, and power management capabilities. 44h ? power management 31:0 provides power management status, pmcsr bridge support extensions, and power management data. 48h ? compactpci hot swap 31:0 hot swap control, hot swap next capability pointer, and hot swap control/status register. 4ch ? pci vital product data 31:0 vpd id, vpd next capability pointer, and vpd address pointer. 50h ? pci vital product data 31:0 vpd data. ? 4eh serial eeprom write-protected address boundary 6:0 15:7 serial eeprom write-protected address boundary. reserved . ? 50h pci target response, serial eeprom, and initialization control 5:0 6 7 8 9 11:10 31 reserved . pci target write fifo full condition. local arbiter lgnt select enable. local ready timeout enable. local ready timeout select. pci target delayed write mode access select. disconnect with flush read fifo. ? 54h general purpose i/o control 26:0 31:27 gpio[8:0] control select bits. reserved. ? 70h hidden 1 power management data select 31:0 data select register for power consumed and dissipated. written only by the serial eeprom. ? 74h hidden 2 power management data scale 7:0 31:8 data scale factor values for power consumed and dissipated. written only by the serial eeprom. reserved.
section 10 registers register address mapping pci 9030 data book version 1.4 10-2 ? 2002 plx technology, inc. all rights reserved. 10.2 register address mapping note: refer to pci r2.2 for definitions of these registers. table 10-2. pci configuration register address mapping pci configuration register address to ensure software compatibility with other versions of the pci 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. pci writable serial eeprom writable 31 30 24 23 16 15 8 7 0 00h device id vendor id n y 04h status command y y [20] 08h class code revision id n y 0ch built-in self test (not supported) header type pci bus latency timer (not supported) cache line size y [7:0] n 10h pci base address 0 for memory accesses to local configuration registers y n 14h pci base address 1 for i/o accesses to local configuration registers y n 18h pci base address 2 for accesses to local address space 0 y n 1ch pci base address 3 for accesses to local address space 1 y n 20h pci base address 4 for accesses to local address space 2 y n 24h pci base address 5 for accesses to local address space 3 y n 28h pci cardbus information structure (cis) pointer (not supported) nn 2ch subsystem id subsystem vendor id n y 30h pci base address for local expansion rom y n 34h reserved new_cap pointer n y [7:0] 38h reserved nn 3ch maximum latency (not supported) minimum grant (not supported) interrupt pin interrupt line y [7:0] y [15:8] 40h power management capabilities power management next_cap pointer power management capability id n y [30:27, 21, 19:16, 15:8] 44h power management data pmcsr bridge support extensions power management control/status y [15, 12:8, 1:0] y [12:8] 48h reserved hot swap control/status hot swap next_cap pointer hot swap capability id y [23:16] y [15:0] 4ch f vpd address vpd next_cap pointer vpd capability id y [31:16] y [15:8] 50h vpd data y n
section 10 register address mapping registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-3 10 ? registers table 10-3. local configuration register address mapping pci (offset from base address) to ensure software compatibility with other versions of the pci 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 0 pci writable serial eeprom writable 00h local address space 0 range y y 04h local address space 1 range y y 08h local address space 2 range y y 0ch local address space 3 range y y 10h expansion rom range y y 14h local address space 0 local base address (remap) y y 18h local address space 1 local base address (remap) y y 1ch local address space 2 local base address (remap) y y 20h local address space 3 local base address (remap) y y 24h expansion rom local base address (remap) y y 28h local address space 0 bus region descriptor y y 2ch local address space 1 bus region descriptor y y 30h local address space 2 bus region descriptor y y 34h local address space 3 bus region descriptor y y 38h expansion rom bus region descriptor y y table 10-4. chip select register address mapping pci (offset from base address) to ensure software compatibility with other versions of the pci 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 0 pci writable serial eeprom writable 3ch chip select 0 base address y y 40h chip select 1 base address y y 44h chip select 2 base address y y 48h chip select 3 base address y y table 10-5. control register address mapping pci (offset from base address) to ensure software compatibility with other versions of the pci 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 28 27 24 23 16 15 0 pci writable serial eeprom writable 4ch reserved serial eeprom write-protected address boundary interrupt control/status y [31:8] y 50h pci target response, serial eeprom control, and initialization control y y 54h reserved general purpose i/o control y y 70h hidden 1 register for power management data select, power consumed and dissipated values n y 74h hidden 2 register for power management data scale, power consumed and dissipated values n y
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-4 ? 2002 plx technology, inc. all rights reserved. 10.3 pci configuration registers all registers may be written to or read from in byte, word, or lword accesses. register 10-1. (pciidr; pci:00h) pci configuration id bit description read write value after reset 15:0 vendor id. identifies manufacturer of device. defaults to the pci sig-issued vendor id of plx (10b5h) if blank or if no serial eeprom is present. yes serial eeprom 10b5h 31:16 device id. identifies particular device. defaults to plx part number for pci interface chip (9030h) if blank or no serial eeprom is present. yes serial eeprom 9030h register 10-2. (pcicr; pci:04h) pci command bit description read write value after reset 0 i/o space. writing 1 allows the device to respond to i/o space accesses. writing 0 disables the device from responding to i/o space accesses. yes yes 0 1 memory space. writing 1 allows the device to respond to memory space accesses. writing 0 disables the device from responding to memory space accesses. yes yes 0 2 master enable. not supported. yes no 0 3 special cycle. not supported . yes no 0 4 memory write and invalidate enable. not supported. yes no 0 5 vga palette snoop. not supported. yes no 0 6 parity error response. writing 0 indicates parity error is ignored and the operation continues. writing 1 indicates parity checking is enabled. yes yes 0 7 stepping control. controls whether a device does address/data stepping. writing 0 indicates the device never does stepping. writing 1 indicates the device always does stepping. note: hardwired to 0. yes no 0 8 serr# enable. writing 1 enables serr# driver. writing 0 disables serr# driver. yes yes 0 9 fast back-to-back enable. indicates what type of fast back-to-back transfers a master can perform on the bus. writing 1 indicates fast back-to-back transfers can occur to any agent on the bus. writing 0 indicates fast back-to- back transfers can occur only to the same agent as in the previous cycle. note: hardwired to 0. yes no 0 15:10 reserved . yes no 0h
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-5 10 ? registers register 10-3. (pcisr; pci:06h) pci status bit description read write value after reset 3:0 reserved. yes no 0h 4 new capability functions support. writing 1 supports new capabilities functions. if enabled, the first new capability function id is located at the pci configuration space offset determined by the new capabilities linked list pointer value at offset 34h. can be written only from the serial eeprom. read-only from the pci bus. yes serial eeprom 1 6:5 reserved. yes no 0 7 fast back-to-back capable. writing 1 indicates an adapter can accept fast back-to-back transactions. note: hardwired to 1. yes no 1 8 master data parity error. not supported. yes no 0 10:9 devsel# timing. indicates timing for devsel# assertion. writing 01 sets this bit to medium. note: hardwired to 01. yes no 01 11 signaled target abort. when set to 1, indicates the pci 9030 signaled a target abort. writing 1 clears this bit to 0. yes yes/clr 0 12 received target abort. when set to 1, indicates the pci 9030 received a target abort signal. not supported. yes no 0 13 received master abort. when set to 1, indicates the pci 9030 received a master abort signal. not supported. yes no 0 14 signaled system error. when set to 1, indicates the pci 9030 reported a system error on serr#. writing 1 clears this bit to 0. yes yes/clr 0 15 detected parity error. when set to 1, indicates the pci 9030 detected a pci bus parity error, even if parity error handling is disabled [the parity error response bit in the command register is clear (pcicr[6]=0]. this bit is set when the pci 9030 detects a parity error during a pci address phase or a pci data phase when it is the target of a write. writing 1 clears this bit to 0. yes yes/clr 0 register 10-4. (pcirev; pci:08h) pci revision id bit description read write value after reset 7:0 revision id. pci 9030 silicon revision. yes serial eeprom current rev # register 10-5. (pciccr; pci:09-0bh) pci class code bit description read write value after reset 7:0 register level programming interface. none defined. yes serial eeprom 0h 15:8 subclass code (other bridge device). yes serial eeprom 80h 23:16 base class code (bridge device). yes serial eeprom 06h
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-6 ? 2002 plx technology, inc. all rights reserved. register 10-6. (pciclsr; pci:0ch) pci cache line size bit description read write value after reset 7:0 system cache line size. specified in units of 32-bit words (8 or 16 lwords). can be written and read; however, the value does not affect pci 9030 operation. yes yes 0h register 10-7. (pciltr; pci:0dh) pci bus latency timer bit description read write value after reset 7:0 pci bus latency timer. not supported . yes no 0h register 10-8. (pcihtr; pci:0eh) pci header type bit description read write value after reset 6:0 configuration layout type. specifies layout of registers 10h through 3fh in configuration space. header type 0 is defined for all pci devices other than pci-to-pci bridges (header type 1) and cardbus bridges (header type 2). yes no 0h 7 multi-function device. value of 1 indicates multiple (up to eight) functions (logical devices) each containing its own, individually addressable configuration space, 64 lwords in size. note: hardwired to 0 (that is, device is single function, as multi-function = false). yes no 0 register 10-9. (pcibistr; pci:0fh) pci built-in self test (bist) bit description read write value after reset 7:0 built-in self test. value of 0 indicates device passed its test. not supported . yes no 0h
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-7 10 ? registers note: pcibar0 can be enabled or disabled by using cntrl[13:12]. note: pcibar1 can be enabled or disabled by using cntrl[13:12]. register 10-10. (pcibar0; pci:10h) pci base address 0 for memory accesses to local configuration registers bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. note: hardwired to 0. yes no 0 2:1 register location. values: 00 = locate anywhere in 32-bit memory address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit memory address space 11 = reserved note: hardwired to 00. yes no 00 3 prefetchable. writing 1 indicates there are no side effects on reads. does not affect pci 9030 operation. note: hardwired to 0. yes no 0 6:4 memory base address. memory base address for access to local configuration registers (requires 128 bytes). note: hardwired to 000. yes no 000 31:7 memory base address. memory base address for access to local configuration registers. yes yes 0h register 10-11. (pcibar1; pci:14h) pci base address 1 for i/o accesses to local configuration registers bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. note: hardwired to 1. yes no 1 1 reserved. yes no 0 6:2 i/o base address. base address for i/o access to local configuration registers (requires 128 bytes). note: hardwired to 0h. yes no 0h 31:7 i/o base address. base address for i/o access to local configuration registers. yes yes 0h
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-8 ? 2002 plx technology, inc. all rights reserved. note: if allocated, local address space 0 can be enabled or disabled by setting or clearing las0ba[0]. note: if allocated, local address space 1 can be enabled or disabled by setting or clearing las1ba[0]. register 10-12. (pcibar2; pci:18h) pci base address 2 for accesses to local address space 0 bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. (specified in the las0rr register.) yes no 0 2:1 register location (if memory space). values: 00 = locate anywhere in 32-bit memory address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in the las0rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 00 3 prefetchable (if memory space). writing 1 indicates there are no side effects on reads. reflects value of las0rr[3] and provides only status to the system. does not affect pci 9030 operation. the associated bus region descriptor register (las0brd) controls prefetching functions of this address space. (specified in the las0rr register.) if i/o space, bit 3 is included in the base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 0. yes yes 0h register 10-13. (pcibar3; pci:1ch) pci base address 3 for accesses to local address space 1 bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. (specified in the las1rr register.) yes no 0 2:1 register location. values: 00 = locate anywhere in 32-bit memory address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in the las1rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 00 3 prefetchable (if memory space). writing 1 indicates there are no side effects on reads. reflects value of las1rr[3] and provides only status to the system. does not affect pci 9030 operation. the associated bus region descriptor register (las1brd) controls prefetching functions of this address space. (specified in the las1rr register.) if i/o space, bit 3 is included in base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 1. yes yes 0h
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-9 10 ? registers note: if allocated, local address space 2 can be enabled or disabled by setting or clearing las2ba[0]. note: if allocated, local address space 3 can be enabled or disabled by setting or clearing las3ba[0]. register 10-14. (pcibar4; pci:20h) pci base address 4 for accesses to local address space 2 bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. (specified in the las2rr register.) yes no 0 2:1 register location. values: 00 = locate anywhere in 32-bit memory address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in the las2rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 00 3 prefetchable (if memory space). writing 1 indicates there are no side effects on reads. reflects value of las2rr[3] and provides only status to the system. does not affect pci 9030 operation. the associated bus region descriptor register (las2brd) controls prefetching functions of this address space. (specified in the las2rr register.) if i/o space, bit 3 is included in base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 2. yes yes 0h register 10-15. (pcibar5; pci:24h) pci base address 5 for accesses to local address space 3 bit description read write value after reset 0 memory space indicator. writing 0 indicates the register maps into memory space. writing 1 indicates the register maps into i/o space. (specified in the las3rr register.) yes no 0 2:1 register location . values: 00 = locate anywhere in 32-bit memory address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in the las3rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 00 3 prefetchable (if memory space). writing 1 indicates there are no side effects on reads. reflects value of las3rr[3] and provides only status to the system. does not affect pci 9030 operation. the associated bus region descriptor register (las3brd) controls prefetching functions of this address space. (specified in the las3rr register.) if i/o space, bit 3 is included in base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 3. yes yes 0h
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-10 ? 2002 plx technology, inc. all rights reserved. register 10-16. (pcicis; pci:28h) pci cardbus information structure pointer bit description read write value after reset 31:0 cardbus information structure (cis) pointer for pc cards. not supported . yes no 0h register 10-17. (pcisvid; pci:2ch) pci subsystem vendor id bit description read write value after reset 15:0 subsystem vendor id (unique add-in board vendor id). yes serial eeprom 0h register 10-18. (pcisid; pci:2eh) pci subsystem id bit description read write value after reset 15:0 subsystem id (unique add-in board device id). yes serial eeprom 0h register 10-19. (pcierbar; pci:30h) pci expansion rom base address bit description read write value after reset 0 address decode enable. writing 1 indicates a device accepts accesses to the expansion rom address. writing 0 indicates a device does not accept accesses to expansion rom address. should be set to 0 if there is no expansion rom. works in conjunction with eromrr[0]. yes yes 0 10:1 reserved . yes no 0h 31:11 expansion rom base address (upper 21 bits). yes yes 0h register 10-20. (cap_ptr; pci:34h) new capability pointer bit description read write value after reset 7:0 new capability pointer. provides an offset into pci configuration space for location of the first item in the new capabilities linked list. bits [1:0] are reserved by pci r2.2 , and should be set to 00 (the byte value points to an lword boundary.) note: these bits must always contain the default value 40h. (refer to pci 9030 errata #9.) yes serial eeprom 40h 31:8 reserved. yes no 0h
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-11 10 ? registers register 10-21. (pciilr; pci:3ch) pci interrupt line bit description read write value after reset 7:0 interrupt line routing value. indicates to which system interrupt controller(s) input the interrupt line is connected. the pci 9030 does not use this value, rather the value is used by device drivers and operating systems for priority and vector information. values in this register are system-architecture specific. for x86-based pcs, the values in this register correspond to irq numbers (0 through 15) of the standard dual 8259 interrupt controller configuration. the value 255 is defined as ? unknown ? or ? no connection ? to the interrupt controller. values 15 through 255 are reserved . yes yes 0h register 10-22. (pciipr; pci:3dh) pci interrupt pin bit description read write value after reset 7:0 interrupt pin register. indicates which interrupt pin the device uses. the following values are decoded: 0h = no interrupt pin 1h = inta# 2h = intb# 3h = intc# 4h = intd# the pci 9030 supports only inta#. because pcihtr[7]=0, values 2h, 3h, and 4h have no meaning. all other values (05h ? ffh) are reserved by pci r2.2 . yes serial eeprom 1h register 10-23. (pcimgr; pci:3eh) pci minimum grant bit description read write value after reset 7:0 min_gnt. specifies the length required for a burst period device, assuming a clock rate of 33 mhz. value is a multiple of 1/4 s increments. not supported . yes no 0h register 10-24. (pcimlr; pci:3fh) pci maximum latency bit description read write value after reset 7:0 max_lat. specifies how often the device must gain access to the pci bus. value is a multiple of 1/4 s increments. not supported . yes no 0h
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-12 ? 2002 plx technology, inc. all rights reserved. register 10-25. (pmcapid; pci:40h) power management capability id bit description read write value after reset 7:0 power management capability id. yes no 1h register 10-26. (pmnext; pci:41h) power management next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for location of the next item in the new capabilities linked list. bits [1:0] are reserved by pci r2.2 , and should be set to 00 (the byte value points to an lword boundary). if power management is the last capability in the list, set to 0h. yes serial eeprom 48h register 10-27. (pmc; pci:42h) power management capabilities bit description read write value after reset 2:0 version. the value 001 indicates compliance with pci bus power management interface specification, revision 1.0 , and its definition for pmc register format. this value can be changed in serial eeprom to 010 to indicate compliance with pci power mgmt. r1.1 . (refer to pci 9030 design note #1 for pmc register definition under pci power mgmt. r1.1 .) yes serial eeprom 001 3 pci clock required for pme# signal. when set to 1, indicates a function relies on pci clock presence for pme# operation. the pci 9030 does not require the pci clock for pme#, so this bit should be set to 0 in serial eeprom. yes serial eeprom 0 4 auxiliary power source. because the pci 9030 does not support pme# while in a d 3 cold state, this bit is always set to 0. not supported. yes no 0 5 device-specific initialization (dsi). when set to 1, the pci 9030 requires special initialization following a transition to a d 0 uninitialized state before a generic class device driver is able to use it. yes serial eeprom 0 8:6 reserved. yes no 000 9 d 1 _support. when set to 1, the pci 9030 supports the d 1 power state. not supported. yes no 0 10 d 2 _support. when set to 1, the pci 9030 supports the d 2 power state. not supported. yes no 0 15:11 pme_support. indicates power states in which the pci 9030 may assert pme#. values: xxxx1 = pme# can be asserted from d 0 xxxxx = the pci 9030 does not support the d 1 power state xxxxx = the pci 9030 does not support the d 2 power state x1xxx = pme# can be asserted from d 3hot xxxxx = pme# cannot be asserted from d 3cold yes [14:11]: serial eeprom [15]: no 01001
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-13 10 ? registers register 10-28. (pmcsr; pci:44h) power management control/status bit description read write value after reset 1:0 power state. determines or changes the current power state. values: 00 = d 0 11 = d 3hot transition from a d 3hot state to a d 0 state causes a soft reset, lreseto# assertion, an lpmint# pulse, clearing of local configuration registers (including the chip select and control registers), and reloading of the configuration registers from the serial eeprom. in a d 3hot state, pci memory and i/o accesses are disabled, as well as pci interrupts, and only configuration is allowed. yes yes 00 7:2 reserved. yes no 0h 8 pme_en. writing 1 enables pme# to be asserted. yes yes/ serial eeprom 0 12:9 data_select. selects which data to report through the data register and data_scale bits. yes yes/ serial eeprom 0h 14:13 data_scale. indicates the scaling factor to use when interpreting the data register value. value and meaning of this bit depends on the data value selected by the data_select bit. when the local cpu initializes the data_scale values, it must use the data_select bit to determine which data_scale value it is writing. for power consumed and power dissipated data, the following scale factors are used. unit values are in watts. values: 0 = unknown 1 = 0.1x 2 = 0.01x 3 = 0.001x note: information regarding hidden register use is provided in section 7.2.1. yes serial eeprom by way of pmdatascale 00 15 pme_status. indicates pme# is being driven if the pme_en bit is set (pmcsr[8]=1). asserting lpmeset input high sets this bit; writing 1 from the pci bus clears this bit to 0. depending on the current power state, set only if the appropriate pme_support bit(s) is set ( for example , pmc[15:11]=1). yes local interrupt/set, pci/clr 0 register 10-29. (pmcsr_bse; pci:46h) pmcsr bridge support extensions bit description read write value after reset 7:0 reserved. yes no 0h
section 10 registers pci configuration registers pci 9030 data book version 1.4 10-14 ? 2002 plx technology, inc. all rights reserved. register 10-30. (pmdata; pci:47h) power management data bit description read write value after reset 7:0 power management data. provides operating data, such as power consumed or heat dissipation. data returned is selected by the data_select bit(s) (pmcsr[12:9]) and scaled by the data_scale bit(s) (pmcsr[14:13]). data select values: 0 = d 0 power consumed 1 = reserved 2 = reserved 3 = d 3 power consumed 4 = d 0 power dissipated 5 = reserved 6 = reserved 7 = d 3hot power dissipated note: information regarding hidden register use is provided in section 7.2.1. yes serial eeprom by way of pmdatasel 0h register 10-31. (hs_cntl; pci:48h) hot swap control bit description read write value after reset 7:0 hot swap id. capability id = 06h for hot swap. yes serial eeprom 06h register 10-32. (hs_next; pci:49h) hot swap next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for location of the next item in the new capabilities linked list. bits [1:0] are reserved by pci r2.2 , and should be set to 00 (the byte value points to an lword boundary). if hot swap is the last capability in the list, set to 0h. yes serial eeprom 4ch register 10-33. (hs_csr; pci:4ah) hot swap control/status bit description read write value after reset 0 reserved. yes no 0 1 enum# interrupt mask (eim). writing 0 enables the interrupt. writing 1 masks the interrupt. yes pci 0 2 reserved. yes no 0 3 led software on/off switch. writing 1 turns on the led. writing 0 turns off the led. yes pci 0 5:4 programming interface 0 (pi = 0). yes no 00 6 enum# status indicator for board removal. value of 1 reports the enum# assertion for removal process. writing 1 clears the enum# interrupt and status bit. yes pci/clr 0 7 enum# status indicator for board insertion. value of 1 reports the enum# assertion for the insertion process. writing 1 clears the enum# interrupt and status bit. yes pci/clr 0 15:8 reserved. yes no 0h
section 10 pci configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-15 10 ? registers register 10-34. (pvpdcntl; pci:4ch) pci vital product data control bit description read write value after reset 7:0 vpd id. capability id = 03h for vpd. pci no 03h register 10-35. (pvpd_next; pci:4dh) pci vital product data next capability pointer bit description read write value after reset 7:0 next_cap pointer. provides an offset into pci configuration space for location of the next item in the new capabilities linked list. bits [1:0] are reserved by pci r2.2 , and should be set to 00 (the byte value points to an lword boundary). because vpd is the last capability in the list, set to 0h. pci serial eeprom 0h register 10-36. (pvpdad; pci:4eh) pci vital product data address bit description read write value after reset 14:0 vpd address. lword-aligned byte address of the vpd address to be accessed. all accesses are 32-bit wide; bits [1:0] must be 00, with the maximum serial eeprom size being 4k bits (supports 2k or 4k bit serial eeprom). bits [14:9] are ignored. pci yes 0h 15 f. flag used to indicate when the data transfer between pvpdata and the storage component completes. writing 0 along with the vpd address causes a read of vpd information into pvpdata. the hardware sets this bit to 1 when the vpd data transfer completes. writing 1 along with the vpd address causes a write of vpd information from pvpdata into a storage component. the hardware sets this bit to 0 after the write operation completes. (refer to pci 9030 errata #1 .) pci yes 0 register 10-37. (pvpdata; pci:50h) pci vpd data bit description read write value after reset 31:0 vpd data register. pci yes 0h
section 10 registers local configuration registers pci 9030 data book version 1.4 10-16 ? 2002 plx technology, inc. all rights reserved. 10.4 local configuration registers register 10-38. (las0rr; 00h) local address space 0 range bit description read write value after reset 0 memory space indicator. writing 0 indicates local address space 0 maps into pci memory space. writing 1 indicates local address space 0 maps into pci i/o space. yes yes 0 2:1 when mapped into memory space, encoding is as follows: 00 = locate anywhere in 32-bit pci address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit pci address space 11 = reserved when mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [27:3] to indicate the decoding range. yes yes 00 3 when mapped into memory space, writing 1 indicates reads are prefetchable (does not affect pci 9030 operation, but is used for system status). when mapped into i/o space, it is included with bits [27:2] to indicate the decoding range. yes yes 0 27:4 specifies which pci address bits to use for decoding a pci access to local address space 0. each bit corresponds to a pci address bit. bit 27 corresponds to address bit 27. write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with pcibar2). default is 1mb. notes: range ( not range register) must be power of 2. ? range register value ? is two ? s complement of range. user should limit each i/o-mapped space to 256 bytes per pci r2.2. yes yes ff0000h 31:28 reserved. (pci address bits [31:28] are always included in decoding.) yes no 0h register 10-39. (las1rr; 04h) local address space 1 range bit description read write value after reset 0 memory space indicator. writing 0 indicates local address space 1 maps into pci memory space. writing 1 indicates local address space 1 maps into pci i/o space. yes yes 0 2:1 when mapped into memory space, encoding is as follows: 00 = locate anywhere in 32-bit pci address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit pci address space 11 = reserved when mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [27:3] to indicate the decoding range. yes yes 00 3 when mapped into memory space, writing 1 indicates reads are prefetchable (does not affect pci 9030 operation, but is used for system status). when mapped into i/o space, it is included with bits [27:2] to indicate the decoding range. yes yes 0 27:4 specifies which pci address bits to use for decoding a pci access to local address space 1. each bit corresponds to a pci address bit. bit 27 corresponds to address bit 27. write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with pcibar3). notes: range ( not range register) must be power of 2. ? range register value ? is two ? s complement of range. user should limit each i/o-mapped space to 256 bytes per pci r2.2. yes yes 0h 31:28 reserved. (pci address bits [31:28] are always included in decoding.) yes no 0h
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-17 10 ? registers register 10-40. (las2rr; 08h) local address space 2 range bit description read write value after reset 0 memory space indicator. writing 0 indicates local address space 2 maps into pci memory space. writing 1 indicates local address space 2 maps into pci i/o space. yes yes 0 2:1 when mapped into memory space, encoding is as follows: 00 = locate anywhere in 32-bit pci address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit pci address space 11 = reserved when mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [27:3] to indicate the decoding range. yes yes 00 3 when mapped into memory space, writing 1 indicates reads are prefetchable (does not affect pci 9030 operation, but is used for system status). when mapped into i/o space, it is included with bits [27:2] to indicate the decoding range. yes yes 0 27:4 specifies which pci address bits to use for decoding a pci access to local address space 2. each bit corresponds to a pci address bit. bit 27 corresponds to address bit 27. write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with pcibar4). notes: range ( not range register) must be power of 2. ? range register value ? is two ? s complement of range. user should limit each i/o-mapped space to 256 bytes per pci r2.2. yes yes 0h 31:28 reserved. (pci address bits [31:28] are always included in decoding.) yes no 0h register 10-41. (las3rr; 0ch) local address space 3 range bit description read write value after reset 0 memory space indicator. writing 0 indicates local address space 3 maps into pci memory space. writing 1 indicates local address space 3 maps into pci i/o space. yes yes 0 2:1 when mapped into memory space, encoding is as follows: 00 = locate anywhere in 32-bit pci address space 01 = pci r2.1 , locate below 1-mb memory address space pci r2.2 , reserved 10 = locate anywhere in 64-bit pci address space 11 = reserved when mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [27:3] to indicate the decoding range. yes yes 00 3 when mapped into memory space, writing 1 indicates reads are prefetchable (does not affect pci 9030 operation, but is used for system status). when mapped into i/o space, it is included with bits [27:2] to indicate the decoding range. yes yes 0 27:4 specifies which pci address bits to use for decoding a pci access to local address space 3. each bit corresponds to a pci address bit. bit 27 corresponds to address bit 27. write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with pcibar5). notes: range ( not range register) must be power of 2. ? range register value ? is two ? s complement of range. user should limit each i/o-mapped space to 256 bytes per pci r2.2. yes yes 0h 31:28 reserved. (pci address bits [31:28] are always included in decoding.) yes no 0h
section 10 registers local configuration registers pci 9030 data book version 1.4 10-18 ? 2002 plx technology, inc. all rights reserved. register 10-42. (eromrr; 10h) expansion rom range bit description read write value after reset 0 address decode enable. bit 0 can only be enabled from the serial eeprom. to disable, set the pci expansion rom address decode enable bit to 0 (pcierbar[0]=0). yes serial eeprom only 0 10:1 reserved. yes no 0h 27:11 specifies which pci address bits to use for decoding a pci-to-local bus expansion rom. each bit corresponds to a pci address bit. bit 27 corresponds to address bit 27. write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with pcierbar). default is 64 kb; minimum range, if enabled, is 2 kb, and maximum range allowed by pci r2.2 is 16 mb. note: range (not range register) must be power of 2. ? range register value ? is two ? s complement of range. eromrr should normally be programmed by way of the serial eeprom to a value of 0h, unless expansion rom is present on the local bus. if the value is not 0h (default value is 64 kb), system bios may attempt to allocate expansion rom address space and th en access it at the local base address specified in eromba (default value is 1 mb) to determine whether the expansion rom image is valid. if the image is not valid, as defined in section 6.3.1.1 (pci expansion rom header format) of pci r2.2, the system bios unmaps the expansion rom address space it initially allocated, by writing 0h to pcierbar[31:0]. yes yes 1111111111110 0000 31:28 reserved. (pci address bits [31:28] are always included in decoding.) yes yes 1111
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-19 10 ? registers register 10-43. (las0ba; 14h) local address space 0 local base address (remap) bit description read write value after reset 0 space 0 enable. writing 1 enables decoding of pci addresses for pci target access to local address space 0. writing 0 disables decoding. yes yes 1 1 reserved. yes no 0 3:2 if local address space 0 is mapped into memory space, bits are not used. when mapped into i/o space, included with bits [27:4] for remapping. yes yes 00 27:4 remap pcibar2 base address to local address space 0 base address. the pcibar2 base address translates to the local address space 0 base address programmed in this register. a pci target access to an offset from pcibar2 maps to the same offset from this local base address. notes: remap address value must be a range multiple ( not the range register). yes yes 0h 31:28 reserved. (local address bits [31:28] do not exist in the pci 9030.) yes no 0h register 10-44. (las1ba; 18h) local address space 1 local base address (remap) bit description read write value after reset 0 space 1 enable. writing 1 enables decoding of pci addresses for pci target access to local address space 1. writing 0 disables decoding. pcibar3 can be enabled or disabled by setting or clearing this bit . yes yes 0 1 reserved. yes no 0 3:2 if local address space 1 is mapped into memory space, bits are not used. when mapped into i/o space, included with bits [27:4] for remapping. yes yes 00 27:4 remap pcibar3 base address to local address space 1 base address. the pcibar3 base address translates to the local address space 1 base address programmed in this register. a pci target access to an offset from pcibar3 maps to the same offset from this local base address. note: remap address value must be a range multiple ( not the range register). yes yes 0h 31:28 reserved. (local address bits [31:28] do not exist in the pci 9030.) yes no 0h
section 10 registers local configuration registers pci 9030 data book version 1.4 10-20 ? 2002 plx technology, inc. all rights reserved. register 10-45. (las2ba; 1ch) local address space 2 local base address (remap) bit description read write value after reset 0 space 2 enable. writing 1 enables decoding of pci addresses for pci target access to local address space 2. writing 0 disables decoding. pcibar4 can be enabled or disabled by setting or clearing this bit . yes yes 0 1 reserved. yes no 0 3:2 if local address space 2 is mapped into memory space, bits are not used. when mapped into i/o space, included with bits [27:4] for remapping. yes yes 00 27:4 remap pcibar4 base address to local address space 2 base address. the pcibar4 base address translates to the local address space 2 base address programmed in this register. a pci target access to an offset from pcibar4 maps to the same offset from this local base address. note: remap address value must be a range multiple ( not the range register). yes yes 0h 31:28 reserved. (local address bits [31:28] do not exist in the pci 9030.) yes no 0h register 10-46. (las3ba; 20h) local address space 3 local base address (remap) bit description read write value after reset 0 space 3 enable. writing 1 enables decoding of pci addresses for pci target access to local address space 3. writing 0 disables decoding. pcibar5 can be enabled or disabled by setting or clearing this bit . yes yes 0 1 reserved. yes no 0 3:2 if local address space 3 is mapped into memory space, bits are not used. when mapped into i/o space, included with bits [27:4] for remapping. yes yes 00 27:4 remap pcibar5 base address to local address space 3 base address. the pcibar5 base address translates to the local address space 3 base address programmed in this register. a pci target access to an offset from pcibar5 maps to the same offset from this local base address. note: remap address value must be a range multiple ( not the range register). yes yes 0h 31:28 reserved. (local address bits [31:28] do not exist in the pci 9030.) yes no 0h register 10-47. (eromba; 24h) expansion rom local base address (remap) bit description read write value after reset 10:0 reserved. yes no 0h 27:11 remap pci expansion rom space into local address space. bits in this register remap (replace) the pci address bits used in decode as local address bits. note: remap address value must be a range multiple ( not the range register). yes yes 0000000100000 0000 31:28 reserved. (local address bits [31:28] do not exist in the pci 9030.) yes no 0h
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-21 10 ? registers register 10-48. (las0brd; 28h) local address space 0 bus region descriptor bit description read write value after reset 0 local address space 0 burst enable. writing 1 enables bursting. writing 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. pci reads are completed as single cycle on the pci bus if local burst is disabled or prefetch is disabled (bits [5:3]=100). yes yes 0 1 local address space 0 ready# input enable. writing 1 enables ready# input. writing 0 disables ready# input. yes yes 0 2 local address space 0 bterm# input enable. writing 1 enables bterm# input. writing 0 disables bterm# input. for more information, refer to section 2.2.4.3. yes yes 0 4:3 prefetch count. number of lwords to prefetch during memory read cycle. used only if bit 5 is high (prefetch counter enabled). values: 00 = do not prefetch. only read bytes specified by c/be lines. 01 = prefetch four lwords if bit 5 is set. 10 = prefetch eight lwords if bit 5 is set. 11 = prefetch 16 lwords if bit 5 is set. yes yes 00 5 prefetch counter enable. when set to 1 and the prefetch count is not 00, the pci 9030 prefetches up to the number of lwords specified in the prefetch count. when set to 0, the pci 9030 ignores the count and continues prefetching, until terminated by pci bus transaction completion if read ahead mode is disabled (cntrl[16]=0), or if read ahead mode is enabled, until the read fifo fills. to disable prefetch, enable the prefetch counter and set the prefetch count to 0 (bits [5:3]=100) . yes yes 0 10:6 nrad wait states. number of read address-to-data wait states (0-31). (wait states between the address cycle and first read data cycle.) yes yes 00000 12:11 nrdd wait states. number of read data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst read.) yes yes 00 14:13 nxda wait states. number of read/write data-to-address wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) yes yes 00 19:15 nwad wait states. number of write address-to-data wait states (0-31). lad/ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) yes yes 00000 21:20 nwdd wait states. number of write data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst write.) yes yes 00 23:22 local address space 0 local bus width. writing of the following values indicates the associated bus width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved yes yes 10
section 10 registers local configuration registers pci 9030 data book version 1.4 10-22 ? 2002 plx technology, inc. all rights reserved. 24 byte ordering. value of 1 indicates big endian. value of 0 indicates little endian. yes yes 0 25 big endian byte lane mode. writing 1 specifies that in big endian mode, use byte lanes [31:16] for a 16-bit local bus and byte lanes [31:24] for an 8-bit local bus. writing 0 specifies that in big endian mode, use byte lanes [15:0] for a 16-bit local bus and byte lanes [7:0] for an 8-bit local bus. yes yes 0 27:26 read strobe delay. number of clocks from beginning of cycle until rd# strobe is asserted (0-3). value must be nrad for rd# to be asserted. yes yes 00 29:28 write strobe delay. number of clocks from beginning of cycle until wr# strobe is asserted (0-3). value must be nwad for wr# to be asserted. yes yes 00 31:30 write cycle hold. number of clocks from wr# de-assertion until end of cycle (0-3). data (lad/ld[31:0]) remains valid, and blast# remains asserted, during write cycle hold bus cycles. yes yes 00 register 10-48. (las0brd; 28h) local address space 0 bus region descriptor (continued) bit description read write value after reset
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-23 10 ? registers register 10-49. (las1brd; 2ch) local address space 1 bus region descriptor bit description read write value after reset 0 local address space 1 burst enable. writing 1 enables bursting. writing 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. pci reads are completed as single cycle on the pci bus if local burst is disabled or prefetch is disabled (bits [5:3]=100). yes yes 0 1 local address space 1 ready# input enable. writing 1 enables ready# input. writing 0 disables ready# input. yes yes 0 2 local address space 1 bterm# input enable. writing 1 enables bterm# input. writing 0 disables bterm# input. for more information, refer to section 2.2.4.3. yes yes 0 4:3 prefetch count. number of lwords to prefetch during memory read cycle. used only if bit 5 is high (prefetch counter enabled). values: 00 = do not prefetch. only read bytes specified by c/be lines. 01 = prefetch four lwords if bit 5 is set. 10 = prefetch eight lwords if bit 5 is set. 11 = prefetch 16 lwords if bit 5 is set. yes yes 00 5 prefetch counter enable. when set to 1 and the prefetch count is not 00, the pci 9030 prefetches up to the number of lwords specified in the prefetch count. when set to 0, the pci 9030 ignores the count and continues prefetching, until terminated by pci bus transaction completion if read ahead mode is disabled (cntrl[16]=0), or if read ahead mode is enabled, until the read fifo fills. to disable prefetch, enable the prefetch counter and set the prefetch count to 0 (bits [5:3]=100) . yes yes 0 10:6 nrad wait states. number of read address-to-data wait states (0-31). (wait states between the address cycle and first read data cycle.) yes yes 00000 12:11 nrdd wait states. number of read data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst read.) yes yes 00 14:13 nxda wait states. number of read/write data-to-address wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) yes yes 00 19:15 nwad wait states. number of write address-to-data wait states (0-31). lad/ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) yes yes 00000 21:20 nwdd wait states. number of write data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst write.) yes yes 00 23:22 local address space 1 local bus width. writing of the following values indicates the associated bus width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved yes yes 10
section 10 registers local configuration registers pci 9030 data book version 1.4 10-24 ? 2002 plx technology, inc. all rights reserved. 24 byte ordering. value of 1 indicates big endian. value of 0 indicates little endian. yes yes 0 25 big endian byte lane mode. writing 1 specifies that in big endian mode, use byte lanes [31:16] for a 16-bit local bus and byte lanes [31:24] for an 8-bit local bus. writing 0 specifies that in big endian mode, use byte lanes [15:0] for a 16-bit local bus and byte lanes [7:0] for an 8-bit local bus. yes yes 0 27:26 read strobe delay. number of clocks from beginning of cycle until rd# strobe is asserted (0-3). value must be nrad for rd# to be asserted. yes yes 00 29:28 write strobe delay. number of clocks from beginning of cycle until wr# strobe is asserted (0-3). value must be nwad for wr# to be asserted. yes yes 00 31:30 write cycle hold. number of clocks from wr# de-assertion until end of cycle (0-3). data (lad/ld[31:0]) remains valid, and blast# remains asserted, during write cycle hold bus cycles. yes yes 00 register 10-49. (las1brd; 2ch) local address space 1 bus region descriptor (continued) bit description read write value after reset
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-25 10 ? registers register 10-50. (las2brd; 30h) local address space 2 bus region descriptor bit description read write value after reset 0 local address space 2 burst enable. writing 1 enables bursting. writing 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. pci reads are completed as single cycle on the pci bus if local burst is disabled or prefetch is disabled (bits [5:3]=100). yes yes 0 1 local address space 2 ready# input enable. writing 1 enables ready# input. writing 0 disables ready# input. yes yes 0 2 local address space 2 bterm# input enable. writing 1 enables bterm# input. writing 0 disables bterm# input. for more information, refer to section 2.2.4.3. yes yes 0 4:3 prefetch count. number of lwords to prefetch during memory read cycle. used only if bit 5 is high (prefetch counter enabled). values: 00 = do not prefetch. only read bytes specified by c/be lines. 01 = prefetch four lwords if bit 5 is set. 10 = prefetch eight lwords if bit 5 is set. 11 = prefetch 16 lwords if bit 5 is set. yes yes 00 5 prefetch counter enable. when set to 1 and the prefetch count is not 00, the pci 9030 prefetches up to the number of lwords specified in the prefetch count. when set to 0, the pci 9030 ignores the count and continues prefetching, until terminated by pci bus transaction completion if read ahead mode is disabled (cntrl[16]=0), or if read ahead mode is enabled, until the read fifo fills. to disable prefetch, enable the prefetch counter and set the prefetch count to 0 (bits [5:3]=100) . yes yes 0 10:6 nrad wait states. number of read address-to-data wait states (0-31). (wait states between the address cycle and first read data cycle.) yes yes 00000 12:11 nrdd wait states. number of read data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst read.) yes yes 00 14:13 nxda wait states. number of read/write data-to-address wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) yes yes 00 19:15 nwad wait states. number of write address-to-data wait states (0-31). lad/ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) yes yes 00000 21:20 nwdd wait states. number of write data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst write.) yes yes 00 23:22 local address space 2 local bus width. writing of the following values indicates the associated bus width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved yes yes 10
section 10 registers local configuration registers pci 9030 data book version 1.4 10-26 ? 2002 plx technology, inc. all rights reserved. 24 byte ordering. value of 1 indicates big endian. value of 0 indicates little endian. yes yes 0 25 big endian byte lane mode. writing 1 specifies that in big endian mode, use byte lanes [31:16] for a 16-bit local bus and byte lanes [31:24] for an 8-bit local bus. writing 0 specifies that in big endian mode, use byte lanes [15:0] for a 16-bit local bus and byte lanes [7:0] for an 8-bit local bus. yes yes 0 27:26 read strobe delay. number of clocks from beginning of cycle until rd# strobe is asserted (0-3). value must be nrad for rd# to be asserted. yes yes 00 29:28 write strobe delay. number of clocks from beginning of cycle until wr# strobe is asserted (0-3). value must be nwad for wr# to be asserted. yes yes 00 31:30 write cycle hold. number of clocks from wr# de-assertion until end of cycle (0-3). data (lad/ld[31:0]) remains valid, and blast# remains asserted, during write cycle hold bus cycles. yes yes 00 register 10-50. (las2brd; 30h) local address space 2 bus region descriptor (continued) bit description read write value after reset
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-27 10 ? registers register 10-51. (las3brd; 34h) local address space 3 bus region descriptor bit description read write value after reset 0 local address space 3 burst enable. writing 1 enables bursting. writing 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. pci reads are completed as single cycle on the pci bus if local burst is disabled or prefetch is disabled (bits [5:3]=100). yes yes 0 1 local address space 3 ready# input enable. writing 1 enables ready# input. writing 0 disables ready# input. yes yes 0 2 local address space 3 bterm# input enable. writing 1 enables bterm# input. writing 0 disables bterm# input. for more information, refer to section 2.2.4.3. yes yes 0 4:3 prefetch count. number of lwords to prefetch during memory read cycle. used only if bit 5 is high (prefetch counter enabled). values: 00 = do not prefetch. only read bytes specified by c/be lines. 01 = prefetch four lwords if bit 5 is set. 10 = prefetch eight lwords if bit 5 is set. 11 = prefetch 16 lwords if bit 5 is set. yes yes 00 5 prefetch counter enable. when set to 1 and the prefetch count is not 00, the pci 9030 prefetches up to the number of lwords specified in the prefetch count. when set to 0, the pci 9030 ignores the count and continues prefetching, until terminated by pci bus transaction completion if read ahead mode is disabled (cntrl[16]=0), or if read ahead mode is enabled, until the read fifo fills. to disable prefetch, enable the prefetch counter and set the prefetch count to 0 (bits [5:3]=100) . yes yes 0 10:6 nrad wait states. number of read address-to-data wait states (0-31). (wait states between the address cycle and first read data cycle.) yes yes 00000 12:11 nrdd wait states. number of read data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst read.) yes yes 00 14:13 nxda wait states. number of read/write data-to-address wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) yes yes 00 19:15 nwad wait states. number of write address-to-data wait states (0-31). lad/ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) yes yes 00000 21:20 nwdd wait states. number of write data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst write.) yes yes 00 23:22 local address space 3 local bus width. writing of the following values indicates the associated bus width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved yes yes 10
section 10 registers local configuration registers pci 9030 data book version 1.4 10-28 ? 2002 plx technology, inc. all rights reserved. 24 byte ordering. value of 1 indicates big endian. value of 0 indicates little endian. yes yes 0 25 big endian byte lane mode. writing 1 specifies that in big endian mode, use byte lanes [31:16] for a 16-bit local bus and byte lanes [31:24] for an 8-bit local bus. writing 0 specifies that in big endian mode, use byte lanes [15:0] for a 16-bit local bus and byte lanes [7:0] for an 8-bit local bus. yes yes 0 27:26 read strobe delay. number of clocks from beginning of cycle until rd# strobe is asserted (0-3). value must be nrad for rd# to be asserted. yes yes 00 29:28 write strobe delay. number of clocks from beginning of cycle until wr# strobe is asserted (0-3). value must be nwad for wr# to be asserted. yes yes 00 31:30 write cycle hold. number of clocks from wr# de-assertion until end of cycle (0-3). data (lad/ld[31:0]) remains valid, and blast# remains asserted, during write cycle hold bus cycles. yes yes 00 register 10-51. (las3brd; 34h) local address space 3 bus region descriptor (continued) bit description read write value after reset
section 10 local configuration registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-29 10 ? registers register 10-52. (erombrd; 38h) expansion rom bus region descriptor bit description read write value after reset 0 expansion rom burst enable. writing 1 enables bursting. writing 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. pci reads are completed as single cycle on the pci bus if local burst is disabled or prefetch is disabled (bits [5:3]=100). yes yes 0 1 expansion rom space ready# input enable. writing 1 enables ready# input. writing 0 disables ready# input. yes yes 0 2 expansion rom space bterm# input enable. writing 1 enables bterm# input. writing 0 disables bterm# input. for more information, refer to section 2.2.4.3. yes yes 0 4:3 prefetch count. number of lwords to prefetch during memory read cycle. used only if bit 5 is high (prefetch counter enabled). values: 00 = do not prefetch. only read bytes specified by c/be lines. 01 = prefetch four lwords if bit 5 is set. 10 = prefetch eight lwords if bit 5 is set. 11 = prefetch 16 lwords if bit 5 is set. yes yes 00 5 prefetch counter enable. when set to 1 and the prefetch count is not 00, the pci 9030 prefetches up to the number of lwords specified in the prefetch count. when set to 0, the pci 9030 ignores the count and continues prefetching, until terminated by pci bus transaction completion if read ahead mode is disabled (cntrl[16]=0), or if read ahead mode is enabled, until the read fifo fills. to disable prefetch, enable the prefetch counter and set the prefetch count to 0 (bits [5:3]=100) . yes yes 0 10:6 nrad wait states. number of read address-to-data wait states (0-31). (wait states between the address cycle and first read data cycle.) yes yes 00000 12:11 nrdd wait states. number of read data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst read.) yes yes 00 14:13 nxda wait states. number of read/write data-to-address wait states (0-3). lad/ld bus write data is not valid during nxda wait states. (wait states between consecutive bus requests. nxda wait states are inserted only after the last data transfer of a pci target access.) yes yes 00 19:15 nwad wait states. number of write address-to-data wait states (0-31). lad/ld bus data is valid during nwad wait states. (wait states between the address cycle and first write data cycle.) yes yes 00000 21:20 nwdd wait states. number of write data-to-data wait states (0-3). (wait states between consecutive data cycles of a burst write.) yes yes 00 23:22 expansion rom local bus width. writing of the following values indicates the associated bus width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved yes yes 00
section 10 registers local configuration registers pci 9030 data book version 1.4 10-30 ? 2002 plx technology, inc. all rights reserved. 24 byte ordering. value of 1 indicates big endian. value of 0 indicates little endian. yes yes 0 25 big endian byte lane mode. writing 1 specifies that in big endian mode, use byte lanes [31:16] for a 16-bit local bus and byte lanes [31:24] for an 8-bit local bus. writing 0 specifies that in big endian mode, use byte lanes [15:0] for a 16-bit local bus and byte lanes [7:0] for an 8-bit local bus. yes yes 0 27:26 read strobe delay. number of clocks from beginning of cycle until rd# strobe is asserted (0-3). value must be nrad for rd# to be asserted. yes yes 00 29:28 write strobe delay. number of clocks from beginning of cycle until wr# strobe is asserted (0-3). value must be nwad for wr# to be asserted. yes yes 00 31:30 write cycle hold. number of clocks from wr# de-assertion until end of cycle (0-3). data (lad/ld[31:0]) remains valid, and blast# remains asserted, during write cycle hold bus cycles. yes yes 00 register 10-52. (erombrd; 38h) expansion rom bus region descriptor (continued) bit description read write value after reset
section 10 chip select registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-31 10 ? registers 10.5 chip select registers note: for a chip select to assert, the address must be encompassed within a local address space. note: for a chip select to assert, the address must be encompassed within a local address space. register 10-53. (cs0base; 3ch) chip select 0 base address bit description read write value after reset 0 chip select 0 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 27:1 local base address of chip select 0. write zeros (0) in the least significant bits to define the range for chip select 0. starting from bit 1 and scanning toward bit 27, the first ? 1 ? found defines size. the remaining most significant bits, excluding the first ? 1 ? found, define base address. yes yes 0h 31:28 reserved. yes no 0h register 10-54. (cs1base; 40h) chip select 1 base address bit description read write value after reset 0 chip select 1 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 27:1 local base address of chip select 1. write zeros (0) in the least significant bits to define the range for chip select 1. starting from bit 1 and scanning toward bit 27, the first ? 1 ? found defines size. the remaining most significant bits, excluding the first ? 1 ? found, define base address. yes yes 0h 31:28 reserved. yes no 0h
section 10 registers chip select registers pci 9030 data book version 1.4 10-32 ? 2002 plx technology, inc. all rights reserved. notes: chip select 2 (cs2#) functionality of the gpio2/cs2# multiplexed pin is enabled by configuring gpioc[6] from the default value of 0 (gpio2) to 1. for a chip select to assert, the address must be encompassed within a local address space. notes: chip select 3 (cs3#) functionality of the gpio3/cs3# multiplexed pin is enabled by configuring gpioc[9] from the default value of 0 (gpio3) to 1. for a chip select to assert, the address must be encompassed within a local address space. register 10-55. (cs2base; 44h) chip select 2 base address bit description read write value after reset 0 chip select 2 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 27:1 local base address of chip select 2. write zeros (0) in the least significant bits to define the range for chip select 2. starting from bit 1 and scanning toward bit 27, the first ? 1 ? found defines size. the remaining most significant bits, excluding the first ? 1 ? found, define the base address. yes yes 0h 31:28 reserved. yes no 0h register 10-56. (cs3base; 48h) chip select 3 base address bit description read write value after reset 0 chip select 3 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 27:1 local base address of chip select 3. write zeros (0) in the least significant bits to define the range for chip select 3. starting from bit 1 and scanning toward bit 27, the first ? 1 ? found defines size. the remaining most significant bits, excluding the first ? 1 ? found, define base address. yes yes 0h 31:28 reserved. yes no 0h
section 10 control registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-33 10 ? registers 10.6 control registers register 10-57. (intcsr; 4ch) interrupt control/status bit description read write value after reset 0 linti1 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 1 linti1 polarity. value of 1 indicates active high. value of 0 indicates active low. yes yes 0 2 linti1 status. value of 1 indicates interrupt active. value of 0 indicates interrupt not active. yes no 0 3 linti2 enable. value of 1 indicates enabled. value of 0 indicates disabled. yes yes 0 4 linti2 polarity. value of 1 indicates active high. value of 0 indicates active low. yes yes 0 5 linti2 status. value of 1 indicates interrupt active. value of 0 indicates interrupt not active. yes no 0 6 pci interrupt enable. value of 1 enables pci interrupt. yes yes 0 7 software interrupt. value of 1 generates pci interrupt (inta# output asserted) if the pci interrupt enable bit is set (bit [6]=1). yes yes 0 8 linti1 select enable. value of 1 indicates enabled edge triggerable interrupt. value of 0 indicates enabled level triggerable interrupt. note: operates only in high-polarity mode (bit [1]=1). yes yes 0 9 linti2 select enable. value of 1 indicates enabled edge triggerable interrupt. value of 0 indicates enabled level triggerable interrupt. note: operates only in high-polarity mode (bit [4]=1). yes yes 0 10 local edge triggerable interrupt clear. writing 1 to this bit clears linti1. yes yes 0 11 local edge triggerable interrupt clear. writing 1 to this bit clears linti2. yes yes 0 15:12 reserved. yes no 0h register 10-58. (prot_area; 4eh) serial eeprom write-protected address boundary bit description read write value after reset 6:0 serial eeprom. serial eeprom starting at lword boundary (48 lwords = 192 bytes) for vpd accesses. serial eeprom addresses below this boundary are read-only. note: pci 9030 configuration data is stored below lword address 22h. yes yes 0110000 15:7 reserved. yes no 0h
section 10 registers control registers pci 9030 data book version 1.4 10-34 ? 2002 plx technology, inc. all rights reserved. register 10-59. (cntrl; 50h) pci target response, serial eeprom, and initialization control bit description read write value after reset 5:0 reserved . yes no 0h 6 pci target write fifo full condition. value of 1 guarantees that when the pci target write fifo is full with pci target write data, there is always one location remaining empty for the pci target read address to be accepted by the pci 9030. value of 0 retries all pci target read accesses when the pci target write fifo is full with pci target write data. yes yes 0 7 local arbiter lgnt signal select enable. value of 1 selects lgnt to remain active until lreq is de-asserted, although the pci 9030 has a pci target transaction pending. value of 0 selects lgnt to be de-asserted as soon as the pci 9030 detects a pci target transaction pending and waits for lreq to be de-asserted (preempt condition). yes yes 0 8 ready# timeout enable. value of 1 enables ready# timeout enable. yes yes 0 9 ready# timeout select. values: 1 = 64 clocks 0 = 32 clocks yes yes 0 11:10 pci target delayed write mode. delay in lclks of ads# from valid address. values: 00 = 0 lclks 10 = 8 lclks 01 = 4 lclks 11 = 16 lclks yes yes 00 13:12 pci configuration base address register (pcibar) enables. values: 00, 11 = pcibar0 (memory) and pcibar1 (i/o) enabled 01 = pcibar0 (memory) only 10 = pcibar1 (i/o) only note: pcibar0 and pcibar1 should be enabled for the pc platform. yes yes 00 14 pci r2.2 features enable. when set to 1, the pci 9030 performs all pci read and write transactions in compliance with pci r2.2 . setting this bit enables delayed reads, 2 15 pci clock timeout on retries, 16- and 8-clock pci latency rules, and enables the option to select pci read no write mode (retries for writes) (bit [17]) and/or pci read with write flush mode (bit [15]). refer to section 4.2.1.2 for additional information. value of 0 causes trdy# to remain de-asserted on reads until read data is available. if read data is not available before the pci target retry delay clocks counter (bits [22:19]) expires, a pci retry is issued. yes yes 0 15 pci read with write flush mode. when the pci r2.2 features enable bit is set (bit [14]=1), value of 1 flushes a pending delayed read cycle if a write cycle is detected. value of 0 (or bit [14]=0) does not affect a pending delayed read when a write cycle occurs. yes yes 0
section 10 control registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-35 10 ? registers 16 pci read no flush mode. value of 1 does not flush the read fifo if the pci read cycle completes (pci target read ahead mode). value of 0 flushes the read fifo if a pci read cycle completes. read ahead mode requires that prefetch be enabled in the las x brd and/or erombrd registers for the memory-mapped spaces that use read ahead mode. the pci 9030 flushes its read fifo for each i/o-mapped access. yes yes 0 17 pci read no write mode (pci retries for writes). when the pci r2.2 features enable bit is set (bit [14]=1), value of 1 forces a pci retry on writes if a delayed read is pending. value of 0 (or bit [14] =0) allows writes to occur while a delayed read is pending. yes yes 0 18 pci write release bus mode enable. value of 1 disconnects if the write fifo becomes full. value of 0 de-asserts trdy# until space is available in the write fifo (pci write hold bus mode). yes yes 0 22:19 pci target retry delay clocks. number of pci clocks (multiplied by 8) from the beginning of a pci target access, after which a pci retry is issued if the transfer has not completed. valid for read cycles only if bit [14]=0. valid for write cycles only if bit [18]=0. yes yes fh 23 pci target lock# enable. value of 1 enables pci target locked sequences. value of 0 disables pci target locked sequences. yes yes 0 24 serial eeprom clock for pci bus reads or writes to serial eeprom. toggling this bit generates a serial eeprom clock. (refer to manufacturer ? s data sheet for the particular serial eeprom being used.) yes yes 0 25 serial eeprom chip select. for pci bus reads or writes to the serial eeprom, setting this bit to 1 provides serial eeprom chip select. yes yes 0 26 write bit to serial eeprom. for writes, this output bit is the input to serial eeprom. clocked into the serial eeprom by serial eeprom clock. yes yes 0 27 read serial eeprom data bit. for reads, this input bit is the output of serial eeprom. clocked out of the serial eeprom by serial eeprom clock. yes no ? 28 serial eeprom present. value of 1 indicates a blank or programmed serial eeprom is present. yes no 0 29 reload configuration registers. when set to 0, writing 1 causes the pci 9030 to reload the local configuration registers from serial eeprom. yes yes 0 30 pci adapter software reset. value of 1 resets the pci 9030 and issues a reset to the local bus (lreseto# asserted). the pci 9030 remains in this reset condition until the pci host clears this bit. the contents of the pci and local configuration registers are not reset. the pci interface is not reset. note: if pci target read ahead mode is enabled (bit [16]=1), disable it prior to a software reset, or if following a software reset, perform a pci target read of any valid local bus address, except the next sequential lword referenced from the last pci target read, to flush the pci target read fifo. yes yes 0 31 disconnect with flush read fifo. when the pci r2.2 features enable bit is set (bit [14]=1), value of 1 causes acceptance of a new read request with flushing of the read fifo when a pci target read request does not match an existing, pending delayed read in the read fifo. value of 0, or clearing of the pci r2.2 features enable bit (bit [14]=0), causes a new target read request (different command, address and/or byte enables) to be retried when a delayed read is pending in the read fifo. yes yes 0 register 10-59. (cntrl; 50h) pci target response, serial eeprom, and initialization control (continued) bit description read write value after reset
section 10 registers control registers pci 9030 data book version 1.4 10-36 ? 2002 plx technology, inc. all rights reserved. register 10-60. (gpioc; 54h) general purpose i/o control bit description read write value after reset 0 gpio0 or waito# pin select. selects the function of gpio0/waito# pin. value of 1 indicates pin is waito#. value of 0 indicates pin is gpio0. yes yes 0 1 gpio0 direction. value of 0 indicates input. value of 1 indicates output. always an output if waito# function is selected. yes yes 0 2 gpio0 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 3 gpio1 or llocko# pin select. selects the function of gpio1/llocko# pin. value of 1 indicates pin is llocko#. value of 0 indicates pin is gpio1. yes yes 0 4 gpio1 direction. value of 0 indicates input. value of 1 indicates output. always an output if llock function is selected. yes yes 0 5 gpio1 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 6 gpio2 or cs2# pin select. selects the function of gpio2/cs2# pin. value of 1 indicates pin is cs2#. value of 0 indicates pin is gpio2. yes yes 0 7 gpio2 direction. value of 0 indicates input. value of 1 indicates output. always an output if cs2# function is selected. yes yes 0 8 gpio2 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 9 gpio3 or cs3# pin select. selects the function of gpio3/cs3# pin. value of 1 indicates pin is cs3#. value of 0 indicates pin is gpio3. yes yes 0 10 gpio3 direction. value of 0 indicates input. value of 1 indicates output. always an output if cs3# function is selected. yes yes 0 11 gpio3 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 12 gpio4 or la27 pin select. selects the function of gpio4/la27 pin. value of 1 indicates la27. value of 0 indicates gpio4. yes yes 1 13 gpio4 direction. value of 0 indicates input. value of 1 indicates output. always an output if la27 is selected. yes yes 0 14 gpio4 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 15 gpio5 or la26 pin select. selects the function of gpio5/la26 pin. value of 1 indicates la26. value of 0 indicates gpio5. yes yes 1 16 gpio5 direction. value of 0 indicates input. value of 1 indicates output. always an output if la26 is selected. yes yes 0 17 gpio5 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 18 gpio6 or la25 pin select. selects the function of gpio6/la25 pin. value of 1 indicates la25. value of 0 indicates gpio6. yes yes 1 19 gpio6 direction. value of 0 indicates input. value of 1 indicates output. always an output if la25 is selected. yes yes 0 20 gpio6 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 21 gpio7 or la24 pin select. selects the function of gpio7/la24 pin. value of 1 indicates la24. value of 0 indicates gpio7. yes yes 1 22 gpio7 direction. value of 0 indicates input. value of 1 indicates output. always an output if la24 is selected. yes yes 0 23 gpio7 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0
section 10 control registers registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 10-37 10 ? registers note: gpio pins configured as outputs are driven only when the pci 9030 owns the local bus. when another local master owns the bus (lgnt asserted), gpio pins configured as outputs are floated. (refer to pci 9030 errata #2 for additional information.) note: this register can be read only eight bits at a time, through pmdata[7:0]. the eight bits of pmdatasel returned in pmdata[7:0] are selected by pmcsr[12:9]. note: this register can be read only two bits at a time, through pmcsr[14:13]. the two bits of pmdatascale returned in pmcsr[14:13] are selected by pmcsr[12:9]. 24 reserved. yes yes 0 25 gpio8 direction. value of 0 indicates input. value of 1 indicates output. yes yes 0 26 gpio8 data. if programmed as output, writing 1 causes corresponding pin to go high. if programmed as input, reading provides state of corresponding pin. yes yes 0 31:27 reserved. yes yes 0h register 10-60. (gpioc; 54h) general purpose i/o control (continued) bit description read write value after reset register 10-61. (pmdatasel; 70h) hidden 1 power management data select bit description read write value after reset 7:0 d 0 power consumed. provides the power consumed in the d 0 state. value read from pmdata register when data_select = 0. refer to note serial eeprom 0h 15:8 d 3 power consumed. provides the power consumed in the d 3 state. value read from pmdata register when data_select = 3. refer to note serial eeprom 0h 23:16 d 0 power dissipated. provides the power dissipated in the d 0 state. value read from pmdata register when data_select = 4. refer to note serial eeprom 0h 31:24 d 3 power dissipated. provides the power dissipated in the d 3 state. value read from pmdata register when data_select = 7. refer to note serial eeprom 0h register 10-62. (pmdatascale; 74h) hidden 2 power management data scale bit description read write value after reset 1:0 data_scale 0. provides the d 0 power consumed scaling factor read in pmdata[7:0]. value read in pmcsr[14:13] when data_select = 0. refer to note serial eeprom 00 3:2 data_scale 3. provides the d 3 power consumed scaling factor read in pmdata[7:0]. value read in pmcsr[14:13] when data_select = 3. refer to note serial eeprom 00 5:4 data_scale 4. provides the d 0 power dissipated scaling factor read in pmdata[7:0]. value read in pmcsr[14:13] when data_select = 4. refer to note serial eeprom 00 7:6 data_scale 7. provides the d 3 power dissipated scaling factor read in pmdata[7:0]. value read in pmcsr[14:13] when data_select = 7. refer to note serial eeprom 00 31:8 reserved. refer to note serial eeprom 0h

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-1 11 ? pin description 11 pin description 11.1 pin summary tables in this section describe each pci 9030 pin. table 11-5 through table 11-10 provide pin information common to all local bus modes of operation: power and ground serial eeprom interface test and debug pci system bus interface pci mode independent interface local bus mode independent interface pins in table 11-11 and table 11-12 correspond to the pci 9030 local bus modes ? multiplexed and non-multiplexed: multiplexed bus mode interface pin description (32-bit address/32-bit data) non-multiplexed bus mode interface pin description (32-bit address/32-bit data) for a visual of the chip pinout, refer to section 13, ? physical specifications. ? the following table lists abbreviations used in this section to represent various pin types. note: a ? # ? in the pin name indicates active low. note for pci pins: do not pull up or down on any pins unless the pci 9030 is being used in an embedded design. refer to pci r2.2. 11.2 pull-up and pull-down resistor recommendations except for a 50k pull-up resistor on eedo and a 50k pull-down resistor on bd_sel#/test, no internal pull-up or pull-down resistors are present in the pci 9030. to prevent oscillation, unused inputs should be terminated rather than left floating. the suggested values for external pull-up and pull-down resistors are 1k to 10k ohms. 11.2.1 input pins (pin type i) this section discusses the pull-up and pull-down resistor requirements for the following input pins ? bd_sel#/test, bterm#, cpcisw, eedo, lclk, linti[2:1], lpmeset, lreq, mode, ready#, tck, tdi, tms, trst#. (refer to table 11-2 for resistor requirements.) table 11-1. pin type abbreviations abbreviation pin type dts driven three-state, driven high for one-half clk before float i input only i/o input and output o output only od open drain sts sustained three-state, driven high for one clk before float tp totem pole ts three-state table 11-2. input pin pull-up and pull-down resistor requirements signal requirements bd_sel#/test for compactpci hot swap, pull up to early power; otherwise, pull or tie low because the internal 50k-ohm pull-down resistor is not sufficiently strong to guarantee proper operation. bterm# if enabled, connect to a pull-up resistor to hold signal in an inactive state. if disabled for all local address spaces (default) in las x brd and erombrd, tie high or low. cpcisw if compactpci hot swap is not used, pull or tie low eedo use an external pull-up resistor due to the weak value (50k ohms) of the internal pull-up resistor. the pull-up resistor must be pulled to early power v dd in compactpci hot swap platforms and normal v dd in regular pci platforms. a missing pull-up resistor for the eedo signal may intermittently bring the pci 9030 to a quiescent state. if no serial eeprom is present, can be tied to v dd . lclk local clock is required. must start prior to pci rst# de-assertion.
section 11 pin description pull-up and pull-down resistor recommendations pci 9030 data book version 1.4 11-2 ? 2002 plx technology, inc. all rights reserved. note: ieee standard 1149.1-1990 requires pull-up resistors on tdi, tms, and trst#. to remain compliant with pci r2.2, no internal pull-up resistors are provided on jtag pins in the pci 9030; therefore, the pull-up resistors must be externally added to the pci 9030. 11.2.2 output pins (pin type o) this section discusses the pull-up and pull-down resistor requirements for the following local bus output pins ? ads#, ale, bclko, blast#, cs[1:0]#, eecs, eedi, eesk, enum#, la[23:2], lbe[3:0]#, ledon#, lgnt, lpmint#, lreseto#, lw/r#, rd#, tdo, and wr#. 11.2.2.1 three-state output pins three-state (ts) output pins are ads#, ale, blast#, cs[1:0]#, la[23:2], lbe[3:0]#, lw/r#, rd#, tdo, and wr#. the pci 9030 drives local bus three-state output signals when it owns the local bus, and floats local bus three-state output signals when it does not own the local bus (lgnt asserted). three-state output signals are also floated during pci reset. when the pci 9030 is used in a system with multiple masters on the local bus, pull-up and/or pull-down resistors may be required on three-state output pins to hold control signals in the inactive state when the pci 9030 does not own the local bus, and/or to reduce noise coupling between local bus devices. 11.2.2.2 totem-pole output pins totem-pole (tp) output pins are bclko, eecs, eedi, eesk, lgnt, lpmint#, and lreseto#. totem-pole outputs are always driven, except when the bd_sel#/test input is high and the eedo input is low (iddq test state). 11.2.2.3 open-drain output pins open-drain (od) output pins are enum# and ledon#. (refer to table 11-3 for resistor requirements.) linti[2:1] if configured as level-sensitive (default) in intcsr[9:8], connect to a pull-up or pull-down resistor to hold the signal in an inactive state, for the polarity configured in intcsr[4, 1] (default is active-low). unused pins can be tied to v dd or v ss to hold the input in the inactive state (v dd for default active-low configuration). lpmeset if used to trigger pme# assertion, connect to a pull-down resistor to hold the signal in the inactive state. if not used, pull low or tie to v ss . lreq pull or drive low, or tie to v ss to provide local bus ownership to the pci 9030. mode tie high for multiplexed mode, or low for non-multiplexed mode. ready# if enabled, connect to a pull-up resistor to hold the signal in an inactive state. if disabled or all local address spaces (default) in las x brd and erombrd, tie high or low. tck if jtag is not used, tie high or low. if used, an external pull-up resistor is required. tdi tms trst# must be pulled low during pci rst# assertion. if jtag is not used, it is recommended that trst# always be pulled low to place jtag functionality in the reset state and enable normal chip logic operation. (refer to pci 9030 errata #5 .) table 11-2. input pin pull-up and pull-down resistor requirements (continued) signal requirements table 11-3. output pin pull-up and pull-down resistor requirements signal requirements enum# enum# is a three-state buffer that is configured as an output; therefore, a pull-up resistor is required to ensure the buffer input value is in a known state. ledon# ledon# is an open-drain output that is always enabled. hs_csr[3] (default = 0) controls whether ledon# sinks current or floats (default = off); therefore, neither a pull-up nor pull-down resistor is required. note: ledon# is also asserted while pci rst# input is asserted.
section 11 pull-up and pull-down resistor recommendations pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-3 11 ? pin description 11.2.3 i/o pins (pin type i/o) this section discusses the pull-up and pull-down resistor requirements for the following local bus i/o pins ? gpio0/waito#, gpio1/llocko#, gpio2/ cs2#, gpio3/cs3#, gpio4/la27, gpio5/la26, gpio6/la25, gpio7/la24, gpio8, lad/ld[31:0]. the pci 9030 drives local bus i/o signals when it owns the local bus, and floats local bus i/o signals when it does not own the local bus (lgnt asserted). during pci reset, the pci 9030 drives the gpio4/ la27, gpio5/la26, gpio6/la25, gpio7/la24, and lad/ld[31:0] signals low. (refer to table 11-4 for resistor requirements and pci 9030 errata #4 .) table 11-4. i/o pin pull-up and pull-down resistor requirements signal requirements gpio0/waito# if gpio[8:0] are configured as inputs and not used, pull or tie these pins to v dd or v ss . under default register configuration, the following pins are configured as inputs ? gpio0/waito#, gpio1/ llocko#, gpio2/cs2#, gpio3/cs3#, and gpio8. note: refer to pci 9030 errata #2, regarding the gpio[8:0] pins which, when configured as outputs, are floated when the pci 9030 does not own the local bus. gpio1/llocko# gpio2/cs2# gpio3/cs3# gpio4/la27 gpio5/la26 gpio6/la25 gpio7/la24 gpio8 lad/ld[31:0] connect unused data bus pins to a pull-up or pull-down resistor. depending upon design, it is recommended to add resistors to all data pins. when reading from a local device, the lad/ld lines are effectively floated, and if the local device is not driving these pins ( such as during wait states), then noise can couple into the lad/ld inputs.
section 11 pin description pinout common to all bus modes pci 9030 data book version 1.4 11-4 ? 2002 plx technology, inc. all rights reserved. 11.3 pinout common to all bus modes note: the die contains 224 pads. power and grounds are double bounded in the pqfp packages to meet proper drive strength of the buffers. table 11-5. power and ground pins (176-pin pqfp) symbol signal name total pins pin type pqfp pin number function v dd power (+3.3v) 11 i 1, 14, 32, 45, 56, 70, 85, 100, 117, 133, 162 3.3v power supply pins for core and i/o buffers. liberal 0.01 to 0.1 f decoupling capacitors should be placed near the pci 9030. v i/o voltage input/output 1i 53 system voltage select, 3.3 or 5v, from the pci bus. v ss ground 14 i 13, 31, 44, 57, 66, 78, 88, 101, 113, 122, 132, 146, 163, 176 ground pins. total 26 table 11-6. power, ground, and no connect pins (180-pin bga) symbol signal name total die pads total pins pin type bga pin number function nc spare ? 4 ? a1, a14, p1, p14 applicable only to 180-pin bga. unused . v dd power (+3.3v) 34 11 i b2, b6, b13, e1, f11, j5, k13, m8, n2, n5, p12 3.3v power supply pins for core and i/o buffers. liberal 0.01 to 0.1 f decoupling capacitors should be placed near the pci 9030. v i/o voltage input/output 11 i l5 system voltage select, 3.3 or 5v, from the pci bus. v ss ground 39 14 i a2, a10, b14, c6, e13, f5, g13, j3, j10, k6, l7, n1, n10, p13 ground pins. total 74 30
section 11 pinout common to all bus modes pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-5 11 ? pin description note: the serial eeprom interface operates at core voltage (+3.3v). the pci 9030 requires a serial eeprom that can operate at 250 khz, and supports sequential reads. table 11-7. serial eeprom interface pins symbol signal name total pins pin type pqfp pin number bga pin number function eecs serial eeprom chip select 1 o tp 6 ma 158 c7 serial eeprom chip select. eedi serial eeprom data in 1 o tp 6 ma 161 d6 write data to serial eeprom. eedo serial eeprom data out 1i 159 e7 read data from serial eeprom. when the bd_sel#/test input pin is pulled high for test mode, the eedo input functions as an iddq test enable pin. when bd_sel#/test input is high and eedo is input low, the pci 9030 output buffers are in a quiescent state and the pci 9030 draws minimum power. when bd_sel#/test and eedo inputs are both high, all outputs except ledon# are floated. however, the analog precharge circuits are active, and power consumption is consequently higher than a quiescent state, but is less than that consumed during normal operation. eesk serial data clock 1 o tp 6 ma 160 a7 serial eeprom clock pin. total 4
section 11 pin description pinout common to all bus modes pci 9030 data book version 1.4 11-6 ? 2002 plx technology, inc. all rights reserved. table 11-8. test and debug pins symbol signal name total pins pin type compactpci hot swap precharge bias voltage pqfp pin number bga pin number function bd_sel# test board select test pin 1 i no connect 112 g11 compactpci hot swap systems: should be pulled high externally. the pull-up resistor needs to be connected to early power. non-hot swap and other systems: should be pulled low externally. in combination with eedo: used as an iddq test enable pin. when pulled high, all outputs except ledon# are placed in three-state, and pci hot swap precharge resistors are active. when pulled low, all outputs remain in normal operation and pci hot swap precharge resistors are not active. tck test clock input 1 i 1v 165 a6 clock source for the pci 9030 test access port (tap). the maximum clock rate into the tck pin is lclk rate or less than one-half of the lclk rate. tdi test data in 1 i 1v 168 a5 used to input serial data into the tap. when the tap enables this pin, it is sampled on the rising edge of tck and the data is input to the selected tap shift register. note: no internal pull-up. tdo test data output 1 o ts pci 1v 167 c5 used to transmit data from the pci 9030 tap. data from the selected tap shift registers is shifted out on tdo. tms test mode select 1 i 1v 166 b5 sampled by tap on the rising edge of tck. the tap state machine uses the tms pin to determine the mode in which the tap operates. note: not used to select jtag operation. trst# test reset 1 i 1v 164 e6 reset used by jtag testers. trst# must be asserted during pci rst# assertion; otherwise, the pci 9030 can initialize into an undefined state, precluding normal logic operation. if jtag is not used, it is recommended that trst# always be pulled low to put jtag functionality into the reset state and enable normal chip logic operation. total 6
section 11 pinout common to all bus modes pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-7 11 ? pin description table 11-9. pci system bus interface pins symbol signal name total pins pin type compactpci hot swap precharge bias voltage pqfp pin number bga pin number function ad[31:0] address and data 32 i/o ts pci 1v 173-175, 2-6, 9-12, 15-18, 30, 33-39, 41-43, 46-50 a3, d4, b3, c3, c2, b1, c1, d3, e4, d1, e3, e2, f3, f2, f4, f1, j2, j1, k2, k3, k1, k4, l2, l3, m1, l4, m2, m3, n3, p2, p3, m4 all multiplexed on the same pci pins. the bus transaction consists of an address phase, followed by one or more data phases. the pci 9030 supports both read and write bursts. c/be[3:0]# bus command and byte enables 4 i 1v 7, 19, 29, 40 d2, g5, j4, l1 all multiplexed on the same pci pins. during the transaction address phase, defines the bus command. during the data phase, used as byte enables. refer to the pci r2.2 for further details. devsel# device select 1 o sts pci 1v 23 g1 when actively driven, indicates the driving device decoded its address as target of current access. enum# enumeration 1 o od pci v i/o 51 n4 interrupt output set when an adapter using the pci 9030 was recently inserted or ready to be removed from a pci slot. used for implementing compactpci hot swap. frame# cycle frame 1 i 1v 20 g2 driven by the current master to indicate the beginning and duration of an access. frame# is asserted to indicate the bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is de-asserted, the transaction is in the final data phase. idsel initialization device select 1i 1v 8 e5 used as a chip select during configuration read and write transactions. inta# interrupt a 1 o od pci v i/o 170 b4 pci interrupt request. irdy# initiator ready 1 i 1v 21 g3 indicates initiating agent (bus master) ability to complete the current transaction data phase. lock# lock 1 i 1v 25 h2 indicates an atomic operation that may require multiple transactions to complete.
section 11 pin description pinout common to all bus modes pci 9030 data book version 1.4 11-8 ? 2002 plx technology, inc. all rights reserved. par parity 1 i/o ts pci 1v 28 h1 even parity across ad[31:0] and c/be[3:0]#. all pci agents require parity generation. par is stable and valid one clock after the address phase. for data phases, par is stable and valid one clock after either irdy# is asserted on a write transaction or trdy# is asserted on a read transaction. once par is valid, it remains valid until one clock after current data phase completes. pclk clock 1i no connection 172 a4 provides timing for all transactions on the pci bus and is an input to every pci device. the pci 9030 operates up to 33 mhz. note: on expansion boards, trace length for the pci pclk signal must be 2.5 inches 0.1 inches, and must be routed to only one load, per pci r2.2. perr# parity error 1 o sts pci 1v 26 h3 reports data parity errors during all pci transactions, except during a special cycle. pme# power management event 1 o od pci v i/o 169 d5 wake-up event interrupt. note: if pme# is implemented, a field-effect transistor (fet) should be used to isolate the signal when power is removed from the card. (refer to pci power mgmt. r1.1.) if pme# is not used, then connect it through a pull-up resistor to v i/o . rst# reset 1i v i/o 171 c4 used to bring pci-specific registers, sequencers, and signals to a default state. serr# system error 1 o od pci 1v 27 h5 reports address parity errors or any other system error where the result is catastrophic. stop# stop 1 o sts pci 1v 24 h4 indicates the current target is requesting that the master stop the current transaction. trdy# target ready 1 o sts pci 1v 22 g4 indicates the target agent (selected device) ability to complete the current data phase transaction. total 51 table 11-9. pci system bus interface pins (continued) symbol signal name total pins pin type compactpci hot swap precharge bias voltage pqfp pin number bga pin number function
section 11 pinout common to all bus modes pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-9 11 ? pin description table 11-10. local bus mode independent interface pins symbol signal name total pins pin type pqfp pin number bga pin number function bclko buffered clock out 1 o tp 12 ma 71 k8 provides a buffered version pci clock for optional use by the local bus. not in phase with the pci clock. cpcisw compactpci switch 1i 54 p4 compactpci board latch status input. cs[1:0]# chip selects 2 o ts 12 ma 148, 147 b9, c9 general purpose chip selects. the base and range of each is programmable by configuration registers. gpio0 waito# general purpose i/o 0 wait out 1 i/o ts 12 ma 154 d8 can be programmed to a configurable general purpose i/o pin, gpio0, or local bus wait out pin, waito#. waito# is asserted when wait states are caused by the internal wait state generator. serves as an output to provide ready-out status. default functionality is gpio0 input. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[1:0] register bits. gpio1 llocko# general purpose i/o 1 llock out 1 i/o ts 12 ma 155 a8 can be programmed to a configurable general purpose i/o pin, gpio1, or local bus llock out pin, llocko#. llocko# indicates an atomic operation that may require multiple transactions to complete and can be used by the local bus to lock resources. default functionality is gpio1 input. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[4:3] register bits. the pci 9030 asserts llocko# during the first clock of an atomic operation (address cycle), and de-asserts it a minimum of one clock following the last bus access for the atomic operation. llocko# is de-asserted after the pci 9030 detects pci frame#, with pci lock# concurrently de-asserted. gpio2 cs2# general purpose i/o 2 chip select 2 out 1 i/o ts 12 ma 156 d7 can be programmed to a configurable general purpose i/o pin, gpio2, or as chip select 2 output pin, cs2#. default functionality is gpio2 input. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[7:6] register bits. gpio3 cs3# general purpose i/o 3 chip select 3 out 1 i/o ts 12 ma 157 b7 can be programmed to a configurable general purpose i/o pin, gpio3, or as chip select 3 output pin, cs3#. default functionality is gpio3 input. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[10:9] register bits.
section 11 pin description pinout common to all bus modes pci 9030 data book version 1.4 11-10 ? 2002 plx technology, inc. all rights reserved. gpio8 general purpose i/o 8 1 i/o ts 12 ma 94 l12 configurable general purpose i/o pin. lclk local bus clock 1 i 145 e9 local clock, up to 60 mhz, and may be asynchronous to pci clock. ledon# led on 1 o od 24 ma 52 k5 hot swap board indicator led. ledon# is controlled by the led software on/off switch bit (hs_csr[3]) and is also asserted during pci reset. lgnt local bus grant 1 o tp 12 ma 150 a9 asserted by pci 9030 to grant control of the local bus to a local bus master. when the pci 9030 requires the local bus, it can optionally signal a preempt by de-asserting lgnt, if the disconnect with flush read fifo bit is clear (cntrl[31]=0) (default). linti1 local interrupt input 1 1 i 152 b8 when enabled (intcsr[0]=1) and asserted, the linti1 status bit sets (intcsr[2]=1). if the pci interrupt enable bit is set (intcsr[6]=1), then inta# asserts. linti1 is programmable for active-low or active-high polarity in intcsr[1] in the default level-sensitive mode (intcsr[8]=0). can be optionally configured as a positive edge-triggered interrupt (intcsr[8, 1, 0]=111) such as in the case of isa compatibility. level-sensitive interrupts are cleared when the interrupt source is no longer active, or linti1 is disabled. an edge-triggered interrupt is set and latched by a linti1 low-to-high transition, and cleared by setting the linti1 local edge triggerable interrupt clear bit (intcsr[10]=1). linti2 local interrupt input 2 1 i 153 c8 when enabled (intcsr[3]=1) and asserted, the linti2 status bit sets (intcsr[5]=1). if the pci interrupt enable bit is also set (intcsr[6]=1), then inta# asserts. linti2 is programmable for active-low or active-high polarity in intcsr[4] in the default level-sensitive mode (intcsr[9]=0). can be optionally configured as a positive edge-triggered interrupt (intcsr[9, 4, 3]=111), such as in the case of isa compatibility. level-sensitive interrupts are cleared when the interrupt source is no longer active, or linti2 is disabled. an edge-triggered interrupt is set and latched by a linti2 low-to-high transition, and cleared by setting the linti2 local edge triggerable interrupt clear bit (intcsr[11]=1). table 11-10. local bus mode independent interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 pinout common to all bus modes pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-11 11 ? pin description lpmeset local power management event set 1 i 103 j12 as an input, the local initiator can issue lpmeset to the pci 9030 in the case of a power management wake-up event. lpmeset must be asserted to the pci 9030 no less than one local clock pulse. the pci 9030 latches the lpmeset assertion, sets the pme_status bit (pmcsr[15]), and asserts pme# to the pci bus, if enabled. lpmint# local power management interrupt 1 o tp 12 ma 126 d13 could be used for local power management events. the pci 9030 drives the interrupt to the external master to request a power state change. lreq local bus request 1 i 151 e8 asserted by a local bus master to request local bus use. the pci 9030 can be made master of the local bus by pulling lreq low (or by grounding lreq). lreseto# local bus reset out 1 o tp 12 ma 149 d9 asserted when the pci 9030 chip is reset. can be used to drive the local processor ? s reset# input. mode bus mode 1i 76 k9 selects the pci 9030 bus operation mode. values: 0 = non-multiplexed mode 1 = multiplexed mode note: the mode input level must be stable at power-on. total 19 table 11-10. local bus mode independent interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 pin description multiplexed local bus mode pinout pci 9030 data book version 1.4 11-12 ? 2002 plx technology, inc. all rights reserved. 11.4 multiplexed local bus mode pinout table 11-11. multiplexed bus mode interface pins symbol signal name total pins pin type pqfp pin number bga pin number function ads# address strobe 1 o ts 12 ma 138 c11 indicates a valid address and start of a new bus access. asserted for the first clock of a bus access. ale address latch enable 1 o ts 12 ma 75 m9 asserted during the address phase and de-asserted before the data phase. blast# burst last 1 o ts 12 ma 139 b11 driven by the current local bus master to indicate the last transfer in a bus access. bterm# burst terminate 1 i 144 b10 if bterm mode (continuous burst) and the bterm# input are disabled (las x brd[2]=0 and/or erombrd[2]=0), the pci 9030 also bursts up to four lwords. if bterm mode (continuous burst) and the bterm# input are enabled (las x brd[2]=1 and/or erombrd[2]=1), the pci 9030 continues to burst until bterm# input is asserted or the burst completes. bterm# is a ready input that breaks up a burst cycle and causes another address cycle to occur. used in conjunction with the pci 9030 programmable wait state generator. bterm# is not sampled until external wait states expire [waito# de-asserted, provided gpio0/waito# is configured as waito# (gpioc[0]=1)]. gpio4 la27 general purpose i/o 4 address bus 1 i/o ts 12 ma o ts 12 ma 137 a12 can be programmed to a configurable general purpose i/o pin, gpio4, or as address bus output pin, la27. default functionality is la27. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[13:12] register bits. gpio5 la26 general purpose i/o 5 address bus 1 i/o ts 12 ma o ts 12 ma 136 a13 can be programmed to a configurable general purpose i/o pin, gpio5, or as address bus output pin, la26. default functionality is la26. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[16:15] register bits. gpio6 la25 general purpose i/o 6 address bus 1 i/o ts 12 ma o ts 12 ma 135 b12 can be programmed to a configurable general purpose i/o pin, gpio6, or as address bus output pin, la25. default functionality is la25. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[19:18] register bits.
section 11 multiplexed local bus mode pinout pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-13 11 ? pin description gpio7 la24 general purpose i/o 7 address bus 1 i/o ts 12 ma o ts 12 ma 134 c12 can be programmed to a configurable general purpose i/o pin, gpio7, or as address bus output pin, la24. default functionality is la24. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[22:21] register bits. la[23:2] address bus 22 o ts 12 ma 131-127, 125-123, 121-118, 116-114, 111-105 c13, d11, c14, d14, d12, e11, e14, e12, f14, f10, f12, f13, g14, g10, g12, h14, h11, h12, h13, h10, j14, j11 carries the upper 22 bits of the 28-bit physical address bus. increments during bursts indicate successive data cycles. lad[31:0] address/ data bus 32 i/o ts 12 ma 61-65, 67-69, 72-74, 77, 79-84, 86-87, 89-93, 95-99, 102, 104 l6, p6, k7, n7, m7, p7, l8, n8, p8, l9, n9, p9, m10, p10, l10, n11, m11, p11, l11, n12, n13, m12, m13, n14, m14, l13, k10, k11, l14, k12, k14, j13 during an address phase, the bus carries the upper 26 bits of 28-bit physical address bus [27:2]. during the data phase, the bus carries 32-, 16-, or 8-bit data quantities, depending on bus width configuration: 8-bit = lad[7:0] 16-bit = lad[15:0] 32-bit = lad[31:0] during an ads# assertion, carries the local address bus (la[27:2]). lbe[3:0]# byte enables 4 o ts 12 ma 55, 58-60 m5, p5, m6, n6 encoded, based on the bus-width configuration: 32-bit bus four byte enables indicate which of the four bytes are active during a data cycle: lbe3# byte enable 3 = lad[31:24] lbe2# byte enable 2 = lad[23:16] lbe1# byte enable 1 = lad[15:8] lbe0# byte enable 0 = lad[7:0] 16-bit bus lbe[3, 1:0]# are encoded to provide bhe#, la1, and ble#, respectively: lbe3# byte high enable (bhe#) = lad[15:8] lbe2# unused lbe1# address bit 1 (la1) lbe0# byte low enable (ble#) = lad[7:0] 8-bit bus lbe[1:0]# are encoded to provide la[1:0], respectively: lbe3# unused lbe2# unused lbe1# address bit 1 (la1) lbe0# address bit 0 (la0) table 11-11. multiplexed bus mode interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 pin description multiplexed local bus mode pinout pci 9030 data book version 1.4 11-14 ? 2002 plx technology, inc. all rights reserved. lw/r# write/read 1 o ts 12 ma 142 a11 asserted low for reads and high for writes. rd# read strobe 1 o ts 12 ma 141 d10 general purpose read strobe. timing is controlled by current bus region descriptor register. normally asserted during nrad wait states, unless read strobe delay clocks are programmed in bits [27:26]. remains asserted throughout burst and nrdd wait states. ready# local ready input 1 i 143 c10 local ready input indicates read data is on the local bus, or that write data is accepted. ready# input is not sampled until internal wait states expire [waito# de-asserted, provided gpio0/waito# is configured as waito# (gpioc[0]=1)]. ready# is ignored when bterm# is enabled and asserted. wr# write strobe 1 o ts 12 ma 140 e10 general purpose write strobe. timing is controlled by the current bus region descriptor register. normally asserted during nwad wait states, unless write strobe delay clocks are programmed in bits [29:28]. remains asserted throughout burst and nwdd wait states. lad/ld data valid time can be extended beyond wr# de-assertion if write cycle hold clocks are programmed in bits [31:30]. total 70 table 11-11. multiplexed bus mode interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 non-multiplexed local bus mode pinout pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-15 11 ? pin description 11.5 non-multiplexed local bus mode pinout table 11-12. non-multiplexed bus mode interface pins symbol signal name total pins pin type pqfp pin number bga pin number function ads# address strobe 1 o ts 12 ma 138 c11 indicates a valid address and start of a new bus access. asserted for the first clock of a bus access. ale address latch enable 1 o ts 12 ma 75 m9 asserted during the address phase and de-asserted before the data phase. blast# burst last 1 o ts 12 ma 139 b11 driven by the current local bus master to indicate the last transfer in a bus access. bterm# burst terminate 1 i 144 b10 if bterm mode (continuous burst) and bterm# input are disabled (lasxbrd[2]=0 and/or erombrd[2]=0), the pci 9030 also bursts up to four lwords. if enabled, the pci 9030 continues to burst until bterm# input is asserted or the burst completes. bterm# is a ready input that breaks up a burst cycle and causes another address cycle to occur. used in conjunction with the pci 9030 programmable wait state generator. gpio4 la27 general purpose i/o 4 address bus 1 i/o ts 12 ma 137 a12 can be programmed to a configurable general purpose i/o pin, gpio4, or as address bus output pin, la27. default functionality is la27. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[13:12] register bits. gpio5 la26 general purpose i/o 5 address bus 1 i/o ts 12 ma 136 a13 can be programmed to a configurable general purpose i/o pin, gpio5, or as address bus output pin, la26. default functionality is la26. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[16:15] register bits. gpio6 la25 general purpose i/o 6 address bus 1 i/o ts 12 ma 135 b12 can be programmed to a configurable general purpose i/o pin, gpio6, or as address bus output pin, la25. default functionality is la25. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[19:18] register bits. gpio7 la24 general purpose i/o 7 address bus 1 i/o ts 12 ma 134 c12 can be programmed to a configurable general purpose i/o pin, gpio7, or as address bus output pin, la24. default functionality is la24. pin configuration occurs when the serial eeprom contents are loaded following pci reset, or upon subsequent writing to the gpioc[22:21] register bits.
section 11 pin description non-multiplexed local bus mode pinout pci 9030 data book version 1.4 11-16 ? 2002 plx technology, inc. all rights reserved. la[23:2] address bus 22 o ts 12 ma 131-127, 125-123, 121-118, 116-114, 111-105 c13, d11, c14, d14, d12, e11, e14, e12, f14, f10, f12, f13, g14, g10, g12, h14, h11, h12, h13, h10, j14, j11 carries the upper 22 bits of the 28-bit physical address bus. increments during bursts indicate successive data cycles. lbe[3:0]# byte enables 4 o ts 12 ma 55, 58-60 m5, p5, m6, n6 encoded, based on the bus-width configuration: 32-bit bus four byte enables indicate which of the four bytes are active during a data cycle: lbe3# byte enable 3 = ld[31:24] lbe2# byte enable 2 = ld[23:16] lbe1# byte enable 1 = ld[15:8] lbe0# byte enable 0 = ld[7:0] 16-bit bus lbe[3, 1:0]# are encoded to provide bhe#, la1, and ble#, respectively: lbe3# byte high enable (bhe#) = ld[15:8] lbe2# unused lbe1# address bit 1 (la1) lbe0# byte low enable (ble#) = ld[7:0] 8-bit bus lbe[1:0]# are encoded to provide la[1:0], respectively: lbe3# unused lbe2# unused lbe1# address bit 1 (la1) lbe0# address bit 0 (la0) ld[31:0] data bus 32 i/o ts 12 ma 61-65, 67-69, 72-74, 77, 79-84, 86-87, 89-93, 95-99, 102, 104 l6, p6, k7, n7, m7, p7, l8, n8, p8, l9, n9, p9, m10, p10, l10, n11, m11, p11, l11, n12, n13, m12, m13, n14, m14, l13, k10, k11, l14, k12, k14, j13 carries 8-, 16-, or 32-bit data quantities, depending upon a target bus-width configuration: 8-bit = ld[7:0] 16-bit = ld[15:0] 32-bit = ld[31:0] lw/r# write/read 1 o ts 12 ma 142 a11 asserted low for reads and high for writes. table 11-12. non-multiplexed bus mode interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 non-multiplexed local bus mode pinout pin description pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 11-17 11 ? pin description rd# read strobe 1 o ts 12 ma 141 d10 general purpose read strobe. timing is controlled by current bus region descriptor register. normally asserted during nrad wait states, unless read strobe delay clocks are programmed in bits [27:26]. remains asserted throughout burst and nrdd wait states. ready# local ready input 1 i 143 c10 local ready input indicates read data on the bus is valid or a write data transfer is complete. ready# input is not sampled until the internal wait state counter expires (waito# de-asserted). wr# write strobe 1 o ts 12 ma 140 e10 general purpose write strobe. timing is controlled by the current bus region descriptor register. normally asserted during nwad wait states, unless write strobe delay clocks are programmed in bits [29:28]. remains asserted throughout burst and nwdd wait states. lad/ld data valid time can be extended beyond wr# de-assertion if write cycle hold clocks are programmed in bits [31:30]. total 70 table 11-12. non-multiplexed bus mode interface pins (continued) symbol signal name total pins pin type pqfp pin number bga pin number function
section 11 pin description debug interface pci 9030 data book version 1.4 11-18 ? 2002 plx technology, inc. all rights reserved. 11.6 debug interface the pci 9030 provides a jtag boundary scan interface which can be utilized to debug a pin ? s connectivity to the board. 11.6.1 ieee 1149.1 test access port (jtag debug port) the ieee 1149.1 test access port (tap), commonly called the jtag (joint test action group) debug port, is an architectural standard described in ieee standard 1149.1-1990. this standard describes a method for accessing internal chip facilities using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. the enhancements, which comply with ieee standard 1149.1-1990 for vendor- specific extensions, are compatible with standard jtag hardware for boundary-scan system testing. jtag signals ? jtag debug port implements the four required jtag signals ? tck, tms, tdi, tdo ? and the optional trst# signal. jtag clock requirements ? the tck signal frequency can range from dc to one-half of the internal chip clock frequency. jtag reset requirements ? jtag debug port logic is reset at the same time as a system reset. upon receiving trst#, the jtag tap controller returns to the test-logic reset state. 11.6.2 jtag instructions the jtag debug port provides the standard extest, sample/preload, and bypass instructions. invalid instructions behave as the bypass instruction. there are three private instructions. (refer to table 11-13.) the instruction register length is 236 bits, and instruction length is 4 bits. the pci 9030 does not have an idcode register. 11.6.3 jtag boundary scan boundary scan description language (bsdl), ieee 1149.1b-1994, is a supplement to ieee standard 1149.1-1990. bsdl, a subset of the ieee 1076-1993 standard vhsic hardware description language (vhdl), allows a rigorous description of testability features in components which comply with the standard. it is used by automated test pattern generation tools for package interconnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical pin map, instruction set, and boundary register description. the logical port description assigns symbolic names to the pins of a chip. each pin has a logical type of in, out, inout, buffer, or linkage that defines the logical direction of signal flow. the physical pin map correlates the logical ports of the chip to the physical pins of a specific package. a bsdl description can have several physical pin maps; each map is given a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the chip in the various test modes defined by the standard. instruction set statements also support descriptions of instructions that are unique to the chip. the boundary register description lists each cell or shift stage of the boundary register. each cell has a unique number; the cell numbered 0 is the closest to the test data out (tdo) pin and the cell with the highest number is closest to the test data in (tdi) pin. each cell contains additional information, including: cell type, logical port associated with the cell, logical function of the cell, safe value, control cell number, disable value, and result value. notes: the pci 9030 bsdl files for the pqfp and bga packages may be downloaded from the pci 9030 toolbox at http://www.plxtech.com/products/9030.htm refer to pci 9030 errata #5, #6, and #8 for information regarding specific jtag issues. table 11-13. jtag instructions instruction input code comments extest 0000 ieee standard 1149.1-1990 sample/preload 0100 bypass 1111
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 12-1 12 ? electrical specs 12 electrical specifications 12.1 general electrical specifications note: package power dissipation derived with assumption that 1.0m/s air flow is available. the following table lists the package thermal resistance ( j-a ). table 12-1. absolute maximum ratings specification maximum rating storage temperature -55 to +125 c ambient temperature with power applied -40 to +85 c supply voltage to ground -0.5 to +4.6v input voltage (v in )v ss -0.5 to 11.0v output voltage (v out )v ss -0.5v to v dd +0.5 maximum package power dissipation 176-pin pqfp 1w 180-pin bga 0.5w table 12-2. operating ranges ambient temperature supply voltage (v dd ) input voltage (v in ) min max -40 to +85 c 3.0 to 3.6v vss 11.0v table 12-3. capacitance (sample tested only) parameter test conditions pin type value units typical maximum c in v in = 0v input 4 6 pf c out v out = 0v output 6 10 pf table 12-4. package thermal resistance air flow package type 0m/s 1m/s 2m/s 3m/s 176-pin pqfp 65 ( c/w) 45 35 30 180-pin bga 48 ( c/w) 34 26 22
section 12 electrical specifications general electrical specifications pci 9030 data book version 1.4 12-2 ? 2002 plx technology, inc. all rights reserved. notes: 1 except in the case of eecs, eedi, eesk, and ledon# pins. 2 i lpc is the dc current flowing from v dd to ground during precharge, as both pmos and nmos devices remain on during precharge. it is not the leakage current flowing into or out of the pin under precharge. 3 v p is precharge bias voltage. table 12-5. electrical characteristics over operating range parameter description test conditions min max units v oh 1 output high voltage v dd = min v in = v ih or v il i oh = -12.0 ma 2.4 ? v v ol 1 output low voltage i ol = 12 ma ? 0.4 v v ih input high level ?? 2.0 11.0 v v il input low level ?? -0.5 0.8 v v oh3 pci 3.3v output high voltage v dd = min v in = v ih or v il i oh = -500 a 0.9 v dd ? v v ol3 pci 3.3v output low voltage i ol = 1500 a ? 0.1 v dd v v ih3 pci 3.3v input high level ?? 0.5 v dd v dd +0.5 v v il3 pci 3.3v input low level ?? -0.5 0.3 v dd v i il input leakage current v ss v in v dd , v dd = max -10 +10 a i lpc 2 dc current per pin during precharge v p = 0.8 to 1.2v 3 ? 1.0 ma i oz three-state output leakage current v dd = max -10 +10 a i cc power supply current v dd = 3.6v, pclk = 33 mhz, lclk = 60 mhz 80 outputs switching simultaneously ? 150 ma i ccl i cch i ccz quiescent power supply current v cc = max v in = gnd or v cc ? 50 a
section 12 local inputs electrical specifications pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 12-3 12 ? electrical specs 12.2 local inputs definitions: t hold ? time that an input signal is stable after the rising edge of the local clock. t setup ? setup time. the time that an input signal is stable before the rising edge of the local clock. figure 12-1. pci 9030 local input setup and hold waveform note: these values are provided as an example and are only representative of plx pci device general performance characteristics. valid t setup t hold inputs local clock table 12-6. ac electrical characteristics (local inputs) over operating range signals (synchronous inputs) c l = 50 pf, v cc = 3.0v, ta = 85 c bus mode t setup (ns) (worst case) t hold (ns) (worst case) bterm# all 7.0 1 lad[31:0] (data) multiplexed 5.0 1 ld[31:0] non-multiplexed 5.0 1 lpmeset all 5.0 1 lreq all 5.0 1 ready# all 7.0 1 input clocks bus mode min max local clock input frequency all 0 60 mhz pci clock input frequency all 0 33 mhz
section 12 electrical specifications local outputs pci 9030 data book version 1.4 12-4 ? 2002 plx technology, inc. all rights reserved. 12.3 local outputs definition: t valid ? output valid (clock-to-out). the time after the rising edge of the local clock until the output is stable. figure 12-2. pci 9030 local output delay notes: all t valid (min) values are greater than 5 ns. timing derating for loading is 35 ps/pf. these values are provided as an example and are representative only of plx pci device general performance characteristics. table 12-7. ac electrical characteristics (local outputs) over operating range signals (synchronous outputs) v cc = 3.0v, ta = 85 c bus mode output t valid (max) ads# all 10.0 blast# all 10.0 cs[3:0]# all 10.0 la[27:2] all 10.0 lad[31:0] (data) multiplexed 10.0 lbe[3:0]# all 10.0 ld[31:0] non-multiplexed 10.0 lgnt all 11.0 llocko# all 10.0 lpmint# all 10.0 lw/r# all 10.0 rd# all 10.0 waito# all 10.0 wr# all 10.0 valid t va lid t va lid outputs local clock (min) (max)
section 12 local outputs electrical specifications pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 12-5 12 ? electrical specs figure 12-3. pci 9030 ale output delay (min/max) to the local clock 1.5v 1.5v address bus 2.9 / 8.5 ns 3.7 / 10.8 ns 3.8 / 10.9 ns local clock ale lc high - 2.2 / -0.8 ns lc high 3.1 / 8.6 ns

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 13-1 13 ? physical specs 13 physical specifications 13.1 176-pin pqfp figure 13-1. 176-pin pqfp package mechanical dimensions ? topside and cross-section views note: plx technology, inc., has standardized the top side marking for all pci products. marking content has changed and affects inspection, pattern recognition, and tray and board loading equipment. 1 refer to table 13-2 for an explanation of these symbols. b h d 132 89 44 133 45 1 176 index h e e d e 88 topside view r 2 a 2 a max a 1 3 l 2 l l 1 c 1 r cross-section view for 176 pqfp, jc = 5 c/w pci 9030 table 13-1. 176-pin pqfp package mechanical dimensions (legend for figure 13-1) lead type std (qfp18-176 pin std) symbol 1 dimensions (mm) symbol 1 dimensions (mm) min. nom. max. min. nom. max. e 23.9 24 24.1 l 0.3 0.5 0.7 d 23.9 24 24.1 l 1 ? 1 ? a ?? 3l 2 ? 0.5 ? a 1 ? 0.1 ? h e 25.6 26 26.4 a 2 2.6 2.7 2.8 h d 25.6 26 26.4 e ? 0.5 ? 2 ? 15 ? b 0.15 0.2 0.3 3 ? 15 ? c 0.1 0.15 0.2 r ? 0.2 ? 0 ? 10 r 1 ? 0.2 ?
section 13 physical specifications 176-pin pqfp pci 9030 data book version 1.4 13-2 ? 2002 plx technology, inc. all rights reserved. figure 13-2. 176-pin pqfp pcb layout suggested land pattern table 13-2. symbol definitions ? pqfp package symbol term definition symbol term definition e package width width of package c lead thickness thickness of lead (excluding surface plating) d package length length of package lead angle angle of leads versus seating plane a mounting height height from the ground plane to the top of the package 2, 3 chamfer angle package chamfer angle a 1 standoff height height from the ground plane to the bottom edge of the package (pga) l, l 1 , l 2 lead length or length of flat lead section lead length or length of flat lead section a 2 package height height of the package (excluding warp of package) h e overall width width including leads e linear lead pitch theoretical lead pitch h d overall length length b lead width lead width or diameter (excluding surface plating) r, r 1 reverse bending reverse bending type pad width 0.3048 mm pad length 1.524 mm pad pitch = 0.500 mm a = 27.178 mm b = 27.178 mm metal pad 1.016 mm fiducial fiducial solder mask keepout area 2.54 mm
section 13 176-pin pqfp physical specifications pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 13-3 13 ? physical specs figure 13-3. 176-pin pqfp pinout 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 ad28 ad27 ad26 ad25 ad24 c/be3# idsel ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2# frame# irdy# trdy# devsel# stop# lock# perr# serr# par c/be1# ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0# ad7 ad6 ad5 ad28 ad27 ad26 ad25 ad24 c/be3# idsel ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2# frame# irdy# trdy# devsel# stop# lock# perr# serr# par c/be1# ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0# ad7 ad6 ad5 ld12 ld13 ld14 ld15 ld16 ld17 ld18 ld19 ld20 mode ale ld21 ld22 ld23 bclko ld24 ld25 ld26 ld27 ld28 ld29 ld30 ld31 lbe0# lbe1# lbe2# lbe3# cpcisw v i/o ledon# enum# ad0 ad1 ad2 ad3 ad4 lad12 lad13 lad14 lad15 lad16 lad17 lad18 lad19 lad20 mode ale lad21 lad22 lad23 bclko lad24 lad25 lad26 lad27 lad28 lad29 lad30 lad31 lbe0# lbe1# lbe2# lbe3# cpcisw v i/o ledon# enum# ad0 ad1 ad2 ad3 ad4 la23 la22 la21 la20 la19 lpmint# la18 la17 la16 la15 la14 la13 la12 la11 la10 la9 bd_sel#/test la8 la7 la6 la5 la4 la3 la2 ld0 lpmeset ld1 ld2 ld3 ld4 ld5 ld6 gpio8 ld7 ld8 ld9 ld10 ld11 la23 la22 la21 la20 la19 lpmint# la18 la17 la16 la15 la14 la13 la12 la11 la10 la9 bd_sel#/test la8 la7 la6 la5 la4 la3 la2 lad0 lpmeset lad1 lad2 lad3 lad4 lad5 lad6 gpio8 lad7 lad8 lad9 lad10 lad11 gpio7/la24 gpio6/la25 gpio5/la26 gpio4/la27 ads# blast# wr# rd# lw/r# ready# bterm# lclk cs0# cs1# lreseto# lgnt lreq linti1 linti2 gpio0/waito# gpio1/llocko# gpio2/cs2# gpio3/cs3# eecs eedo eesk eedi trst# tck tms tdo tdi pme# inta# rst# pclk ad31 ad30 ad29 gpio7/la24 gpio6/la25 gpio5/la26 gpio4/la27 ads# blast# wr# rd# lw/r# ready# bterm# lclk cs0# cs1# lreseto# lgnt lreq linti1 linti2 gpio0/waito# gpio1/llocko# gpio2/cs2# gpio3/cs3# eecs eedo eesk eedi trst# tck tms tdo tdi pme# inta# rst# pclk ad31 ad30 ad29 v ss v ss v ss v dd v ss v dd v ss v ss v ss v dd v ss v dd v dd v dd v ss v dd v ss v ss v dd v dd v ss v dd v ss v ss v ss v dd v ss v dd v ss v ss v dd v dd v ss v dd v ss v dd v ss v ss v dd v dd v dd v ss v dd v ss v ss v dd v ss v dd v ss v ss pci 9030 non-multiplexed (inner column) multiplexed (outer column)
section 13 physical specifications 180-pin bga pci 9030 data book version 1.4 13-4 ? 2002 plx technology, inc. all rights reserved. 13.2 180-pin bga figure 13-4. 180-pin bga package mechanical dimensions ? topside, underside, and cross-section views note: plx technology, inc., has standardized the top side marking for all pci products. marking content has changed and affects inspection, pattern recognition, and tray and board loading equipment. 1 refer to table 13-4 for an explanation of these symbols. cross-section view a a 1 d y s s d topside view underside view e e s d z d z e s e ? b ? x m pci 9030 pnmlk j hgfedcba abcdefghj k lmnp 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 table 13-3. 180-pin bga package mechanical dimensions (legend for figure 13-4) symbol 1 dimensions (mm) symbol 1 dimensions (mm) min. nom. max. min. nom. max. d 11.85 12.0 12.3 x ?? 0.08 e 11.85 12.0 12.3 y ?? 0.10 a ?? 1.20 s d ? 0.40 ? a 1 0.30 0.35 0.45 s e ? 0.40 ? e ? 0.80 ? z d ? 0.80 ? ? b 0.400.450.55 z e ? 0.80 ?
section 13 180-pin bga physical specifications pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 13-5 13 ? physical specs figure 13-5. 180-pin bga pcb layout suggested land pattern table 13-4. symbol definitions ? bga package symbol term definition symbol term definition e package width width of package a 1 ball height height from the ground plane to the bottom edge of the package (pga) d package length length of package e ball pitch theoretical lead pitch a height height from the ground plane to the top of the package b ball width ball width or diameter (excluding surface plating) solder mask 0.35 mm diameter land solder mask keepout 0.05 ? 0.07 mm 0.15 mm fhs 0.508 mm via pad diameter detail of each pad and breakout creating a solder mask clearance using the via pad is not recommended. 13 mm 13 mm topside view copper crop lines (allows for visual inspection of whether the bga is centered on the pads) pin a1 pin a1 designator (silkscreen) 0.8 mm 0.25 mm 1.27 mm
section 13 physical specifications 180-pin bga pci 9030 data book version 1.4 13-6 ? 2002 plx technology, inc. all rights reserved. figure 13-6. 180-pin bga physical layout with pinout ? topside view 14 nc v ss la21 la20 la17 la15 la11 la8 la3 lad1 (m) ld1 (nm) lad3 (m) ld3 (nm) lad7 (m) ld7 (nm) lad8 (m) ld8 (nm) nc 13 gpio5 la26 v dd la23 lpmint# v ss la12 v ss la5 lad0 (m) ld0 (nm) v dd lad6 (m) ld6 (nm) lad9 (m) ld9 (nm) lad11 (m) ld11 (nm) v ss 12 gpio4 la27 gpio6 la25 gpio7 la24 la19 la16 la13 la9 la6 lpmeset lad2 (m) ld2 (nm) gpio8 lad10 (m) ld10 (nm) lad12 (m) ld12 (nm) v dd 11 lw/r# blast# ads# la22 la18 v dd bd_sel# test la7 la2 lad4 (m) ld4 (nm) lad13 (m) ld13 (nm) lad15 (m) ld15 (nm) lad16 (m) ld16 (nm) lad14 (m) ld14 (nm) 10 v ss bterm# ready# rd# wr# la14 la10 la4 v ss lad5 (m) ld5 (nm) lad17 (m) ld17 (nm) lad19 (m) ld19 (nm) v ss lad18 (m) ld18 (nm) 9 lgnt cs1# cs0# lreseto# lclk mode lad22 (m) ld22 (nm) ale lad21 (m) ld21 (nm) lad20 (m) ld20 (nm) 8 gpio1 llocko# linti1 linti2 gpio0 waito# lreq bclko lad25 (m) ld25 (nm) v dd lad24 (m) ld24 (nm) lad23 (m) ld23 (nm) 7 eesk gpio3 cs3# eecs gpio2 cs2# eedo lad29 (m) ld29 (nm) v ss lad27 (m) ld27 (nm) lad28 (m) ld28 (nm) lad26 (m) ld26 (nm) 6 tck v dd v ss eedi trst# v ss lad31 (m) ld31 (nm) lbe1# lbe0# lad30 (m) ld30 (nm) 5 tdi tms tdo pme# idsel v ss c/be2# serr# v dd ledon# v i/o lbe3# v dd lbe2# 4 pclk inta# rst# ad30 ad23 ad17 trdy# stop# c/be1# ad10 ad6 ad0 enum# cpcisw 3 ad31 ad29 ad28 ad24 ad21 ad19 irdy# perr# v ss ad12 ad8 ad4 ad3 ad1 2 v ss v dd ad27 c/be3# ad20 ad18 frame# lock# ad15 ad13 ad9 ad5 v dd ad2 1 nc ad26 ad25 ad22 v dd ad16 devsel# par ad14 ad11 c/be0# ad7 v ss nc abcdefghjklmnp 14 13 12 11 10 9 8 7 6 5 4 3 2 1
section 13 180-pin bga physical specifications pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. 13-7 13 ? physical specs table 13-5. 180-pin bga six-layer board routing example (four routing layers) ? sample parameters routing layer parameters via size (mm) other parameters via size (mm) component side 0.509 land pad side 0.350 first inside layer 0.634 solder mask opening 0.549 second inside layer 0.634 trace width 0.127 solder side 0.634 drill size for the via 0.254 hole side for the via 0.152
section 13 physical specifications 180-pin bga pci 9030 data book version 1.4 13-8 ? 2002 plx technology, inc. all rights reserved. figure 13-7. 180-pin bga six-layer board routing example (four routing layers) ? component side figure 13-8. 180-pin bga six-layer board routing example (four routing layers) ? first inside layer figure 13-9. 180-pin bga six-layer board routing example (four routing layers) ? second inside layer figure 13-10. 180-pin bga six-layer board routing example (four routing layers) ? solder side via solder trace solder pad
pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. a-1 a ? general info a general information the pci 9030 is a 32-bit, 33-mhz pci bus target interface device featuring advanced smartarget technology, which includes a programmable target interface. the pci 9030 offers 3.3, 5v tolerant pci and local signaling, supports universal pci adapter designs, 3.3v core, low-power cmos offered in two package options ? 176-pin pqfp and 180-pin (ball) bga . the device is designed to operate at industrial temperature range. a.1 ordering instructions continuing its drive to provide single-chip pci interfaces for every market, plx offers to designers its pci 9030 pci smartarget picmg 2.1, r2.0 pi = 0 compliant, i/o accelerator for adapters and embedded systems. a.2 united states and international representatives, and distributors a list of plx technology, inc., representatives and distributors can be found at http: ?? www.plxtech.com. a.3 technical support plx technology, inc., technical support information is listed at http: ?? www.plxtech.com, or call 408 774-9060 or 800 759-3735. table a-1. available packages package ordering part number 176-pin pqfp pci 9030-aa60pi 180-pin bga pci 9030-aa60bi

pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-1 index index a abort, master, not supported 10-5 abort, target 2-1, 10-5 absolute maximum ratings 12-1 ac electrical characteristics 12-3, 12-4 accelerator, i/o 1-1 accesses 1-4, 2-1, 2-10, 3-1, 4-4, 4-5, 10-4, 10-10, 10-11 disabled 7-2, 7-3 hot swap 8-1, 8-2, 8-3 i/o 3-7, 10-13 internal register 3-6 ? 3-7 local bus 2-6, 2-8, 2-10 memory 2-9, 3-6 pci 2-1, 2-2, 4-1, 4-6, 4-7, 10-3, 10-19, 10-20, 10-35 base address registers 10-7 ? 10-9 slave 1-3 tap 11-18 vpd 9-1, 10-15, 10-33 ad[31:0] 11-7, 13-3, 13-6 adapter card compactpci 1-2 pmc 1-3 address address-to-data 2-8 boundary 2-9 burst start 2-10 bus state 2-3 chip select base registers 10-31, 10-32 cycle 2-9, 2-10 decode 10-10, 10-18 eromba 10-20 invariance 2-1, 2-11 local address space bus region descriptor registers 10-21 ? 10-27 local address space local base address registers 10-19 ? 10-20 local address space range registers 10-16 ? 10-17 local bits 2-2 mapping 4-3, 4-4 multiplexed and non-multiplexed bus modes 11-1 multiplexed bus mode 11-12 non-multiplexed bus mode 11-15 pci 3-7, 4-3 ? 4-7, 10-15 base address registers 10-7 ? 10-9 system bus interface pins 11-7 pointer 10-1 prot_area 10-33 read ahead mode, pci target 4-3 register mapping 10-2 ? 10-3 registers 1-5, 3-3, 4-1 spaces 1-1, 1-3, 1-5, 2-10, 5-1 ? 5-2 stepping 10-4 vpd 9-1 address/data 1-3, 2-3, 2-4, 2-6, 2-9, 4-4, 10-4, 11-13 ads# 11-12, 11-15, 13-3, 13-6 ale 2-4, 11-12, 11-15, 13-3, 13-6 arbitration, local bus 2-3, 2-5 timing diagram 2-6, 4-9 architecture boundary scan 11-18 risc and bridge 2-2 asynchronous resets 1-2, 8-1 atomic operations llocko# 2-4, 11-3, 11-9, 13-3, 13-6 lock# 11-7, 13-3, 13-6 locked 4-1 b b 0 -b 3 power management states 7-1 back-to-back fast 10-4, 10-5 timing diagrams 4-23 ? 4-26 bclko 11-9, 13-3, 13-6 bd_sel# 8-1, 11-1, 11-6, 13-3, 13-6 big endian see endian, big/little bios 2-1, 3-6, 6-1, 7-1, 10-18 blast# 11-12, 11-15, 13-3, 13-6 board routing, bga 13-7 ? 13-8 bridge architecture 2-2 bterm# 2-8, 2-9, 11-1, 11-12, 11-15, 13-3, 13-6 buffers enum# three-state 11-2 i/o 1-2, 8-1, 8-2, 11-4 output 8-1, 11-5 posted memory write (pmw), bridge 2-2 bursts continuous mode 2-9 ? 2-10 expansion rom enable 10-29 last and terminate 11-12, 11-15 memory space enable 10-21 ? 10-27 pci 4-1, 4-3, 4-4 period device 10-11 read and write 11-7 timing diagrams 4-16 ? 4-20, 4-29 ? 4-31, 4-36 ? 4-41 transfers 1-1, 1-3
bus modes to deadlock, avoided with pmw pci 9030 data book version 1.4 index-2 ? 2002 plx technology, inc. all rights reserved. bus modes see multiplexed mode and non-multiplexed mode bus region descriptor registers 2-4, 3-4, 4-5, 4-6, 10-8, 10-9, 10-21 ? 10-29, 11-14, 11-17 address mapping 10-3 bus states 2-3 byte conversion, big/little endian 1-1, 1-3 byte enables 2-1, 2-10, 4-2 pci target 4-7 see also c/be[3:0]# and lbe[3:0]# byte merging 2-1 ? 2-2 c c/be[3:0]# 2-1, 4-2, 11-7, 13-3, 13-6 cache line size, pci 3-6, 10-6 cap_ptr 3-3, 3-7, 7-1, 10-10 capacitance 12-1 chip select 11-9 base address registers 5-1 ? 5-4, 10-31 cntrl 10-35 idsel and initialization device 11-7 local 5-1 ? 5-4, 10-3 lsw and msw 3-4 pins 11-9 programmable 1-2, 1-3 registers, address mapping 10-3 serial eeprom 10-35, 11-5 smartarget 1-1 timing diagrams 4-12, 4-16, 5-3 ? 5-4 clocks 1-4, 4-2, 7-1, 10-34, 11-8 bus access 11-12, 11-15 delay 10-35 eesk 3-1, 11-5 local 6-2, 11-1, 11-10, 12-3 ? 12-5 pci 1-3, 1-5, 3-1, 3-8, 4-3, 4-4, 4-13, 6-2, 10-12, 11-9, 11-10, 12-3 serial eeprom 3-1, 10-35, 11-5 cntrl 1-5, 2-5, 3-1, 3-4, 4-1, 4-2, 4-4, 4-8, 10-34 ? 10-35 command codes, pci target 2-1 compactpci hot swap 1-2, 8-1 ? 8-4 compliant 1-3 registers 10-1, 10-2, 10-14 configuration accesses 1-4, 3-1, 7-2, 10-13 big/little endian 4-4 bterm# 11-12, 11-15 bus-width 11-13, 11-16 command type 2-1 control/status register 8-3 cs[1:0]# 11-9 cycles 3-7, 7-1, 7-3 hot swap 8-1, 8-3 i/o-mapped register 3-7 idsel 11-7 load information 1-4 local registers 3-1, 3-6 memory-mapped register 3-7 new capabilities 9-1 new capability linked list 10-1 pci cycles 7-1 pci registers 3-6, 3-7, 10-4 ? 10-15 power management 7-2 read and write 11-7 register space 1-4 registers 3-1, 4-1, 11-9, 11-12, 11-15 serial eeprom 3-1 software reset 3-1 space 8-3, 9-1, 10-1 subsystem id and subsystem vendor id 1-4 system reconfiguration 8-1, 8-3 target bus-width 11-16 timing diagrams, initialization 3-9 ? 3-10, 4-14 ? 4-15 vpd 9-1 wait states counter 2-8 continuous burst mode 2-9 ? 2-10 continuous prefetch mode 4-3, 4-4 control registers 10-33 ? 10-37 address mapping 10-3 control signals 2-3 control/status 2-4 ? 2-5 controller, programmable interrupt 1-1, 1-3 conversion, big/little endian 1-1, 1-3, 1-5, 4-4 counter prefetch 1-5, 4-1 register bits 10-21, 10-23, 10-25, 10-27, 10-29 timing diagrams, settings in 4-30, 4-40 wait states 2-8 cpcisw 8-1, 11-1, 11-9, 13-3, 13-6 cpu host 2-6, 8-3 local 7-3, 10-13 cs[1:0]# 11-9, 13-3, 13-6 cs0base 3-4, 10-31 cs1base 3-4, 10-31 cs2# 11-3, 11-9, 13-3, 13-6 cs2base 3-4, 10-32 cs3# 11-3, 11-9, 13-3, 13-6 cs3base 3-4, 10-32 d d 3hot 10-12 data/wait bus state 2-3 deadlock, avoided with pmw 1-3
debug to i/o pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-3 index debug interface and port 11-18 pins 11-6 decode 4-5 address enable 10-10 delayed read mode, pci target 1-5, 4-2, 4-3 cntrl 10-34 read accesses 2-10 delayed write mode, pci target 1-3, 1-5, 4-3, 10-34 timing diagram 4-16, 5-4 descriptors, bus region 2-4, 3-4, 4-5, 10-8, 10-9, 10-21 ? 10-29, 11-14, 11-17 address mapping 10-3 device chip select 5-1, 5-2 configuration header 3-6 id 3-1, 3-3, 9-1, 10-4 devsel# 11-7, 13-3, 13-6 direct slave see pci target disconnect after transfer for all pci target i/o accesses 4-1 flush read fifo 10-35 pci bus 3-7, 4-4 pci r2.2 features enable 4-42 pci write 10-35 dsp devices 2-2 e early power 8-1, 8-2, 11-1, 11-6 eecs 11-5, 13-3, 13-6 eedi 11-5, 13-3, 13-6 eedo 11-1, 11-5, 11-6, 13-3, 13-6 eesk 11-5, 13-3, 13-6 electrical specifications 12-1 ? 12-5 embedded design 11-1 systems 1-1 endian, big/little 2-10 ? 2-12 byte lane mode and byte ordering 10-22, 10-24, 10-26, 10-28, 10-30 conversion 1-1, 1-3, 1-5, 4-4 local bus 2-10 ? 2-11 pci bus little endian mode 2-1 enum# 1-2, 8-1, 8-3, 10-14, 11-2, 11-7, 13-3, 13-6 eromba 3-4, 4-4, 10-20 erombrd 3-4, 4-5, 10-29 eromrr 3-3, 4-4, 10-10, 10-18 expansion rom 1-3, 2-10, 3-3, 4-1, 4-4, 4-7, 10-2, 10-3 local bus width 10-29 space 3-7, 4-1, 4-7 access, address decode enable 10-10 input enables, bterm# and ready# 10-29 local address 4-1 remap 10-20 external wait states 2-10, 4-1, 4-41 f fifos 10-35 cntrl, in 10-35 continuous burst mode 2-10 pci target 1-3 ? 1-5, 3-1, 4-1 ? 4-3, 4-4 response to full/empty 4-8 flush 4-2 frame# 11-7, 13-3, 13-6 g general purpose i/o 6-1 ? 6-3, 11-3, 11-9, 13-3, 13-6 control register (gpioc) 10-36 ? 10-37 timing diagrams 4-11, 6-5 see also gpio-related entries generator programmable interrupt 1-1, 1-3 programmable wait states 4-1, 11-9, 11-12, 11-15 gpio programmable general purpose i/o 1-3 smartarget 1-1 see also general purpose i/o gpio[7:4] 4-11, 6-5, 11-3, 11-13, 11-15, 13-3, 13-6 gpio[8, 3:0] 4-11, 6-5, 11-3, 11-10, 13-3 gpioc 6-3, 10-36 ? 10-37 h header format 10-18 pci type 3-6 hidden registers 3-4, 3-5, 7-2, 7-3, 10-1, 10-3, 10-13, 10-14, 10-37 high-polarity mode 10-33 hold waveform 12-3 hot swap 8-1 ? 8-4, 10-14 control/status register (hs_csr) 1-2, 8-1 silicon 1-2 see also compactpci hot-plug system driver 8-3 hs_cntl 3-3, 8-4, 10-14 hs_csr 1-2, 8-1, 8-3, 10-14, 11-2 hs_next 3-3, 3-7, 8-4, 10-14 i i/o accelerator 1-1 accesses 2-1, 4-4, 10-7, 10-13 disabled in d 3hot state 7-2 internal registers 3-7 base address 10-7 buffers 1-2, 8-1, 8-2, 11-4
i960j function, not supported to lclk pci 9030 data book version 1.4 index-4 ? 2002 plx technology, inc. all rights reserved. data i/o for programming serial eeprom values 3-2 general purpose 6-1 ? 6-3, 11-3, 11-9, 13-3, 13-6 gpioc register 10-36 ? 10-37 hot swap requirement 8-1 initialization control (cntrl) 10-34 ? 10-35 insertion and extraction, during 8-2 mapped accesses 1-3 mapped configuration registers 10-2 pin type 11-3, 11-7, 11-11, 11-13, 11-16 read 2-1 smartarget 1-1 space access 10-4, 10-7, 10-8, 10-9, 10-16, 10-17, 10-19, 10-20 tolerance 1-4 write 2-1 i960j function, not supported 2-10 id capability 10-2 class code 9-1 configuration 10-4 device 1-4, 1-5, 3-1, 9-1, 10-2, 10-4 hot swap 8-4, 10-14 network 1-4 new capability function 10-5 power management 7-1, 10-1, 10-12 revision 3-3, 3-6, 9-1, 10-2, 10-5 silicon revision 1-4, 10-5 subsystem and subsystem vendor 1-4, 3-1, 9-1, 10-2, 10-10 vendor 1-4, 1-5, 3-1, 9-1, 10-2, 10-4 vpd 9-1, 10-1, 10-15 idle bus state 2-3 idsel 11-7, 13-3, 13-6 ieee standard 1149.1-1990 11-18 ieee standard test access port and boundary-scan architecture see ieee standard 1149.1-1990 initialization 4-5 configuration timing diagrams 3-9 ? 3-10, 4-14 ? 4-15 control (cntrl) register 10-3, 10-34 ? 10-35 functional description 3-1 idsel 11-7 pci 4-7 pmc 10-12 serial eeprom 3-1 ? 3-10 serial eeprom (2k or 4k) timing diagram, from 3-8, 4-13 input, general purpose see general purpose i/o inta# 6-1, 10-11, 11-7, 13-3, 13-6 intcsr 3-4, 6-2, 10-33 interface chip, target 1-3 internal wait states 2-5, 2-7 ? 2-8, 2-10, 4-1, 4-35, 10-21 ? 10-29, 11-9, 11-14 interrupt control/status 10-3, 10-33 controller 1-1, 1-3 disabled 7-1, 10-13 enum# 8-3, 10-14 generator 1-1, 1-3 input, lint[2:1] 11-2, 11-10, 13-3, 13-6 line 10-2, 10-11 local level and edge-triggered 4-10, 6-4 linti1 and linti2 11-10 power management (lpmint#) 7-3, 11-11 lsw 3-4 output set by enum# 11-7 pci and local 6-1 ? 6-3 pci power management functional description 7-1 ? 7-3 pin 3-3, 10-2, 10-11 registers 3-7 request 6-1, 10-11, 11-7 timing diagrams 4-10, 6-4 wake-up event 11-8 interrupts enum# 8-4 irdy# 2-1, 11-7, 13-3, 13-6 irq 6-1 isa bus interface 1-5 j jtag 11-18 l la[23:2] 11-13, 11-16, 13-3, 13-6 la[27:24] 11-3, 11-12, 11-15, 13-3, 13-6 lad[31:0] 2-3, 11-3, 11-13, 13-3, 13-6 las0ba 3-3, 4-4, 4-7, 10-8, 10-19 las0brd 2-8, 3-4, 4-3, 4-5, 10-21 las0rr 3-3, 4-4, 10-8, 10-16 las1ba 3-4, 4-4, 4-7, 10-8, 10-19 las1brd 2-8, 3-4, 4-3, 4-5, 10-23 las1rr 3-3, 4-4, 10-8, 10-16 las2ba 3-4, 4-4, 10-9, 10-20 las2brd 2-8, 3-4, 4-3, 4-5, 10-25 las2rr 3-3, 4-4, 10-9, 10-17 las3ba 3-4, 4-4, 10-9, 10-20 las3brd 2-8, 3-4, 4-3, 4-5, 10-27 las3rr 3-3, 4-4, 10-9, 10-17 latency timer, pci, not supported 10-2, 10-6 layers, routing, bga 13-7 ? 13-8 lbe[3:0]# 2-4, 11-13, 11-16, 13-3, 13-6 lclk 11-1, 11-10, 12-2, 13-3, 13-6
ld[31:0] to memory pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-5 index ld[31:0] 2-4, 11-3, 11-16, 13-3, 13-6 ledon# 8-1, 11-2, 11-10, 13-3, 13-6 level-sensitive mode 6-1, 6-2, 11-10 lgnt 2-5, 11-10, 13-3, 13-6 linti[2:1] 11-2, 11-10, 13-3, 13-6 little endian see endian, big/little llocko# 1-5, 2-4, 4-44, 6-3, 10-36, 11-3, 11-9, 13-3, 13-6 local clocks 1-4, 6-2, 11-1, 12-3 ? 12-5 configuration registers 10-3, 10-16 ? 10-30, 10-33 input setup 12-3 power management enumerator set 6-2 signals 2-3, 12-4 local address big/little endian mode 2-10 bits la[1:0] 2-2 expansion rom local base address register 10-20 increment 11-13, 11-16 mapping 4-4 pci 1-3, 4-7 base address registers 10-8 ? 10-9 space bus region descriptor registers 10-21 ? 10-27 space local base address registers 10-19 ? 10-20 space range registers 10-16 ? 10-17 spaces 1-5, 4-1, 10-2, 10-3 local bus 2-2 ? 2-12 characteristics 4-5 configuration registers 10-3 control 4-4 delayed read mode, pci target 4-2 fifo, response to full or empty 4-8 i/os 8-2 independent interface pins 11-9 internal register access 3-6 memory map example 5-2 pci target 1-3, 1-5, 3-1, 4-1 ? 4-7, 10-35 pcisr 10-5 pin information 11-1 pmcsr 10-13 power management 7-1 prefetch 4-3 programmable 1-3 read ahead mode, pci target 4-3 ready# timeout 10-34 serial eeprom 3-1 signaling 1-4, 1-5 soft reset 7-2 vpd 9-1 width 1-1, 4-7 local bus region descriptor registers 2-4, 4-5, 10-21 ? 10-29, 11-14, 11-17 address mapping 10-3 local chip selects see chip select lock 4-1 atomic operations 11-9 cntrl 10-35 cycles 1-5 llocko# 2-4, 11-3, 11-9, 13-3, 13-6 lock# 10-35, 11-7, 13-3, 13-6 pci target enable 10-35 lock# 10-35, 11-7, 13-3, 13-6 lpmeset 11-2, 11-11, 13-3, 13-6 lpmint# 6-2, 11-11, 13-3, 13-6 lreq 2-5, 11-2, 11-11, 13-3, 13-6 lreseto# 3-1, 11-11, 13-3, 13-6 lw/r# 2-4, 11-14, 11-16, 13-3, 13-6 m map memory 5-2 pci software 4-5 pci target 1-3 read accesses 4-4 registers 3-7 serial eeprom memory 3-2 see also mapping and remap mapping address 4-3 expansion rom local base address register 10-20 local address space local base address registers 10-19 ? 10-20 local registers 4-1 memory, prefetchable 2-1 ? 2-2 register address 10-2 ? 10-3 master abort, not supported 10-5 maximum ratings 12-1 memory accesses 2-9, 3-6, 3-7, 10-2, 10-7, 10-8, 10-9 address spaces 10-16, 10-17, 10-19, 10-20 bterm# 2-9 burst memory-mapped 1-3 commands aliased to basic 2-1 cycle 3-7 disabled 7-1 local controller 2-8 local spaces 1-3 map example 5-2 mapping, prefetchable 2-1 ? 2-2 pci 4-4, 7-2, 10-13 posted writes (pmw) 1-3 read 2-1, 4-4
bga to pci r2.2 pci 9030 data book version 1.4 index-6 ? 2002 plx technology, inc. all rights reserved. cycle 10-21, 10-23, 10-25, 10-27, 10-29 serial eeprom map 3-2 timing diagrams 3-10, 4-15 write 2-1, 10-4 bga product ordering and support a-1 layers, routing 13-7 ? 13-8 package mechanical dimensions 13-4 pcb layout suggested land pattern 13-5 pinout 13-6 mode 11-2, 11-11, 13-3, 13-6 modes, bus see multiplexed mode and non-multiplexed mode multiplexed mode 11-2, 11-7, 11-9 ? 11-11 bus mode 11-12 ? 11-14 byte number and lane cross-reference 2-11 interface pin 11-1 local bus 1-3, 2-6 programmable local bus 1-3 recovery states 2-10 timing diagrams 4-9 ? 4-31 n nc (bga) 11-4, 13-6 networking 1-1 new capabilities functions support 10-5 linked list 7-1 next_cap pointer 8-4 pointer (cap_ptr) 7-1, 10-1, 10-10 structure 3-7, 8-4, 9-1 support bit 7-1 vpd 9-1 non-burst see burst non-multiplexed mode 11-9 ? 11-11 big/little endian byte number and lane cross-reference 2-11 bus mode 11-15 ? 11-17 interface pin 11-1 local bus 1-3, 2-6 programmable local bus modes 1-3 recovery states 2-10 timing diagrams 4-9 ? 4-26, 4-32 ? 4-45 nrad, nrdd, nwad, nwdd, and nxda 2-8, 10-21 ? 10-29 see also internal wait states o operating ranges 12-1 output, general purpose see general purpose i/o p package mechanical dimensions bga 13-4 pqfp 13-1 par 11-8, 13-3, 13-6 pci 3-6, 3-7, 4-38 applications 1-2 ? 1-3 clock 1-3, 1-4, 1-5, 3-1, 3-8, 4-2, 4-3, 4-13, 6-2, 10-12, 10-34, 11-9, 12-3 pci 9030 compared with pci 9050 and 9052 1-5 compatibility with other plx chips 1-4 product ordering and customer support a-1 smartarget features 1-3 pci bus 1-3, 2-1 ? 2-2, 2-10, 11-11, 12-3, 12-4 access to internal registers 3-7 board healthy 8-2 cntrl 10-35 cycles 2-1 disconnect 4-4 fifo, response to full or empty 4-8 gpioc 6-3 hot swap ready target device 1-1 input rst# 3-1 interface 2-1 latency timer, not supported 10-2, 10-6 little endian mode 2-1 local address spaces 4-4, 4-7 pci target operation 4-1, 4-4 pcisr 3-3, 7-1, 10-5 region 4-5, 4-6, 10-3, 10-8, 10-9 soft reset 7-1, 7-2 software reset 3-1 system bus interface pins 11-7 ? 11-8 target lock 4-1 transactions 4-4 v cc 1-5 vpd 9-1 wait states 2-1, 2-8 pci bus power management interface specification, revision 1.1 see pci power mgmt. r1.1 pci configuration registers 10-4 ? 10-15 address mapping 10-2 pci industrial implementations 1-1 pci initiator, not supported 2-6 pci local bus specification, revision 2.2 see pci r2.2 pci power mgmt. r1.1 1-1, 7-1, 7-2, 7-3, 10-12 pci r2.2 1-1, 1-2, 1-5, 2-1, 3-6, 4-2, 4-42, 7-1, 9-1, 10-2, 10-16, 10-17, 10-34, 11-1, 11-7
pci target to pins, no connect (nc, bga) pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-7 index pci target 4-1 ? 4-45 abort 2-1, 10-5 accesses 10-19, 10-20 8- or 16-bit local bus, to 2-2 big endian/little endian mode, local bus 2-10 partial lword 2-10 big endian/little endian cycle reference table 2-11 bterm# input 2-9 bursting 1-3 command codes 2-1 delayed read mode 1-5, 4-2, 10-34 delayed write mode 1-3, 1-5, 10-34 timing diagram 5-4 description 1-1 fifo depth 1-3, 1-5 interface chip 1-3 power management 7-1 power mode example 7-3 read ahead mode 1-1, 1-3, 2-10, 3-1, 10-35 ready# timeout, local bus 1-5, 10-34 response (cntrl) 10-3, 10-34 ? 10-35 smartarget 1-1 timing diagram 4-16 transactions 1-3 wait states 2-8 pcibar0 3-7, 4-4, 10-7 pcibar1 3-7, 4-4, 10-7 pcibar2 4-4, 10-8 pcibar3 4-4, 10-8 pcibar4 4-4, 10-9 pcibar5 4-4, 10-9 pcibistr (not supported) 10-6 pciccr 3-3, 10-5 pcicis (not supported) 10-10 pciclsr 3-6, 10-6 pcicr 6-2, 10-4 pcierbar 3-7, 4-4, 10-10 pcihtr 3-6, 10-6 pciidr 3-3, 10-4 pciilr 3-3, 10-11 pciipr 3-3, 10-11 pciltr (not supported) 10-6 pcimgr (not supported) 10-11 pcimlr (not supported) 10-11 pcirev 3-3, 10-5 pcisid 3-3, 10-10 pcisr 3-3, 7-1, 10-5 pcisvid 3-3, 10-4, 10-10 pclk 11-8, 12-2, 13-3, 13-6 performance features 1-3 perr# 11-8, 13-3, 13-6 physical specs 13-1 ? 13-8 picmg 2.1, r2.0 1-2, 1-3, 8-1, 8-1 pinout bga 13-6 pqfp 13-3 pins bd_sel# 8-1 cpcisw 8-1 enum# 1-2, 8-1 ledon# 8-1 v io 8-1 pins, debug and test see pins, test and debug pins, hot swap bd_sel# 11-1, 11-6 cpcisw 11-1, 11-9 enum# 11-2, 11-7 ledon# 11-2, 11-10 pins, local bus mode independent interface bclko 11-9, 13-3, 13-6 cpcisw 11-1, 11-9, 13-3, 13-6 cs[1:0]# 11-9, 13-3, 13-6 cs2# 11-3, 11-9, 13-3, 13-6 cs3# 11-3, 11-9, 13-3, 13-6 gpio[8, 3:0] 4-11, 6-5, 11-3, 11-10, 13-3 lclk 11-1, 11-10, 12-2, 13-3, 13-6 ledon# 11-2, 11-10, 13-3, 13-6 lgnt 2-5, 11-10, 13-3, 13-6 linti[2:1] 11-2, 11-10, 13-3, 13-6 llocko# 2-4, 11-3, 11-9, 13-3, 13-6 lpmeset 11-2, 11-11, 13-3, 13-6 lpmint# 11-11, 13-3, 13-6 lreq 2-5, 11-2, 11-11, 13-3, 13-6 lreseto# 3-1, 11-11, 13-3, 13-6 mode 11-2, 11-11, 13-3, 13-6 waito# 2-5, 11-3, 11-9, 13-3, 13-6 pins, multiplexed bus mode interface ads# 2-4, 11-12, 13-3, 13-6 ale 2-4, 11-12, 13-3, 13-6 blast# 11-12, 13-3, 13-6 bterm# 2-8, 11-1, 11-12, 13-3, 13-6 gpio[7:4] 4-11, 6-5, 11-3, 11-13, 13-3, 13-6 la[23:2] 11-13, 13-3, 13-6 la[27:24] 11-3, 11-12, 13-3, 13-6 lad[31:0] 2-3, 11-3, 11-13, 13-3, 13-6 lbe[3:0]# 2-4, 11-13, 13-3, 13-6 lw/r# 2-4, 11-14, 13-3, 13-6 rd# 2-4, 10-22 ? 10-30, 11-14, 13-3, 13-6 ready# 2-5, 2-8, 11-2, 11-14, 13-3, 13-6 wr# 2-5, 10-22 ? 10-30, 11-14, 13-3, 13-6 pins, no connect (nc, bga) 11-4, 13-6
pins, non-multiplexed bus mode interface to prefetch pci 9030 data book version 1.4 index-8 ? 2002 plx technology, inc. all rights reserved. pins, non-multiplexed bus mode interface ads# 11-15, 13-3, 13-6 ale 11-15, 13-3, 13-6 blast# 11-15, 13-3, 13-6 bterm# 11-15, 13-3, 13-6 gpio[7:4] 11-15, 13-3, 13-6 la[23:2] 11-16, 13-3, 13-6 la[27:24] 11-15, 13-3, 13-6 lbe[3:0]# 2-4, 11-16, 13-3, 13-6 ld[31:0] 2-4, 11-3, 11-16, 13-3, 13-6 lw/r# 2-4, 11-16, 13-3, 13-6 rd# 2-4, 11-17, 13-3, 13-6 ready# 2-5, 11-17, 13-3, 13-6 wr# 2-5, 11-17, 13-3, 13-6 pins, pci system bus interface ad[31:0] 11-7, 13-3, 13-6 c/be[3:0]# 4-2, 11-7, 13-3, 13-6 devsel# 11-7, 13-3, 13-6 enum# 11-2, 11-7, 13-3, 13-6 frame# 11-7, 13-3, 13-6 idsel 11-7, 13-3, 13-6 inta# 10-11, 11-7, 13-3, 13-6 irdy# 2-1, 11-7, 13-3, 13-6 lock# 11-7, 13-3, 13-6 par 11-8, 13-3, 13-6 pclk 11-8, 12-2, 13-3, 13-6 perr# 11-8, 13-3, 13-6 pme# 11-8, 13-3, 13-6 rst# 3-1, 11-8, 13-3, 13-6 serr# 11-8, 13-3, 13-6 stop# 11-8, 13-3, 13-6 trdy# 2-1, 4-4, 11-8, 13-3, 13-6 pins, power and ground (bga) v dd 11-4, 13-6 v i/o 11-4, 13-6 v ss 11-4, 13-6 pins, power and ground (pqfp) v dd 11-1, 11-4, 13-3 v i/o 11-4, 13-3 v ss 11-2, 11-4, 13-3 pins, serial eeprom interface eecs 11-5, 13-3, 13-6 eedi 11-5, 13-3, 13-6 eedo 11-1, 11-5, 11-6, 13-3, 13-6 eesk 11-5, 13-3, 13-6 pins, test and debug bd_sel# 11-1, 11-6, 13-3, 13-6 tck 11-2, 11-6, 11-18, 13-3, 13-6 tdi 11-2, 11-6, 11-18, 13-3, 13-6 tdo 11-6, 11-18, 13-3, 13-6 test 11-1, 11-6, 13-3, 13-6 tms 11-2, 11-6, 11-18, 13-3, 13-6 trst# 11-2, 11-6, 11-18, 13-3, 13-6 platform, reset 8-2 plx technology, inc. company background 1-1 product ordering and customer support a-1 plxmon 3-2, 6-2 pmc register 3-3, 3-5, 7-2, 10-12 typical adapter card 1-3 pmcapid 3-3, 7-1, 10-12 pmcsr 3-3, 3-5, 6-2, 7-2, 7-3, 10-1, 10-2, 10-13, 10-14, 10-37, 11-11 pmcsr_bse 10-13 pmdata 3-5, 7-2, 7-3, 10-14, 10-37 pmdatascale (hidden 2) 7-2, 7-3, 10-13, 10-37 pmdatasel (hidden 1) 7-2, 7-3, 10-14, 10-37 pme# 11-8, 13-3, 13-6 pmnext 3-3, 3-7, 7-1, 10-12 power management 7-1 ? 7-3 capabilities 10-2, 10-12 capability id register 10-12 control/status 10-13 d 0 -d 3 and d 3hot states 10-12 data 10-1, 10-14, 10-37 enumerator set 6-2 features 1-3 hidden registers 10-1, 10-3 id 10-1 local interrupt 6-2 new capability function 3-7 next capability pointer 10-12 pci specification 1-3, 1-5, 7-2, 10-12 pins 11-8, 11-11 registers 3-3, 3-6, 10-1, 10-2, 10-3, 10-12 ? 10-13, 10-14, 10-37 status 10-1 power, early 8-1, 8-2, 11-1, 11-6 see early power pqfp product ordering and support a-1 specs 13-1 ? 13-3 precharge bias voltage 8-1, 8-2, 12-2 bus interface pins 11-7 ? 11-8 test and debug pins 11-6 preempt 2-5, 11-10 prefetch counter 10-21 ? 10-29 programmable 1-5 size 4-1 timing diagrams, settings in 4-30, 4-40
product ordering and support to registers pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-9 index local bus 4-3 memory mapping 2-1 ? 2-2 pci target 4-1 ? 4-4, 10-21 ? 10-29 product ordering and support a-1 programmable bursts 1-1, 1-3 chip select 1-2, 5-1 ? 5-2 fifos, zero wait state burst 1-3 internal registers 3-1, 4-1 prefetch counter 1-5 wait state generator 11-12, 11-14, 11-15 wait states 1-3, 1-5 programming interface 0 1-2, 8-1, 8-4, 10-14 prot_area 3-4, 9-2, 10-33 pull-up/pull-down resistors 8-1, 11-1 ? 11-3 pvpd_next 3-3, 3-7, 9-1, 10-15 pvpdad 9-1, 10-15 pvpdata 9-1, 10-15 pvpdcntl 3-3, 9-1, 10-15 r ranges, operating 12-1, 12-2 rd# 2-4, 10-22 ? 10-30, 11-14, 11-17, 13-3, 13-6 read 2-1 accesses 2-10, 3-7, 4-4 fifos 1-3, 1-5, 2-10, 4-4 local bus accesses 2-10 pci configuration timing diagram 3-9, 4-14 pci initialization 4-5 pci memory timing diagrams 3-10, 4-15 pci power mode example 7-3 pci r2.2 features enable 4-42 pci target 1-3, 1-5, 3-1, 4-1, 4-2, 4-3, 4-4, 4-8, 10-35 programmable strobe timing on local bus 1-1 random read and write 9-2 registers 10-4 ? 10-37 sequential read only 9-1 serial eeprom 1-5, 3-1 ? 3-2, 9-2 timing diagrams see timing diagrams 4-33 vpd 9-1 ? 9-2 write pci power management 7-1 read ahead mode, pci target 1-1, 3-1, 4-3, 10-35 prefetch mode, in addition to 4-1 read accesses 2-10 supported by pci 9030 1-3 timing diagram 4-43 read strobe delay 1-1, 2-6, 10-22 ? 10-30, 11-14, 11-17 ready# 2-5, 2-8, 11-2, 11-14, 11-17, 13-3, 13-6 expansion rom bus region descriptor register 10-29 input 2-10, 10-21, 10-23, 10-25, 10-27 timeout logic, smartarget 1-1 timing diagram 4-34 wait states 4-1 reconfiguration, system see configuration recovery states 2-3, 2-10 register addresses 1-5, 10-2 ? 10-3 registers cap_ptr 3-3, 3-7, 7-1, 10-10 cntrl 1-5, 2-5, 3-1, 3-4, 4-1, 4-2, 4-4, 4-8, 10-34 ? 10-35 cs0base 3-4, 10-31 cs1base 3-4, 10-31 cs2base 3-4, 10-32 cs3base 3-4, 10-32 eromba 3-4, 4-4, 10-20 erombrd 3-4, 4-5, 10-29 eromrr 3-3, 4-4, 10-10, 10-18 gpioc 6-3, 10-36 ? 10-37 hs_cntl 3-3, 8-4, 10-14 hs_csr 1-2, 8-1, 8-3, 10-14 hs_next 3-3, 3-7, 8-4, 10-14 intcsr 3-4, 6-2, 10-33 las0ba 3-3, 4-4, 4-7, 10-8, 10-19 las0brd 2-8, 3-4, 4-3, 4-5, 10-21 las0rr 3-3, 4-4, 10-8, 10-16 las1ba 3-4, 4-4, 4-7, 10-8, 10-19 las1brd 2-8, 3-4, 4-3, 4-5, 10-23 las1rr 3-3, 4-4, 10-8, 10-16 las2ba 3-4, 4-4, 10-9, 10-20 las2brd 2-8, 3-4, 4-3, 4-5, 10-25 las2rr 3-3, 4-4, 10-9, 10-17 las3ba 3-4, 4-4, 10-9, 10-20 las3brd 2-8, 3-4, 4-3, 4-5, 10-27 las3rr 3-3, 4-4, 10-9, 10-17 pcibar0 3-7, 4-4, 10-7 pcibar1 3-7, 4-4, 10-7 pcibar2 4-4, 10-8 pcibar3 4-4, 10-8 pcibar4 4-4, 10-9 pcibar5 4-4, 10-9 pcibistr (not supported) 10-6 pciccr 3-3, 10-5 pcicis (not supported) 10-10 pciclsr 3-6, 10-6 pcicr 6-2, 10-4 pcierbar 3-7, 4-4, 10-10 pcihtr 3-6, 10-6 pciidr 3-3, 10-4 pciilr 3-3, 10-11 pciipr 3-3, 10-11 pciltr (not supported) 10-6 pcimgr (not supported) 10-11
registers, hidden (pmdatasel, pmdatascale) to system reconfiguration pci 9030 data book version 1.4 index-10 ? 2002 plx technology, inc. all rights reserved. pcimlr (not supported) 10-11 pcirev 3-3, 10-5 pcisid 3-3, 10-10 pcisr 3-3, 7-1, 10-5 pcisvid 3-3, 10-4, 10-10 pmc 3-3, 3-5, 7-2, 10-12 pmcapid 3-3, 7-1, 10-12 pmcsr 3-3, 3-5, 6-2, 7-2, 7-3, 10-1, 10-2, 10-13, 10-14, 10-37, 11-11 pmcsr_bse 10-13 pmdata 3-5, 7-2, 7-3, 10-14, 10-37 pmdatascale 7-2, 7-3, 10-13, 10-37 pmdatasel 7-2, 7-3, 10-14, 10-37 pmnext 3-3, 3-7, 7-1, 10-12 prot_area 3-4, 9-2, 10-33 pvpd_next 3-3, 3-7, 9-1, 10-15 pvpdad 9-1, 10-15 pvpdata 9-1, 10-15 pvpdcntl 3-3, 9-1, 10-15 registers, hidden (pmdatasel, pmdatascale) 7-2 ? 7-3, 10-37 registers, new definitions summary 10-1 remap local base address 4-7 pci-to-local addresses 4-5 serial eeprom register load sequence 3-3 see also map and mapping reset initialization 4-5 platform 8-2 serial eeprom 3-1 ? 3-10 soft 7-1, 7-2 software 3-1, 10-35 resistors 8-1, 11-1 ? 11-3 retry delay timer 4-4 revision id 3-6, 10-5 risc architecture 2-2 routing, board, bga 13-7 ? 13-8 rst# 3-1, 11-8, 13-3, 13-6 s serial eeprom accidental write to 9-2 cntrl register 10-34 ? 10-35 control 10-3 device id and vendor id registers 10-4 interface 1-4 interface pins 11-1, 11-5 internal registers access 2-6 prot_area 10-33 random read and write 9-2 read control 1-5 read-only portion 9-1 reset and initialization 3-1 ? 3-10 support 1-5 timing diagrams 4-13 ? 4-15 vendor id and device id registers 10-4 vpd 9-1 ? 9-2 write 9-2, 10-5, 10-10, 10-11, 10-14, 10-15, 10-18 write-protected address boundary register (prot_area) 10-1, 10-3, 10-33 serr# 11-8, 13-3, 13-6 setup and hold waveform, local input 12-3 signal names local bus mode independent interface 11-9 multiplexed bus mode interface 11-12 non-multiplexed bus mode interface 11-15 pci system bus interface 11-7 ? 11-8 power and ground 11-4 serial eeprom interface 11-5 test and debug 11-6 signaling 1-4, 1-5 signals 2-3 synchronous 12-3, 12-4 silicon revision id 1-4, 10-5 single cycle mode 2-9 smartarget technology 1-1, 1-3 see also pci target soft reset 7-1, 7-2 software connection control 8-2 development 1-1 hot swap system 8-3 pci 4-5 reset 3-1, 10-35 spaces 1-3, 2-10, 3-3, 4-1, 4-4, 4-7 local address space bus region descriptor registers 10-21 ? 10-27 local address space local base address registers 10-19 ? 10-20 local address space range registers 10-16 ? 10-17 pci base address registers 10-8 ? 10-9 register address mapping 10-2, 10-3 spare pins (bga) 11-4, 13-6 specifications see electrical specifications, or general electrical specifications states, basic bus 2-3 stepping 10-4 stop# 11-8, 13-3, 13-6 strobe 11-14, 11-17 strobe timing, programmable read and write 1-1, 2-6, 10-22 ? 10-30 subsystem id and subsystem vendor id 3-1, 10-10 system reconfiguration see configuration
target abort to zero wait states pci 9030 data book version 1.4 ? 2002 plx technology, inc. all rights reserved. index-11 index t target abort 2-1, 10-5 target interface chip 1-3 tck 11-2, 11-6, 11-18, 13-3, 13-6 tdi 11-2, 11-6, 11-18, 13-3, 13-6 tdo 11-6, 11-18, 13-3, 13-6 test 11-1, 11-6, 13-3, 13-6 test pins 11-6, 11-18 thermal resistance 12-1 timer, retry delay 4-4 timing diagrams arbitration 2-6, 4-9 chip select 4-12, 4-16, 5-3 ? 5-4 configuration initialization 3-9 ? 3-10, 4-14 ? 4-15 general purpose i/o 4-11, 6-5 interrupts 4-10, 6-4 pci target, multiplexed mode 4-16 ? 4-31 pci target, non-multiplexed mode 4-16 ? 4-26, 4-32 ? 4-45 serial eeprom initialization 3-8, 4-13 timing, strobe programmable read and write 1-1 tms 11-2, 11-6, 11-18, 13-3, 13-6 transfer, unaligned 4-39 trdy# 2-1, 4-4, 11-8, 13-3, 13-6 trst# 11-2, 11-6, 11-18, 13-3, 13-6 2 15 pci clock timeout 4-2, 10-34 u user i/o 4-11, 6-5 v v dd 11-1, 11-4, 12-1, 12-2, 13-3, 13-6 vendor id 1-4, 3-1, 3-3, 9-1, 10-4 v i/o 11-4, 13-3, 13-6 v io 8-1 vital product data (vpd) 1-3, 1-5, 3-1, 3-6, 3-7, 9-1 ? 9-2, 10-1 registers 10-1, 10-2, 10-15 serial eeprom accesses 10-33 values programmed with 3-2 voltage, precharge bias 8-1, 8-2, 12-2 bus interface pins 11-7 ? 11-8 test and debug pins 11-6 vpd see vital product data v ss 11-2, 11-4, 13-3, 13-6 w wait states 2-5 ? 2-8, 2-10, 4-1, 11-14 counter 11-17 cycle control 10-4 external 4-41 generation 1-5, 4-1, 4-4, 11-12, 11-15 internal 4-1, 4-35, 10-21 ? 10-29, 11-9 pci bus 2-1 programmable 1-3, 1-5 timing diagrams 4-19 ? 4-20, 4-34 ? 4-35, 4-41 waito# 11-9 zero 1-3 waito# 2-5, 11-3, 11-9, 13-3, 13-6 width control, smartarget 1-1 wr# 2-5, 10-22 ? 10-30, 11-14, 11-17, 13-3, 13-6 write 2-1 accesses 3-7 cycles 9-1 fifos 1-3, 1-5, 2-10, 4-1 flush pending 4-2 local bus accesses 2-10 pci configuration timing diagrams 3-9, 4-14 pci memory timing diagrams 3-10, 4-15 pci power management 7-1 pci power mode example 7-3 pci target 1-3, 1-5, 4-4, 4-8 posted memory (pmw) 1-3 random read and write 9-2 registers 10-4 ? 10-37 serial eeprom 3-1, 3-2, 9-2 strobe timing local bus, programmable 1-1 timing diagrams see timing diagrams 4-44 vpd 9-1 ? 9-2 wake-up request example 7-3 write cycle hold 2-6, 10-22 ? 10-30 write strobe delay 1-1, 2-6, 10-22 ? 10-30, 11-14, 11-17 z zero wait states 1-3

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