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| june 2013 docid15687 rev 5 1/29 PM0059 programming manual stm32f205/215, stm32f207/21 7 flash programming manual intr oduct i on th is p r o g r a mm ing ma nu al de scr i bes ho w to p r o g r a m the f l ash me mor y o f st m32 f 20 5/215 and stm32f207/217 microcontro llers. for convenienc e, thes e will be referred to as stm 32f 20x and st m32 f 21 x in the r e st o f this docum ent un less othe rwise specified . th e stm3 2f2 0 x a n d s t m 32f 21xem bed de d flash me mor y can b e pr ogr am med u s in g in- circu i t pr og ra mming or in -ap p lication p r o g r a mm ing. th e in-c ir cuit pr ogra m ming ( i cp) me thod is used to up da te the entir e co nten t s of th e f l ash me m o r y , us ing t h e jt ag , swd pr ot oc ol or the bo ot lo a d e r to lo a d th e u s er a p p lic at ion int o the microcontroller . ic p of fers quick an d ef ficie n t d e sign iter ation s a nd elim inate s u nne ce ssa r y p a ckag e ha ndlin g or so cketin g of d e vices. in contrast to the ic p met h od, in-a pplicat ion progr amming (iap) ca n use an y com m un ica t io n inter f ace su pp or te d by th e mi croc ontroller (i/os , us b, ca n, u a r t , i 2 c, spi, e t c.) to down l oad p r o g r a mmin g da t a into me mor y . with iap , the fla s h memo ry ca n be r e - p r o g ra mme d wh ile the ap plication is ru nn ing. ne ver t h e less, p a r t o f the ap plication h a s to h a ve be en pr eviou s ly pr og ram m ed in th e flash me mor y u s in g icp . t h e f l as h int e r fa c e im ple m en t s in st ru ctio n ac ce ss an d da t a ac ce ss ba se d on th e ahb p r o t o c o l . it imp l eme n t s a pr efetch buf fer tha t spe eds up cpu cod e execution . it a l so im ple m e n t s t h e lo gic n e ce ss ar y t o ca rry o u t f l as h me m o r y o p e r a t i on s ( p ro gr am /e r a se ) . pr ogr am /e ra se o per ation s can b e pe rfor med o v er the who l e pr od uct volt ag e ra ng e. rea d /write pr otections an d opt ion byte s a r e also imp l em ented. www.s t.c om http://
contents PM0059 2/29 docid15687 rev 5 co nten t s 1 g lossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 f la sh memory interfa ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 1 introdu ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 2 m ain feat ures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 3 f lash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. 4 r e ad in terface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.1 r elatio n betwee n cpu clo ck fre que nc y a nd fla s h m e mo ry rea d time . . 8 2.4.2 a da ptive r e a l -time m e mo ry acce ler a tor (ar t accelerator? ) . . . . . . . . . 9 2. 5 e rase a nd pro g ram o perations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2.5.1 u nlocking the flash control regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2.5.2 p ro gr am/er a se p a r a lleli sm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.3 e ras e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.4 p rogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.5 i nterrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2. 6 o ption bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 d esc r iption of us er opt i on bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.2 p rogramming user option byt e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 r ead protect i on (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.4 w rite protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2. 7 o ne -time progra m mable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2. 8 f lash in terface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8.1 f las h ac ces s c o ntrol regis t er (flash _ac r ) . . . . . . . . . . . . . . . . . . . . 20 2.8.2 f lash key register (flash_keyr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8.3 f las h option key regist er (flash_op t k eyr) . . . . . . . . . . . . . . . . . . . 21 2.8.4 f las h st atus register (flash_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.8.5 f la sh con t rol r egister ( f l a sh_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8.6 f las h option cont rol register (fla sh_optcr ) . . . . . . . . . . . . . . . . . . . 24 2.8.7 f las h int e rface regis t er map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 r evision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 docid15687 rev 5 3/29 list of t a bles 3 list of t a bles table 1. applicable produc ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 t a b l e 3. nu mb e r o f wa it st at es a cco rd ing t o cpu cloc k (hclk) frequency . . . . . . . . . . . . . . . . . . . . 8 table 4. program/ e ras e parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. flash interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. option by te organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. descript i on of t h e opt i on byt e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 t a b l e 8. acce ss ve rs us re a d p r ot ect i on le vel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. otp part organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ta ble 1 0 . f la sh re giste r ma p and r e set valu es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of figures 4/29 docid15687 rev 5 list of figures fig u r e 1. fla s h memo ry inter f a c e co nne ctio n inside syste m architec ture . . . . . . . . . . . . . . . . . . . . . . 6 fig u r e 2. se que ntial 32 -bi t instru ction e x ecution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. rdp levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 docid15687 rev 5 5/29 pm0 059 gl oss a ry 28 1 glossary t h is se ctio n giv e s a br ie f d e f i nit i on o f a c r o n y m s an d ab b r e v ia tio n s us ed in th is do cu m e n t: ? the cpu co re in te gr ates two de bu g por t s : ? j t a g de bug p o r t ( j t a g- dp) p r o v id es a 5- pin stan dar d inter f ace ba se d on the j o in t t e s t a ctio n gr ou p (j t a g ) pr ot oc ol. ? s wd d e b u g po r t ( s wd- d p) pr o vide s a 2- pin ( clo ck an d da t a ) in te rf ac e b a se d on th e seri al wir e d ebu g (swd) pr otocol. for b o th the jt ag a nd swd p r oto c o l s, pl ea se re fe r to th e co rtex m3 t e chn i ca l re fe re nce man u a l ? w o rd : da t a /ins tr uct i on o f 32 -b it le n g t h . ? half wo rd: da t a /instr uction o f 16 -b it len g th. ? byte : da t a of 8-b i t le ngth. ? double word: dat a of 64 -b it len g th. ? ia p (in-applic ation programmin g): iap is the ability to repr ogram the flash memory of a microc ontroller while the user pro g r a m is r u n n in g. ? ic p (in-circ uit programming): ic p is the ability to program the flash memory of a m i cr oc on tr olle r usin g th e jt ag pr ot oc ol, th e swd pr ot oco l o r th e bo o t loa d e r wh ile th e de vice is mou n ted on th e user a p p lica t io n bo ard . ? i-cod e : this bu s conn ect s the instr u ctio n bu s of th e cpu core to the f l ash instru ction inter f ace. pr efetch is p e rfo rme d on this bus. ? d-cod e : this bu s co nne ct s th e d-co de bus ( lite r a l loa d a nd deb ug access) o f th e cpu to th e flash d a t a inte rface. ? o p t i on b yte s: p r o d u ct co nf igu r a t io n bit s st or ed in th e f l as h me m o r y . ? obl : optio n byte load er . ? ahb: ad va nced h i gh- pe rfor man c e bus. ? cpu: re fe rs to the co rtex-m 3 co re . flash memory interface PM0059 6/29 docid15687 rev 5 2 flash memory interface 2.1 introduction t h e f l as h me m o r y inte r f ac e ma n a g e s cp u ah b i-cod e an d d- code acce sses to th e 1 m byte ( 6 4 kb it 1 2 8 b i t s ) flash me mor y . it im plem ent s th e er ase an d pr ogr am f l ash m e m o ry op er a t ion s an d th e re ad a n d writ e p r ot ect i on m e ch an ism s . the f l as h me m o r y inte r f ac e ac ce le r a t e s co de e x e c u t io n w i th a sys te m of in str u c t ion p r e f e t ch an d cache lin es. 2.2 main features ? f l as h me m o r y re ad o p e r atio n s ? fla s h m e mo ry p r o g r a m/er ase op er ation s ? read / write pr otections ? pr ef et ch on i - co d e ? 64 cach e lines of 128 b i t s o n i- code ? 8 cache lin es o f 1 28 bit s on d- co de fig u r e 1 shows th e flash me mor y in te rface con nection in sid e the system ar chitectu re . figure 1 . flas h memory int e rf ac e con n ect ion inside sy st em arc h ite c tu re # o r t e x c o r e % t h e r n e t 5 3 " ( 3 $ - ! $ - ! $ c o d e b u s ) # o d e b u s # o r t e x - ) # o d e $ # o d e 3 b u s p e r i p h & l a s h m e m o r y & l a s h i n t e r f a c e 3 2 ! - s ! ( " p e r i p h & , ) 4 & r e g i s t e r s & 3 - # & l a s h m e m o r y b u s b i t s b i t ! ( " i n s t r u c t i o n b u s ! ( " d a t a b u s b i t ! ( " s y s t e m b u s b i t ! c c e s s t o i n s t r u c t i o n s i n & l a s h m e m o r y ! c c e s s t o d a t a l i t e r a l p o o l i n & l a s h m e m o r y & , ) 4 & r e g i s t e r a c c e s s a i docid15687 rev 5 7/29 pm0 059 f l ash me mory inte rf ace 28 2.3 flash memory t h e f l as h me m o r y ha s t h e f o llo win g ma in fe at ur es : ? cap a city up to 1 mbyt e ? 12 8 bit s wid e da t a re ad ? byte , ha lf- w or d, wor d an d do uble wo rd write ? sector a nd ma ss er ase ? me mor y or ga nization the flash me mor y is org a n i ze d as fo llows: ? m ain me mor y b l ock con t ain i ng 4 sector s of 16 kbytes, 1 sector o f 6 4 kbyte s , an d 7 s ec to rs of 12 8 kb yte s ? s ystem mem o r y used to b oot the de vice in syste m mem o ry bo ot m ode . this a r ea is r e ser v e d fo r stm i cr oe lectr o n i cs and cont a i ns the bo otloa der which is used to re pr ogr am the f l ash mem o r y thr oug h on e of the fo llowing in te rfaces: usar t1, usar t3 , can2 , usb o tg fs in dev i ce m ode (dfu: d e v i ce f i r m war e upg ra de) . th e b ootlo ade r is pr ogr am med by st when the de vice is ma nufa c tur e d , a n d pr ot ec ted a g a in st sp ur iou s writ e/ er as e o p e r a t i on s. ? 512 otp (on e - t im e pr ogr am mab l e) b y tes fo r use r da ta t h e ot p ar ea c o n t ain s 16 a d d i tio n a l b yt e s us ed t o lock th e co rr es po nd in g ot p d a t a blo ck. ? o ption b y te s: rea d an d wr ite p r o t e c tio n s, bor level, watchd og sof t wa re /h ar dwar e and r e set wh en the d e vice is in s t a ndb y or s t o p mod e . ? lo w p o wer m ode s ( f o r de t a ils re fe r to th e power co ntro l ( p wr) se ction of the refe ren ce ma nua l) t a ble 2 . flas h mo dule org a nization bloc k n am e b lo ck ba se ad dre sse s s ize main m e mory sector 0 0 x0800 000 0 - 0 x 0 800 3f f f 16 kbyte sector 1 0 x0800 400 0 - 0 x 0 800 7f f f 16 kbyte sector 2 0 x080 0 8000 - 0x08 00 bff f 16 kbyte sector 3 0 x0800 c 000 - 0x080 0 ff ff 16 kbyte sector 4 0 x08 01 000 0 - 0x0 801 f f f f 64 kbyte sector 5 0 x08 02 000 0 - 0x0 803 f f f f 128 kb yte sector 6 0 x08 04 000 0 - 0x0 805 f f f f 128 kb yte . . . . . . . . . sector 1 1 0 x080e 00 00 - 0 x 0 80f ff ff 128 kb yte syste m memory 0 x1ff f 00 00 - 0 x1ff f 77 ff 30 kbyte otp area 0x1 f f f 780 0 - 0x1 f f f 7a0f 5 28 bytes option b ytes 0 x1f f f c0 00 - 0 x1ff f c0 0f 16 b y tes flash memory interface PM0059 8/29 docid15687 rev 5 2.4 read interface 2.4.1 relation between cpu clock fre quen cy and f l ash memory read time t o cor r e c tly r e a d dat a fr om fla s h m e mo ry , th e nu mbe r of wa it st ates (l a t ency) m u st b e cor r e c tly pro g r a mm ed in the f l ash access cont r o l re giste r ( f lash_acr) acco rd ing to the fr eq ue n cy of th e cpu cloc k ( hcl k) an d th e su pp ly v o lt a g e of th e de vice . ta b l e 3 shows th e cor r e s p o n den ce between wa it st ates and cpu clo c k fr eq uen cy . th e pr efetch must b e disab l ed whe n th e supp ly volt a ge is belo w 2 . 1 v . af ter r e set, th e cpu clo c k fre que ncy is 16 mhz a n d 0 wait st ate (ws) is co nfigur ed in th e f l ash _ac r r e g i st er . it is hig h ly r e com m en ded to u s e the fo llowing sof t war e se que nces to tu ne the n u mb er o f wait st a t es n eed ed to access the f l ash me mor y with th e cpu fr eq uen cy . inc r e asing th e cpu frequ ency 1 . pro g r a m the ne w n u mb er o f wait st a t e s to the la tency bit s in th e flash_acr re gister 2 . check th at the n e w num ber of wai t st ates is t a ken into acc o unt to acc e ss the flas h me mor y by re ad ing the fl ash_ acr re giste r 3. modify the cpu clock source by writin g the s w bit s in the rc c_cfgr regis t er 4 . if ne ede d, mod i fy th e cpu clock p r esca ler by w r iting the hpre bi t s in rc c_c f gr 5 . check that the new cpu clo c k sou r ce o r /a nd the new cpu clock prescaler value is/ a re t a ken in to acco un t by re adin g the clock sou r ce st atus (sws b i t s ) or /a nd the ahb pr escaler va lue ( h pre bit s), re sp ec tively , in the rcc _c fgr register . t a ble 3. nu mb er of wait st at es ac cor d in g to cpu cloc k (hclk) f r equ e nc y w a it st ates (w s) (la t ency) hclk (mhz) v o lt ag e r a n g e 2.7 v - 3.6 v vo l t a g e r a n g e 2.4 v - 2.7 v v o lt ag e ran g e 2.1 v - 2.4 v vo l t a g e r a n g e 1.8 v - 2.1 v (1 ) 0 ws (1 cpu cycl e ) 0 flash memory interface PM0059 10/29 docid15687 rev 5 figu re 2. seque ntia l 32 -bit ins t ru ction e xec ut ion whe n th e cod e is no t se que ntial (b ra nch) , th e in str u ction may n o t b e p r e s e n t in the cur r en tly u s e d instruction lin e or in th e pr efetch ed in str u ction line. in this case (m iss ) , th e pe na lty in term s o f n u mb er o f cycles is a t lea s t eq ual to the nu mbe r of wait st ate s . a i & & & & $ $ $ $ % % % % & & & & $ $ $ % % 2 e a d i n s ' i v e s i n s 2 e a d i n s ' i v e s i n s i n s f e t c h i n s f e t c h i n s f e t c h i n s f e t c h i n s f e t c h i n s f e t c h i n s f e t c h i n s f e t c h 7 ! ) 4 7 ! ) 4 $ % & & & & $ $ $ % % & & & & $ $ $ % % 7 a i t d a t a % 2 e a d i n s ' i v e s i n s ' i v e s i n s 2 e a d i n s 2 e a d i n s i n s i n s f e t c h i n s i n s 7 i t h o u t p r e f e t c h 7 i t h p r e f e t c h & $ % # o r t e x - p i p e l i n e ! ( " p r o t o c o l a d d r e s s r e q u e s t e d & & e t c h s t a g e $ $ e c o d e s t a g e % % x e c u t e s t a g e i n s f e t c h i n s f e t c h i n s f e t c h f e t c h f e t c h f e t c h i n s f e t c h docid15687 rev 5 11/29 pm0 059 f l ash me mory inte rf ace 28 ins t ru ction ca che me mory t o limit the time los t due to jump s, it is possible to ret a in 64 lines of 12 8 bit s in an in str u c tio n cache m e mo ry . this fe atur e can be e n a b led b y setting the in str u ctio n cache en ab le (icen) bit in t h e f l ash _ac r re g i ste r . e a ch tim e a m i ss occ u r s ( r e q u e s te d d a t a n o t pr es en t in th e cur r e n tly u s e d instru ction lin e, in th e pr efetc hed ins t ruction line or in the ins t ruct ion cache me mor y ), th e line r e a d is copi ed into the in str u ctio n cache me mor y . if som e da t a co nt ain e d in th e inst ru ctio n ca ch e me m o r y ar e re qu e s te d by th e cpu, th e y a r e p r o v id ed w i th ou t ins e rting any delay . once all the instruc t ion ca ch e mem o r y line s h a ve bee n filled, th e lru ( l ea st re cently used) po licy is used to deter min e the lin e to r e p l ac e in th e inst ru ctio n me m o r y cache. this fe at ur e is p a r t icu l ar ly us eful in case of co de cont ainin g loo p s. dat a manage ment l i te ra l p ools ar e fetch ed fro m flash me mor y thr o u gh the d-co de bu s d u rin g the exe c u t io n st ag e of th e cpu pip e line . the cpu pip e line is conseq ue ntly st alle d until the re qu este d literal pool is prov ided. t o limit the time lo st du e to li te ral p ools, a cce sses thro ug h th e ahb d a t a b u s d- code h a ve pr ior i ty over acce ss e s thr oug h th e ahb instru ctio n bus i-cod e . if som e lite r a l p o o l s ar e fre que ntly u s e d , th e dat a ca ch e mem o ry can be e n a b led b y setting th e da t a ca ch e en ab le (d cen) b i t in t h e f l a s h_ acr re gis t er . t h is f e a t u r e w o r ks lik e th e in str u ctio n cache me mor y , b u t the ret a ine d dat a size is li mite d to 8 ro ws of 128 b i t s . note: d at a in user con f ig ur ation sector a r e n o t ca ch eab le. 2.5 erase and program operations fo r an y fla sh memo ry pr ogr am o per ation ( e r a se or pr ogr am ), the cpu clo c k fr eq ue ncy (h clk ) m u st be a t le a st 1 m hz . t h e co nt en t s of the flash me mor y ar e no t g uar an te ed if a d e vice rese t occur s du rin g a flash me mor y o p e r atio n. dur i ng a write/er ase o p e r atio n to the f l ash me mory , any attempt to re ad th e f l a sh m e m o ry will c a used the bus to st all. read operations are proc es sed c o rrectly onc e the program op e r a t io n ha s c o m p let e d . t h is m e an s th at co de or d a t a fetches cann ot b e pe rfor med wh ile a writ e/ er as e op er a t ion is o n g o in g . 2.5.1 unlocking the flash control register af te r re se t, w r it e is n o t a l lo we d in th e fla s h c o n t r o l re gist er ( f l ash _cr ) to pr ot ec t t h e fla sh memo ry ag ainst p o ssible un wanted o p e r a t io ns d u e , for e x a m ple , to ele c tr ic d i stur ba nces. th e followin g se que nce is u sed to unl ock this r e g i ste r : 1. w r ite key1 = 0x45670123 in the flash key register (flash_keyr) 2. w r ite key2 = 0xcdef89a b in the flash key register (fla sh_keyr) any wrong sequenc e will return a bus error and lock up the flash_cr regis t er until the next reset. th e fl ash_cr reg i ste r can be lo cke d aga in by so f t wa re b y setti ng the lock b i t in the fl ash_ c r re gister . note: t he flash_cr register is not accessible in wr ite mode when the bsy bit in the flas h_ sr regis t er is set. any attempt to w r ite to i t with the b sy bit se t will ca use the ahb bus to st all until the b sy bit is cleared. flash memory interface PM0059 12/29 docid15687 rev 5 2.5.2 program/erase p a rallelism th e par a lle lism size is con f ig ur ed thr oug h t he psiz e field in th e flash_cr r e g i ster . it r e p r ese n t s th e n u mb er of bytes to be pr ogr am med each tim e a wr ite op er ation o c cu rs to the fla s h memo ry . psiz e is limite d by th e supp ly volt a ge an d by wh ethe r the exter nal v pp sup p ly is used o r no t. it mu st th er efor e be cor r e c tly co nfigur ed in th e flash_cr r e g i ster b e for e any pr ogr am ming /e ra sin g op era t ion. a f l a s h m e m o ry er as e op er a t ion c a n o n ly b e pe r f o r m ed by secto r s, b ank or fo r th e whole fla s h memo ry (m ass er ase) . t he er ase time de pe nds on psize p r o g r a mm ed value . fo r mo re d e t a ils on th e er ase tim e , r e fer to the el ectrical cha r acter i stics section of the devic e da t a sh ee t. note: a n y p r og ra m or er ase op er ation st a r ted with in co nsiste nt pr ogr am p a r a lle lism/vo lt age ra nge settings ma y lea d to un pre d icted r e sult s. even i f a sub s e que nt re ad op er ation in dicates th at the logical value w a s effectiv ely written to the memory , th is v a lue may not be ret a ined. t o use v pp , an e x ter n a l h i gh- volt a ge supp ly ( betwee n 8 and 9 v ) must b e app lied to the v pp p a d . the extern al supp ly mu st be a b le to sustain this vo lt ag e ra nge e ven if the dc con s u m ptio n exce ed s 10 m a . it is a d vised to lim it th e use of vpp to initial pr og ram m ing o n the factor y lin e. t he v pp supp ly mu st no t be a p p lied for m o re th an an h o u r , othe rwise th e fla sh memo ry migh t b e dam age d. 2.5.3 erase t h e f l as h me m o r y er as e o p e r a t i on c a n b e pe rf o rme d at se cto r level or on the who l e flash me mor y ( m a s s erase ) . m a ss er ase do es n o t a f fe ct th e otp secto r or th e configu r a t io n sector . sect or erase t o er ase a sector , follo w the p r oce dur e be low: 1. check that no flash memo ry operation is ongoi ng by checking the bsy bit in the flash_sr re giste r 2 . set th e ser bit an d se lect the se ctor (o ut o f the 12 sectors in the ma in me mor y b l ock) you wish to eras e (snb ) in the flash_cr register 3 . set th e str t b i t in the f l ash_cr r egister 4. w a it for the bsy bit to be cleared t a bl e 4. pro g ra m/e r as e p a ra ll eli s m v o lt ag e ra n g e 2.7 - 3 . 6 v with external v pp v o lt ag e ran g e 2.7 - 3.6 v v o lt ag e ran g e 2.4 - 2.7 v v o lt ag e r a n g e 2.1 - 2 . 4 v v o lt ag e ran g e 1 . 8 v - 2. 1 v (1) 1. if irr o f f is set to vdd on stm32f 20xx d e vice s, th is value can be lower ed to 1.65 v w hen the de vice oper ates in a r educed temper ature r ange. parall elism size x64 x32 x16 x8 psiz e(1 : 0 ) 1 1 10 01 00 docid15687 rev 5 13/29 pm0 059 f l ash me mory inte rf ace 28 mass erase t o pe rfor m mass er ase, the followin g se qu ence is r e com m en ded : 1. check that no flash memo ry operation is ongoi ng by checking the bsy bit in the flash_sr re giste r 2. se t t h e m e r bit in th e f l ash _c r r e g i ste r 3 . set th e str t b i t in the f l ash_cr r egister 4. w a it for the bsy bit to be cleared 2.5.4 programming s t a ndard programmi ng th e fla s h m e mo ry p r o g r a mm ing sequ en ce is as fo llows: 1 . check tha t no main fla s h me mor y op er ation is on goin g b y checking the bsy bit in the flash_sr re giste r . 2 . set th e pg bit in th e flash_cr r e g i ster 3. pe rf or m th e da t a wr ite op e r a t io n( s) to th e de sir e d m e m o r y a d d r ess ( i nsid e m a in me mor y blo c k or otp ar ea) : ? b yte access in case of x8 p a rallelism ? h alf-word acc e s s in case of x 1 6 p a rallelism ? w or d ac ce ss in c a s e o f x3 2 p a r a llelism ? d ou b l e w o r d ac ce ss in c a s e of x6 4 p a ra llelism 4. w a it for the bsy bit to be cleared note: s u c cessive wr ite ope ra tio n s a r e p o ssible withou t the n eed o f a n er ase ope ra tio n when changing bit s from ?1? to ?0?. writ ing ?1 ? r e q u i re s a f l a s h me m o ry er as e op er at ion . if a n er ase an d a pr ogr am o per ation a r e r e q ues ted simu lt ane ou sly , th e er ase op er ation is p e r f o rme d first. programmi ng errors it is not allo we d to pr ogr am da t a to th e flash m e mo ry tha t wou l d cross th e 128 -b it r o w b oun da ry . in such a case, th e write op er ation is not per for m ed a nd a p r og ra m align m en t e r r o r flag ( p gaerr) is set in th e flash_sr re giste r . t h e writ e a cce ss t y pe (b yt e, h a lf -w or d, w o r d o r d o u b le wo rd ) m u s t co rr es po nd to th e ty pe of p a r a lle lism cho s en (x8 , x16, x32 or x6 4) . if no t, the write op er ation is n o t p e r f o r m e d an d a p r o g ra m p a ra llelism er ro r flag ( p gperr) is s e t in the flash_sr regis t er . if the st a nda rd p r o g ra mmin g sequ ence is not re sp ected ( f o r exam ple, if the r e is an attemp t to wr ite to a fla s h mem o r y a ddr ess when th e pg b i t is n o t se t) , th e o per ation is a b o r ted and a pr og ra m se q u e n c e er ro r fla g (pg serr ) is se t in t h e f l ash_ s r r e gist er . programmi ng and c aches if a f l ash mem o r y write access con c e r n s some dat a in th e dat a ca ch e, the flash write a c cess mod i fie s the d a t a in the fla s h mem o ry an d th e da t a in th e cache. if an erase operation in flash memory also conc erns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code flash memory interface PM0059 14/29 docid15687 rev 5 e x e c u t i on. if this can not be do ne safely , it is re co mmen d e d to flush the ca ch es by settin g the dcrst a nd icrst bit s in the fl ash_ cr re giste r . note: t h e i/d ca che shou ld be flush ed on ly whe n it is disable d (i/dcen = 0) . 2.5.5 interrupt s se tting the e nd of ope ra tio n inter r u p t e nab le bit ( e opie) in th e flash_cr r e g i ster e n a b les in te rr up t ge ner ation wh en an era s e or p r og ra m ope ra tio n en ds, tha t is whe n the bu sy bit ( bsy) in th e flash_sr re giste r is cle a re d (o pe ra tion c o mplet e d, c o rrect l y or not). in t h is case, th e en d of ope ra tio n (eop) bit in th e flash_sr r e g i ste r is set. if a n er ro r occur s du rin g a pr ogr am o r er ase op er ation r equ est, on e of th e fo llowing e r r o r flag s is se t in the fl ash_ s r r egister : ? pgaerr, pgperr, pgserr ( p ro gr am er ro r flag s) ? wr perr (pr o t e c t io n e r ro r f l ag ) in this cas e , if the error inte rrupt enable bit (errie) is s e t in the flash_sr regis t er , an in te rr up t is g ene ra te d an d th e op er ation er r o r bi t (operr) is se t in the f l ash_sr r egister . note: if several successiv e er ro rs a r e de te cte d ( f or examp l e, in case o f dma tra n sfe r to the flash m e m o ry) , t h e e r r o r f l a g s c a n n o t be c l ea re d un til th e e n d of th e su cce ssiv e writ e re qu e s t s . refer to t a b l e 5 : flash inter r u p t re que st s fo r summ ar y of flash in te rr upt re que st. 2.6 option bytes 2.6.1 description of user option bytes th e o p tion byte s are configu r e d b y the en d u s e r d epe nd ing o n the ap plication re quir e me nt s. ta b l e 6 shows the o r g ani za tio n of th ese bytes ins i de th e u ser c o n f ig ur at ion s e ct or . t a ble 5 . flas h int e rr upt r e que st s in terr up t e ven t s ev ent flags e n a ble co ntr o l b i t s end o f ope ration eop e opie w r it e p r ot ec ti on e rro r w r per r e rr i e programm ing error p gaerr, pgperr, pgserr e rrie ta ble 6. opt i on byt e org a nizat i on add r es s [ 63 :16] [1 5:0] 0x1f ff c0 00 re se rve d rop & u ser o p tion bytes ( rdp & user ) 0 x 1ff f c0 08 re se rve d w r ite protection s nw rp docid15687 rev 5 15/29 pm0 059 f l ash me mory inte rf ace 28 2.6.2 programming user option bytes t o r un an y o per ation o n this sector , the o p ti on lo ck bit (opt lock) in the f l ash op tio n con t r o l r egister (fl a sh_ o ptcr) must be clea re d. t o b e allo we d to clear th is b i t, yo u ha ve to pe rfor m the followin g se que nce: 1. w r ite optkey1 = 0x0819 2a3b in the fl ash option key regi ster (fla sh_optkeyr) 2. w r ite optkey2 = 0x4c5d 6e7f in the flash option key regi ster (flas h _optkeyr) t a b l e 7 . des c ript io n o f th e opt io n byt e s op tio n b y tes (word , ad dr ess 0 x1f ff c0 00) rdp: r e a d p r ot ec ti on o p t i o n by te . th e re ad protection i s use d to pro t ect th e sof twa re co de s to r ed in f l ash m e m o ry . bit s 15:8 0xaa: l e vel 0, n o protection 0xcc: level 2 , chip p r ote cti on (debu g and bo ot from ram features disa bled ) othe rs: leve l 1 , read p r ote cti on of memo ri es (d ebu g fea t u r e s limite d) user: u s e r o p tion byte thi s byte is used to configu r e the followin g fe atu r es: ? s e l ect the wa tch dog even t: hardw a re or so f t ware ? reset e vent w hen en te ring the s t op mod e ? r eset e vent w hen en te ring the s t an dby mode bit 7 nr st_stdby 0: re set ge nerated w hen en te ri ng the s t an dby mo de 1: no re se t ge nerated bit 6 nr st_st o p 0: re set ge nerated when en te ri ng the s t op mod e 1: no re se t ge nerated bit 5 wd g_sw 0: ha rdware wa tchd og 1: sof t ware watchdo g bit 4 0 x1: not used bit s 3:2 bor_lev : bor reset level th ese bit s con t a in th e su pply le vel th reshol d tha t activates/relea ses the re se t. th ey ca n b e writte n to prog ram a n e w bor leve l va lue in to flash memory . 00: b o r level 3 (vbor3). reset thre shol d level from 2.7 0 to 3 . 60 v 01: b o r level 2 (vbor2). reset thre shol d level from 2.4 0 to 2 . 70 v 10: b o r level 1 (vbor1). reset thre shol d level from 2.1 0 to 2 . 40 v 1 1 : bor of f (vbor0 ), reset th reshol d level from 1 . 8 to 2.10 v bit s 1:0 0 x1: not used optio n b y tes (word , ad dr ess 0 x1f ff c0 08) bit s 15 :1 2 0 xf : not used nw rp : f l ash memory write p r ote cti on optio n b yte s se cto r s 0 to 1 1 ca n be write protected. bit i (0 i 11 ) nwrpi 0: w r ite protection active on sector i 1: w r ite protection no t active on sector i flash memory interface PM0059 16/29 docid15687 rev 5 th e user option byte s can b e pr otecte d ag ai nst unwan te d er ase/pr og ra m o p e r a t io ns b y setting the optloc k bit by sof t ware. modifying user optio n bytes t o m o d i fy th e us er o p t i on va lue , follo w the seq uen ce belo w : 1. check that no flash memo ry operation is ongoi ng by checking the bsy bit in the flash_sr re giste r 2 . w r ite the de sired option va lue in the fl ash_ o ptcr r e g i ster 3 . set th e optio n st a r t bit ( o ptst r t ) in th e fl ash_optcr r egister 4. w a it for the bsy bit to be cleared no te : t he v a lu e o f an op tio n is au to m a t i ca lly m o dif i e d b y first er asing the user con f ig ur ation secto r a nd th en pr og ra mming a ll the op tio n b y te s wi th the value s co nt a i ned in the flash_optcr re gis t e r . 2.6.3 read protection (rdp) th e user ar ea in the fla s h memo ry ca n be p r o t e c ted aga inst r ead ope ra tio n s b y a n e n tru s ted co de. thr e e r e a d pr otectio n levels ar e defin ed: ? le ve l 0 : n o re ad pr otection when the r e a d p r o t e c tion level is set to level 0 by writin g 0xaa into th e r e a d pr otection op tio n byte (rdp), a ll rea d /write op er ations ( i f n o writ e pr ot ec tio n is se t) fr om / t o th e f l as h me m o r y or th e ba ck up sr am ar e po ss ible in a ll b o o t c o n f ig ur a t ion s (f la sh us er bo ot, de bu g or b oot from ram) . ? level 1: me mor y r e a d pr otecti on. it is the defau lt r ead p r o t e ctio n level af ter option byte e r a s e . the re ad p r ote c tion l e vel 1 is ac tivated by writing any v a lue (except for 0xaa and 0 xcc used to set level 0 a nd le ve l 2, r e spectively) in to the rdp op tio n by te . wh en th e r e ad pr ot ec tio n l e v e l 1 is se t: ? n o a c ce ss (r ead , e r a s e , pr og ra m) to flash me mor y o r ba ckup sram can b e per form ed while the d e b ug fea t u r e is co nne cte d or while boo tin g from ram or syste m mem o ry bo otload er . a bu s er ro r is g e n e r a ted in case of re ad r equ est. ? w he n bo o t in g fro m f l as h me m o r y , a cc e s ses ( r e a d , er as e, pr og r a m ) to f l as h memo ry and backup sram fr om u s e r code a r e a llowed . when l e vel 1 is active, pr ogr am ming the pr ot ect i on o p t ion b yt e (rd p ) t o le ve l 0 causes the fla s h m e mo ry and the backup sr am t o be m a ss- er as ed . a s a r e s u lt th e user co de a r ea i s clear ed b e for e th e re ad p r o t e c tion is re move d. t he ma ss er ase on ly er ases th e user co de ar ea . th e othe r op tio n bytes i n clu d in g wr ite pr otectio n s re main docid15687 rev 5 17/29 pm0 059 f l ash me mory inte rf ace 28 un ch an ged fr om be fo re the m a ss- e r a se op er ation . th e otp ar ea is not af fecte d by ma ss er ase and rem a ins un ch ang ed . m a ss e r a s e is per fo rm ed on ly when l e vel 1 i s acti ve an d leve l 0 re qu este d. whe n th e pr otection le ve l is incre a sed ( 0 - > 1 , 1 - >2, 0- >2 ) ther e is n o mass e r a s e . ? le ve l 2 : disable deb ug/chip r e a d pr otectio n when th e re ad pr otection l e vel 2 is set by wr itin g 0xcc to the rdp op tion byte: ? a ll p r ote c tion s pr ovid ed by leve l 1 a r e a c tive. ? b o o ting fr om system me mor y is not allo we d anymo re . ? j t a g , sw v (s ing l e - wir e vie w er ) ar e dis a b l ed . ? u ser option byte s can n o long er b e chan ged . ? w he n bo o t in g fro m f l as h me m o r y , a cc e s ses ( r e a d , er as e a n d pr og ra m ) to f l ash memo ry and backup sram fr om u s e r code a r e a llowed . me mor y r e a d p r otection leve l 2 is an irr e ve r s ib le o per ation . wh en l e vel 2 is activate d, the leve l o f protection can not be d e cre a sed to le ve l 0 or l e vel 1. note: t h e jt ag por t is pe rm ane ntly d i sa ble d when lev el 2 is a c tive ( a ctin g as a jt ag fu se ). as a con s e q u ence, bo und ar y sca n cann ot b e pe rfor m e d. st mic r o e le ct ro nic s is no t ab le to p e r f o rm an alysis on defective p a rt s on whic h the le vel 2 pr otectio n ha s be en set. fig u r e 3 shows how to g o from o n e rdp le ve l to a nothe r , an d ta b l e 8 su mm a r iz es th e me mor y a c ce sses ve rsus the pr otection le ve l. t a ble 8. ac ces s ve rsus r ead pr ote c t i o n le vel me mor y area prote c t io n le vel de bu g fea t u r es , boo t from ram o r from sy stem memo ry b o o t lo ad er boot ing fro m fl as h memo ry r ead w r ite er ase re ad w r ite eras e main flash memory and back up sram leve l 1 n o n o (1 ) yes leve l 2 n o yes op ti on byte s leve l 1 y es yes leve l 2 n o n o ot p leve l 1 n o n a yes na leve l 2 n o n a yes na 1. t he main flash memory and b a ckup sram ar e only er ase d when the rdp changes from level 1 t o 0. the ot p area r e mains un chan ged. flash memory interface PM0059 18/29 docid15687 rev 5 f i g u r e 3. rdp le ve ls 2.6.4 w r ite p r o t ections th e user se ctor s ( 0 to 1 1 ) in fla s h memo ry ca n be p r o t e c ted aga inst u n wanted wr ite o per ation s d ue to loss o f pr og ra m co unter co ntext s. whe n th e no t write pr otection b i t in sector i (nwr pi, 0 i 1 1 ) is low , the co rr espon din g se cto r cann ot b e er ased o r p r o g ra mme d. co nsequ en tly , a mass e r a s e ca nno t b e per form ed if one o f the sector s is wri t e - pr otected . if an e r a se / p r o g r a m op e r a t io n t o a writ e- pr ot ec te d p a r t of th e fla sh m e mo ry is at te mp te d ( s e cto r pr otected by writ e pr otection bi t, otp p a rt locked or p a rt of the flash memory that ca n ne ve r be wr itte n like th e ic p), th e writ e pr ot ec tion e r r o r f l ag ( w rper r) is s e t in th e fl ash_ s r r egister . note: w he n the me mor y r ead p r o t e ctio n level is se lected (rdp lev e l = 1), it is not poss ible to p r o g ra m or er ase flash m e mo ry se cto r i if th e cpu de bug fe atur es ar e co nn ecte d ( j t a g or sing le wire) or b oot code is be ing execu t e d fr om ram, e ven if n w rpi = 1. , e v e l l e v e , l e v e , h ! ! 0 $ 2 h # # 0 $ 2 2 $ 0 ! ! h 2 $ 0 # # h d e f a u l t / p t i o n s w r i t e 2 $ 0 l e v e l i n c r e a s e i n c l u d e s / p t i o n s e r a s e . e w o p t i o n s p r o g r a m / p t i o n s w r i t e 2 $ 0 l e v e l d e c r e a s e i n c l u d e s - a s s e r a s e / p t i o n s e r a s e . e w o p t i o n s p r o g r a m / p t i o n s w r i t e 2 $ 0 l e v e l i d e n t i c a l i n c l u d e s / p t i o n s e r a s e . e w o p t i o n s p r o g r a m 2 $ 0 ! ! h / t h e r s o p t i o n s m o d i f i e d 2 $ 0 ! ! h # # h / t h e r s o p t i o n s m o d i f i e d 7 r i t e o p t i o n s i n c l u d i n g 2 $ 0 ! ! h 7 r i t e o p t i o n s i n c l u d i n g 2 $ 0 # # h 7 r i t e o p t i o n s i n c l u d i n g 2 $ 0 # # h 7 r i t e o p t i o n s i n c l u d i n g 2 $ 0 # # h ! ! h a i docid15687 rev 5 19/29 pm0 059 f l ash me mory inte rf ace 28 w r i t e protection erro r fl ag if a n er ase/pr ogr am o per ation to a wr ite p r o t e c te d ar ea of th e fla s h m e mo ry is pe rfor med , the w r ite pr otection er ror fla g (wrper r) is s e t in the flash_sr regis t er . if a n er ase op era t ion is r e q u e s ted , the wrperr bit is se t whe n : ? m a s s o r se cto r er as e ar e co nfig u r e d (m er or m e r/ mer 1 an d ser = 1 ) ? a se ctor era se is r equ este d an d th e sector num ber snb fie l d is n o t va lid ? a ma ss er a se is r e q u e s t ed w h ile a t le a st on e of th e us er se ct or is writ e pr ot ec ted b y op tio n bit (mer or m e r/mer1 = 1 a nd nwrpi = 0 with 0 i 1 1 bit s in the flash_optcrx register ? t h e f l a sh m e m o ry is r e ad ou t pr ot ec te d a n d an in tr usio n is de te cte d . if a pr og ra m o p e r a tio n is r e qu es te d, th e wrpe rr b i t is se t wh en : ? a wr ite ope ra tio n is p e rfor me d on system m e mo ry o r on th e re se rved p a r t o f the u s e r specific sector . ? a wr ite ope ra tio n is p e rfor me d to th e user con f ig ur ation sector ? a writ e o p e r a t i on is pe r f o r m e d o n a se cto r writ e pr ot ec te d b y op tio n bit . ? a wr ite ope ra tio n is r equ ested on a n ot p a r ea wh ich is alr e a d y lo cked ? the flash me mor y is rea d protect ed an d an in tr usio n is de te cte d . 2.7 one-time programmable bytes ta b l e 9 sh ows the o r g ani za tio n of th e one -time p r o g r a mma ble ( o tp) p a rt of the otp ar ea. th e otp are a is divide d into 1 6 ot p d a t a b l ocks o f 3 2 bytes and on e lock otp blo c k of 16 b y tes. t he otp d a t a a nd lock blocks can not be e r ase d . t he lock block co nt ain s 16 byte s lockbi (0 i 15 ) to lock the cor r e spon din g otp da t a block (blo cks 0 to 15) . each otp d a t a blo ck can b e pro g r a mm ed un til the va lue 0x00 is pr og ra mmed in th e co rr espo ndin g otp lock byte. the loc k bytes mus t only c ont ain 0 x00 and 0xff va lues, othe rwise the ot p by tes might not be t a ken int o acc o unt correctly . t a ble 9. otp p a rt o r gan i zat i on bloc k [ 1 28:96 ] [ 9 5 :64] [63:32 ] [ 31:0] add re ss by te 0 0 otp0 otp0 otp0 otp0 0x 1fff 7800 otp0 otp0 otp0 otp0 0x 1fff 7810 1 otp1 otp1 otp1 otp1 0x 1fff 7820 otp1 otp1 otp1 otp1 0x 1fff 7830 . . . . . . . . . 15 otp1 5 o t p 15 otp15 o tp1 5 0x1f f f 79e0 otp1 5 o t p 15 otp15 o tp1 5 0x1 f f f 79f 0 lo ck bl ock lockb15 ... lockb12 lockb1 1 ... lockb8 lo ckb7 .. . lockb4 lo ckb3 .. . lockb0 0x1f f f 7a00 flash memory interface PM0059 20/29 docid15687 rev 5 2.8 flash inte rface registers 2.8.1 flash access control register (fl a sh_acr) t h e f l as h ac ce ss c o n t r o l re gis t e r is u s ed t o e n a b le/disab le the accele ra tio n fe atur es and con t r o l the fla s h memo ry access time accor d in g to cpu fr equ ency . ad dre s s of fse t : 0x00 re se t va lu e: 0 x 00 0 0 00 00 access : no wait s t ate, word , half-w o rd and by te access 3 1 30 29 28 2 7 26 2 5 24 23 2 2 21 20 19 18 17 16 reserved 1 5 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 reserved d crs t i crst dce n i ce n p rften re se r ve d l a t e ncy r w wr w r w r w r wr w r w bi t s 31:1 1 rese rve d , must be kept cl eared . bit 12 dcrst : dat a cache reset 0: dat a cache is not reset 1: dat a cache is reset t h i s bi t ca n be w r i t te n on l y w h e n th e d ca ch e is d i sa b l ed . bi t 1 1 icrst : instruction cache reset 0: instruction cache is not reset 1: instruction cache is reset t h i s bi t ca n be w r i t te n on l y w h e n th e i cach e i s d i sa bl e d . bit 10 dcen: dat a cache en abl e 0: da t a cach e is d i sabl ed 1: da t a cach e is e nabl ed bit 9 icen: instruction cache e nabl e 0: instructi on cache i s di sa ble d 1: instructi on cache i s en able d bit 8 prften: prefe t ch en abl e 0: prefetch is disab l ed 1: prefetch is enab led bit s 7 : 3 r ese r ve d, must be kept cl eared . bit s 2:0 la tency : latency th ese bit s rep r esent th e ra ti o of the cpu cl ock perio d to the f l ash memory access time. 000 : ze ro wait st ate 001 : on e wait st ate 010 : t w o wa it st ates 01 1 : th re e wait st ates 100 : fo ur wait st ates 101 : fi ve w a it st ates 1 1 0 : six wait st ates 111: seven wait states docid15687 rev 5 21/29 pm0 059 f l ash me mory inte rf ace 28 2.8.2 flash key reg i ster (flash_keyr) th e fla s h key re gister is used to allo w access to the fla s h co ntro l r e g i ster and so , to allo w p r o g ra m an d era s e ope ra tio n s. ad dre s s of fse t : 0x04 re se t va lu e: 0 x 00 0 0 00 00 access : no wait s t at e, word access 2.8.3 flash o p tion key regi ster (flash_optkeyr) t h e f l as h op tio n ke y r e g i st er is use d to a llow p r o g r a m an d er as e op er a t ion s in th e u se r conf iguration sector . ad dre ss of fse t : 0x08 re se t va lu e: 0 x00 0 0 00 00 access : no wait s t at e, word access 3 1 30 29 28 2 7 26 2 5 24 23 2 2 21 20 19 1 8 17 16 ke y[ 31: 16] wwww ww w w w w w w w w w w 1 5 1 4 1 3 1 2 1 1 1 0 9 8 76 5432 1 0 k e y [ 1 5: 0] wwww ww w w w w w w w w w w bi t s 31:0 fkeyr : fpec key t h e foll owin g va lue s must b e progra m med con s ecutively to unlo ck the f l ash_cr regi ste r a nd al low prog ra mmi ng/erasin g it: a) key1 = 0 x 4 567 0123 b) key2 = 0x cdef89ab 31 30 29 28 2 7 26 2 5 24 23 2 2 21 20 19 1 8 17 16 optke y r[ 31: 16 wwww ww w w w w w w w w w w 1 5 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 op tk ey r[ 15 :0 ] wwww ww w w w w w w w w w w bit s 31:0 op tkeyr : option byt e key th e fol l owi ng valu es must be prog ra mme d co nsecutivel y to unl ock the f l ash_optcr register and a llow pro g ramming it: a ) opt k ey1 = 0 x 081 92a3b b ) optkey2 = 0x4c5d6e7f flash memory interface PM0059 22/29 docid15687 rev 5 2.8.4 flash st atus register (flash_sr) th e fla s h st atus re gister g i ve s info rma tio n on o ngo ing p r o g ra m an d er ase ope ra tio n s. ad dre s s of fse t : 0x0c re se t va lu e: 0 x 00 0 0 00 00 access : no wait s t ate, word , half-w o rd and by te access 31 3 0 29 28 27 26 25 24 23 2 2 2 1 20 19 18 17 16 reserved bs y r 15 1 4 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 re s e r v e d pg serr p gp err p gae r r w rpe r r reser v e d o perr e op rc_w1 r c_w1 rc_w1 r c_w1 r c _w1 r c_w1 bit s 3 1 :1 7 re se rved, must be kept cleare d . bit 16 bsy : busy t h i s bi t ind i cates th at a f l ash memory opera t io n is in progre s s. it is se t at the b egin n in g o f a f la s h memo ry op eration an d cl eared w hen the op eration fini sh es or a n error o ccurs. 0 : no f l ash memory o pera t io n ongo ing 1 : fl ash me mory o peration o ngo ing bit s 15:8 re se rved, must be kept cleare d . bit 7 pgserr: pr ogramming sequenc e err o r set by hardwa r e when a write access to the f l ash memory is p e rformed by th e co de whi l e the con t rol reg i ster h a s n o t b een correctly configu r ed. cl eared b y writin g 1. bit 6 pgperr: pr ogramming p a rallelism error set by hard w are whe n th e size of th e access (byte , ha lf-word, word, dou ble wo rd ) d u ring the p r o g ram se que nce doe s no t correspo nd to the p a rall elism configu r a t i on psiz e (x8, x16, x32, x64). cl eared b y writin g 1. bit 5 pgaerr: programming a lig nment e r ro r set by hardwa r e when the da t a to progra m cann ot b e co nt aine d in th e same 128-b i t f l ash memory row . cl eared b y writin g 1. bit 4 wrperr: w r it e p r ot ec ti on e rro r set by hardwa r e when an a ddress to b e eras ed /p ro grammed be long s to a write-protected p a rt of the flash memory . cl eared b y writin g 1. docid15687 rev 5 23/29 pm0 059 f l ash me mory inte rf ace 28 2.8.5 flash control reg i ster (flash_cr) th e fla s h con t r o l r egister is used to con f ig ur e and st a r t f l ash me mor y op er ation s . ad dre s s of fse t : 0x10 re se t va lu e: 0 x 80 0 0 00 00 access: no wait st a t e wh en no flash me mor y o per ation is on goin g , wo rd, ha lf- w ord and by te access. bi t s 3:2 r eserved, must be kep t clea red. bit 1 operr: op eration error set by hardwa r e when a flash op eration (pro gramming / e r ase) re que st is detected and ca n n o t be run b e cause o f p a ra lleli sm, ali gnmen t, se quen ce or w r i t e p r o t e ctio n error . th is bit i s set onl y if error i n terrupt s a r e e nab led (errie = 1). bit 0 eop : en d of op eration set by hardwa r e when on e or mo re f l ash memory ope rations (prog r a m /era se ) h a s/ha ve completed successfully . it is se t only if the end of o peratio n i n terrupt s are en able d (eopie = 1) . cl eared b y writin g a 1 . 31 3 0 29 28 27 2 6 25 24 23 22 2 1 20 1 9 18 1 7 1 6 lock re s e rved errie e opie reser v e d str t rs rw r w rs 15 1 4 13 12 1 1 1 0 9 8 7 6 5 4 3 2 1 0 re se r ve d p s i ze [1 :0 ] reserv ed s n b[ 3:0 ] mer s er pg r w rw r w rw rw rw rw rw rw bit 31 lock: lo ck w r it e to 1 only . w h en it is set, this bit indicate s tha t the fl ash_cr regi ster is locked . it is clea red by hardw are af ter detectin g the u n lock sequ ence. in the e v ent o f an u n successful unl ock o peration , this bit remains set u n til th e next re se t. bit s 31 :26 rese rve d , must b e kept cl eared . bit 25 errie: erro r in te rru pt en abl e this bit e nab les th e interrupt gene ration whe n th e operr bit in the fl ash _ sr re gister is set to 1. 0: erro r in te rru p t ge neratio n disab l ed 1: erro r in te rrup t ge neratio n enab led bit 24 eopie: end of o peratio n interrupt ena ble t h is bit e nab les th e interrupt gene ration whe n th e eop bit i n th e f l ash_ s r reg i ste r g oes to 1. 0: interrup t ge neratio n d i sabled 1: interrup t ge neratio n e nab led bit s 23 :17 r e served, mu st be kept cleare d . bit 16 strt : st a r t t h is bit trig gers an erase o peration w hen set. it is set o n ly by so f t ware an d cleare d when the bsy bit is cleared. bit s 15 :10 r e served, mu st be kept cleare d . flash memory interface PM0059 24/29 docid15687 rev 5 2.8.6 flash option contro l register (flash_optcr) th e fl ash_optcr r egister is used to mo dify the u s e r op tio n bytes. ad dre s s of fse t : 0x14 reset value: 0x0fff aaed. the option bit s are loaded with values from flash memory at r e set re lease. access: no wait st a t e wh en no flash me mor y o per ation is on goin g , wo rd, ha lf- w ord and by te access. bit s 9:8 psize: pr ogram size t hese bit s se lect the p r o g ram p a ral l eli sm. 00 pro g ram x8 01 pro g ram x1 6 10 pro g ram x3 2 1 1 program x64 bit 7 r e served, mu st be kept cleare d . bit s 6:3 snb: sector number t hese bit s se lect the sector to e r ase. 00 00 sector 0 00 01 sector 1 .. . 101 1 sector 1 1 othe rs no t al lowe d bit 2 mer: m a ss erase erase activated for a ll user sectors. bit 1 ser: sector erase sector era se a cti va te d. bit 0 pg: progr a mm ing f l ash prog rammi ng activated. 3 1 30 29 28 2 7 26 2 5 24 23 2 2 21 20 19 1 8 17 16 re se r ve d nwrp[ 1 1:0 ] rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 8 76 5432 1 0 rdp[7:0 ] nrs t _ stdby nrst_ st o p wdg_ sw re se r v ed bo r _ lev op ts t rt op tl o ck rw rw rw r w rw rw rw rw rw rw rw rw rw rs rs docid15687 rev 5 25/29 pm0 059 f l ash me mory inte rf ace 28 bit s 31 :28 rese rve d , must b e kept cl eared . bit s 27:16 nw rp: n o t wri t e pro t ect t hese bit s co nt ain the valu e of the write-pro t ectio n o p tion bytes af te r reset. t h e y can be written to p r ogram a new write pr otect va lue in to f l ash memory . 0: w r ite protection a ctive 1: w r ite protection n o t a c tive bit s 1 5 :8 rd p: rea d protect t hese bit s co nt ain the valu e of the read -protection op tio n level a f ter re set. th ey can be written to p r ogram a new read p r ote cti on value i n to fla sh me mo ry . 0xaa: l e vel 0, re ad protection n o t active 0xcc: leve l 2 , chip re ad protection active othe rs: leve l 1 , read p r ot ecti on of memo ri es a cti ve bit s 7:5 user: user optio n b yte s t hese bit s co nt ain the valu e of the user op ti o n byte a f ter reset. t hey can be written to program a n e w user option b y te val ue into fl ash memory . bit 7: nrst_stdby bit 6: nrst_st o p bit 5: wdg_sw no te : w he n chang ing the wd g mode from h a rdware to sof t ware o r from sof t w a re to hardware, a system reset is required to make the change effective. bit 4 r e served, mu st be kept cleare d . bit s 3:2 bor_lev : bor rese t leve l t hese bit s co nt ain the supp ly l e vel thresho ld th at a ctiva te s/rele ases th e reset. th ey ca n be written to p r ogram a new bor le vel. by de fau l t, bor is off. wh en th e suppl y vol t a ge (v dd ) drop s b e low the sele cte d bor leve l, a de vi ce re set is ge nerated . 00 : bor le vel 3 (vbor3), re set thresho l d leve l 3 0 1 : bor le vel 2 (vbor2), re set thresho l d level 2 1 0 : bor le vel 1 (vbor1), re set thresho l d level 1 1 1 : bor of f (vbor0), por/pdr re set thresho l d leve l is a ppli ed. no te : f o r ful l de t a i l s abo ut bor ch aracteristi cs, refer to the ? e lectric a l char acter i stics? section in the device d a t a sheet. bit 1 opt s trt : option st art t h is bit trig gers a user option o peratio n when set. it is set o n ly by sof t ware a nd clea re d when the bsy bit is cleared. bit 0 optlock: option lock w rit e to 1 only . w h en t h is bit is set, it indi cates tha t the fl ash_opt cr regi ster is locked . t h is bit i s cle a red by hard ware af te r de te ctin g th e unlo ck seq uence . in the e vent o f an u n successful unl ock o peration , this bit remains set u n til th e next re se t. flash memory interface PM0059 26/29 docid15687 rev 5 2.8.7 flash interface register map t a b l e 1 0 . f l a s h re giste r map an d r ese t va lu es o ffs et r e gi s t er 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 flash_a c r reser v e d dcrst icrst dce n icen pr f t en re s e rved la t e n c y reset value 00000 00 0 0x04 fl as h _ ke y r k ey[ 31: 16] k ey[ 15: 0] reset v a lue 0000 0000 0000 0000 0000 0000 0000 000 0 0x08 fl ash_o pt k eyr op tkeyr[ 31: 16 ] o ptkey r[15 :0 ] reset v a lue 0000 0000 0000 0000 0000 0000 0000 000 0 0x0c flash_ s r reserved bsy reserved pg serr pg p er r pg a er r wrpe rr rese rved operr eop reset va lue 0 0000 0 0 0x10 flas h_cr lo c k reserved eo p i e reserved st r t rese r v e d psi z e[ 1: 0 ] re se rved snb [ 3 : 0] mer se r pg reset v a lue 1 0 0 00 000 0 0 0 0x14 fl ash_o pt cr reser v e d nwrp[ 1 1: 0] rdp[ 7:0 ] n r st_stdby nrst_stop wdg_sw reserved bor_lev optstrt optlock reset value 1111 1111 1111 1010 1010 111 110 1 docid15687 rev 5 27/29 pm0 059 re vision hist ory 28 3 revision history t a b l e 1 1 . do cume nt re vision hist ory date re vis i on changes 2 4 -jun-2 010 1 upd a ted memory o r gani zati on in section 2 .3: flash memory , an d replace user-speci f i c bl ock b y otp area . upd a ted add resses i n t a ble 6 : op tio n byte o r gani zation . defin i ti on o f bor_l e v[3:2] bi t s up dated i n t abl e 7 : description of the optio n byte s an d secti o n 2 .8.6: f l ash op ti on control reg i ste r (fl a sh _optcr) . mod i fied f l ash_opt cr reset value i n section 2 .8.6: fla sh o p tion con t rol re gister (flash_optc r ) an d t abl e 1 0: f l ash reg i ste r map a nd reset va lues . upda te d opt l o c k de fin ition. upda ted defin iti on of er rie bit in section 2 .8.5: f l ash c o ntrol regi ster (fl ash_cr) . 09 -d ec-201 0 2 upd a ted size o f otp are a , and o p tion b y te b a se ad dress and si ze in t abl e 2 : f l ash modu le organ ization . cha nge d 1.62 to 2.1 v ran ge to 1.8 to 2.1 v , add ed no te 1 as wel l as wait st at es 4 to 7 in t t a b l e 3 : n u m b e r of w a it st at es a ccor d i n g to cpu clock (hclk) freq uency . upda ted t able 4 : program/erase p a ralle lism . updated bor_level description in t able 7 : descrip tion of the op tio n byte s . ren a med fl ash_focr, fl ash_ optcr in section 2 .6.2: programmin g user option bytes . upd a ted leve l 1 a nd leve l 2 description s i n sect ion 2 .6.3: read protection (rd p ) . upd a ted la ten c y b i t s in section 2 .8.1: flash access contr o l register (fl ash_acr) t o su pp o r t up t o 7 wa it st at es. cha nge d a ccess type to bit s 0 to 7 to rc-1, a nd operr de scrip t i o n in section 2 .8 .4: fl ash st at us regi ster (fl a sh _sr) . cha nge d a ccess type to bit s 1 6 a nd 31 to rs in se ct io n 2 . 8 .5 : fl ash control regi ste r (f lash_cr) . cha nge d access type to bi t s 0 and 1 to rs, an d add ed no te rel a ted to bit 7 to 5 in section 2 .8 .6 : fl ash opt io n co ntro l register (fl a sh _optcr) . 30-mar-201 1 3 upd a ted ot p a r ea in section 2 .3: fl ash me mo ry . upda ted section 2 .5: era se a nd prog ram o peratio ns to mention the fact that re ad op erations cann ot b e performed duri ng write/erase op erations. revision history PM0059 28/29 docid15687 rev 5 10 -m ay-2 0 1 1 4 modi fie d note 1 in t a ble 3 : number of wait st ates accordi ng to cpu clock (hclk) freq uen cy and no te 1 in t a b l e 3 : nu mber of wai t st a t e s acco rd ing to cpu cl ock (h clk) frequ ency . 0 7 -jun-2 013 5 upda ted section 2 .4.1: relation bet ween cpu clock frequency and flas h memory read time to a dd prefetch disa blin g when the supp ly vo lt a ge is bel ow 2.1 v . adde d note in section : s t an dard pro g ramming upda ted section 2 .5.2: progra m/e r ase p a ral l eli s m . adde d t a ble 5 : fl ash interrupt reque st s . upda ted section 2 .6.3: r ead prot e c tio n (r dp) . upda ted section 2 .6.4: w r ite protections . modi fie d bor_ lev b i t s de fin i tion in sectio n 2 .8 .6 : fl ash optio n control register (flash_optcr) . docu me nt con verte d to ne w temp late and di sclaimer upd ated. t a ble 1 1 . doc u ment rev i s i on h i s t or y (c ont inu e d) date re vis i on changes docid15687 rev 5 29/29 29 pl ea se r e ad c a re fu lly : in f or m at i on i n t hi s d oc umen t i s p r o v i de d so l el y i n co nn ec ti on wi th st pr od uc ts . s t mi cr oe le ct ro ni cs nv an d i t s su bsi d ia ri e s (? s t ?) re ser v e th e ri gh t t o ma ke ch an ges , co rr ecti o ns, mo di f i c at i on s o r i m p r o vem ent s , t o t hi s d oc ume nt , and t he pr od ucts a nd ser vi c es de scr i be d h e r ei n at any t i me, with ou t no tic e . al l st pr odu ct s a r e s o l d pu rs ua nt to s t ? s t e r m s an d co nd it i o n s of sal e . pur c h a s e r s a r e so le l y r e s pon si bl e fo r t h e c hoi c e , se le ct i o n an d us e o f th e s t pr od uc ts an d s e r v i c e s d e s c r i b e d he re in , and st as sume s n o li a b i l i t y wh at so ev er r e l a t i ng t o t h e cho i ce, se le ct i o n o r u s e o f t h e s t pr odu ct s a nd s e r v i c e s de sc ri be d he re in . no l i c e n se , e x p r e s s o r i m pl i e d , b y e s t o p pel or ot he rw is e, t o an y i n t e l l e c t u a l pr op er ty ri gh t s i s gr an te d u nde r t h i s doc ume n t . i f an y pa rt of t h i s do cume nt re f er s t o an y t hi r d pa rt y p r o duc t s or se rv ic es i t sh al l n ot be d ee m ed a li ce ns e gr an t b y st fo r t he use of su ch t hi r d par ty pr od uc ts or ser vi c es, or an y in t el l e ct ua l p r o pe r t y c ont a i n ed t he r e i n or con si de r e d as a war r ant y c ov er i n g t he u se i n a ny ma nn er w hat s oev er o f su ch th i r d p a r t y pr od uct s o r se rv i c es or a n y i n t e ll e c t u a l pr op er t y co nt ai ne d ther ei n . unle ss o t her w ise se t for t h in s t ?s t e rms and co nditions o f sa le s t disc laims an y ex pres s or imp l ied warrant y wit h r espe ct to th e use and/or sa le of st p r oduct s in cluding withou t limit a tion imp l ied warrant ie s of merch antab il it y, fitne ss f o r a parti cul ar p urpos e ( and t heir e q uivale nts under the laws of any j urisdiction) , o r inf r in gement o f any pat e nt, copy right or oth e r in tel l ect ual pro pert y rig h t. st produ c ts are not author i z e d f o r us e in w e apon s. nor are st produc ts designe d or autho rize d for u s e in : (a) s a fet y c r it ic al a ppl ica t ion s s uch as l i f e s u ppo rting , a c tive implant ed device s or sy stems with prod uct fu nctional safe ty re quirement s ; (b) aero nautic ap plica t ions ; ( c) au t o motive appl ica t io ns or enviro nments , and /or ( d) a e rosp a ce appl ica t ions or env i r o nment s . whe re st pro ducts a re not des i g ned for such us e, th e p urchas er shal l u se prod ucts a t purch aser?s sol e ris k , ev en if s t ha s b een informe d in writing of s uch u s age , unle ss a p r oduct is exp ress l y de signa t ed by st as being inten d ed for ?au t omotive , aut omot iv e saf e ty or me dical? industr y domains ac cording t o st p r oduct design sp ecifica t ions . prod ucts formal l y es cc, qml or jan qualif ie d are deeme d suit ab le f o r use in aer o sp ace by t he corre spon d in g g o vern m ent a l ag ency . res al e of st pr od uct s wi t h pr ov is io ns d i f f er en t f r o m t he s t at eme nt s an d/ or t ec hn i c al fe at ur es s et f o rt h i n th is d oc ume nt s ha l l i mme di at el y v o i d a n y w a r ra n ty gr an te d b y s t f o r t h e st pr od u c t o r s e r v ic e d e s c rib ed he re in an d s h a ll n o t c re a t e o r ex te nd in a n y ma nn er w h at so ev er, a n y l i ab il ity of st. st a nd t he s t lo go a r e tr ad ema r k s or re gi st er ed t r ad emar ks of s t i n va ri ou s co un tr i es. in f o r m at i on i n t h i s do cu men t su pe rs ed es a nd r e p l a c e s al l i n fo rma t i o n pr ev io us ly s u p p l i e d . th e st l o g o is a re gi ste re d tr ad ema rk o f s t micr oe le ct ro ni cs . a ll ot he r n a m es a re th e pr op er ty of th ei r r e s p e c tiv e ow n e r s . ? 20 13 st mi cr oel e c t r o n i c s - al l r i g h t s r e s e r v e d s t mi cr oe le ctr o n i c s gr ou p of co mp an ie s aus t r al i a - b el gi um - b r a zi l - can ad a - ch in a - cz ech rep ub l i c - f i nl an d - fr an ce - ger m an y - ho ng k ong - i ndi a - is ra el - i t a l y - ja pa n - m a l a y si a - ma lt a - morocco - p h i l i p pi nes - si ngapor e - sp ai n - s w eden - swi t zer l and - un it ed kingd om - u n i t e d st at e s of amer i ca www.s t.co m |
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