257 n replaces 8 potentiometers and 8 op amps n operates from single +5v supply n 5 mhz 4-quadrant multiplying band- width n eight inputs/eight outputs (SP9840) four inputs/eight outputs (sp9843) n 3-wire serial input n 0.8mhz data update rate n +3.25v output swing n midscale preset n programmable signal inversion n low 70mw power dissipation (9mw/dac) ?
+ 4 8 8 8 dac 1 dac 8 8 8 x 8
dac
register serial
register logic decoded
address data clock
serial data input
serial data output
preset
load v in 1
v out 1 v in 8
v out 8 v ref low SP9840 shown description the SP9840 and sp9843 are general purpose octal dacs in a single package. the SP9840 features eight individual reference inputs, while the sp9843 provides four pair of voltage reference inputs. both parts feature 5mhz bandwidth, fourCquadrant multiplication, and a threeC wire serial interface. other features include midscale preset, programmable signal inversion and low power dissipation from a single +5v supply. devices are available in commercial and industrial temperature ranges. SP9840/43 8-bit octal, 4-quadrant multiplying, bicmos dac
258 absolute maximum ratings these are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v dd to gnd ...................................................................... -0.3v, +7v v in x to gnd ............................................................................... v dd v ref l to gnd ............................................................................. v dd v out x to gnd ............................................................................ v dd short circuit i out x to gnd ............................................ continuous digital input & output voltage to gnd ....................................... v dd operating temperature range commercial ............................................................... 0 c to +70 c extended industrial ................................................. -40 c to +85 c maximum junction temperature (t j max) .......................... +150 c storage temperature ................................................. -65 to 150 c lead temperature (soldering, 10 sec) ............................... +300 c package power dissipation .................................. (t j max - t a )/8ja thermal resistance 8 ja p-dip .................................................................................. 57 c/w soic-24 .............................................................................. 70 c/w caution: while all input and output pins have internal protection networks, these parts should be considered esd (electrostatic discharge) sensitive de- vices. permanent damage may occur on unconnected devices subject to high en- ergy electrostatic fields. unused devices must be stored in conductive foam or shunts. personnel should be properly grounded prior to handling this device. the protective foam should be discharged to the destination socket before devices are removed. specifications (v dd = +5v, all v in x= 0v, v ref l = 1.625v, t a = 25 c for commercialCgrade parts; t min t a = t max for industrialCgrade parts; specifications apply to all dac's unless noted otherwise.) parameter min. typ. max. units conditions signal inputs input voltage range 0 3.25 v v dd = 4.75v, v refl = 1.625v input resistance d = 2b h , code dependent SP9840 3.1 6.2 k w sp9843 1.55 3.1 k w input capacitance note 1 SP9840 19 30 pf sp9843 38 60 pf v refl resistance 0.68 1.3 k w note 1 and 2 v refl capacitance 190 250 pf note 1 digital inputs logic high 2.4 v logic low 0.8 v input current 10 m a input capacitance 8 pf input coding offset binary note 3 static accuracy resolution 8 bits integral nonlinearity 0.75 1.5 lsb note 4 differential nonlinearity 0.3 1 lsb note 4 half-scale output voltage 1.600 1.625 1.650 v pr = low, v refl = 1.625v minimum output voltage 20 100 mv d=ff h ; i sink = 0.1ma output voltage drift 25 m v/ c pr = low dynamic performance multiplying gain bandwidth 3 5 mhz v in (x) = 100mv pCp + 1.625v dc slew rate measured 10% to 90% positive 3.0 7.9 v/ m s d v = 3.2v negative C3.0 C8.3 v/ m s d v = C3.2v total harmonic distortion 0.003 % v in (x) = 3v pCp +1.625v dc, d=ff h ; 1khz, f lp =80khz output settling time 0.7 m s 1 lsb error band crosstalk 60 70 db note 5 digital feedthrough 6 nvs d = 0 h to ff h wideband noise 42.5 m vrms v out = 3.25v, 400hz to 80khz sinad 89 db v in (x) = 3v pCp +1.625v dc, d=ff h ; 1khz, f lp =80khz digital crosstalk 6 nvs note 6
259 specifications (continued) v dd = +5v, all v in x= +0v, v ref l = 1.625, t a = 25 c for commercialCgrade parts; t min t a = t max for industrialCgrade parts; specifications apply to all dac's unless noted otherwise.) parameter min. typ. max. unit conditions dac outputs voltage range 0 v dd C 1.5 v r l = 5k w , v dd = 4.75v output current 10 15 ma note 7 capacitive load 47,000 pf no oscillation digital output logic high 3.5 v i oh = C0.4ma logic low 0.4 v i ol = 1.5ma power requirements power supply range 4.75 5.00 5.25 v to rated specifications positive supply current 14 ma pr = low power dissipation 70 mw pr = low environmental and mechanical operating temperature range commercial 0 +70 c industrial C40 +85 c storage temperature range C65 +150 c package SP9840n 24Cpin, 0.3" plastic dip SP9840s 24Cpin 0.3" soic sp9843s 20Cpin, 0.3" soic note 8 notes: 1. code dependent 2. all v in (x) = gnd; d = 55 h 3. offset binary refers to the output voltage with respect to the signal ground at v refl . for a positive v in (x), the output will increase from negative fullscale to v refl to positive (fullscaleC1 lsb) as the input code is incremented from 0 to 128 to 255. note that when v in (x) is tied to ground and v refl is driven to +1.625v, as in the production tests above, then the resulting dc at v out (x) will decrease from +2v refl to v refl /128 as the code is increased from 00 h to ff h , due to the v in (x) input being tied negative with respect to v refl . 4. the op amp limits linearity for v out <100mv. when v in (x) is driven above ground such that the output voltage remains above 100mv, then the linearity specifications apply to all codes. for v refl =1.625v, and v in (x)=gnd, codes 248 through 255 are not included in differential or integral linearity tests. integral and differential linearity are computed with respect to the best fit straight line through codes 0 through 248. 5. SP9840 is measured between adjacent channels, f=100khz. sp9843 is measured between adjacent pairs, f=100khz. 6. sp9843 only; measured between channels with shared input; d = 7f h to 80 h 7. d v out < 10mv, v refl = 1.625v, pr = low. 8. for plastic dip, consult factory
260 SP9840 pinout 24 v out d
23 v in c
22 v in d
21 v dd
20 sdi
19 gnd
18 sdo
17 clock
16 loadh
15 v in h
14 v in g
13 v out h v out c 1
v out b 2
v out a 3
v in b 4
v in a 5
v refl 6
presetl 7
v in e 8
v in f 9
v out e 10
v out f 11
v out g 12 SP9840 pin 1 v out c dacc voltage output. pin 2 v out b dacb voltage output. pin 3 v out a daca voltage output. pin 4 v in b dac b reference voltage input. pin 5 v in a dac a reference voltage input. pin 6 v ref l dac reference voltage input low, common to all dacs. pin 7 presetl preset input; active low; all dac registers forced to 80 h . pin 8 v in e dac e reference voltage input. pin 9 v in f dac f reference voltage input. pin 10 v out e dace voltage output. pin 11 v out f dacf voltage output. pin 12 v out g dacg voltage output. pin 13 v out h dach voltage output. pin 14 v in g dacg reference voltage input. pin 15 v in h dach reference voltage input. pin 16 loadh load dac register strobe; active high input that transfers the data bits from the serial input register into the decoded dac register. refer to table 1. pin 17 clock serial clock input; positive-edge triggered. pin 18 sdo serial data output; active totem-pole output. pin 19 gnd ground. pin 20 sdi serial data input. pin 21 v dd positive 5v power supply. pin 22 v in d dacd reference voltage input. pin 23 v in c dacc reference voltage input. pin 24 v out d dacd voltage output. sp9843 pinout 20 v out d
19 v in c/d
18 v dd
17 sdi
16 gnd
15 sdo
14 clock
13 loadh
12 v in g/h
11 v out h v out c 1
v out b 2
v out a 3
v in a/b 4
v ref l 5
presetl 6
v in e/f 7
v out e 8
v out f 9
v out g 10 sp9843 pin 1 v out c dacc voltage output. pin 2 v out b dacb voltage output. pin 3 v out a daca voltage output. pin 4 v in a/b daca and b reference voltage input. pin 5 v ref l dac reference voltage input low, common to all dacs. pin 6 presetl preset input; active low; all dac registers forced to 80 h . pin 7 v in e/f dac e and f reference voltage input. pin 8 v out e dace voltage output.
261 pin 9 v out f dacf voltage output. pin 10 v out g dacg voltage output. pin 11 v out h dach voltage output. pin 12 v in g/h dacg and h reference voltage input. pin 13 loadh load dac register strobe; active high input that transfers the data bits from the serial input register into the decoded dac register. refer to table 1. pin 14 clock serial clock input; positive-edge triggered. pin 15 sdo serial data output; active totem-pole output. pin 16 gnd ground. pin 17 sdi serial data input. pin 18 v dd positive 5v power supply. pin 19 v in c/d dacc and d reference voltage input. pin 20 v out d dacd voltage output. SP9840/sp9843 theory of operation each of the eight channels of the SP9840/9843 can be used for signal reconstruction, as a pro- grammable dc source, or as a programmable signed attenuator of C1 to +0.992 times a multi- plying ac reference input. the rugged wideband output amplifiers provide both current sink and source capability to dc applications, even into difficult loads. the dc source mode mimics the functionality of a programmable trimpot, with the added benefit of a lowCimpedance buffered output. the amplifier's bandwidth and high open loop gain allow use in programmable signed attenuator applications where even lowCdistor- tion, high resolution signals, such as audio, must be gated on and off, programmable phase shifted by 0 or 180 or gain controlled over a C42 to 0db range at either phase. each channel consists of a voltageCoutput dac, realized using cmos switches and thinCfilm resistors in an inverted rC2r configuration. each dac drives the positive terminal of an op amp, configured for a gain of C1 to +1 using equal value thinCfilm feedback and gainCsetting resistors. signal return is the v refl pin, the common reference input return for the eight dacCop amp channels. as shown in figure 1 , the dac section can be thought of as a potentiometer across v in (x) to v refl . if this potentiometer is set to its minimum value of 0/256, the potentiometer will have no effect on the gain, and the output will be Cr f /r in = C1 times the input. if the potentiometer could be set to 256/256, then the amplifier positive terminal would see 100% of any input and no current would flow through r in . the circuit would behave as a nonCinverting unity gain circuit, although with a noise gain of two, not one. in reality, the "potentiometer" can only be set to 255/256, and the maximum positive gain is 0.992 times the voltage between v in (x) and v refl . the true relation between the dc levels at the v in (x) pins, v ref l and the output can be de- scribed as: f1 where d is programmable from 0 to 255. for single supply operation v refl is usually externally driven to some voltage above ground typically 1.5 to 2.5v. if v refl is driven to 1.5v, and v in (x) is grounded, then code 0 would output +3.0v, and code 255 would output +11.7mv. if v refl were grounded and v in (x) driven to 1.5v, then codes between 0 and 128 would attempt to drive the output below ground, which will saturate the output amplifier at some voltage slightly above ground. v d vv v out in refl refl = () - () *- () + 128 1 using the SP9840/9843 multiplication of input voltages while both the SP9840 and sp9843 are capable of fourCquadrant multiplication, this terminology is not
262 last d 0
lsb data address d 1 d 2 d 3 d 4 d 5 d 6 d 7
msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dac output voltage
v out = ?v ref l a 0
lsb a 1 a 2 a 3
msb a 3 a 2 a 1 a 0 dac updated first 0
0
0
0
0
0
0
0
1
1
.
.
1 0
0
0
1
1
1
1 0
0
1
0
0
1
1 0
0
1
0
0
1
1 0
0
1
0
0
1
1 0
0
1
0
0
.
.
.
1
1 0
0
1
0
0
1
1 0
0
1
0
0
1
1 0
1
1
0
1
0
1 0
0
0
0
1
1
1
1
0
0
.
.
1 0
0
1
1
0
0
1
1
0
0
.
.
1 0
1
0
1
0
1
0
1
0
1
.
.
1 no operation
daca
dacb
dacc
dacd
dace
dacf
dacg
dach
no operation
.
.
no operation
.
.
. d vv v in refl ref 128 1 - ? ? ? ? *- () + table 1. serial input decoded truth table in reality, it is possible to define a dc voltage as a signal ground in a single supply system. if the dac's v refl pin is driven to the voltage chosen as pseudoC ground, then each voltage output will exhibit 4C quadrant behavior with respect to pseudoground. for codes greater than 128, the output voltage will enter the quadrant below the pseudoground voltage when the input voltage goes below pseudoground. for codes less than 128, the output voltage will be below pseudoground when the input is above pseudoground. when v refl is driven to some positive voltage and v in (x) is grounded, the device performs as if it were a buffered trimpot tied between ground and a voltage equal to two times v refl . this mode of operation can be used as an "inverted singleC quadrant" source with an approximate range of 0 to (v refl *2)volts. because the output voltage will decrease as the code is increased, this mode is considered to be inverted with respect to normal singleCquadrant operation. note that the mini- mum output voltage will be 1lsb above v in (x). figure 2a and 2b show "inverted singleCquadrant" and 4Cquadrant performance of the SP9840/9843 . very precise when describing a system which runs from a single positive supply. traditionally, the quad- rants have been defined with respect to 0v. a twoC quadrant multiplying dac could produce negative output voltages only if a negative voltage reference were applied. a fourCquadrant device could also produce a codeCcontrolled negative output from a positive reference, or a codeCcontrolled positive out- put from a negative reference. if ground is used to delineate the quadrants, then the SP9840/sp9843 should be considered singleCquadrant multiplying devices, as their output op amps cannot produce voltages below ground. ? + dac 3 v refl +5v v dd v in (x) v out v d vv v out in refl refl =- - + ? ? ? ? () 128 1 figure 1. dac and output amplifier circuit
263 a) b) figure 2. a) inverted singleCquadrant operation; b) 4Cquadrant operation applications which require twoCquadrant operation with respect to pseudoground should use the sipex sp9841 or sp9842 twoCquadrant multiplying dacs. the choice of voltage to use for the pseudoground is limited by the legal voltage swing at the op amp output. the op amp exhibits excellent linearity for output voltages between, conservatively, 100mv and v dd C 1.5v. the op amp bicmos output stage consists of an npn follower loaded by an nmos common sourced to ground. this circuit exhibits wide bandwidth and can source large currents, while retaining the capabil- ity of driving the output to voltages close to ground. at output voltages below 25mv, feedback forces some op amp internal nodes toward the supply rails. the nmos pullCdown device gets driven hard and the nmos device enters the linear region it begins to function in the same manner as a 50 ohm resistor. in reality, the wideband amplifier output stage sinks some internal quiescent current even when driving the output towards ground. this sunk current drops across the output stage nmos transistor onC resistance and internal routing resistance to pro- vide a minimum output voltage below which the amplifier cannot drive. this minimum voltage is in the 15 to 25mv range. it varies within a package with each op amp's offset voltage and biasing variations. if an input voltage lower than this minimum, such as code 255 when v in (x) is grounded, is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. nonCsaturated monotonic be- havior returns between 25mv and 100mv at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mv above the negative supply. fourCquad- rant (programmable signed attenuator) applica- tions usually bias v refl up at system pseudoground, well above this saturation re- gion, and therefore maintain linearity even at high attenuations (i.e. near code 80 hex ). driving the reference inputs the eight independent v in inputs of the SP9840 , and the fourCpair of inputs in the sp9843 , exhibit a codeC dependent input resistance, as shown in the specifica- tions, and as a typical graph. in general, these inputs should be driven by an amplifier capable of handling table 2. logic control input truth table. sdi clk loadh presetl logic operation x l l h no change data l h shift in one bit from sdi shift out 12Cclock delayed data at sdo x x x l all dac registers preset to 80 h (note 1) x l h h load serial register data into dac(x) register note 1: "preset" may not persist at all dacs if loadh is high when presetl returns high.
264 the specified load resistance and capacitance. the reference inputs are useful for both ac and dc input sources. however, series resistance into these pins will degrade the linearity of the dac 50 ohms of series resistance can cause up to 0.5lsb of additional integral linearity degradation for codes near zero, due to the codeCdependent input current dropping across this error resistance. acCcoupled applications should use the largest capacitor value (lowest series imped- ance) which is practical, or use an external buffer to drive the inputs. the dac switches function in a breakCbeforeCmake manner in order to minimize current spikes at the reference inputs. the reference inputs can withstand driving voltages slightly beyond the power rails with- out harm; the gain of 1 at the op amps limits the choice of v in /v refl combinations if clipping is to be avoided at very high or very low codes. note that railC toCrail inputs can always be attenuated by choosing a code nearer midscale, if clipping of the output is undesirable. output considerations each dac output amplifier can easily drive 1kohm loads in parallel with 15pf at its rated slew rate. the unique bicmos amplifier design also ensures stabil- ity into heavily capacitive loads up to 47,000pf. under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance the slew rate will be severely degraded, and some damped ringing will occur. especially under heavy capacitive loading, a large, low imped- ance local bypass capacitor will be required. a 0.047 m f ceramic in parallel with a lowCesr 2.2 to 10 m f tantalum are recommended for worstCcase loads. the amplifier outputs can withstand momentary shorts to v dd or ground. continuous short circuit operation can result in thermally induced damage, and should be avoided. if the input reference voltage is reduced to 0.6v, then both the amplifier and dac are functional at room temperature at supply voltages as low as 2.5v. at v dd = 2.7v, power dissipation is 9.3mw typical, with the serial clock at 4mhz, or 7.0mw typical with the serial clock gated off. interfacing to the SP9840/sp9843 a simple serial interface, similar to that used in a 74hc594 shiftCregister with output latch, has been implemented in these products. a serial clock is used to strobe serial data into a 12Cstage shiftCregister at each rising clock edge. the first four serial bits contain the address of the dac to be updated, msb first. the next 8 bits contain the binary value to be loaded into the desired dac, again msb first. after the 12th serial bit is clocked in, the loadh line can be strobed to latch the 8 bits of data into the data holding register for the desired dac. the address bits feed a decoding network which steers the loadh pulse to the clock input of the desired dac data holding register. the output of the 12th shiftCregister is also buffered and brought out as the serial data out (sdo), which can be used to cascade multiple devices, or for data verification purposes. the address field is set up such that daca is ad- dressed at 0001 (binary) and the others consecutively through dach at 1000(binary). address 0000(bi- nary) will not affect the operation of any channel, as this combination is easily generated inadvertently at powerCup. other noCoperation addresses exist at 1001(binary) through 1111(binary). another use for noCoperation addresses is to mask off updates of any dac channel in a multipleCpart system with cas- caded serial inputs and outputs. by sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the loadh pin at each part in parallel from a single source. table 1 shows a registerClevel diagram of the addresses, data, and the resulting operation. a fourth control pin, presetl, can be used to simultaneously preset all dac data holding registers to their midCscale (80 h ) values. this will asynchro- nously force all dac outputs to buffer the voltages at their respective inputs to their outputs with unity gain. this feature is useful at powerCup, as a simple resistor to the supply and capacitor to ground can insure that all dac outputs start at a known voltage. for fourC channel multiplying applications, this sets the default startCup gain to zero; only C70db of feedthrough from the v in (x) inputs will be present at the outputs. table 2 summarizes the operation of the four digital inputs.
265 the four digital control input pins have been designed to accept ttl (0.8v to 2.0v minimum) or full 5v cmos input levels. the serial data output can drive either ttl or cmos inputs. timing information is shown in figure 3 . serial data is fully clocked into the shiftCregister after 12 clock rising edges, subject to the described setup and hold times. after the shiftCregister data is valid, the loadh line can be pulsed high to load data into the desired dac data register, which switches the dac to the new input code. the serial clock input should not see a rising edge while the loadh pulse is high in order to prevent shiftC register data from corruption during data register loading. the serial clock and data input pins are designed to be compatible as slaves under national semiconductor 's microwire? and microwireplus? protocols and under motorola 's spi? and qspi? protocols. in some microCcontrollers, the interface is completed by programming a bit in a generalCpurpose i/o port as a level, used to strobe the loadh line at the dacs. this is done in a manner similar to that used for generating a chip select signal, which is necessary when driving some other microwire? peripherals. figure 3. timing characteristics (typical @ 25 c with v dd = +5v unless otherwise noted.) parameter min. typ. max. unit conditions input clock pulse width (t ch , t cl )50 ns data setup time (t ds )30 ns data hold time (t dh )20 ns clk to sdo propagation delay (t pd ) 100 ns dac register load pulse width (t ld )50 ns preset pulse width (t pr )50 ns clock edge to load time (t ckld )30 ns load edge to next clock edge (tldck) 60 ns 1
0 a 3 a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1
0 1
0 fs
0 sdi clock load v out 1
0 1
0 1
0 (ff h )
(08 h ) serial
data in serial data input timing detail (preset = logic "1"; v in(x) = 1.5v; v ref l = 0v) 1
0 serial
data out clock load v out t ds t ch t cl t ld t s t ldck ? lsb
error band t clkd t pd t dh a x or d x 1
0 preset t s t pr ? lsb
error band (ff h )
(08 h ) v out
266 ordering information model reference inputs temperature range package SP9840kn ................................... eight, independent ............................................... 0 to + 70 c ................................. 24Cpin, 0.3" plastic dip SP9840bn ................................... eight, independent ............................................... C40 to + 85 c ............................. 24Cpin, 0.3" plastic dip SP9840ks ................................... eight, independent ............................................... 0 to + 70 c ........................................... 24Cpin, 0.3" soic SP9840bs ................................... eight, independent ............................................... C40 to + 85 c ....................................... 24Cpin, 0.3" soic sp9843ks ................................... four pair ............................................................... 0 to + 70 c ........................................... 20Cpin, 0.3" soic sp9843bs ................................... four pair ............................................................... C40 to + 85 c ....................................... 20Cpin, 0.3" soic
|
