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267 n replaces 8 potentiometers and 8 op amps n operates from single +5v supply n 6.3 mhz 2-quadrant multiplying gain band- width n no signal inversion n eight reference inputs, eight voltage outputs (SP9841) n four reference inputs, eight voltage outputs (sp9842) n 3-wire serial input n 0.8mhz data update rate n +3.25 volt output swing n midscale preset n low 65 mw power dissipation (8 mw /dac) description the SP9841 and sp9842 are general purpose octal dacs in a single package. the SP9841 features eight individual reference inputs, while the sp9842 provides four pair of voltage reference inputs. both parts feature 6.3mhz bandwidth, twoCquadrant multiplication, and a threeCwire serial interface. other features include midscale preset, no signal inversion and low power dissipation from a single +5v supply. devices are available in commercial and industrial temperature ranges. + 4 8 8 8 dac a 8 x 8 dac register serial register logic decoded address data clock serial data input serial data output preset load v ref low sp9842 + 8 dac b v in a/b v out b v out a + 8 dac g + 8 dac h v in g/h v out h v out g sp9842 block diagram 4 8 8 8 dac a dac h 8 8 x 8 dac register serial register logic decoded address data clock serial data input serial data output preset load v in a v out a v in h v out h v ref low SP9841 + SP9841 block diagram SP9841/42 8-bit octal, 2-quadrant multiplying, bicmos dac
268 absolute maximum ratings these are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v dd to gnd ...................................................................... -0.3v, +7v v in x to gnd ............................................................................... v dd v ref l to gnd ............................................................................. v dd v out x to gnd ............................................................................ v dd short circuit i out x to gnd ............................................ continuous digital input & output voltage to gnd ....................................... v dd operating temperature range commercial: SP9841k/sp9842k .............................. 0 c to +70 c extended industrial: SP9841b/sp9842b ................ -40 c to +85 c maximum junction temperature (t j max) .......................... +150 c storage temperature ................................................. -65 to 150 c lead temperature (soldering, 10 sec) ............................... +300 c package power dissipation ................................. (t j max - t a )/ ? ja thermal resistance ? ja p-dip .................................................................................. 57 c/w soic-24 .............................................................................. 70 c/w specifications (v dd = +5v, all v in x= +1.625v, v ref l = 0v, t a = 25 c for commercialCgrade parts; t min t a = t max for industrialCgrade parts; specifications apply to all dac's unless noted otherwise.) parameter min. typ. max. units conditions signal inputs input voltage range 0 1.625 v v refl = gnd, v dd = 4.75v input resistance d = 55 h ; code dependent SP9841 510 k w sp9842 2.5 5 k w input capacitance code dependent SP9841 19 30 pf sp9842 38 60 pf v refl resistance 0.375 0.75 k w all d = ab h ; code dependent v refl capacitance 190 250 pf code dependent digital inputs logic high 2.4 v logic low 0.8 v input current 10 m a input capacitance 8 pf input coding binary static accuracy resolution 8 bits integral nonlinearity 0.25 1.0 lsb note 1 differential nonlinearity 0.2 1.0 lsb note 1 half-scale output voltage 1.600 1.625 1.650 v pr = low, sets d = 80 h zero-scale output voltage 20 100 mv d = 00 h output voltage drift 25 m v/ c pr = low, sets d = 80 h dynamic performance multiplying gain bandwidth 4 6.3 mhz v in x = 100 mv p-p+ 1.0v dc slew rate measured 10% to 90% positive 3.0 7.9 v/ m sv out x = 100mv to +3.1v negative C3.0 C8.3 v/ m sv out x = +3.1v to 100mv total harmonic distortion 0.005 % v in x = 0.8v dc + 1.4v p-p d= ff h ; 1khz, f lp = 80 khz output settling time 0.7 m s 1 lsb error band, 8 h to 255 h crosstalk 60 70 db note 2 digital feedthrough 6 nvs v ref l = +1.625v, d = 0 to ff h wideband noise 42.5 m v rms v out = 3.25v; 400hz to 80khz caution: while all input and output pins have inter- nal protection networks, these parts should be considered esd (electrostatic dis- charge) sensitive devices. permanent dam- age may occur on unconnected devices sub- ject to high energy electrostatic fields. un- used devices must be stored in conductive foam or shunts. personnel should be prop- erly grounded prior to handling this device. the protective foam should be discharged to the destination socket before devices are re- moved.
269 specifications (continued) (v dd = +5v, all v in x= +1.625v, v ref l = 0v, t a = 25 c for commercialCgrade parts; t min t a = t max for industrialCgrade parts; specifications apply to all dac's unless noted otherwise.) parameter min. typ. max. unit conditions dynamic performance sinad 85 db v in x = 0.8v dc + 1.4v p-p d= ff h ; 1khz, f lp = 80 khz digital crosstalk 6 nvs sp9842 only; measured between adjacent channels of same pair; d = 7f h to 80 h dac outputs voltage range 0 v dd C1.5 v r l = 5k w ; v dd = 4.75v output current 10 15 ma d v out < 10mv, v in x=1.625v, pr = low capacitive load 47,000 pf no oscillation digital output logic high 3.5 v i oh = -0.4ma logic low 0.4 v i ol = 1.6ma power requirements power supply range 4.75 5.00 5.25 v to rated specifications positive supply current 13 ma pr = low power dissipation 65 mw environmental and mechanical operating temperature range commercial 0 +70 c industrial C40 +85 c storage temperature range C65 +150 c package SP9841n 24Cpin plastic dip SP9841s 24Cpin soic sp9842s 20Cpin soic note 3 notes: 1 the op amp limits the linearity for v out 100mv. when v refl is driven above ground such that the output voltage remains above 100mv, then the linearity specifications apply to all codes. for v refl = gnd, v in = 1.5v, codes 0 through 7 are not included in differential or integral linearity tests. integral and differential linearity are computed with respect to the best fit straight line through codes 8 through 255. 2 SP9841 is measured between adjacent channels, f = 100khz; sp9842 is measured between adjacent pairs, f = 100khz. 3 for plastic dip packaging of sp9842 , please consult factory.
270 plot 1. integral linearity error versus code. plot 2. differential nonClinearity error versus code. plot 3. integral linearity matching; v out a through v out d.
271 plot 4. integral linearity matching; v out e through v out h. plot 5. thd versus frequency. plot 6. psrr versus frequency.
272 plot 8. full scale pulse response. plot 7. small signal gain versus frequency. v dd = 5v v in = 0.05v to 1.55v v out = 0.1v to 3.1v plot 9. positive full scale settling. v dd = 5v v in = 0.05v to 1.55v v out = 0.1v to 3.1v
273 plot 10. negative full scale settling. plot 11. v in (x) current versus code. v dd = 5v v in = 0.05v to 1.55v v out = 0.1v to 3.1v plot 12. i refl current input current versus code.
274 plot 13. typical midscale output versus temperature. plot 14. supply current versus temperature. plot 15. output short circuit current versus v out (x).
275 plot 16. sink current at zero scale. plot 17. typical v out max versus v dd . plot 18. typical v out min versus v dd versus i sink .
276 plot 20. integral error versus code versus v dd ; v in (x) = 0.6v. plot 19. integral error versus code versus v dd ; v in (x) = 0.5v.
277 a) b) c) d) plot 21. pulse response a) c load = 470pf, r load = 10mohm; b) c load = 470pf, r load = 1kohm; c) 50ohms in series with c load = 470pf; d) r load = 1kohm, 50ohms in series with c load = 470pf.
278 a) b) c) d) plot 22. pulse response a) c load = 4,700pf; b) c load = 4,700pf, r load = 1kohm; c) 30 ohms in series with c load = 4,700pf; d) r load = 1kohm, 30ohms in series with c load = 4,700pf.
279 a) b) c) d) plot 23. pulse response a) c load = 47,000pf; b) c load = 47,000pf, r load = 1kohm; c) 15 ohms in series with c load = 47,000pf; d) r load = 1kohm, 15 ohms in series with c load = 47,000pf.
280 a) b) c) d) plot 24. pulse response a) c load = 0.47 m f; b) c load = 0.47 m f, r load = 1kohm; c) 8.2 ohms in series with c load = 0.47 m f; d) r load = 1kohm, 8.2 ohms in series with c load = 0.47 m f.
281 pinout 24 v out d 23 v in c 22 v in d 21 v dd 20 sdi 19 gnd 18 sdo 17 clock 16 loadh 15 v in h 14 v in g 13 v out h v out c 1 v out b 2 v out a 3 v in b 4 v in a 5 v refl 6 presetl 7 v in e 8 v in f 9 v out e 10 v out f 11 v out g 12 SP9841 20 v out d 19 v in c/d 18 v dd 17 sdi 16 gnd 15 sdo 14 clock 13 loadh 12 v in g/h 11 v out h v out c 1 v out b 2 v out a 3 v in a/b 4 v ref l 5 presetl 6 v in e/f 7 v out e 8 v out f 9 v out g 10 sp9842 pin 18 sdo serial data output; active totemC pole output. pin 19 gnd ground. pin 20 sdi serial data input. pin 21 v dd positive 5v power supply. pin 22 v in d dac d reference voltage input. pin 23 v in c dac c reference voltage input. pin 24 v out d dac d voltage output. sp9842 pinout pin 1 v out c dac c voltage output. pin 2 v out b dac b voltage output. pin 3 v out a dac a voltage output. pin 4 v in a/b dac a and b reference voltage input. pin 5 v ref l dac reference voltage input low, common to all dacs. pin 6 presetl preset input; active low; all dac registers forced to 80 h . pin 7 v in e/f dac e and f reference voltage input. pin 8 v out e dac e voltage output. pin 9 v out f dac f voltage output. SP9841 pinout pin 1 v out c dac c voltage output. pin 2 v out b dac b voltage output. pin 3 v out a dac a voltage output. pin 4 v in b dac b reference voltage input. pin 5 v in a dac a reference voltage input. pin 6 v ref l dac reference voltage input low, common to all dacs. pin 7 presetl preset input; active low; all dac registers forced to 80 h . pin 8 v in e dac e reference voltage input. pin 9 v in f dac f reference voltage input. pin 10 v out e dac e voltage output. pin 11 v out f dac f voltage output. pin 12 v out g dac g voltage output. pin 13 v out h dac h voltage output. pin 14 v in g dac g reference voltage input. pin 15 v in h dac h reference voltage input. pin 16 loadh load dac register strobe; active high input that transfers the data bits from the serial input register into the decoded dac register. refer to table 1. pin 17 clock serial clock input; positiveC edge triggered.
282 pin 10 v out g dacg voltage output. pin 11 v out h dach voltage output. pin 12 v in g/h dacg and h reference voltage input. pin 13 loadh load dac register strobe; active high input that transfers the data bits from the serial input register into the decoded dac register. refer to table 1. pin 14 clock serial clock input; positiveC edge triggered. pin 15 sdo serial data output; active totemC pole output. pin 16 gnd ground. pin 17 sdi serial data input. pin 18 v dd positive 5v power supply. pin 19 v in c/d dacc and d reference voltage input. pin 20 v out d dacd voltage output. features the SP9841 and sp9842 include eight separate op ampCbuffered eightCbit dacs. these can be used to replace up to eight trimpots with eight lowCimped- ance programmable sources. the SP9841 uses eight separate multiplying reference inputs, while the sp9842 provides four pair of multiplying inputs. all of the reference inputs, in either case, are returned to a common voltage reference low pin. the inherent 2x gain from the twoCquadrant multiplying reference inputs to the outputs allows the use of ac or dc multiplying reference inputs generated from a single, low supply voltage. each dac has its own data register which holds its output state. these data registers are updated from an internal serial-to-parallel shift register which is loaded from a standard 3-wire serial input digital interface. twelve data bits make up the data word clocked into the serial input register. this data word is decoded such that the first 4 bits determine the address of the dac register to be loaded and the last 8 bits are the data. a serial data output pin at the opposite end of the serial register allows simple daisy-chaining in mul- table 1. serial input decoded truth table last d 0 lsb data address d 1 d 2 d 3 d 4 d 5 d 6 d 7 msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dac output voltage v out = d/128 (v in ?v ref l) + v ref l v ref l 1/128 (v in ?v ref l) + v ref l 127/128 (v in ?v ref l) + v ref l v in (preset value) 129/128 (v in ?v ref l) + v ref l 254/128 (v in ?v ref l) + v ref l 255/128 (v in ?v ref l) + v ref l a 0 lsb a 1 a 2 a 3 msb a 3 a 2 a 1 a 0 dac updated first 0 0 0 0 0 0 0 0 1 1 . . 1 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 . . . 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 . . 1 0 0 1 1 0 0 1 1 0 0 . . 1 0 1 0 1 0 1 0 1 0 1 . . 1 no operation daca dacb dacc dacd dace dacf dacg dach no operation . . no operation . . . . . . . . .
283 tiple dac applications without additional external decoding logic. the SP9841/9842 consume only 65 mw from a single +5v power supply. the SP9841 is available in 24-pin plastic dip and soic packages. the sp9842 is available in a spaceCsaving 20Cpin soic package. for applications requiring codeCcontrolled output polarity reversal regardless of the reference input level (i.e. fourCquadrant multiplication), please see the sp9840/sp9843 product data sheet. using the SP9841/9842 theory of operation each of the eight channels of the SP9841/sp9842 can be used for signal reconstruction, as a programmable dc source, or as a programmable gain/attenuation block, multiplying an ac reference input by factors of 0 to 1.992. the rugged, wideband output amplifiers provide both current sink and source capability for dc applications, even those driving difficult loads. the dc source mode mimics the functionality of a program- mable trimpot with the added benefit of a low imped- ance buffered output. the amplifier's bandwidth and high openCloop gain allow its use in programmable gain applications where even a low distortion, high resolution signal (such as audio) must be gated on and off or gainCcontrolled over a C42 to +6db range. each channel consists of a voltageCoutput dac, implemented using cmos switches and thinCfilm resistors in a inverted rC2r ladder configuration. each dac drives the positive terminal of an op amp + 8 dac 1 r r v in v dac v out v out = 2 x v dac when v ref l = 0v = 2(d/256) x v in = d/128 x v in v ref l v out = d/128 x (v in ?v ref l) +v ref l figure 1. dac and output amplifier circuit configured for a nonCinverting gain of 2 using equal value thinCfilm feedback and gainCsetting resistors. signal ground is the v refl pin, the common reference input return for the 8 dacCop amp channels. as shown in figure 1 , the dac section can be thought of as a potentiometer across v in (x) to v refl . when this potentiometer reaches its maximum output value of 255/256 times v in , the output will be 1+(r fb /r gain ) or 2 times the value of v dac (actually up to 1.9921875 times the input voltage, with v refl tied to ground). when the potentiometer is at its minimum value of 0/ 256, the output will try to be 0v, again assuming v refl is tied to ground. the true relation between the dc levels at the v in pin, v refl and the output can be described as: v out = ((1 + r fb /r g ) * (data/256) * (v in C v refl )) + v refl where data is programmable from 0 to 255, and r fb = r g . 2.5 1.5 0 v out(x) (volts) 0 0.5 1.5 v ref l= 0v v in(x) (volts) d = ff h d = 80 h d = 00 h 1.0 0.5 1.0 2.0 3.0 2.5 1.5 0 v out(x) (volts) 0.75 2.25 v ref l= 1.5v v in(x) (volts) d = ff h d = 80 h d = 00 h 1.5 0.5 1.0 2.0 3.0 figure 2. a) singleCquadrant, and b) twoCquadrant operation a) b)
284 when v refl is tied to ground, this expression reduces to: v out = (data/128) *v in multiplication of input voltages while both the SP9841 and sp9842 are capable of twoCquadrant multiplication, this terminology is not very precise when describing a system which runs from a single positive supply. traditionally, the quad- rants have been defined with respect to 0v. a twoC quadrant multiplying dac could produce negative output voltages only if a negative voltage reference were applied. a fourCquadrant device could also produce a codeCcontrolled negative output from a positive reference, or a codeCcontrolled positive out- put from a negative reference. if ground is used to delineate the quadrants, then the SP9841/sp9842 should be considered singleCquadrant multiplying devices, as their output op amps cannot produce voltages below ground. in reality, it is possible to define a dc voltage as a signal ground in a single supply system. if the dac's v refl pin is driven to the voltage chosen as pseudoground, then each voltage output will exhibit 2Cquadrant behavior with respect to pseudoground; that is the output voltage will enter the quadrant below the pseudoground only when the reference input voltage goes below pseudoground. this mode of operation is useful when implementing programmable gain/at- tenuator sections, especially when the input signal is bipolar with respect to pseudoground, or is acC coupled into the v in (x) pin. when v refl is tied to power supply ground, only output voltages greater than v refl are possible, and the device performs singleCquadrant multiplication, much like a buffered programmable trimpot across a single supply. fig- ures 2a and 2b show singleCquadrant and 2Cquadrant performance of the SP9841/sp9842 . applications which require 4Cquadrant operation with respect to pseudoground should use the sipex sp9840 or sp9843 4Cquadrant multiplying dacs. the choice of voltage to use for the pseudoground is limited by the legal voltage swing at the op amp output. the op amp exhibits excellent linearity for output voltages between, conservatively, 100mv and v dd C 1.5v. the op amp bicmos output stage consists of an npn follower loaded by an nmos common sourced to ground. this circuit exhibits wide bandwidth and can source large currents, while retaining the capability of driving the output to volt- ages close to ground. at output voltages below 25mv, feedback forces some op amp internal nodes toward the supply rails. the nmos pullCdown device gets driven hard and the nmos device enters the linear range it begins to function in the same manner as a 50 ohm resistor. in reality, the wideband amplifier output stage sinks some internal quiescent current even when driving the output towards ground. this sunk current drops across the output stage nmos transistor onCresis- tance and internal routing resistance to provide a minimum output voltage, below which the amplifier cannot drive. this minimum voltage is in the 15 to 25mv range. it varies within a package with each op amp's offset voltage and biasing varia- tions. if an input voltage lower than this mini- mum, such as code 0 or 1, when v refl is ground, 2.5 1.5 0 v in(x) (volts) v refl (volts) 0.5 1.0 2.0 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = 4.75v minimum; v outmax < +3.25v 2.5 1.5 0 v in(x) (volts) v refl (volts) 0.5 1.0 2.0 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = 4.75v minimum; v outmax >100mv a) b) figure 3. reference voltages a) normal operation; b) maximum linearity near code 1
285 is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. nonCsaturated monotonic behavior returns between 25mv and 100mv at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mv above the negative supply. applications which require good linearity for codes near zero should drive the v refl input at least 100mv above the ground pin, as this insures that the output voltage will not go below 100mv for any legal input voltage. twoCquadrant applications (programmable gain/attenuator) usually bias v refl up at system pseudoground, well above this saturation region, and therefore maintain linearity even at high attenuations (i.e. at code 1). the allowable, useful values of v in (x) and v refl are limited if a legal output value is to be expected for all input codes. at maximum gain (dac code 255) v out is approximately equal to 2v in (x) C v refl . by solving this equation twice, once with v out set to 0v, and then again with vout set to v dd C1.5v, the chart of figure 3a results. this chart can be used to find the maximal v in (x) voltage excursions for any given voltage driven into v refl . the upper line plots the maximum voltage at v in (x) and the lower line plots the mini- mum voltage at v in (x) at each value of v refl drive. normal operation would be for v in (x) anywhere between the two lines. for example, assume a 4.75v supply voltage, and that the dac code is set to 255. if v refl is driven to 1.6v, v in (x) below 0.8v would require the output amplifier to swing below ground. v in (x) above 2.425v would require output voltages greater than v dd C 1.5v, or 3.25v. figure 3b shows the limits on v in when the mini- mum v out is constrained to be greater than 100mv, for extremely linear operation, even at dac code 1. in this case, the lower line is 50mv above its position in figure 3a , except that below v refl = 100mv, the minimum input voltage stays at 100mv. it should be noted that v in (x) can always be driven to or slightly beyond the supply rails without harm. under such circumstances, the dac code can always be set to provide sufficient attenu- ation to get an undistorted output. driving the reference inputs the v in inputs exhibit a codeCdependent input resis- tance, as shown in the specifications. in general, these inputs should be driven by an amplifier capable of handling the specified load resistance and capaci- tance. the reference inputs are useful for both ac and dc input sources. however, series resistance into these pins will degrade the linearity of the dac. a series resistance of 50 ohms can cause up to 0.5lsb of additional integral linearity degradation for codes near full scale, due to the codeCdependent input current dropping across this error resistance. acC coupled applications should use the largest capacitor value (lowest series resistance) which is practical, or, use an external buffer to drive the inputs. the dac switches function in a breakCbeforeCmake manner in order to minimize current spikes at the reference inputs. as previously noted, the reference inputs can withstand driving voltages slightly beyond the power supply rails without harm. the gain of 2 at the op amps limits the choice of v in /v refl combina- tions if clipping is to be avoided at the higher codes. output considerations each dac output amplifier can easily drive 1kohm loads in parallel with 15pf at its rated slew rate. the unique bicmos amplifier design also ensures stabil- ity into heavily capacitive loads up to 47,000pf. under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance the slew rate will be severely degraded, and some damped ringing will occur. especially under heavy capacitive loading, a large, low imped- ance local bypass capacitor will be required. a 0.047 m f ceramic in parallel with a lowCesr 2.2 to 10 m f tantalum are recommended for worstCcase loads. the amplifier outputs can withstand momentary shorts to v dd or ground. continuous short circuit operation can result in thermally induced damage, and should be avoided. if the input reference voltage is reduced to 0.6v, then both the amplifier and dac are functional at room temperature at supply voltages as low as 2.5v. at v dd = 2.7v, power dissipation is 9.3mw typical, with the serial clock at 4mhz, or 7.0mw typical with the serial clock gated off. interfacing to the SP9841/sp9842 a simple serial interface, similar to that used in a 74hc594 shiftCregister with output latch, has been implemented in these products. a serial clock is used
286 figure 4. timing. characteristics (typical @ 25 c with v dd = +5v unless otherwise noted.) parameter min. typ. max. unit conditions input clock pulse width (t ch , t cl )50 ns data setup time (t ds )30 ns data hold time (t dh )20 ns clk to sdo propagation delay (t pd ) 100 ns dac register load pulse width (t ld )50 ns preset pulse width (t pr )50 ns clock edge to load time (t ckld )30 ns load edge to next clock edge(t ldck )60 ns 1 0 a 3 a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 0 fs 0 sdi clock load v out 1 0 1 0 1 0 (ff h ) (08 h ) serial data in serial data input timing detail (preset = logic "1"; v in(x) = 1.5v; v ref l = 0v) 1 0 serial data out clock load v out t ds t ch t cl t ld t s t ldck ? lsb error band t clkd t pd t dh a x or d x 1 0 preset t s t pr ? lsb error band (ff h ) (08 h ) v out table 2. logic control input truth table. sdi clk loadh presetl logic operation x l l h no change data l h shift in one bit from sdi shift out 12Cclock delayed data at sdo x x x l all dac registers preset to 80 h (note 1) x l h h load serial register data into dac(x) register note 1: "preset" may not persist at all dacs if loadh is high when presetl returns high.
287 to strobe serial data into a 12Cstage shiftCregister at each rising clock edge. the first four serial bits contain the address of the dac to be updated, msb first. the next 8 bits contain the binary value to be loaded into the desired dac, again msb first. after the 12th serial bit is clocked in, the loadh line can be strobed to latch the 8 bits of data into the data holding register for the desired dac. the address bits feed a decoding network which steers the loadh pulse to the clock input of the desired dac data holding register. the output of the 12th shiftCregister is also buffered and brought out as the serial data out (sdo), which can be used to cascade multiple devices, or for data verification purposes. the address field is set up such that dac a is addressed at 0001 (binary). address 0000(binary) will not affect the operation of any channel, as this combination is easily generated inadvertently at powerCup. other noCoperation addresses exist at 1001(binary) through 1111(binary). another use for noCoperation addresses is to mask off updates of any dac channel in a multipleCpart system with cas- caded serial inputs and outputs. by sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the loadh pin at each part in parallel from a single source. table 1 shows a registerClevel diagram of the addresses, data, and the resulting operation. a fourth control pin, presetl, can be used to simultaneously preset all dac data holding registers to their midCscale (80 h ) values. this will asynchro- nously force all dac outputs to buffer the voltages at their respective inputs to their outputs with unity gain. this feature is useful at powerCup, as a simple resistor to the supply and capacitor to ground can insure that all dac outputs start at a known voltage. it can also be used to implement stand-alone (nonCprogrammed) applications, such as a unity gain octal cable driver. table 2 summarizes the operation of the four digital control inputs. the four digital control input pins have been designed to accept ttl (0.8v to 2.0v minimum) or full 5v cmos input levels. timing information is shown in figure 4 . serial data is fully clocked into the shiftCregister after 12 clock rising edges, subject to the described setup and hold times. after the shiftCregister data is valid, the loadh line can be pulsed high to load data into the desired dac data register, which switches the dac to the new input code. the serial clock input should not see a rising edge while the loadh pulse is high in order to prevent shiftCregister data from corrup- tion during data register loading. the serial clock and data input pins are designed to be compatible as slaves under national semiconductor 's microwire? and microwireplus? protocols and under motorola 's spi? and qspi? protocols. in some microCcontrollers, the interface is completed by programming a bit in a generalCpurpose i/o port as a level, used to strobe the loadh line at the dacs. this is done in a manner similar to that used for generating a cs signal, which is necessary when driving some other microwire? peripherals. low voltage operation at nominal v dd , the cmos switches used in the dac obtain sufficient drive to maintain an on- resistance much lower than the thinCfilm resistors. this keeps the nonClinear voltageCdependent portion of their on-resistances low, and guarantees both excellent dac linearity versus code, and lowCdistor- tion multiplication of largeCswinging ac inputs. the devices in the op amp also receive sufficient drive to guarantee the specified bandwidth and output drive current. however, all circuits within the dacs are quite "functional" at very low values of v dd . by reducing the reference voltages such that the maxi- mum v out is near the target of v dd -1.5v, the dacs will provide better than 0.5lsb typical integral per- formance for dc output voltages between 100mv and v dd -1.5v. reducing the reference voltage actu- ally aids the linearity of the dacs, even at nominal v dd . this occurs because the nmos half of the cmos switches are more fully utilized at reference voltages closer to ground, thus further reducing the onCresistance of the switches. reference input cur- rents are proportional to the reference voltages and will also decrease with the reference voltages. plot 19 shows typical dc output linearity for v in (x) set to 0.5v, with v dd at 2.5, and then 3.5v. note that at 3.5v, the linearity is actually much better than the 0.25lsb typical performance at v in (x) = 1.625v and v dd = 5v. similarly, plot 20 shows that this performance level persists for v dd = 4.5v and 5.5v, with v in (x) set to 0.6v. the price paid for low voltage operation is in op amp gain, bandwidth and esC pecially current sinking at the dac output. plots 17
288 through 19 show that for lower output current values less than 1 ma, the SP9841/9842 can be used effec- tively even with v dd in the range of 2.7 to 3.3v. application circuits figure 5 shows an inexpensive singleCquadrant dc source for generating voltages from near ground to near 2.44v. when using a twoCtermi- nal reference, the pullCup resistor should be chosen so that the minimum input resistance of 5kohms at each v in (x) can be driven at the lowest expected v dd . at v dd = 4.75v, and v refl = 1.25v, each input to be driven needs 0.248ma, and the regulator needs 0.1ma to stay well regulated. thus, to drive all eight inputs, r pullup should be chosen to supply at least 2ma. to operate at 4.75v, 1.75kohms is required; the 1.5kohms shown will suffice even if its value is 5% high. to drive a single input, a 10kohm value could be used. in order to reduce reference and supply generated noise, an optional capaci- tor of 1 to 100 m f bypasses the reference. figure 6 shows a circuit which generates dc voltages roughly symmetric with respect to 2.446v. two bandgap references are stacked to first drive v refl to 1.223v, and the input to 2.446v. the pullCup resistor value should again be scaled for worstCcase loading in order to drive all eight inputs at 4.75v, a value of 620 ohms is required. at fullscale, the dac output is near 3.65v. while typical units will source 5ma at an output voltage figure 5. inexpensive dc source. + dc out 1/8 of SP9841 3 +5v 1.22v dc out = 20mv to +2.44v for data = 00 h to ff h . at preset, dc out = +1.22v r pullup 1.5kohms icl8069 45?* (*optional noise reduction) figure 6. pseudo bipolar source generates voltages above and below 2.44v. + dc out 1/8 of SP9841 3 +5v 1.22v dc out = +1.22v to +3.66v for data = 00 h to ff h . at preset, dc out = +2.44v 2kohm icl8069 1.22v icl8069 +1.22v +2.44v 45?* (*optional noise reduction) 45?*
289 figure 7. generating programmable dc voltages. + dc out 1/8 of SP9841 3 icl8069 + op?0 1.22v r1 10k w r2 4.75k w +1.8v dc out = 20mv to +3.6v for data = 00 h to ff h . at preset, dc out = +1.8v + r3 1.2k w 45?* (*optional noise reduction) v i figure 8 shows a nonCprogrammed standalone appli- cation. by tying presetl to ground, all channels are permanently set to unity gain. while preset, the input impedance at each input is set to 40kohms nominal (20kohms minimum), which minimizes required input current drive. the tl431 reference is pro- grammed by resistors r 1 and r 2 for 3.3v. r 3 is chosen to provide at least 165 m a for each input driven, plus 0.5ma for the reference at the minimum supply value to be considered. in the figure , the 560 ohms shown will drive all eight inputs. the excellent capacitive load capability of the output amplifiers handles any value of capacitive bypass loads without oscillation; however, to minimize ringing at powerup, load ca- pacitance can be chosen to be greater than 0.1 m f or less than 1,000pf. of 3.75v while running from a 4.75v supply, this behavior is not tested in device production. if maximum linearity is required near the 3.66v fullscale voltage, then output loading should be kept under 1ma. figure 7 uses a 1.8v reference to provide an output voltage range from near ground to almost 3.6v. the external micropower reference uses a bandgap in a bootstrapped configuration, which guarantees excellent supply rejection. voltage at v 1 is set by 1.223 r2 (r1 r2) * + ? ? ? v out is 1.223v +v 1 . r 3 is used to set the quies- cent current through the bandgap, i=v 1 /r 3 . the op amp will easily drive one to all eight inputs. figure 8. generating up to eight (8) 3.3v @ 10ma dc supplies with logicClevel controlled shutdown (nonCprogrammed). + dc out 1/8 of SP9841 preset eight independent 3.3v @ 10ma supplies with logic?evel controlled shutdown. 32k w +5v + 2.5v 100k w tl431 560 w ac04 dig in dig in dc out 0 1 3.3v 0v
290 figure 9 shows a dac channel controlling the output voltage of an lm317 voltage regulator. by program- ming the code, the dac changes its own supply voltage. this circuit can be modified for wider output voltage ranges by reducing the value of r 4 . however, the circuit as shown requires the dac to sink 1ma to the negative rail at code 0 at its lowest v dd , at which point the output voltage is 62mv. thus, programming codes 0 through 5 will do little to influence the output. if r 4 is replaced with a short circuit, useful operation would be between 3.9v and 6.15v output; however, the dac output must then sink 2.5ma at v dd = 3.9v, which results in a minimum dac output voltage of figure 9. programmable 1amp power source. + v out 1/8 of SP9841 3 +12v icl8069 at preset, v out = 5.0v 10kohms r1 499ohms v a v out = 4.5v to 5.5v at 1amp for data = 00 h to ff h . lm317 10? in out adjust r2 1kohms r3 511ohms 1.22v v dd r4 681ohms around 150mv. codes above 17 will then provide equally spaced output voltage increments. figure 10 shows how the gain of an external nonC inverting op amp can be programmed. r f and r g are chosen for nominal gain. r trimrange is then ratioed to r f to provide the desired range of gain trim. a wide gain grange is achievable for example, with r f = 11kohms, r g = 1kohms and r trimrange = 2.74kohms, gain would be programmed linearly from 8 to just under 16. the opC491 shown in figure 10 is capable for figure 10. adjustable gain of external nonCinverting opamp circuit; v out = railCtoCrail. + sig out 1/8 of SP9841 3 1/4 of op?91 +5v set r trimrange for desired gain-trim range. for r trimrange = 20kohms: code 0, a v = +5.5 code 128, a v = +5.0 code 255, a v = +4.51 + r f 10kohms r trimrange 20kohms r ibias 50kohms v refl = up to v dd /2 (2.5v nominal for rail?o?ail output at sig out) 1v p-p 2.2? r gain 2.5kohms v refl a r r v f g f trimrange dr r =+ + - ? ? ? ? 1 1 128 , d = 0 to 255 +5v v dd
291 railCtoCrail output swing. in order to obtain this performance, v refl must be externally driven to v dd /2, perhaps by use of the circuit of figure 11 . at v refl near 2.5v and v dd = 4.75v, the typical positive output headroom at the dac is limited to 1.15v above 2.5v, so that this circuit is useful for railCtoCrail outputs for gains higher than 4.35 (i.e. 1.15v pp maximum input). note that while an acCcoupled input is shown, this cir- cuit is just as useful for dcCcoupled inputs which are generated with respect to the v refl pseudoground voltage. r ibias is used for the acCcoupled circuit for opamp bias current re- turn when the dac is programmed to code 0, as no current flows into v in (x) at code 0. figure 11 shows a minimal parts count method figure 11. programmable, bootstrapped, 1.4v to 2.2v v refl drive. the usable range for the bootstrapped v refl circuit is 1.4 to 2.4v out at v dd = 5v, r isrc = 2kohms. to increase the upper usable limit, decrease value of r isrc . + v out a 1/8 of SP9841 3 icl8069 at preset, v out = 1.3v (not well?egulated) r isrc 2kohm load code 45?* 301ohm 1.22v + v refl v in a + 1/8 of SP9841 3 v in b *(optional noise reduction) +5v 112 for 1.4v out = v refl 96 for 1.6v out = v refl 70 for 2.2v out = v refl v out b + 1/8 of SP9841 3 v in h v out h
292 of generating a programmable pseudoground voltage at the v refl terminal. a pseudoground is very useful if any channels are to be used in acC multiplying applications. in such applications, the pseudoground will set the dc offset of the output signal. the voltage output of this circuit as the code is decreased is nonClinear because the dac bootstraps the increased output volt- age by a larger fraction at each code. it is really meant to be programmed only over a range of codes between 104 and perhaps 60. it does exhibit a fairly wellCdefined output, even if nonCintentional codes are programmed. for codes above 112, the output stage resembles a 50 ohm resistor to ground, and the v refl output will be near 1.3v, depending upon the loading at the other v in (x) inputs. for codes below 60, the output voltage will continue to rise until limited by available current through r isrc . note that r isrc supplies the actual current into v refl , and must be chosen in order to supply enough cur- rent for all channels, especially if any of the other eight inputs are to be grounded. a plot of v refl versus code is shown with the figure , for all other inputs either grounded or tied to the supply. figure 12 shows a programmable gain/attenua- tor section using the programmable vrefl drive. the vrefl of each dac is actually internally connected. when the optional 45 m f noise reduction capacitor is included, this cir- cuit is capable of 86db of snr and 74 to 84db of sinad at 1khz, depending on the pro- figure 12. acCcoupled, programmable gain/attenuator with bootstrapped programmable output dc offset (v refl drive). + v out a 1/8 of SP9841 3 icl8069 r isrc 2kohm load daca with code 90; sets v refl =1.7v. then, load dacb with desired gain: 45?* 301 w 1.22v + v refl v in a *(optional noise reduction) +5v code 255 = +6db code 128 = 0db code 64 = ?db code 1 = ?2db code 0 = ?0db + v out b 1/8 of SP9841 v refl v in b 2.2? ?.75v
293 grammed gain. please refer to the thd versus frequency plot, which was generated by termi- nating a 600 ohm source with 150 ohms to ground, then into this circuit. for the best gain linearity versus code, use the largest (lowest series impedance) coupling capacitor available, or externally buffer the input. figure 13 shows an external op amp with an inverting programmable gain. in this circuit the maximum output swing at the dac occurs at the maximum circuit gain. thus, the headroom re- striction at the dac output applies at the maxi- mum gain, which, for railCtoCrail outputs (v refl = 2.5v or v dd /2) should be greater than 4.3. by making the programmable gain range large, this circuit can be used to provide railCtoCrail out- puts even at the lower gains. this circuit has been ratioed to provide exact integer gain incre- ments for every increase in 25 codes, over the range of C1 to C11. this large range of gain comes at a slight cost the output offset of the dac amplifier will be gained up by C5.12 times at sig out. if this is a problem, a second dac channel can be set up with a programmable dc offset adjustment with its output summed through a large resistor into the opC491 inverting termi- nal. note that when rtrimrange is set up for only unity gain change range as in figure 12 , only C0.5 times the dac output offset will appear at sig out. another application for the circuits of both figure 10 and 13 could be to force precise gains from circuits made from imprecise resistors. by restricting the programmable gain range to 2% (by setting r trimrange to be 100 times r f ), the resistors could be 1% values and the program- mable gain resolution would increase to better than 12Cbits (0.0156%). in this case, only 1% of the dac output offset voltage would appear at sig out. figure 14 shows a window comparator and two channels of programmable-gain input. while the input signal is shown as acCcoupled, dc signals of up to railCtoCrail amplitude could be measured by setting the attenuation at the signal figure 13. adjustable gain of external inverting opamp circuit, v out = railCtoCrail. + sig out 1/8 of SP9841 3 1/4 of op?91 +5v set r trimrange for desired gain-trim range. for r trimrange = 1.5kohms: code 0, a v = -1 code 25, a v = -2 code 75, a v = -4 code 175, a v = -8 code 225, a v = -10 code 250, a v = -11 gain resolution = 4% + r f 7.68kohms r trimrange 1.5kohms v refl = up to v dd /2 1.25v p-p 2.2? r gain 7.68kohms v refl +5v v dd , d = 0 to 255 a r r v f g f trimrange dr r =- - ? ? ? ? ? ? ? ? 128
294 figure 14. twoCchannel multiplexed window comparator with programmable gain and limits. + 1/2 of SP9841 3 +5v 10k w + sig1 out + v lo compare + v hi compare sig2 out + + 1/2 of lm339 +5v 360 w "error" led ?.75v sig 2 any dc voltage 1.0? ?.75v sig 1 any dc voltage 1.0? + + op-290 v ref low = 1.67v 10k w 10k w v hi = 2.5v v low = 0.83v 2.5v muxed (or mixed!) signal v hi compare: 1.67v < v out < 3.33v for data = 0 h to ff h . at preset, v out = 2.5v v low compare: 1.67v < v out < 0v for data = 0 h to ff h . at preset, v out = 0.83v sig1 out : gain = 0 to 2x for ?.75v in 0.17v < v out < 3.17v at maximum gain for data = 0 h to ff h . at preset, gain = 1x. 499 w 499 w
295 input dacs to the proper code. the lm339 does not really drive the led to full illumina- tion, due to limited output current, but a pullCup resistor alone will yield a functional ttl error signal. external op amps could use the v refl voltage as pseudoground. the outputs of the two signal dacs must be isolated with resistors if the two signals are to be multiplexed. this will reduce the signal gain to 255/256 maximum, due to the resistive divider created at the com- parator input. if only a single channel was to be windowCcompared, then the maximum gain to the comparator would be the usual 255/128. figure 15 shows the schematic of an evaluation board, which can be used with an ibmCcompat- ible (xt or at) computer and the simple quickbasic routine of figure 16 to load each dac channel with its desired code. a straightC through 25-pin cable can be used, or the board can be plugged directly into the back of the pc. data is first latched into each 'hc165 parallelC toCserial converter. then a small state machine is initiated by strobing ini. it clocks the latched data into the serial data input and strobes the loadh input at the dac. a pair of banana jacks is used for applying v dd from an external supply. a trimpotCadjustable voltage reference is tied to all eight dac inputs. on the evaluation board, jumpers will allow this reference to drive any v in (x) input or the v refl pin. the other three op amps in the quad opC491 are available for breadboarding circuits, such as in figures 1 through 14 . if the reference voltage is adjusted down to 0.5v, the dac and the board should function with v dd as low as 2.5v. driving capacitive loads unlike many other products, the SP9841/9842 will not oscillate under purely capacitive load- ing. however, fullscale step outputs will show overshoot and ringing of up to 40% at worstC case purely capacitive loading (between 1,000 and 10,000pf). figures 17 through 20 show near fullscale steps under capacitive loads of between 470pf and 0.47 m f. for capacitance up to 10,000pf, the addition of a resistive load to ground at the op amp output will decrease set- tling times without adversely affecting the posi- tiveCgoing slew rate. for higher capacitances, this settling time enhancement comes at the expense of positive slew rate, as not all instan- taneous current can be used to charge the capaci- tor. for all values of capacitive load, settling time can be dramatically reduced by adding a small resistor in series with the dac outputs. such series resistors will degrade the current sinking ability at the dac outputs for voltages near ground; while the dacs typically sink 2ma at v dd =5v at v out = 110mv, the addition of a 50ohm resistor would require 210mv after the resistor to sink 2ma. large capacitances require lower values of series resistance in order to obtain critical damping.
296 figure 15. evaluation board loads SP9841/9842 from ibm pc parallel port p5v r1 49.9kohm c8 0.1? u7 1 mr 9 10 7 2 3 4 5 6 spe te pe clk p0 p1 p2 p3 q0 q1 q2 q3 14 13 12 11 tc 15 clk p5v u6b 6 5 1 4 3 2 qpr clk d q clr p5v clkn ctrl0 8 9 10 11 12 q pr clk d q clr 13 u6a 8 9 10 11 12 q pr clk d q clr 13 6 5 4 3 2 q pr clk d q clr 1 u3b u3a p5v 11 12 13 u4a p5v clk test points 1v out cv out d24 2v out bv in c23 3v out av in d22 4v in av dd 21 5v in b sdi 20 6 vrefl gnd 19 7 pre sdo 18 8v in e clk 17 9v in fld16 10 v out ev in h15 11 v out fv in g14 12 v out gv out h13 dacld SP9841 loadl pwrupl pwrupl c9 0.1? p5v gclk a1 14 13 12 11 1 2 3 4 outa u1, u2 ?74hc165 u3, u6 ?74fc74 u4 ?74hc02 u5 ?dale x0?38?.0, 8mhz oscillator u7 ?74hc161 u8 ?icl8069 a1 ?op?91 c1 ?c10 ?0.1? ceramic c11, c12 ?10?/30v c13 ?3pf j1 ?banana jack j2 -j4 ?0.5 inch jumpers s1 ?25-pin d connector (amp #747469?) r1 ?49.9k ohm r2 ?2kohm trimpot r3 ?1.5kohm r4 ?1.5kohm r5 ?3kohm r6, r7, r8 ?10kohm u5 out 8 14 gnd c5 0.1? p5v 7 u4b u4c u4d 5 6 2 3 1 9 8 10 clk clkn gclk dacld v dd 4 p5v 10? c11 j1 str d0 d1 d2 d3 d4 d5 d6 d7 alf ini gnd 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 14 16 18 sh/ld clk e f g h son gnd v dd clk-ih d c b a si so pc printer port s1 16 15 14 13 12 11 10 9 address addr msb addr2 addr1 addr lsb u1 1 2 3 4 5 6 7 8 sh/ld clk e f g h son gnd v dd clk-ih d c b a si so 16 15 14 13 12 11 10 9 u2 clkn v dd v dd data d0 d1 d2 d3 d4 d5 d6 d7 (msb) note: 1. all digital ic's bypassed with 0.1? to ground 2. three uncommitted op amps in the op?91 package are available for user applications. c12 10? r2 2kohm 10 5 9 6 8 7 c10 0.1? p5v p5v r3 1.5kohm r4 1.5kohm r5 3kohm c13 3pf r7 10kohm r8 10kohm r6 10kohm ina- ina+ v+ inb+ inb- outb outd ind- ind+ v- inc+ inc- outc u8 icl8069
297 figure 16. microsoft qbasic program to load evaluation board with desired codes. SP9841.bas 'this program accepts an address (1 through 8) and data (0 through 255) 'in decimal and sends them to the dac. addresses 1 through 8 will 'correspond to converters a through h respectively. the appropriate 'output will be: vout-(data/128)*vref volts. 'we found that for our ibm pc/at the lpt1 port address was 378h (data 'register 378h and control register 37ah) while for our ibm pc/xt the 'lpt1 port address was 3bch (data register #bch and control register 3beh). dim lsb as integer dim msb as integer dim datareg as integer dim contrlreg as integer dim n as integer cls do input "enter type of pc, at or xt: ", type$ in ucase$(type$) = "at" or ucase$(type$) = "xt" then exit do else print "please enter either at or xt.": print end if loop if ucase$(type$) = "at" then datareg = &h378: cntrlreg = &h37a if ucase$(type$) = "xt" then datareg = &h3bc: cntrlreg = &h3be cls n=0 do while n=0 do test$ ="" input "enter address (1 through 8): ", lsb if lsb < 1 or lsb> 8 then test$ = "false" if test$ = "false" then print "please enter a valid address.": print loop until test$ <> "false" do test$ = "" print input "enter data (0 through 255 in decimal): ", msb if msb < 0 or msb > 255 then test$ = "false" if test$ = "false" then print "please enter valid data.": print loop until test$ <> "false" out cntrlreg, $h3 'set both latch clocks low out datareg, &h0 + msb 'send most significant byte to port out cntrlreg, &h2 'clock u1 out datareg, &h0 + lsb 'send least significant byte to port out cntrlreg, &h0 'clock u2 out cntrlreg, &h4 'enable u7, set u1 & u2 to serial out mode print : print "strike spacebar to enter new data or q to quit." do x$ = inkey$ if ucase$(x$) = "q" then n=1 loop until x$ = " " or ucase$(x$) = "q" loop end
298 ordering information model reference inputs temperature range package SP9841kn ................................... eight, independent ................................................... 0 to + 70 c .............................. 24Cpin, 0.3" plastic dip SP9841ks ................................... eight, independent ................................................... 0 to + 70 c ........................................ 24Cpin, 0.3" soic sp9842ks ................................... four pair ................................................................... 0 to + 70 c ........................................ 20Cpin, 0.3" soic SP9841bn ................................... eight, independent ............................................... C40 to + 85 c .............................. 24Cpin plastic, 0.3" dip SP9841bs ................................... eight, independent ............................................... C40 to + 85 c ........................................ 24Cpin, 0.3" soic sp9842bs ................................... four pair ............................................................... C40 to + 85 c ........................................ 20Cpin, 0.3" soic

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