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d a t a sh eet objective speci?cation file under integrated circuits, icxx 2001 september 19 integrated circuits UAA3536HN low power gsm/dcs/pcs multi-band transceiver free datasheet http://www.datasheet-pdf.com/
2001 september 19 2 philips semiconductors objective specitcation low power gsm/dcs/pcs multi-band transceiver uaa3536 features multiple band application for gsm, dcs and pcs cellular phone systems compliant to gprs class 12 operation compliant to edge rx operation low noise and wide dynamic range low if receiver more than35db on chip image rejection in receive more than 84 db gain control range in receive integrated channel filter integrated tx filters high precision iq modulator multi-band tx modulation loop architecture including offset mixer and phase-frequency detector fully integrated fractional n rf synthesiser with afc control possibility fully integrated rf vco with integrated supply regulator semi integrated reference oscillator with integrated coarse afc possibility and with integrated supply regulator two outputs to control rf frontend switches (pin diodes) fully differential design minimizing cross-talk and spurs functional down to 2.4 v and up to 3.3 v 3-wire serial bus interface hvqfn40 package applications gsm 900 mhz, dcs 1800 mhz and pcs 1900 mhz hand-held transceivers. general description the uaa3536 integrates the receiver and most of the transmitter section of gsm, dcs and pcs hand-held transceiver. the receiver consists of two distinct parts. first, the rf receiver front-end which amplifies the gsm, dcs or pcs aerial signal, converts the chosen channel down to a low if of 100 khz, and provides in addition more than 35 db image suppression. the frontend gain is switchable by one 20db gain step. some selectivity is provided at this stage by an on-chip low-pass filter, and channel selectivity is provided by means of a high performance integrated band-pass filter. then, the if section further amplifies the wanted channel, performs gain control to tune the output level to the desired value and rejects dc. the if gain can be varied over a range of 68 db. the transmitter consists of a closed loop modulation architecture. the down converted feedback rf transmit signal is mixed with the iq modulation signals. in a phase frequency detector it is compared with the lo signal divided down to about 60 or 114 mhz and drives the charge pump for the external tx vco. the local oscillators (lo) signals required are provided by an on chip vco for operation of the rf section. the frequencies of the rf vco are set by an internal fractional n synthesiser pll circuit, which are programmable via a 3-wire serial bus. comparison frequency is 26 mhz (12 hz step programmability) derived from the 26 mhz reference signal which is generated with the semi integrated reference oscillator. the quadrature phase rf lo signals required for iq mixers in reception are generated internally. the reference oscillator can be without frequency control. in this case the precise receive and transmit frequencies have to be programmed via the fractional n synthesiser. a coarse afc control is possible via programmable switched capacitors. two outputs are available to control external rf frontend switches, e.g. used for band selection. free datasheet http://www.datasheet-pdf.com/
2001 september 19 3 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 the circuit can be powered-up into four different modes, rx, tx, syn or ref mode, depending on supply voltages applied, the logical level at pins rxon/txon/synon and the 3-wire bus serial programming. in rx (tx) mode, all sections required for receive (transmit) are turned on. the syn mode is used to power-up the synthesiser and the rf vco prior to the rx or tx mode. in the syn mode, some internal lo buffers are also powered-up such that vco pulling is minimized when switching on the receiver or the transmitter. the reference oscillator (ref mode) is turned on by applying the supply voltage. additionally band selection is done using the 3-wire bus serial programming allowing the proper enabling of the lnas and tx charge-pump current programming. ordering information block diagram type number package name description version UAA3536HN hvqfn40 plastic, heatsink very thin quad ?at package; 40 terminals; 6 6 0.85 mm sot618-1 fig.1 block diagram. quad pfd cp cp 3w bus ctl reg pwr en gnd gsmia gsmib v cc(rf) dcsia dcsib v cc(rfvco) rfcpo v cc(rfcp) txrfi txon refin en clk data qa qb ia ib txcpo v cc(txcp) extres v cc(if) v cc(syn) fracn pfd pcsia pcsib rftune clkfdbx clkout v cc(ref) 26mhz v cc(rflo) 60/114mhz div div quad synon rxon div vreg vreg fesw1 fesw2 feswon cafcsup :1/:2 free datasheet http://www.datasheet-pdf.com/
2001 september 19 4 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 pinning symbol pin description txrfi 1 input from rf transmit vcos extres 2 reference resistor for transmit modulation loop txcpo 3 transmit modulation loop charge-pump output v cc(txcp) 4 transmit modulation loop charge-pump supply txon 5 tx mode control pin ia 6 baseband input-output; i path ib 7 baseband input-output; i path qa 8 baseband input-output; q path qb 9 baseband input-output; q path v cc(if) 10 if supply clkout 11 reference oscillator output cafcsup 12 coarse afc memory supply clkfdbx 13 reference oscillator feedback refgnd 14 ground for reference oscillator refin 15 reference oscillator input v cc(ref) 16 reference oscillator supply data 17 3-wire bus; data input clk 18 3-wire bus; clock input en 19 3-wire bus; enable control pin v cc(rfcp) 20 rf charge-pump supply rfcpo 21 rf charge-pump output v cc(syn) 22 synthesizer supply rxon 23 rx mode control pin synon 24 syn mode control pin v cc(rfvco) 25 rf vco supply rftune 26 tuning input of rf vco gndtune 27 ground for rf vco tuning v cc(rflo) 28 rf lo supply fesw1 29 frontend switch control output fesw2 30 frontend switch control output v cc(rf) 31 rf front-end and transmit modulation loop supply gsmia 32 receiver gsm rf input gsmib 33 receiver gsm rf input rfgnd1 34 ground for rf frontend pcsia 35 receiver pcs rf input pcsib 36 receiver pcs rf input free datasheet http://www.datasheet-pdf.com/
2001 september 19 5 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 rfgnd2 37 ground for rf frontend dcsia 38 receiver dcs rf input dcsib 39 receiver dcs rf input feswon 40 frontend switch control input symbol pin description fig.2 pin configuration txcpo qa ib vcc(rflo) ia rfcpo txon vcc(ref) gsmib vcc(rf) gsmia fesw1 uaa3536 vcc(if) pcsib pcsia dcsib vcc(syn) data txrfi clkout vcc(rfcp) en dcsia cafcsup qb vcc(txcp) feswon extres clk clkfdbx refin vcc(rfvco) fesw2 rftune gndtune synon rxon gnd is supplied through the backside of the package rfgnd2 rfgnd1 refgnd free datasheet http://www.datasheet-pdf.com/
2001 september 19 6 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 functional description rf receiver the receiver front-end converts the aerial rf signal from egsm (925 - 960 mhz), dcs (1805 - 1880 mhz) or pcs (1930 - 1990 mhz) bands down to a low intermediate frequency (if) of 100 khz. the first stages are symmetrical low noise amplifiers (lnas) with one 20db gain step. they are matched to 50 w using external baluns. the lnas are followed by an i, q down-mixer. it consists of two mixers in parallel but driven by quadrature out of phase lo signals. the in phase (i) and quadrature phase (q) if signals are low pass filtered to provide protection from high frequency offset interferers. the low if i and q signals are then fed into the channel filter. channel ?lter and agc the front-end low if i and q outputs enter the integrated bandpass channel filter with provision for five 8 db gain steps in front of the filter. the filter is a self-calibrated fifth order band-pass filter centred around 100 khz and has a bandwidth of 240 khz for gsm mode, 300khz for edge mode. being filtered the low if i and q are further amplified with provision for ten 4 db gain steps and fully integrated dc offset compensation. realised with an active high pass circuit this compensation either operates continuously or keeps the acquired offset correction during the bursts depending on the programming. the low if output buffer provides close to rail-to-rail output signals. iq modulator i and q baseband signals are applied to the iq modulator that shifts the modulation spectrum up to the transmit if. it is designed for low harmonic distortion, low carrier leakage and high image rejection to keep the phase error as small as possible. the modulator is loaded at its if output by an integrated low pass filter that supress unwanted spurs prior to get into the phase detector. the clock drive is generated by division of the rflo signal provided for the transmit offset mixer. transmit modulation loop the analog transmit modulation loop is composed by an on-chip offset mixer with spur filter and by a phase/frequency detector with charge pump. the loop is closed off-chip by a loop filter and transmit vco. the analog pll copies the modulation to the off-chip transmit vco and acts as a tracking filter. a pll of at least third order is required to meet noise requirements at 20 mhz offset from carrier. the pll bandwidth must be greater than 700 khz in order to keep a low dynamic phase error and to minimize the acquisition time. the if frequencies used are about 60 mhz for gsm/pcs and about 114 mhz for dcs. rf vco the rf vco is fully integrated and self calibrating on manufacturing tolerances. it consists of 20 different frequency ranges that are selected internally depending on the frequency programming. it covers the necessary bandwidth of 1804 to 1991mhz and is tuned via the rf charge pump and the external loop filter. an internal supply voltage regulator using v cc(rflo) as input supplies the rf vco and minimises parasitic couplings and pushing. this regulator and the rf vco are turned on by the synon signal. the 20 different frequency ranges are realised by switching of varactors cathodes between gnd and an internal supply that is generated dynamically. due to slow discharge of this supply burst mode operation is possible only. for test purpose a fixed supply can be chosen. rf lo section the rf lo section covering the 1804 to 1991 mhz bandwidth is driven by the internal rf vco module. it includes the lo buffering for the rf pll, a divider by two or one for gsm and dcs/pcs respectively which drives a quadrature generation network to supply the rx iq down-mixer or it drives the transmit modulation loop offset mixer and the clock divider driving the iq modulator. free datasheet http://www.datasheet-pdf.com/
2001 september 19 7 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 rf fracn synthesiser pll a high performance rf fractional n synthesiser pll is included on chip which allows to synthesise the frequencies of the rf vco. very low close-in phase noise is achieved which allows to widen the pll loop bandwidth for shorter settling time. the programmable main dividers are controlled by a second order sd modulus controller. they divide the rf vco signal down to frequencies of 26 mhz (12 hz step programmability). their phase is then compared in a digital phase/frequency detector (pfd) to that of the 26 mhz reference clock signal. the phase error information is fed back to the vco via the charge pump circuit that sources into or sinks current from the loop filter capacitor, changing the vco frequency such that the loop gets finally phase locked. the charge pump output current is adapted internally to compensate for changes of rf vco gain so that the tolerance of the pll bandwidth is minimised. reference oscillator an amplifier is integrated to build a crystal oscillator. externally only a quartz and few passive components are needed. 26 mhz is the reference frequency. it is turned on when the supply voltage v cc(syn) is applied. after division by two a reference clock of 13mhz is supplied to the other parts of the system through the pin clkout. on request 26mhz can be made available on this pin. an internal supply voltage regulator using v cc(syn) as input supplies the reference oscillator and minimises parasitic couplings and pushing. afc can be done by the fracn synthesiser programming or via an external varactor. additionally a coarse afc control with a resolution of 8 bit is integrated via switchable capacitors. the programming of the coarse afc capacitors is maintained during sleep mode through supplying the register via pin cafcsup. an off chip capacitor is connected to cafcsup and is charged via an internal diode from pin v cc(ref) . furthermore instead of realising this semi-integrated oscillator a reference clock coming from an external module can be applied to pin refin. this module can be supplied through v cc(ref) pin. control of frontend switches two outputs are provided to drive rf switches of the phone, e.g. for switching between bands. power-up reset a power-up reset generates a reset pulse at power supply ramp-up to initialise digital functions. free datasheet http://www.datasheet-pdf.com/
2001 september 19 8 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 limiting values thermal characteristics dc characteristics v cc = 2.6v; v cc cp = 4.0 v; t amb =25 c; unless otherwise stated . symbol description min. max. unit t amb operating ambient temperature -30 +70 c t stg storage temperature -40 +150 c v cc supply voltages -0.3 3.6 v v cccp supply voltages for rx and tx charge pumps -0.3 4.25 v p max maximum power dissipation - 1 w symbol parameter value unit r th j-c thermal resistance from junction to case 25 k/w symbol parameter conditions min. typ. max. unit pins vcc(rf), vcc(if), vcc(rflo) and vcc(syn) v cc supply voltage note 1 2.4 - 3.3 v pin vcc(rfvco) v cc(rfvco ) internal supply voltage of rf vco output only 1.75 1.87 2 v pin vcc(ref) v cc(ref) internal supply voltage of reference oscillator output only; vcc(syn)>=2.6v; -30 c<=t amb <=70 c 2.3 - 2.5 v i outref source current to external vcc(syn) turned on 2 - - ma pin vcc(rfcp) v cc(rfcp) supply voltage of phase detector and charge pump 3.8 - 4.25 v pin vcc(txcp) v cc(txcp) supply voltage of phase detector and charge pump 2.6 - 4.25 v pins vcc(rf), vcc(if), vcc(rflo), vcc(syn), vcc(txcp) and vcc(rfcp) i ccpd supply current (v cc = 2.6 v; v cc cp = 4.0 v); normal mode power-down (total); vcc(syn)=0v; rxon, txon, synon and feswon = hi z; pins en, data, and clk = hi z -1030 m a i ccpd pres supply current (v cc = 2.6v, v cc cp = 4.0v); preset mode power-down (total); vcc(syn)=0v; rxon, txon, synon and feswon = 0; pins en, data and clk = 1 - 100 200 m a free datasheet http://www.datasheet-pdf.com/
2001 september 19 9 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 i ccref supply current ref mode reference oscillator active (synvcc=2.6v) - 4.6 5.3 ma i ccrx supply current rx mode rx and syn mode active; fesw off - 6982ma i cctx supply current tx mode tx and syn mode active; fesw off - 6987ma i cctxfesw supply current tx mode, fesw active tx and syn mode active; i fesw1 = 2ma; i fesw2 = 2ma - 7391ma i ccsyn supply current syn mode syn mode active - 40 46 ma pin vcc(rf) i ccrx supply current of rf receiver and rfquad (one lna only) rx mode active - 18 - ma i cclna supply current of one lna only rx mode active - 7.5 - ma i cctx supply current of transmit modulation loop (without charge pump) tx mode active - 14 - ma pin vcc(if) i ccrx supply current for iq low if bandpass ?lter rx mode active - 4 - ma i ccrx supply current iq agc and buffer rx mode active - 3 - ma i cctx supply current iq modulator path tx mode active - 10.5 - ma pin vcc(rflo) i ccrx supply current of rf vco, rf lo buffer and divider section syn mode active; rx mode active -24-ma i cctx supply current of rf vco, rf lo buffer and divider section syn mode active; tx mode active -28-ma i ccsyn supply current of rf vco and rf lo buffer syn mode active - 19 - ma pin vcc(syn) i ccref supply current of reference oscillator - 4.6 - ma i ccsyn supply current of reference oscillator and rf synthesizer syn mode active - 17 - ma symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 10 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes: 1. for vcc < 2.6v only functionality is guaranteed, ac characteristics are not guaranteed 2. these performances are measured and guaranteed on evaluation board. 3. rx mode: dc supplied from the ic tx mode: dc supplied from external 4. currents are supplied from open drain pmos transistors. pin vcc(rfcp) i cprf supply current rflo charge pump syn mode active; ext. resistor = 22.6 k w (1%); programmed to 0.52ma; in lock: during freq. acquisition: during precharge (for 32.5 m s after synth. turnon); note 2 -- 0.32 0.87 6 ma pin vcc(txcp) i cptx supply current tx charge pump tx mode active; ext. resistor = 22.6 k w (1%); txi1=1; txi2=1; in lock; during freq. acquisition; note 2 -- 0.9 2.45 ma pins ia, ib, qa and qb v iq common mode input-output iq voltage range (via + vib )/2or (vqa + vqb) / 2; note 3 1.15 1.25 1.35 v pin extres v extres reference voltage for i cp r ext =22.6k w (1%) 0.95 1.0 1.05 v pin cafcsup v cafcsup internal supply voltage synon=1 - vcc(ref) - pins fesw1, fesw2 (4) v fesw output voltage i source =10ma 2.3 - 2.5 v v fesw output voltage outputs in tri-state 0 - vcc(rf) logical input levels: pins en, data, clk, rxon, txon, synon, feswon v ih logical high level 0.9 - vcc(syn) + 0.3 v v il logical low level -0.3 - 0.3 v symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 11 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 ac characteristics v cc = 2.6v; v cc cp = 4.0 v; t amb = -30 to +70 c; unless otherwise stated rf receiver section measured in a 50 w impedance system, including external input baluns and matching networks to 50 w . symbol parameter conditions min. typ. max. unit pins gsmia and gsmib f rf rf input frequency range 925 - 960 mhz r in differential input resistance parallel rc input model - 110 - w c in differential input capacitance parallel rc input model - 1.0 - pf nf noise ?gure; max agc gain notes 1, 1 - 3.7 4.2 db nf lg noise ?gure; max agc gain; low lna gain hglg = 0; notes 1, 2 - 23 - db d g lna lna gain step hglg = 0 <-> 1 16 20 24 db g off lna off-state gain difference lna = 1 <-> 0; note 1 45 - - db p off lna off-state power handling lna = 0; note 1, 3 3 - - dbm pins dcsia and dcsib f rf rf input frequency range 1805 - 1880 mhz r in differential input resistance parallel rc input model - 170 - w c in differential input capacitance parallel rc input model - 0.8 - pf nf noise ?gure, max agc gain notes 1, 2 - 4.2 4.7 db nf lg noise ?gure; max agc gain; low lna gain hglg = 0; notes 1, 2 - 23 - db d g lna lna gain step hglg = 0 <-> 1 16 20 24 db g off lna off-state gain difference lna = 1 <-> 0; note 1 45 - - db p off lna off-state power handling lna = 0; notes 1, 3 6 - - dbm pins pcsia and pcsib f rf rf input frequency range 1930 - 1990 mhz r in differential input resistance parallel rc input model - 170 - w c in differential input capacitance parallel rc input model - 0.7 - pf nf noise ?gure, max agc gain notes 1, 2 - 4.4 4.9 db nf lg noise ?gure; max agc gain; low lna gain hglg = 0; notes 1, 2 - 23 - db d g lna lna gain step hglg = 0 <-> 1 16 20 24 db g off lna off-state gain difference lna = 1 <-> 0; note 1 45 - - db p off lna off-state power handling lna = 0; note 1, 3 6 - - dbm free datasheet http://www.datasheet-pdf.com/
2001 september 19 12 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 pins gsmia, gsmib, dcsia, dcsib, pcsia and pcsib s11 input power matching note 1 - -15 -10 db spur in spurious power level at rf input in 900 to 1000 mhz band, note1 - - -57 dbm in 1800 to 2000 mhz band, note 1 - - -47 dbm out of preceding bands, note 1 - - -45 dbm cp1 1 db input compression point; minimum agc gain t amb =25 c; hglg=1; note 1 -25 - - dbm cp1 lg 1 db input compression point; minimum agc gain t amb =25 c; hglg=0; note 1 -7 - - dbm ip3 input referred 3rd order intercept; maximum agc gain t amb =25 c; hglg=1; notes 1, 4 -18 - - dbm ip3 lg input referred 3rd order intercept; maximum agc gain t amb =25 c; hglg=0; notes 1, 4 0 - - dbm ip2 input referred 2nd order intercept; maximum agc gain t amb =25 c; hglg=1; notes 1,5 27 - - dbm ip2 lg input referred 2nd order intercept; maximum agc gain t amb =25 c; hglg=0; notes1, 5 40 - - dbm blocking c/n ratio at blocking t amb =25 c; d f = 3 mhz; gsm: p w = -101dbm; p int = -25dbm; note 1 dcs/pcs: p w = -101dbm; p int = -28dbm; note 1 8 8 - - - - db imrej image rejection d f if = 200 khz; t amb =25 c; note 1 35 38 - db d gvrf gain mismatch between operation of different bands note 1 - - 2 db pins ia, ib, qa and qb (rx mode) gv min voltage conversion gain agc gain set to min.; hglg=1; notes 1, 6 20 26 32 db gv max voltage conversion gain agc gain set to max.; hglg=1; notes 1, 6 90 94 98 db d gvbw gain difference between gsm and edge mode rxbw = 0 <-> 1 - 1.7 - db d gviq gain mismatch i and q paths - - 0.5 db gv step voltage conversion gain step note 6 - 4 - db agc lin gain control linearity t amb = 25 c; note 6, 7 -2 - 2 db over any 20 db gain range; note 7 -0.5 - 0.5 db symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 13 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes: 1. measured and guaranteed only on uaa3536 evaluation board. 2. this value excludes printed circuit board and balun losses. 3. no spurs are created as specified in spur in . 4. ip3 related to an im3 measurement with two tones at 800 and 1600khz offset. 5. ip2 related to an im2 measurement with two tones at 6 and 6.1mhz offset. 6. voltage gain defined as the differential baseband rms output voltage (either at pins ia and ib or pins qa and qb measured in standard load) divided by the rms input voltage at the rf baluns. 7. values are not applicable for hglg=0. 8. valid for following max. rf input power: hglg=1: -31 dbm; hglg=0: -15 dbm v out,lin linear output voltage per pin r l = 100 k w differential; c l =10pf differential; thd < 3%; note 8 0.75 - - v pk v out,max maximum output voltage per pin r l = 100 k w differential; - - vcc(if) / 2 v pk i out maximum output current per pin - - 2000 m a v offset differential output offset voltage in settled conditions -300 - +300 mv f hp,-3db - 3db high pass corner frequency (dc notch) fastsetl=0; stopsetl=0 468khz bw gsm - 3db low if ?lter bandwidth for gsm operation 100 khz center frequency gsm mode; rxbw=0 220 240 260 khz bw edge - 3db low if ?lter bandwidth for edge operation 100 khz center frequency edge mode; rxbw=1 275 300 325 khz dt gd group delay variation 30 khz < f out < 170 khz - 1.5 2 m s att gsm low if ?lter attenuation (5 th order) in gsm mode rxbw = 0 f out = 100 khz 200 khz 17 31 - db f out = 100 khz 400 khz 54 64 - db f out = 100 khz 600 khz 73 82 - db att edge low if ?lter attenuation (5 th order) in edge mode rxbw = 1 f out = 100 khz 200 khz 10 19 - db f out = 100 khz 400 khz 45 54 - db f out = 100 khz 600 khz 64 73 - db symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 14 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 transmit modulation loop section general conditions: v mod = 0.5 v pk ; f mod = 67.7 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit pins ia, ib, qa and qb (mode tx) f mod modulation frequency range 3 db low pass cutoff frequency 1 - - mhz v mod modulation level single ended; peak value - 0.5 0.55 vpk r in dynamic input resistance single ended - 14.4 - k w offset mixer: pin txrfi f rf rf input frequency range gsm dcs pcs 880 1710 1850 - - - 915 1785 1910 mhz r in single ended input resistance parallel rc input model 900mhz 1900mhz - - 65 35 - - w c in single ended input capacitance parallel rc input model 900mhz 1900mhz - - 3.4 2.0 - - pf p in input power -22 -19 -16 dbm cp1 1 db input compression point t amb =25 c - -22 - dbm spur in spurious power level at rf input lo leakage - -50 -45 dbm other - - -45 dbm v txrfi range of applied voltage -0.3 - vcc(rf) + 0.3 v phase detector: pin txcpo i cp charge pump maximum sink or source current r ext = 22.6 k w (1%); over v cp range; txi1 = 0; txi2=0; txi1 = 1; txi2=0; txi1 = 0; txi2=1; txi1 = 1; txi2=1 0.42 0.63 0.85 1.27 0.5 0.75 1 1.5 0.58 0.87 1.15 1.73 ma f txif txif frequency gsm/pcs dcs - - 60 114 - - mhz n txifdiv txif divider ratio gsm/dcs;ifdiv=0 pcs; ifdiv=1 -16 32 -- k f phase frequency detector gain -i cp /2 p - a/rad v cp charge pump output voltage 0.4 - v cccp - 0.4 v r out output resistance v out = v cccp / 2 100 - - k w r out(off) output resistance to ground when powered down tx mode disabled - 500 - w free datasheet http://www.datasheet-pdf.com/
2001 september 19 15 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes 1. measured and guaranteed only on uaa3536 evaluation board. 2. measured at external transmit vco output. 3. spur is not critical for pseudo random and application modulation spectrum. iq modulator; f mod =67.7khz f noise phase noise output power density t amb =25 c; d f = 400 khz; note 1, 2; gsm dcs, pcs - -122 -118 -120 -116 dbc/hz t amb =25 c; d f = 1.8 mhz; note 1, 2; gsm dcs,pcs - -126 -122 -123 -119 dbc/hz t amb =25 c; d f = 20 mhz; note 1, 2; gsm dcs/pcs -- -163 -157 dbc/hz lo out local oscillator feedthrough f = (f c + f mod ) +/- f mod ; note 1, 2 - -40 -32 dbc im out image level f = (f c + f mod ) +/ - 2 * f mod ; note 1, 2 - -45 -37 dbc spur4f m spurious level at 4 * f mod offset from wanted f = (f c + f mod ) +/ - 4 * f mod ; note 1, 2 - -55 -46 dbc spur16f m spurious level at 16 * f mod offset from wanted f = (f c + f mod ) +/ - 16 * f mod ; gsm, dcs; notes 1, 2, 3 - - -60 dbc spur32f m spurious level at 32 * f mod offset from wanted f = (f c + f mod ) +/ - 32 * f mod ; pcs; notes 1, 2, 3 - - -65 dbc spur other spurious level at other frequencies abs(f-(f c +f mod ))>=400khz note1, 2 - - -70 dbc symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 16 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 synthesizer and rf vco symbol parameter conditions min. typ. max. unit rf synthesizer; pin rfcpo f rflo synthesizer frequency range 1774.5 - 2047.5 mhz f comprf comparison frequency - 26 - mhz f steprf freq. step programmability f comp = 26 mhz - 12.4 - hz f noise close-in phase noise d f = 2 khz; note 1, 2 - -85 -82 dbc/hz p spur spur levels d f > 400khz - - -70 dbc i cp charge pump maximum sink or source current r ext = 22.6 k w (1%); over v cp range; currents set internally: for i cp = 310 m a for i cp = 380 m a for i cp = 420 m a for i cp = 520 m a for i cp = 540 m a for i cp = 650 m a for i cp = 660 m a for i cp = 800 m a 260 320 350 440 450 540 550 680 310 380 420 520 540 650 660 800 360 440 490 600 630 760 770 920 m a k f phase freq. detector gain - i cp /2 p - a/rad t prech loop ?lter precharge time after synon = 0 -> 1 - 32.5 - m s i leak charge pump leakage current in off state over full v cp range -1 - 1 m a v cp charge pump output voltage 0.4 - v cccp - 0.4 v r out(off) output resistance to ground when powered down syn mode disabled - 50 - w fractional n synthesiser n integer divider ratio f comp =26mhz 8 - 28 k fractional divider programming word f comp =26mhz 524,287 - 1,572,864 k frac fractional divider ratio f comp =26mhz 0.25 - 0.75 formulas for frequency calculation: ; ; integrated rf vco: pin rftune f rf rf frequency range 1804 - 1991 mhz g vco vco gain vtune=2.0v 15 20 25 mhz/v d g (vco*k f) vco gain times phase freq. detector gain variation d g (vco*k f) / g (vco*k f) -30 - 30 % r tune rftune series resistor inside the ic -50- w c tune parallel capacitor to ground inside the ic after r tune freq = 400khz; 0.4v; freq = 400 khz; 3.4v -20 17 -pf fvco () f comp n 128 + 2 -------------------- kfrac + ? ? = kfrac k 2 21 --------- - 1 2 22 --------- - + ? ? ? = free datasheet http://www.datasheet-pdf.com/
2001 september 19 17 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes 1. these performances are measured and guaranteed on evaluation board. 2. for measurement tx mode is activated and signal is taken from tx vco output. v tune tuning voltage range 0.4 - v cccp -0.4 v d f vcc,rflo pushing - - 2 mhz/v t vco,cal vco calibration time after synon = 0 -> 1 - 32.5 - m s symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 18 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 low noise crystal oscillator symbol parameter conditions min. typ. max. unit pins refin, clkfdbx f ref reference frequency - 26 - mhz r refin input resistance f=26 mhz - 2.6 - k w c refin input capacitance f=26 mhz - 0.7 - pf v refin intern. supplied dc input voltage 1.0 1.1 1.15 v r clkfdbx output resistance f=26 mhz; cafc0/.../7=0; f=26 mhz; cafc0/.../7=1 - - 800 900 - - w v clkfdbx dc output voltage 1.8 2.0 2.2 v v in(refin) input voltage level note 1 300 - - mv pp v clkfdbx limiting output voltage swing note 1 - 1700 - mv pp g v small signal voltage gain (refin, clkfdbx) f=2.6mhz; cafc0/.../7=0; pin < -42dbm; note 2 - 26.0 - db spur out spurious emission f = 2 * f ref , note 1 - -32 -20 dbc spurious emission non harmonics, note 1 - - -70 dbc d f vcc,ref pushing synvcc: 2.6v -> 3.3v - - 1 ppm coarse afc c cafc,lo clkfdbx output capacitance lo cafc0/.../7=0 17 19 21 pf c cafc,hi clkfdbx output capacitance hi cafc0/.../7=1 32 38 44 pf c cafc,lsb lsb for coarse afc capacitor cafc1/.../7 =0 cafc0 = 0 <-> 1 51 70 86 ff pin cafcsup i cafcsup leakage current v ccsyn = 0v; v cafcsup = 2.3v - - 100 na v store,cafc cafcsup storage voltage cafc bits remain stored 0.6 - - v pin clkout f clkout reference output frequency note 3 - 13 - mhz r clkout output resistance at dc output voltage - 130 - w v clkout dc output voltage note 1 synvcc - 1.8 synvcc - 1.6 synvcc - 1.4 v v clkout limiting output voltage swing notes 1, 3 0.75 1 1.15 vpp s clkout,pos positive slew rate between v dc - 100mv and v dc + 100mv; notes 1, 4 55 - - mv/ns s clkout,neg negative slew rate between v dc - 100mv and v dc + 100mv; notes 1, 4 - - -35 mv/ns d clkout duty cycle note 1 40 - 60 % f noise-bb phase noise at clkout d f = 2 khz, note 1 - - -105 dbc/hz jitter xo timing jitter at clkout notes 1, 4 -1 - 1 ns g reverse reverse isolation to pin clkfdbx; bw<100mhz; note 1 - - -20 db free datasheet http://www.datasheet-pdf.com/
2001 september 19 19 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes 1. these performances are measured and guaranteed on evaluation board. the 26 mhz quartz is outside the ic. c load, quartz =10pf 2. gain value is also valid for 26mhz not taking into account loading by c cafc and external capacitor. 3. 26 mhz reference output frequency is available on request. 4. c load,clkout = 20pf. d f ref, cafc residual frequency error after coarse afc alignment, t amb =25 c, quartz speci?ed with max. +/- 10ppm; note 1 -0.5 - 0.5 ppm d f/f (t) frequency stability as a function of temperature over full temperature range, quartz speci?ed with max. +/- 20ppm, note 1 -24 - 24 ppm d f/f (t) frequency stability as a function of time quartz speci?ed with +/- 1ppm, t amb =25 c, note 1 -1.2 - 1.2 ppm/y symbol parameter conditions min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
2001 september 19 20 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 timing speci?cations notes 1. these performances are measured and guaranteed on evaluation board. 2. rf vco self calibration needs to be activated for every frequency change. additionally the dynamically generated internal varactor supply discharges over time and needs recharging. for test purpose permanent varactor supply can be chosen by control bit varcpvcc. new self calibration and recharging are started with synon going from 0 to 1. 3. only valid after crystal oscillator has locked. 4. measured acc. gsm specification. 5. a new rxdc settling is provoked when changing agc bits g2, g3, g4, or g5. no change of rxdc settling will occur after changing agc bits g0 and g1. 6. for smartsetl=1 internally defined timings are chosen with settling mode sequences as shown in table below (timing reference is rxon going from 0 to 1). normal settling means that the active dc compensation is operating continuously with bandwidth as described in rf receiver section. stopsetl and fastsetl function is described in operating modes section. for smartsetl=0 the settling mode is defined by user programming of the bits fastsetl and stopsetl. symbol parameter conditions min. typ. max. unit t ref,on turn on time of reference oscillator settled to d f=0.1ppm of ?nal frequency, note 1 - - 8.6 ms t vco, reset vco calibration reset time synon=0; note 2 10 - - m s t vco,active active vco time vco remains locked; note 2 6 - - ms t syn,on turn on time of rf synthesiser settled to d f=0.1ppm of ?nal frequency; notes 1, 3, 4 -- 200 m s t rx,on rx dc settling time v(ia-ib) settled to 50mv from ?nal dc value; max. agc gain; smartsetl=0; stopsetl=0;fastsetl=0; notes 1, 5 - - 200 m s t rx, smart activation time of smart rx dc settling v(ia-ib) settled to 50mv from ?nal dc value; max. agc gain; smartsetl=1; fastsetl=1; notes 5, 6 161 - - m s d t syn-rx, smart delay for activation of smart rx dc settling smartsetl=1; fastsetl=1 40 - - m s t tx,on tx loop settling time setlled to d f=0.1ppm of ?nal value of f tx,out ; notes 1, 4 txi1=txi2=0 txi1=txi2=1 - - - - 150 80 m s smartsetl fastsetl stopsetl 0-40 m s 40-80 m s 80-120 m s 120-160 m s >160 m s 1 0 0 stopsetl normal normal normal normal 1 1 0 stopsetl fastsetl normal normal normal 1 0 1 stopsetl normal normal normal stopsetl 1 1 1 stopsetl fastsetl normal normal stopsetl 0 x x depending on user programming free datasheet http://www.datasheet-pdf.com/
2001 september 19 21 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 power supply concept three different voltage supplies are needed: 1. for the charge pump blocks: supply can be turned off in sleep mode. 2. for the reference oscillator (vccsyn) and other blocks: supply has to be turned off in sleep mode to turn off the reference oscillator. 3. for tx and rx signal path: supply can be turned off in sleep mode. the following power supply scheme is proposed: synon rxon txon synon rx timing relation tx timing relation t syn,on t rx,on t tx,on t syn,on fig.3 hardware control timing diagram t rx,smart user programmed settling smart settling burst active d t syn-rx,smart fig.4 power supply concept voltage multiplier v batt vccrf vccif vccrfcp vcctxcp bias bias vccsyn vccrflo vccrfvco vccref uaa3536 cafcsup linear regulator linear regulator free datasheet http://www.datasheet-pdf.com/
2001 september 19 22 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 operating modes basic operating mode the circuit can be powered up into different operating modes depending on the voltage level applied at pins rxon, txon, synon (hardware control) and supply voltage applied. the control bits synon, rxon, txon of the 3-wire bus must be set to logical high accordingly. this defines five main modes called idle, ref, syn, rx and tx mode. the operation mode status depends on the control pins synon, rxon, txon and v cc(syn) according to the table below. notes 1. the synthesiser includes the lo buffers common also to the receive and transmit sections. 2. when the receiver is on, it is possible to switch off the low noise amplifier. refer to receiver control described below. tx charge pump current status control the transmit modulation loop includes a transmit charge pump where sink and source currents are determined by an external resistor. there are four modes with different currents to cope with different transmit vco gains, e.g. between bands. the selection of these two modes is accomplished by means of the bit txi1 and txi2. the tx charge pump current status depends on the control bit txi according to the table below. txif ?lter status control the transmit section integrates two switchable low pass filters, one for about 60 mhz if and the other one for about 114 mhz if. the selection of these two modes is accomplished by means of the bit filt. the transmit filter status depends on the control bit filt according to the table below. mode synthesiser (1) (synon) receiver (2) (rxon) transmitter (txon) v cc(syn) idle off off off off ref off off off on syn on off off on rx on on off on tx on off on on txi1 bit status txi2 bit status mode of operation 00i txcp = 0.5ma 10i txcp = 0.75ma 01i txcp = 1ma 11i txcp = 1.5ma filt bit status mode of operation 0 60 mhz if 1 114 mhz if free datasheet http://www.datasheet-pdf.com/
2001 september 19 23 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 txif divider ratio status control the txif clock is generated by division of the lo signal of the tx offset mixer. the selection of the division ratios is accomplished by means of the bit ifdiv. the divider ratios depend on the control bit ifdiv according to the table below. transmit if clock i/q polarity control the polarity of the i/q signal for txif clock can be changed. the selection of these two modes is accomplished by means of the bit iqpol. the txif clock i/q polarity depends on the control bit iqpol according to the table below. frontend switch control there are two output pins fesw1 and fesw2 that can supply currents. they are controlled by means of the bits fesw1h, fesw2h, fesw1l and fesw2l combined with the hardware control pin feswon. this allows to program a changed state to the control register and activate it later on by changing the logic state at the control pin. the switch status depends on the control bits feswxx according to the table below. rx gain adjust +2db status control the rx gain can be adjusted by +2db by means of the bit gadjplus. the rx gain adjust +2db status depends on the control bit gadjplus acc. the table below. rx gain adjust -1db status control the rx gain can be adjusted by -1db by means of the bit gadjmin. the rx gain adjust -1db status depends on the control bit gadjmin acc. the table below. ifdiv bit status mode of operation 0 divide by 16 (gsm, dcs) 1 divide by 32 (pcs) iqpol bit status mode of operation 0 i signal 90 degree before q 1 q signal 90 degree before i feswxh bit status feswxl bit status feswon pin status status at feswx pin x 0 0 tri-state x 1 0 source current supplied 0 x 1 tri-state 1 x 1 source current supplied gadjplus bit status mode of operation 0 rx gain unchanged 1 rx gain increased by 2db gadjmin bit status mode of operation 0 rx gain unchanged 1 rx gain decreased by 1db free datasheet http://www.datasheet-pdf.com/
2001 september 19 24 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 lna gain control the lnas have a gain control to switch between a nominal and a low gain state. the low gain state can be used especially to ensure linear operation in case of high input levels with edge modulation. the lna gain status depends on the control bit hglg according to the table below. receiver power status control when the receiver is on, it is possible to switch off the low noise amplifier separately. separate control of the low noise amplifier is accomplished by mean of the bit lna. the lna status depends on the control bit lna according to the table below. sideband select status control the receiver includes an image rejection front end which allows the use of a rf lo 100 khz below the rf input frequency (infradyne) or 100 khz above the rf input frequency (supradyne), between these two states the proper image should be selected for rejection. the selection of these two modes is accomplished by mean of the bit sbd. the sideband status depends on the control bit sbd according to the table below. rxif ?lter bandwidth control the bandwidth of the rxif bandpass filter can be switched between 240 and 300khz. the larger bandwidth can especially be useful for cochannel performance under edge modulation. as for higher bandwidth (edge operation) the gain of the receive path is 2db lower compensation can be done with gadjplus control. the rxif filter bandpass filter bandwidth depends on the control bit rxbw according to the table below. hglg bit status mode of operation 0 low gain 1 high gain lna bit status power status of lna 0 off 1on sbd bit status mode of operation 0 supradyne 1 infradyne rxbw bit status mode of operation 0 240khz bandwidth 1 300khz bandwidth free datasheet http://www.datasheet-pdf.com/
2001 september 19 25 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 fast settling mode the rxif part contains an active dc compensation (dc notch) that needs significant settling time. to speed it up a fast settling mode is implemented with a higher bandwidth of the notch. in this mode dc settling of the receiver is achieved after max. 50 m s. afterwards it has to be set back again to normal settling to allow proper reception. the mode is controlled by the bit fastsetl. the fast settling mode is defined according to the table below. stop settling mode the active dc compensation (dc notch) of the rxif part can be switched to static dc compensation. after switching to stop settling the achieved differential offsets at the i/q output pins are kept and can have little drift through internal leakage. it is controlled by the bit stopsetl. the stop settling mode is defined according to the table below. notch remove mode the active dc compensation (notch) of the rxif part can be disconnected for test purpose. it is controlled by the bit ntchrem. this notch remove mode is defined according the table below. smart settling mode the settling of the rxif part can be switched to internal timing control. the available timing modes can be seen under timing specifications in the ic specification. internal timing is controlled by the bit smartsetl. the internal timing control can be selected acc. the table below. fastsetl bit status mode of operation bw of dc notch 0 normal settling 6khz 1 fast settling 24khz stopsetl bit status mode of operation 0 dc compensation dynamic 1 dc compensation static ntchrem bit status mode of operation 0 notch connected 1 notch disconnected smartsetl bit status mode of operation 0 internal timing not activated 1 internal timing activated free datasheet http://www.datasheet-pdf.com/
2001 september 19 26 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 band status control the receiver includes three rf front ends and their rf lo sections. for gsm the rf lo signal is divided by two. the selection of the different bands is accomplished by means of the bits bnd1/bnd2. the band status depends on the control bits bnd1/bnd2 according to the table below. coarse afc control the coarse afc capacitors of the reference oscillator are controlled via the binary weighted bits cafc0/1/2/3/4/5/6/7. their weight is defined according to the table below. rf vco varactor supply control for normal operation the cathodes of the switched varactors are connected to gnd or a dynamically generated internal supply voltage. for test purpose this internal supply voltage can be switched to v cc(rfcp) . this selection is accomplished by means of the bit varcpvcc. the varactor supply control status depends on the control bit varcpvcc according to the table below. bnd1 bit status bnd2 bit status mode of operation 1 0 gsm 0 1 dcs 1 1 pcs name of the bit value of the bit cafc0 lsb cafc7 msb varcpvcc bit status mode of operation 0 dynamic varactor supply 1 static varactor supply free datasheet http://www.datasheet-pdf.com/
2001 september 19 27 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 programming serial programming bus a simple 3-line unidirectional serial bus is used to program the circuit. the 3 lines are data, clk and en (enable). the data sent to the device is loaded in bursts framed by en. programming clock edges are ignored until en goes active low. the programmed information is loaded into the addressed latch when en returns inactive high. this is allowed when clk is in either state without causing any consequences to the register data. only the last 21 bits serially clocked into the device are retained within the programming register. additional leading bits are ignored, and no check is made on the number of clock pulses. the fully static cmos design uses virtually no current when the bus is inactive. it can always capture new programming data even during power-down of the synthesizer. data format data is entered with the most significant bit first. the leading bits make up the data field, while the trailing four bits are an address field. the address bits are decoded on the rising edge of en. this produces an internal load pulse to store the data in the addressed latch. to ensure that data is correctly loaded on first power-up, en should be held low and only taken high after having programmed an appropriate register. to avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. this condition is guaranteed by respecting a minimum en pulse width after data transfer. free datasheet http://www.datasheet-pdf.com/
2001 september 19 28 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 register bit allocation the fractional-n rf synthesiser is programmed through the integer bits rfn0 ... rfn5 and the fractional bits rfk0 ... rfk20 (see formula on page 15 ). x = dont care. first register allocation last bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address xvar cp vcc (0) 0 (vtune meas) 0 (chg cal1) 0 (chg cal2) 0 (rfcpi temp low) cafc 7 cafc 6 cafc 5 cafc 4 cafc 3 cafc 2 cafc 1 cafc 0 xxx 0101 rfk20 rfk19 rfk18 rfk17 rfk16 rfk15 rfk14 rfk13 rfk12 rfk11 rfk10 rfk9 rfk8 rfk7 0 (rfcp i2) 0 (rfcp i1) 0 (rfcp itest) 0100 rfk6 rfk5 rfk4 rfk3 rfk2 rfk1 rfk0 1 (rfk-1) rfn5 rfn4 rfn3 rfn2 rfn1 rfn0 bnd2 bnd1 syn on 0011 smar tsetl ntch rem stop setl fast setl rxbw sbd lna hglg g 5 g 4 g 3 g 2 g 1 g 0 1 (rxif on) 1 (rxrf on) rxon 0010 gadj min gadj plus xxfe sw2h fe sw1h xfe sw2l fe sw1l x x iqpol if div filt txi2 txi1 txon 0001 for test purpose only; all bits must be set to zeros for normal operation; this is forbidden adress 0000 for test purpose only; all bits must be set to zeros for normal operation; this is forbidden adress 0110 free datasheet http://www.datasheet-pdf.com/
2001 september 19 29 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 agc gain lookup table (hglg ?xed to 1); note 1 agc gain lookup table; note 1 hglg (4) g5 (3) g4 (3) g3 g2 g1 g0 attenuation from max gain (db) (2) 1111111 0 1111110 4 1111101 8 1111100 12 1101101 16 1101100 20 1011101 24 1011100 28 1010111 32 1010110 36 1000111 40 1000110 44 1001001 48 1001000 52 1000011 56 1000010 60 1000001 64 1000000 68 hglg (4) g5 (3) g4 (3) g3 g2 g1 g0 attenuation from max gain (db) (2) 1111111 0 1111110 4 1111101 8 1111100 12 1110111 16 1101100 20 1100111 24 1100110 28 1100101 32 1100100 36 1010101 40 1010100 44 1000101 48 0100101 52 0100100 56 0010101 60 free datasheet http://www.datasheet-pdf.com/
2001 september 19 30 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 notes 1. all codes not included in table are forbidden. 2. this is voltage gain attenuation for complete receiver. 3. steps in front of the bandpass filter. 4. step in the lna 0010100 64 0000101 68 0000100 72 0000011 76 0000010 80 0000001 84 0000000 88 hglg (4) g5 (3) g4 (3) g3 g2 g1 g0 attenuation from max gain (db) (2) free datasheet http://www.datasheet-pdf.com/
2001 september 19 31 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 register preset conditions the uaa3536 programming registers have a preset state. the preset values can be found in the following table. conditions for gu aranteed preset values at power on is as follow: data, clock, en and rxon, txon, synon, feswon must be at logic low level. preset value is guaranteed 288ms after synv cc rising to 90% of 2.6 v. frequency is preset for gsm receive, channel 62 (947.4mhz) agc is set to maximum gain. preset values notes 1. sv means stored values. all control bits that are used for coarse afc are stored in a memory during the sleep period of the phone and are recalled at turn on of v cc(syn) so that the reference oscillator restarts with the latest setting. the available storage time depends on the value of the external capacitor at pin cafcsup. first register allocation last bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address 000000svsvsvsvsvsvsvsv000 0101 01100010011101000 0100 10001001010001010 0011 00000011111111110 0010 00000000000100000 0001 for test purpose only; all bits are set to zero; this is forbidden address 0000 for test purpose only; all bits are set to zero; this is forbidden address 0110 free datasheet http://www.datasheet-pdf.com/
2001 september 19 32 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 serial bus timing characteristics v cc = 2.6 - 3.3v; t amb = -30 to +70 c ; unless otherwise speci?ed. symbol parameter min. typ. max. unit serial programming clock; pin clk t r , t f input rise and fall times - - 20 ns t cy clock period 67 - - ns t pu,hi clock pulse width high 30 - - ns t pu,lo clock pulse width low 30 - - ns enable programming; pin en t start delay to rising clock edge 200 - - ns t end delay from last falling clock edge 100 - - ns t w minimum inactive pulse width 400 - - ns t su;en enable set-up time to next clock edge 200 - - ns register serial input data; pin data t su;data input data to clock set-up time 25 - - ns t hd;data input data to clock hold time 25 - - ns fig.5 serial bus timing diagram. free datasheet http://www.datasheet-pdf.com/
2001 september 19 33 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 application information fig.6 application diagram bal bal bal gsmtx pcstx gsm/dcs/pcs gsmrx dcsrx pcsrx i i/o ib i/o q i/o qb i/o 26mhz crystal dcstx vcc vcp en clk data vcp vcc vcc rxon txon synon vcc feswon fesw1 clkout fesw2 quad pfd cp cp 3w bus ctl reg pwr en fracn pfd 26mhz 60/114mhz div div quad div vreg vreg :1/:2 resonator free datasheet http://www.datasheet-pdf.com/
2001 september 19 34 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 package outline 0.5 1.00 a 4 max. e h b unit y e references outline version european projection issue date iec jedec eiaj mm 6.05 5.95 d h 4.25 3.95 y 1 6.05 5.95 4.25 3.95 e 1 4.5 e 2 4.5 0.35 0.18 0.80 0.05 0.1 dimensions (mm are the original dimensions) sot618-1 mo-220 0.50 0.30 l 0.2 v 0.1 w 0 2.5 5 mm scale sot618-1 hvqfn40: plastic, heatsink very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm a max. a a 4 detail x y y 1 c e l e h d h e e 1 b 11 20 40 31 30 21 10 1 x d e c b a e 2 01-06-07 01-08-08 terminal 1 index area pin 1 index 1/2 e 1/2 e a c c b ? v m ? w m e (1) note 1. plastic or metal protrusions of 0.076 mm maximum per side are not included. d (1) free datasheet http://www.datasheet-pdf.com/
2001 september 19 35 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all hvqfn packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for hvqfn packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. free datasheet http://www.datasheet-pdf.com/
2001 september 19 36 philips semiconductors objective speci?cation low power gsm/dcs/pcs multi-band transceiver uaa3536 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. free datasheet http://www.datasheet-pdf.com/

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