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| ? 2009-2011 microchip technology inc. preliminary ds70590c mrf49xa data sheet ism band sub-ghz rf transceiver
ds70590c-page 2 preliminary ? 2009-2011 microchip technology inc. information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009-2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-846-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semico nductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection featur e may be a violation of the digi tal millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 3 mrf49xa features ? fully integrated sub-ghz transceiver ? supports proprietary sub-ghz wireless protocols ? 4-wire serial peripheral interface (spi) compatible interface ? cmos/ttl compatible i/os ? clock and reset signals for microcontroller ? integrated 10 mhz oscillator circuitry ? integrated low battery voltage detector ? supports power-saving modes ? operating voltage: 2.2v?3.8v ? low-current consumption, typically: - 11 ma in rx mode - 15 ma in tx mode -0.3 a in sleep mode ? industrial temperature range ? 16-pin tssop package rf/analog features ? supports ism band sub-ghz frequency ranges (433 mhz, 868 mhz and 915 mhz) ? modulation technique: fsk with frequency hopping spread spectrum (fhss) capability ? supports high data rates: - digital mode 115.2 kbps, max. - analog mode 256 kbps, max. ? differential rf input/output: - -110 dbm typical sensitivity with 0 dbm maximum input level - +7 dbm typical transmit output power ? high-resolution programmable phase-locked loop (pll) synthesizer ? integrated power amplifier ? integrated low phase noise voltage controlled oscillator (vco) frequency ? synthesizer and pll loop filter ? automatic frequency control (afc) baseband features ? supports programmable tx frequency deviation and rx baseband bandwidth (bbbw) ? analog and digital rssi outputs with dynamic range ? rx synchronous pattern recognition ? 16-bit rx data fifo ? two 8-bit tx data registers ? low-power duty cycle mode ? advanced adjacent channel rejection/blocking capability ? internal data and clock recovery ? supports data filtering ? data quality indicator (dqi) typical applications ? home/industrial automation ? remote control ? wireless pc peripherals ? remote keyless entry ? vehicle sensor monitoring ? telemetry ? data logging systems ? remote automatic meter reading ? security systems for home/industrial environment ? automobile immobilizers ? sports and performance monitoring ? wireless toy controls ? medical applications ism band sub-ghz rf transceiver mrf49xa ds70590c-page 4 preliminary ? 2009-2011 microchip technology inc. pin diagram: 16-pin tssop int /dio rssio v dd rfn rfp v ss reset rfxtl/extref sdi sck cs sdo irq fsk/data/fsel rclkout/fcap/fint clkout 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 mrf49xa ? 2009-2011 microchip technology inc. preliminary ds70590c-page 5 mrf49xa table of contents 1.0 introduction................................................................................................................ ................................................................... 7 2.0 hardware description........................................................................................................ ........................................................... 9 3.0 functional description...................................................................................................... .......................................................... 43 4.0 application details......................................................................................................... ............................................................. 73 5.0 electrical characteristics .................................................................................................. .......................................................... 79 6.0 packaging information....................................................................................................... ......................................................... 89 appendix a: read sequence and packet structures ................................................................................ .......................................... 93 appendix b: revision history................................................................................................... ............................................................ 95 the microchip web site ......................................................................................................... .............................................................. 99 customer change notification service ........................................................................................... ..................................................... 99 customer support ............................................................................................................... ................................................................. 99 reader response ................................................................................................................ .............................................................. 100 product identification system .................................................................................................. .......................................................... 101 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicat ions to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regard ing this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documen tation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and dat a sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. mrf49xa ds70590c-page 6 preliminary ? 2009-2011 microchip technology inc. notes: ? 2009-2011 microchip technology inc. preliminary ds70590c-page 7 mrf49xa 1.0 introduction microchip?s mrf49xa is a fully integrated sub-ghz rf transceiver. this low-power single chip frequency shift keying (fsk) baseband transceiver supports: ? zero-if architecture ? multi-channel and multi-band ? synthesizer with pll ? power amplifier (pa) ? low noise amplifier (lna) ? i/q down converter mixers ? i/q demodulator ? baseband filters (bbfs) and amplifiers the simplified functional block diagram of mrf49xa is shown in figure 1-1 . the mrf49xa is an ideal choice for low-cost, high-volume, low data rate (<256 kbps), two-way and short range wireless applications. this transceiver can be used in the unlicensed 433 mhz, 868 mhz and 915 mhz frequency bands, and for applications looking for fcc, ic or etsi certification in the ism band. the mrf49xa has a low phase noise and provides an excellent adjacent channel interference, bit error rate (ber) and larger commun ication coverage along with higher output power. the mrf49xa device?s afc feature allows for the use of a low-accuracy, low-cost crystal. in order to minimi ze the total system cost, a communication link in most of the applications can be created using a low-cost, generic 10 mhz crystal, a bypass filter and an affordable microcontroller. the mrf49xa provides a clock signal for the microcontroller and avoids the need for a second crystal on the circuit board. the transceiver can be interfaced with many popular microchip pic ? microcontrollers through a 4-wire spi, interrupt (iro ) and reset. the interface between the microcontroller and mrf49xa is shown in figure 1-2 . the mrf49xa supports the following digital data processing features: ? pll and i/q vco with calibration ? receiver signal st rength indicator ? data quality indicator ?afc ? baseband power amplifier ? tx and rx buffers the receiver?s baseband bandwidth (bbbw) can be programmed to accommodate various deviations, data rates and crystal tolerance requirements. the high-resolution pll allows: ? the usage of multiple channels in any of the bands ? the rapid settling time allows for faster frequency hopping, bypassing multipath fading and interference to achieve robust wireless links the transceiver is integrated with different sleep modes and an internal wake-up timer to reduce the overall current consumption, and to extend the battery life. the device?s small size with low-power consumption makes it ideal for various shor t range radio applications. mrf49xa ds70590c-page 8 preliminary ? 2009-2011 microchip technology inc. figure 1-1: functional node block diagram figure 1-2: microcontroller to mrf49xa interface matching circuitry antenna 10 mhz mcu interface rfp rfn mrf49xa power management memory pa/lna and pll/clk block rf block baseband amplifier/ filter/ limiter data processing unit spi signals other handshaking signals sdo sdi sck i/o i/o pic ? mcu sdi sdo sck i/o clkout* osc1 iro rclkout/fcap/fint* i/o mrf49xa * implies optional signals. cs __ int i/o/ss reset* int/dio* fsk/data/fsel* ? 2009-2011 microchip technology inc. preliminary ds70590c-page 9 mrf49xa 2.0 hardware description the mrf49xa is an integrated, single chip ism band sub-ghz transceiver. a simp lified architectural block diagram of the mrf49xa is shown in figure 2-1 . the frequency synthesizer is clocked by an external 10 mhz crystal and generates the 433, 868 and 915 mhz radio frequency. the receiver with a zero-if architecture consists of the following components: ?lna ? down conversion mixers ? channel filters ? baseband limiting amplifiers ? receiver signal strength indicator the transmitter with a direct conversion architecture has a typical output power of +7 dbm. an internal transmit/receive switch combines the transmitter and receiver circuits into differential rfp and rfn pins. these pins are connected to the impedance matching circuitry (balun) and to the external antenna connected to the device. the device operates in the low-voltage range of 2.2v? 3.8v, and in sleep mode, it oper ates at a very low-current state, typically 0.3 a. the quality of the data is checked or validated using the rssi and dqi blocks built into the transceiver. data is buffered in transmitter r egisters and receiver fifos. the afc feature allows the use of a low-accuracy and low-cost crystal. the clko ut is used to clock the external controller. the transceiver is controlled through a 4-wire spi, interrupt (int /dio and iro ), fsk/data/fsel , rclkout/fcap/fint and reset pins. see table 2-1 for pin details. the mrf49xa supports th e following feature blocks: ? clock generation ? data filtering and amplification ? data pattern recognition and timing ? data processing and storage ? independent transmit and receiver fifo buffers ? registers these features reduce the processing load, and hence, allows the use of low-cost 8-bit microcontrollers for data processing. mrf49xa ds70590c-page 10 preliminary ? 2009-2011 microchip technology inc. figure 2-1: mrf49xa archit ectural block diagram 8 pa/lna and pll/clk block baseband amplifier/filter/limiter block low-power block microcontroller interface block power supply block data processing block afc dqi comparator fifo data filtering and clock recovery unit i/q demod lbdb wutm with calibration osc clk rssi 1 3 2 4 10 5 16 14 11 9 15 self calibration pll and i/q vco with calibration mix mix 12 13 6 7 clk data sdi sck sdo fsk/data/ fsel rclkout/ fcap/fint clkout rssio v dd v ss rfp rfn rfxtl/ extref i q ____ clock block lna pa amp cal ckt amp cal ckt iro cs __ int/dio reset ? 2009-2011 microchip technology inc. preliminary ds70590c-page 11 mrf49xa table 2-1: pin description pin symbol type description 1 sdi digital input serial data input interface to mrf49xa (spi input signal). 2 sck digital input serial clock interface (spi clock). 3cs digital input serial interface chip select (spi chip/device select). 4 sdo digital output serial data output interface from mrf49xa (spi output signal). 5iro digital output interrupt request output: receiver generates an active-low interrupt request for the microcontroller on the following events: ? the txbreg (see table 2-4 ) is ready to receive the next byte. ? the rxfiforeg (see table 2-4 ) has received the preprogrammed amount of bits. ? rxfiforeg overfl ow/txbreg underrun. ? negative pulse on interrupt input pin (int ). ? wake-up timer time-out. ? supply voltage below the preprogrammed value is detected. ? power-on reset (por). 6 fsk/data/fsel digital input/output frequency shift keying: transmit fsk data input (with internal pull-up resistor of 133 k ). data: when configured as data, this pin functions as follows: ? data in: manually modulates the data from the external host microcontroller when the internal txbreg is dis- abled. if the txbreg is enabled, this pin can be tied ?high? or left unconnected. when reading the internal rxfiforeg, this pin must be pulled ?low?. ? data out: receives data in conjunction with rclkout when the internal fifo is not used. fifo select: selects the fifo and the first bit appears on the next clock when reading the rxfiforeg. the fsel pin has an internal pull-up resistor. this pin must be ?high? when the tx register is enabled. in order to achieve minimum current consumption, keep this pin ?high? in sleep mode. 7 rclkout/fcap/ fint digital input/output recovery clock output: provides the clock recovered from the incoming data if: ? ftype bit of bbfcreg (see ta b l e 2 - 1 0 ) is configured as digital filter and ? fifo is disabled by configuring fifoen bit of gencreg (see ta b l e 2 - 1 0 ) filter capacitor: this pin is a raw baseband data if the ftype bit of bbfcreg is conf igured as a configuration filter. the pin can be used by the host microcontroller for data recovery. fifo interrupt: when the internal fifo, fifoen bit of gencreg is enabled, this pin acts as a fifo full interrupt, indicating that the fifo has be en filled to its preprogrammed limit (see ffbc<3:0> bits in fiforstreg in ta b l e 2 - 1 0 ). 8 clkout digital output clock output: the transceiver?s clock output can be used by the host microcontroller as a clock source. refer register 2 for more details. mrf49xa ds70590c-page 12 preliminary ? 2009-2011 microchip technology inc. 9 rfxtl/extref analog input rf crystal: this pin is connected to a 10 mhz series crystal or to an external oscillator reference. the crystal is used as a reference for the pll which generates the local oscillator frequency. it is possible to ?pull? the crystal to the accurate frequency by changing the load capacitor value. external reference input: an external reference input, such as an oscillator, can be connected as a reference source. connect the oscillator through a 0.01 f capacitor. 10 reset digital input/output active- low hardware pin. this pin has an open-drain reset output with internal pull-up and input buffer. refer to section 3.1, reset for more details. 11 vss ground ground reference. 12 rfp rf input/output differential rf input/output (+). 13 rfn rf input/output differ ential rf inpu t/output (-). 14 v dd power rf power supply. bypass with a capacitor close to the pin. see section 2.1, power and ground pins for more details. 15 rssio analog input/output received signal streng th indicato r output: the analog rssi output is used to determi ne the signal strength. the response and settling time depends on the external filter capacitor. typically, a 4-10 nf capacitor provides optimum response time for most applications. 16 int /dio digital input/output interrupt: this pin can be configured as an active-low external interrupt to the device. if a logic ? 0 ? is applied to this pin, it causes the iro pin to toggle, signaling an interrupt to the external microcontroller. th e source of interrupt can be determined by reading the first four bits of stsreg (see ta b l e 2 - 4 ). this pin can be used to wake-up the device from sleep. data indicator output: this pin can be configured to indicate valid data based on the actual internal settings. table 2-1: pin description (continued) pin symbol type description ? 2009-2011 microchip technology inc. preliminary ds70590c-page 13 mrf49xa 2.1 power and ground pins the power supply bypassing is very essential for better handling of signal surges and noise in the power line. the large value decoupling capacitors should be placed at the pcb power input. the smaller value decoupling capacitors should be placed at every power point of the device and at bias points for the rf port. poor bypassing leads to conducted interference which can cause noise and spurious signals to couple into the rf sections, thereby si gnificantly reducing the performance. the v dd pin requires two bypass capacitors to ensure sufficient bypass and decoupling. however, based on the selected carrier frequency, the bypass capacitor values vary. the recomm ended bypass capacitor values are listed in table 2-2 and the type of capacitor to be used is listed in ta b l e 2 - 3 . the bypass capacitors are connected to pin 14, as shown in figure 4-1 . the trace length (v dd pin to bypass capacitors) should be made as short as possible. 2.2 reset pin an external hardware reset of mrf49xa can be performed by asserting the reset (pin 10) to low. after releasing the pin, it takes slightly more than 0.25 ms for the transceiver to be released from the reset. the pin is driven with an open-drain output, and hence, it is pulled down while the device is in por. the reset pin has an internal, weak, on-chip, pull-up resistor. the device will not accept commands during the reset period. the device enters the reset mode if any of the following events take place: ? power-on reset ? power glitch reset ? software reset ? reset pin software reset can be issued by sending the appropriate control command to the device. the result of the command is similar to por, but the duration of the reset event is much le ss, typically 0.25 ms. the software reset works only when the sensitive reset mode is selected. see section 3.1, reset for details on reset; for connection details, see figure 4-1 . 2.3 power amplifier the pa has an open-collector differential output and can directly drive different pcb antennas, like loop or dipole, with a programmable output power level during signal transmission. however, certain types of antennas, like monopole, need an additional matching circuitry. a built-in, automatic antenna tuning circuit is used to avoid the manual tuning and tri mming procedures during production process; the so called ?hand effect?. 2.4 low noise amplifier the lna has approximately 250 of differential input impedance which functions well with the proposed antenna (pcb/monopole) during signal transmission. the lna, when connected to the 50 device, needs an external matching circuit (balun) for correct matching and to minimize the noise figure of the receiver. the lna gain can be selected in four steps for different gain factors (between 0 db and -20 db relative to the highest gain) based on the required rf signal strength. this gain selection feature is useful in a noisy environment. table 2-2: recommended bypass capacitors value band (mhz) c1( f) c2 (nf) c3 (pf) 433 2.2 10 220 868 2.2 10 47 915 2.2 10 33 table 2-3: recommended bypass capacitors property c1 c2 c3 smd size a 0603 0603 dielectric tantalum ceramic ceramic mrf49xa ds70590c-page 14 preliminary ? 2009-2011 microchip technology inc. 2.5 rfxtl/extref and clkout pins the mrf49xa has an internal, integrated crystal oscillator circuit, and theref ore, a single rfxtl/extref pin is used as a crystal osc illator. the crystal oscillator circuit, with internal loading capacitors, provides a 10 mhz reference signal for the pll. the pll, in turn, generates the local oscillator frequency. it is possible to ?pull? the crystal to the ac curate frequency by changing the load capacitor value. this reduces the external component count and simplifie s the design. the crystal load capacitor is programmable from 8.5 pf?16 pf in 0.5 pf steps. thus, the crystal o scillator circuit can accept a wide range of crystals from different manufacturers with different load capacitance requirements. the ability to vary the load capacitance also helps in fine tuning the final carrier frequency as the crystal itself is the pll reference for the carrier. an external reference input, such as an oscillator, can be connected as a reference source. the oscillator can be connected through a 0.01 f capacitor. choosing better crystal results in a lesser tx to rx frequency offset and smaller deviation in bbbw. hence, the recommended crystal accuracy should be 40 ppm. deviation and bbbw are discussed in detail in section 2.8, baseband/data filters . the guidelines for selecting the appropriate crystal are explained in section 3.6, crystal selection guidelines . the transceiver can provide a clock signal through the clock output (clkout) pin to the microcontroller for accurate timing, and thus, eliminating the need for a second crystal. this also results in reducing the component count. 2.6 phase-locked loop the pll circuitry determines the operating frequency of the device. this programmable pll synthesizer requires only a single 10 mhz crystal reference source. the pll maintains accuracy using the on-chip crystal controlled reference oscillat or and provides maximum flexibility in performance to the designers. it is possible to change the crystal to the accurate frequency by changing the load capacitor value. the rf stability can be controlled by selecting a crystal with specifications which satisfy the application and by providing the functions required to gener ate the carriers, and by tuning each of the bands. for more details, see section 3.6, crystal selection guidelines . the pll?s high resolution allows the use of multiple channels in any of the bands. the on-chip pll is able to perform manual and automatic calibration to compensate for the changes in temperature or operating voltage. 2.7 automatic frequency control the pll in mrf49xa is capable of performing automatic fine adjustment for the carrier frequency by using an integrated afc feature. the receiver uses the afc feature to minimize the frequency offset between the tx/rx signals in discrete steps, which gives the advantage of: ? narrower receiver bandwidth for increased sensitivity can be achieved ? higher data rates can be achieved ? usability of any locally available, low-accuracy and inexpensive crystals can be used the mrf49xa can be programmed to automatically control the frequency or can be manually activated by a strobe signal. 2.8 baseband/data filters the bbfs are user-programmable. the receiver bandwidth can be set by programming the bandwidth of the bbfs. the receiver, when programmed, is set up according to the characteristics of the signal to be received. the baseband receiver has several programming options to optimize the communication for a variety of applications. the programmable functions are as follows: ? baseband analog filter ? baseband digital filter ? receive bandwidth ? receive data rate ? clock recovery the output data filtering can be performed using either an external capacitor or a di gital filter based on the user application. the rclko ut/fcap/fint pin in mrf49xa provides the raw baseband data if configured as a configuratio n filter. it can be used by the host microcontroller to perform the data recovery. 2.9 clock recovery circuit the clock recovery circuit (clkrc) is used to render a synchronized clock source to recover the data using an external microcontroller. the clkrc works by sampling the preamble on the received data. the preamble contains a sequence of 1 and 0 for the clkrc to properly extract the data timing. in slow mode, the clkrc requires more sampling (12?16 bits), and hence, has a longer settling time before locking. in fast mode, it uses less samples (6?8 bits) before locking, and thereby, the settling time is short which makes timing accu racy less critical. the rclkout/fcap/fint pin provides the clock recovered from the incoming data if the baseband filter is configured as a digital filter. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 15 mrf49xa 2.10 data validity blocks 2.10.1 receive signal strength indicator the mrf49xa provides the rssi signal to the host microcontroller, and hence, supports the monitoring of analog and digital signal strengths. a digital rssi output is provided to monitor the input signal level through an internal status register. the digital rssi goes high, if the received signal strength exceeds a given preprogrammed rssi threshol d level. the digital rssi can be monitored by reading the stsreg. alternatively, an analog rssi signal is also available at pin 15 (rssio) to determine the signal strength. the analog rssi settling time depends on the external filter capacitor. typically, a 4? 10 nf capacitor provides optimum response time for most of the applications. see section 4.0, application details and section 5.0, electrical characteristics for details on filter capacitors for analog rssi. the typical relationship between analog rssi voltage and rf input power is graphically represented in figure 2-2 . 2.10.2 data quality indicator the data quality indicator (dqi) is a special function which indicates the quality of the received signal and the link. the unfiltered received data is sampled and the number of spikes are counted in the received data for a specified time. if the input signals are of high value, it indicates the operating fsk transmitter of the high output signal within t he baseband filter bandwidth from the local oscillator. 2.10.3 data indicator output the data indicator output (d io) is an extension of dqi. the dio pin can be configured to indicate valid data based on the actual internal settings. when an incoming signal is detected, the dio uses the dqi clock recovery lock and digital rssi signals to determine the validity of the incoming signal. the dio searches for the valid data transitions at an expected data rate. the desired data rate and the acceptance criteria for valid data are user-programmable through the spi port. the dio signal is valid when using the internal receive fifo or an external pin to capture baseband data. the dio has three modes of operation: slow, medium and fast. each mode is dependent on the type of signals it uses to determine the valid data and the number of incoming preamble bits present at the beginning of the packet. the dio can be multiplexed with the int pin for external usage. figure 2-2: analog rssi voltage vs . rf input power 450 -100 -65 1150 analog rssi voltage (mv) input power (dbm) mrf49xa ds70590c-page 16 preliminary ? 2009-2011 microchip technology inc. 2.11 power-saving blocks 2.11.1 low battery voltage detector the integrated low-battery voltage detector circuit monitors the supply voltage against a preprogrammed value and generates an interrupt on the iro pin if it falls below the programmed threshold level. the detector circuit has a built-in 50 mv hysteresis. 2.11.2 wake-up timer the current consumption of the programmable wake-up timer is very low, typically 1.5 a. it is programmable from 1 ms to several days with an accuracy level of 10%. the calibration of the wake-up timer takes place at every start-up and every 30s thereafter, and is referenced with the crystal oscillator. the calibration is performed even in sleep mode. the calibration process for the wake-up timer takes around 500 s, and for proper calibration, the crystal oscillator must be running before the wake-up timer is enabled. if any wake-up event occurs, including the wake-up timer, the wake-up logic generates an interrupt signal on the iro pin which can be used to wake-up the microcontroller and this re duces the period that the microcontroller needs to be active. if the oscillator circuit is disabled, the calibration circuit turns it on for a brief period to perform the calibration in order to maintain accurate timing before returning to sleep. 2.11.3 low duty cycle mode the mrf49xa can be made to enter into a low duty cycle mode operation to decrease the average power consumption in receive mode. the low duty cycle mode is normally used in conjunction with the wake-up timer for its operation. the dcsreg may be configured so that when the wake-up timer brings the device out of sleep mode, the receiver is turned on for a short time to sample for a signal. then, the device returns to sleep and this process repeats. 2.12 int , iro pins and interrupts the interrupt pin (int ) can be configured as an active-low external interrupt to mrf49xa which is provided from the host microcontroller. the device generates an interrupt request for the host microcontroller by pulling the iro pin low if the following events occur: ? tx register is ready to receive the next byte ? rx fifo has received the preprogrammed amount of bits ? fifo overflow/tx register underrun (txurow overflow in receive mode and underrun in transmit mode) ? negative pulse on interrupt input pin, int ? wake-up timer time-out ? supply voltage below the preprogrammed value is detected ? power-on reset the status bits should be re ad out to identify the source of interrupt. the interrupts are cleared by reading the status register. see section 3.9, interrupts for functional description of interrupts. 2.13 transmit register the transmit register in mrf49xa is configured as two, 8-bit shift registers connected in series to form a single 16-bit shift register. when the transmitter is enabled, it starts sending out data from the first register with respect to the set bit rate. after power-up and with the transmit registers enabled, the transmitter preloads the tx la tch with 0xaaaa. this can be used to generate a preamble before sending actual data. in hardware, the fsk/data/fsel has two functions: ? as frequency shift keying pin, it basically takes care of transmitting the fsk data input. the pin has an internal pull-up resistor of 133 k ? . this pin must be ?high? when the tx register is enabled to take care of the transmission. ? as data (data out), this pin receives the data in conjunction with rclkout when the internal fifo is not used. when reading the internal rxfiforeg, this pin must be pulled ?low?. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 17 mrf49xa 2.14 receive fifo the received data in mrf49xa is filled into a 16-bit first in first out (fifo) register. the fifo is configured to generate an interrupt after receiving a defined number of bits. when the internal fifo is enabled, the fifo interrupt pin (rclkout/fcap/fint) acts as a fifo full interrupt, indicating that the fifo has been filled to its preprogrammed limit. the rece iver starts filling fifo with data when it identifies the synchronous pattern through the synchronous pa ttern recognition circuit. during this process, the fintdio bit changes its state. the fifo interrupt level is programmable from 1 to 16 bits. it is recommended to set the threshold to at least half the length of the register (8 bits) to ensure that the external host microcontrolle r has time to set up. the synchronous pattern recognition circuit prevents the fifo from being filled up with noise, and hence, avoids overloading the external host microcontroller. the fifo read clock (sck) must be < f xtal /4 or < 2.5 mhz for 10 mhz on rfxtal. the fsk/data/fsel as the fifo select pin, selects the fifo and the first bit appears on the next clock when reading the rxfiforeg. in hardware, the fsk/data/fsel pin is configured as data (data in) and with internal txbreg disabled; this manually modulates the da ta from the external host microcontroller. if the txbreg is enabled, this pin can be tied ?high? or can be left unconnected. the internal synchronous pattern and the pattern length are user-programmable. if the chip select (cs ) pin is low, the data bits on the sdi pin are shifted into the device on the rising edge of the clock on the sck pin.the serial interface is initialized if the cs signal is high. 2.15 serial peripheral interface the mrf49xa communica tes with the host microcontroller through a 4-wire spi port as a slave device. an spi compatible serial interface lets the user select, command and monitor the status of the mrf49xa through the host microcontroller. all registers consist of a command code, followed by a varying number of parameter or data bits. as the device uses word writes, the cs pin should be pulled low for 16 bits. data bits on the sdi pin are shifted into the device upon the rising edge of the clock on the sck pin whenever the cs pin is low. the maximum clock frequency for the spi bus is 20 mhz. the mrf49xa supports spi mode 0,0 which requires the sck to remain idle in a low state. the cs pin must be held low to enable communication between the host microcontroller and the mrf49xa. the device?s timing specification details are given in table 5-8 . data is received by the transceiv er through the sdi pin and is clocked on the rising edge of sck. the timing diagram is shown in figure 5-1 . mrf49xa sends out the data through the sdo pin and is clocked out on the falling edge of sck. the most significant bit (msb) is sent first (e.g., bit 15 for a 16-bit command) in any data. the por circuit sets default values in all control and command registers. the sdo pin defaults to a low state when the cs pin is high (the mrf49xa is not selected). this pin has a tri-state buffer and uses a bus hold logic. for the spi interface, see figure 4-1 . the following parameters can be programmed and set through spi: ? frequency band ? center frequency of the synthesizer ? division ratio for the microcontroller clock ? wake-up timer period ? bandwidth of the baseband signal path ? low supply voltage detector threshold any of these auxiliary functions can be disabled when not required. after power-on, all parameters are set to default values. the programmed values are retained during sleep mode. the interface supports the read out of a status register which provides detailed information about the status of the transceiver and the received data. note: the synchronous word is not accessible in the rx fifo. the synbreg provides this information to the host microcontroller. note: special care must be taken when the microcontroller?s built-in hardware serial port is used. if the port cannot be switched to a 16-bit mode, then a separate i/o line should be used to control the cs pin to ensure a low level during the complete duration of the communication (command) or a software serial control interface should be implemented. note: to test the spi interface lines, set the lbd (low battery detector) threshold below the actual v dd and the device must generate an interrupt. mrf49xa ds70590c-page 18 preliminary ? 2009-2011 microchip technology inc. 2.16 memory organization the memory in mrf49xa is implemented as static ram and is accessible through the spi port. each memory location functionally addresses a register, con- trol, status or data/fifo fields, as shown in table 2-10 . the command/control register s provide control, status and device address for transceiver operations. the fifos serve as temporary buffers for data transmission and reception. the commands to the device are sent serially. all 17 commands basically address the 17 registers affiliated to it. the registers consist of a command code, followed by control, data, status or parameter bits. the msb is sent first in all of the commands (e.g., bit 15 for a 16-bit command). the por circuit sets the default values in all control and command registers. in general, mrf49xa registers are read only. hence the chip status can only be read by the status read register. during write, only appropriate byte is written to the desired register. it is not desired to read/write all registers and there is no way to read back the register. table 2-4: control (comm and) register description si. no. register name register description related control functions 1 stsreg status read register receive register/fifo, transmit register, interrupt, frequency control and signal strength, por, wake-up timer, low battery detect, data quality, clock recovery 2 gencreg general configurati on register frequency band select, enables tx and rx registers, crystal load capacitor bank value 3 afccreg afc configuration register afc locking range, mode, accuracy and enable 4 txcreg transmit configuration register m odulation polarity, modulation bandwidth, transmit power and deviation 5 txbreg transmit byte register transmit data byte 6 cfsreg center frequency value set register transmit or receive frequency 7 rxcreg receive control register func tion of pin 16, dio mode, rx bbbw, lna gain, digital rssi threshold 8 bbfcreg baseband filter configuration regi ster clock recovery mode, data indicator parameter value and filter type 9 rxfiforeg receiver fifo read register receive data byte 10 fiforstreg fifo and reset mode configuration register fifo interrupt level, fifo start control and fifo enable, por sensitivity mode, synchronous character length 11 synbreg synchronous byte configuration register synchronous character pattern 12 drsreg data rate value set register data rate prescalar set 13 pmcreg power management configuration regi ster enables receive and transmit chain, baseband circuit, synthesizer circuit, oscillator, wake-up timer, low battery detect and clock out 14 wtsreg wake-up timer value set register wake-up timer values for time interval 15 dcsreg duty cycle value set register duty cycle mode and value 16 bcsreg battery threshold detect and clock output value set register low battery detect threshold values and clock output frequency 17 pllcreg pll configuration register clock out buffer speed, pll bandwidth, dithering and delay ? 2009-2011 microchip technology inc. preliminary ds70590c-page 19 mrf49xa 2.17 control ( command ) register details register 2-1: stsreg: status read register (por: 0x0000) (1) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 txrxfifo por txowrxof wutint lcexint lbtd fifoem atrssi bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dqdo clkrl afcct offsv offsb<3:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 txrxfifo: transmit register or receive fifo bit transmit mode: transmit register ready bit (2) indicates whether the transmit register is read y to receive the next byte for transmission. 1 = ready (5) 0 = not ready receive mode: receive fifo fill (interrupt) bit (2,3) indicates whether the rx fifo ha s reached the preprogrammed limit. 1 = reached the preprogrammed limit (5) 0 = programming limit has not been reached bit 14 por: power-on reset bit 1 = por has occurred (5) 0 = por has not occured bit 13 txowrxof: transmit overwrite receive overflow bit transmit mode: transmit register underrun or overwrite bit 1 = underrun or overwrite (5) 0 = operating normally receive mode : receive fifo overflow bit 1 = fifo overflow (5) 0 = operating normally bit 12 wutint: wake-up timer (interrupt) overflow bit 1 = timer overflow has occurred (5) 0 = operating normally bit 11 lcexint: logic change on external interrupt bit indicates a high-to-low logic level change on external interrupt pin (int /dio) (5) . 1 = high-to-low transition has occurred 0 = high-to-low transition has not occured note 1: all register commands begin with logic ? 1 ? and only the status register read command begins with logic ? 0 ?. 2: this bit is multiplexed for transmit or receive mode. 3: see the ffbc bits (fiforstreg<3:0>) in register 2-10 . 4: to get accurate values, the afc should be disabled during the read by clearing the fofen bit (afccreg<0>). the afc offset value (offsb bits in the status word) is represented as a two?s complement number. the actual frequency offset can be calculated as the afc offset value multiplied by the current pll frequency step from cfsreg (freqb<11:0>). 5: this bit is cleared after stsreg is read. mrf49xa ds70590c-page 20 preliminary ? 2009-2011 microchip technology inc. bit 10 lbtd: low battery threshold detect bit indicates whether the battery or supply voltage is below th e preprogrammed threshold limit. 1 = supply voltage is below threshold 0 = normal supply voltage feed bit 9 fifoem: fifo empty bit indicates whether the receiv e fifo is empty or filled. 1 = fifo is empty 0 = fifo is filled bit 8 atrssi: antenna tuning and received signal strength indicator bit transmit mode: the bit indicates that the antenna tuning ci rcuit has detected a strong rf signal. 1 = strong rf signal present 0 = weak or absence of rf signal receive mode: the bit indicates that the incoming rf signal is above the preprogrammed digital rssi limit. 1 = rf signal is above the threshold value set 0 = rf signal is less than the threshold value set bit 7 dqdo: data quality detect/indicate output bit indicates good data quality output. 1 = quality data is detected 0 = quality data is unavailable bit 6 clkrl: clock recovery lock bit indicates clock re covery is locked. 1 = clock recovery locked 0 = clock recovery unlocked bit 5 afcct: automatic frequency control cycle toggle bit for each afc cycle run, this bit toggles between logic ? 1 ? and logic ? 0 ?. 1 = afc cycle has occurred 0 = no afc in this cycle bit 4 offsv: offset sign value bit indicates the measured difference or frequency offset of any afc cycle (sign of the offset value). 1 = higher than the chip frequency 0 = lower than the chip frequency bit 3-0 offsb<3:0>: offset bits the offset value to be added to the frequency control parameter (internal pll) (4) . 1 = result is negative 0 = result is positive register 2-1: stsreg: status read register (por: 0x0000) (1) (continued) note 1: all register commands begin with logic ? 1 ? and only the status register read command begins with logic ? 0 ?. 2: this bit is multiplexed for transmit or receive mode. 3: see the ffbc bits (fiforstreg<3:0>) in register 2-10 . 4: to get accurate values, the afc should be disabled during the read by clearing the fofen bit (afccreg<0>). the afc offset value (offsb bits in the status word) is represented as a two?s complement number. the actual frequency offset can be calculated as the afc offset value multiplied by the current pll frequency step from cfsreg (freqb<11:0>). 5: this bit is cleared after stsreg is read. note: see appendix a: ?read sequence and packet structures? for the stsreg read sequence. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 21 mrf49xa register 2-2: gencreg: general conf iguration register (por: 0x8008) w-1 w-0 w-0 w-0 w-0 w-0 w-0 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-0 w-0 w-1 w-0 w-0 w-0 txden fifoen fbs<1:0> lcs<3:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 10000000b ) are serially sent to the microcon troller to identify the bits to be written in the gencreg. bit 7 txden: tx data register enable bit 1 = internal tx data register enabled (1) 0 = internal tx data register disabled; no transmit bit 6 fifoen: fifo enable bit 1 = internal data fifo enabled; the fifo is used to store data during receive (2) 0 = fifo disabled; fsk/data/fsel and rclkout/fcap/fint are used to receive data bit 5-4 fbs<1:0>: frequency band select bits these bits set the frequency band to be used in sub-ghz range. 11 = 915 mhz 10 = 868 mhz 01 = 433 mhz 00 = reserved bit 3-0 lcs<3:0>: load capacitance select bits these bits set and vary the internal lo ad capacitance for the crystal reference. 1111 = 16.0 pf 1110 = 15.5 pf 1101 = 15.0 pf 1100 = 14.5 pf 1011 = 14.0 pf 1010 = 13.5 pf 1001 = 13.0 pf 1000 = 12.5 pf 0111 = 12.0 pf 0110 = 11.5 pf 0101 = 11.0 pf 0100 = 10.5 pf 0011 = 10.0 pf 0010 = 9.5 pf 0001 = 9.0 pf 0000 = 8.5 pf note 1: if the internal tx data register is used, the data/fsk/fsel pin must be pulled ?high?. 2: if the data fifo is used, the data/fsk/fsel pin must be pulled ?low?. mrf49xa ds70590c-page 22 preliminary ? 2009-2011 microchip technology inc. register 2-3: afccreg: automatic freq uency control configuration register (por: 0xc4f7) w-1 w-1 w-0 w-0 w-0 w-1 w-0 w-0 ccb<15:8> bit 15 bit 8 w-1 w-1 w-1 w-1 w-0 w-1 w-1 w-1 automs<1:0> arfo<1:0> mfcs ham foren fofen bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11000100b ) are serially sent to the microcont roller to identify the bits to be written in the afccreg. bit 7-6 automs<1:0>: automatic mode select ion bits (for afc) these bits select the operation type (automatic/manual) for perfor ming afc based on the status of the mfcs bit. 11 = keeps offset independent for the state of the dio signal 10 = keeps offset only while receiving (dio = high) 01 = runs and measures only once after each power-up cycle 00 = auto mode off (controlled by microcontroller) bit 5-4 arfo<1:0>: allowable range for frequency offset bits these bits select the offset range allowable between transmitter and receiver frequencies. 11 = +3 f res to -4 f res (1) 10 = +7 f res to -8 f res 01 = +15 f res to -16 f res 00 = no restriction bit 3 mfcs: manual frequency control strobe bit this bit is the strobe signal which initiates the manual frequency control sample to calculate the offset error. 1 = a sample of a received signal is compared with a receiver local oscillator (lo) signal and an offset error is calculated. if bit 1 is enabled, the value is stored in the offset r egister of the afc block. (2) 0 = ready for the next sample bit 2 ham: high-accuracy (fine) mode bit (3) 1 = switches the frequency control mode to high-accuracy mode 0 = frequency control mode works in regular mode bit 1 foren: frequency offset register enable bit 1 = enables the offset value calculated by the offset sample. the offset value is added to the frequency control word of the pll which t unes the desired carrier frequency. 0 = denies the addition of the offset valu e to the frequency control word of the pll bit 0 fofen: frequency offset enable bit 1 = enables the frequency offset calculation using the afc circuit 0 = disables the frequency offset calculation using the afc circuit note 1: the f res is the frequency tuning resolution for each band. the f res for each band is as follows: 433 mhz = 2.5 khz 868 mhz = 5 khz 915 mhz = 7.5 khz 2: the offset error value is stored in the offset register (foren bit should be enabled) in the afc block and is added to the frequency control word of the pll. reset this bit before initiating another sample. 3: in high-accuracy (fine) mode, the processing time is t wice the regular mode, but the uncertainty of the measurement is significantly reduced. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 23 mrf49xa register 2-4: txcreg: transmit configuration register (por: 0x9800) w-1 w-0 w-0 w-1 w-1 w-0 w-0 w-0 ccb<15:9> modply bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 modbw<3:0> r otxpwr<2:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 ccb<15:9>: command code bits the command code bits ( 1001100b ) are serially sent to the microcont roller to identify the bits to be written in the txcreg. bit 8 modply: modulation polarity bit (for fsk) when modply is configured as high/low: 1 = logic ? 0 ? is the higher channel frequency and logic ? 1 ? is the lower channel frequency (negative deviation) 0 = logic ? 0 ? is the lower channel frequency and logic ? 1 ? is the higher channel frequency (positive deviation) bit 7-4 modbw<3:0>: modulation bandwidth bits these bits set the fsk frequency deviation for transmitting the logic ? 1 ? and logic ? 0 ? (1) . 1111 = 240 khz 1110 = 225 khz 1101 = 210 khz 1100 = 195 khz 1011 = 180 khz 1010 = 165 khz 1001 = 150 khz 1000 = 135 khz 0111 = 120 khz 0110 = 105 khz 0101 = 90 khz 0100 = 75 khz 0011 = 60 khz 0010 = 45 khz 0001 = 30 khz 0000 = 15 khz bit 3 reserved: write as ? 0 ? note 1: the transmitter fsk modulation parameters are used for calculating the resulting output frequency, as shown in equation 2-1 . 2: the output transmit power range is relative to the maximum available power, which depends on the actual antenna impedance. mrf49xa ds70590c-page 24 preliminary ? 2009-2011 microchip technology inc. equation 2-1: bit 2-0 otxpwr<2:0>: output transmit power range bits (2) these bits set the transmit output power range. the output power is programmable from 0 db (max.) to -17.5 db in -2.5 db steps. 111 = -17.5 db 110 = -15.0 db 101 = -12.5 db 100 = -10.5 db 011 = -7.5 db 010 = -5.0 db 001 = -2.5 db 000 = 0 db register 2-4: txcreg: transmit config uration register (por: 0x9800) (continued) note 1: the transmitter fsk modulation parameters are used for calculating the resulting output frequency, as shown in equation 2-1 . 2: the output transmit power range is relative to the maximum available power, which depends on the actual antenna impedance. f fskout = f 0 +[(? 1) sign x (mb + 1) x (15 khz)] where: f 0 is the channel center frequency (see register 2-6 for f 0 calculation) mb is the 4-bit binary number (modbw<3:0>) sign = modply xor fsk ? 2009-2011 microchip technology inc. preliminary ds70590c-page 25 mrf49xa register 2-5: txbreg: transmit byte register (por: 0xb8aa) w-1 w-0 w-1 w-1 w-1 w-0 w-0 w-0 ccb<15:8> bit 15 bit 8 w-1 w-0 w-1 w-0 w-1 w-0 w-1 w-0 txdb<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 10111000b ) are serially sent to the microcont roller to identify the bits to be written in the txbreg. bit 7-0 txdb<7:0>: transmit data byte bits the transmit data bits hold the 8 bits that are to be transmitted. to use this register, set the bit, txden = 1 (gencreg<7>). if txden is not set, use the fsk/data/fsel pin to manually modulate the data. mrf49xa ds70590c-page 26 preliminary ? 2009-2011 microchip technology inc. equation 2-2: register 2-6: cfsreg: center frequency value set register (por: 0xa680) w-1 w-0 w-1 w-0 w-0 w-1 w-1 w-0 ccb<15:12> freqb<11:8> bit 15 bit 8 w-1 w-0 w-0 w-0 w-0 w-0 w-0 w-0 freqb<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 ccb<15:12>: command code bits the command code bits ( 1010b ) are serially sent to the microcontro ller to identify the bits to be written in the cfsreg. bit 11-0 freqb<11:0>: center frequency set bits these bits set the center frequency to be used during transmit or receive. the 12-bit value (f val ) must be in a decimal range of 96 to 3903. the value outside this range results in the previous value being retained and used such that no frequency change occurs (1) . note 1: to calculate the center frequency (f0), use equation 2-2 and the values from ta b l e 2 - 5 . the cfsreg sets the frequency within the selected band for transm it or receive. each band has a range of frequencies available for changing channels or frequency hopping. the selectable frequencies for each band are given in ta b l e 2 - 6 . f 0 = 10 x fa1 x (fa0 + f val /4000) mhz where: f val = decimal value of freqb<11:0> = 96 < f val < 3903 where fa0 and fa1 are constant values as given in table 2-5 to calculate the center frequency. table 2-5: center frequency value range fa1 fa0 433 mhz 1 43 868 mhz 2 43 915 mhz 3 30 table 2-6: frequency band tuning resolution frequency band (mhz) mi n. (mhz) max. (mhz) tuni ng resolution (khz) 400 430.2400 439.7575 2.5 800 860.4800 879.5150 5.0 900 900.7200 929.2725 7.5 ? 2009-2011 microchip technology inc. preliminary ds70590c-page 27 mrf49xa register 2-7: rxcreg: receive co ntrol register (por: 0x9080) w-1 w-0 w-0 w-1 w-0 w-0 w-0 w-0 ccb<15:11> fintdio diort<1:0> bit 15 bit 8 w-1 w-0 w-0 w-0 w-0 w-0 w-0 w-0 rxbw<2:0> rxlna<1 :0> drssit<2:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 ccb<15:11>: command code bits the command code bits ( 10010b ) are serially sent to the microcontroller to identify the bits to be written in the rxcreg . bit 10 fintdio: function interrupt/data indicator output bit sets the pin 16 function as the dio or interrupt. 1 = dio output 0 = int input bit 9-8 diort<1:0>: data indicator output response time bits if pin 16 is selected as dio, these bits set the re sponse time within which the transceiver detects and indicates the incoming synchronous bit pattern, and issues an interrupt to the host microcontroller. 11 = continuous 10 = slow 01 = medium 00 = fast bit 7-5 rxbw<2:0>: receiver baseband bandwidth bits these bits set the bandwidth of demodulated da ta. the bandwidth can accommodate different data rates and deviations during frequency keying. 111 = reserved 110 = 67 khz 101 = 134 khz 100 = 200 khz 011 = 270 khz 010 = 340 khz 001 = 400 khz 000 = reserved bit 4-3 rxlna<1:0>: receiver lna gain bits these bits, when set to different values, can accommodate environments with high interferences. the lna gain also affects the true rssi value. 11 = -20 db 10 = -14 db 01 = -6 db 00 = 0 db mrf49xa ds70590c-page 28 preliminary ? 2009-2011 microchip technology inc. bit 2-0 drssit<2:0>: digital rssi threshold bits these bits can be set to indicate the incoming si gnal strength above a preset limit. the result enables or disables the dqdo bit (stsreg<7>). 111 = reserved 110 = reserved 101 = -73 db 100 = -79 db 011 = -85 db 010 = -91 db 001 = -97 db 000 = -103 db register 2-7: rxcreg: receive control register (por: 0x9080) (continued) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 29 mrf49xa register 2-8: bbfcreg: baseband filter configuration register (por: 0xc22c) w-1 w-1 w-0 w-0 w-0 w-0 w-1 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-1 w-0 w-1 w-1 w-0 w-0 acrlc mcrlc r ftype r dqti<2:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11000010b ) are serially sent to the microcon troller to identify the bits to be written in the bbfcreg. bit 7 acrlc: automatic clock recove ry lock control bit 1 = configures the clock recovery lock control as aut omatic. in this setting, the clock recovery starts in fast mode and automatically switches to slow mode after locking 0 = clock recovery lock is controlled in manual mode bit 6 mcrlc: manual clock recovery lock control bit 1 = configures the clock recovery lock control to fa st mode. fast mode requires a preamble of at least 6-8 bits to determine the cl ock rate and then it locks. 0 = configures the clock recovery lock control to slow mode. slow mode takes a bit longer period and requires a preamble of at least 12-16 bits to determine the clock rate and then it locks. slow mode requires more accurate bit timing. see register 2-12 for the relationship between data rate and clock recovery. bit 5 reserved: write as ? 1 ? bit 4 ftype: filter type bit 1 = configures the baseband filter as an analog rc low-pass filter 0 = configures the baseband f ilter as a digital filter (1) bit 3 reserved: write as ? 1 ? bit 2-0 dqti<2:0>: data quality threshold indicator bits the threshold parameter for the dqi should be set to le ss than four to report good signal quality if the bit rate is close to the deviation. usually, if the data rate falls less than the deviation, a higher threshold parameter is permitted and might report a good signal quality (2) . note 1: the digital filter is a digital version of a simple rc lo w-pass filter followed by a comparator with hysteresis. the time constant for the digital filter is automatically calculated based on the bit rate set in the drsreg. the bit rate in this mode should not exceed 115 kbps. in analog rc filter, the demodulator output is fed to the rclkout/fcap/fint pin over a 10 k ? resistor. the filter cutoff frequency is set by the external capacitor connected to this pin and v ss . ta b l e 2 - 6 shows the optimum filter c apacitor values for different data rates. 2: the dqi parameter is calculated using equation 2-3 . the dqi parameter in bbfcreg should be chosen according to the following rules: - the parameter should be > 4, otherwise, noise might be treated as a valid fsk signal. - the maximum value is 7. mrf49xa ds70590c-page 30 preliminary ? 2009-2011 microchip technology inc. equation 2-3: dqi par = 4 x (deviation ? tx/rx offset )/bit rate table 2-7: data rate vs . filter capacitor value data rate filter capacitor value 1.2 kbps 12 nf 2.4 kbps 8.2 nf 4.8 kbps 6.8 nf 9.6 kbps 3.3 nf 19.2 kbps 1.5 nf 38.4 kbps 680 pf 57.6 kbps 270 pf 115.2 kbps 150 pf 256 kbps 100 pf ? 2009-2011 microchip technology inc. preliminary ds70590c-page 31 mrf49xa register 2-9: rxfiforeg: receiver fifo read register (por: 0xb000) w-1 w-0 w-1 w-1 w-0 w-0 w-0 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 rxdb<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 10110000b ) are serially sent to the microcont roller to identify the bits to be written in the rxfiforeg. bit 7-0 rxdb<7:0>: receiver data byte bits these are the recovered data bits stored in the fifo. the controller can read 8 bits from the receiver fifo over the spi bus. the fifoen bit (gencreg<6>) should be set to receive these bits. mrf49xa ds70590c-page 32 preliminary ? 2009-2011 microchip technology inc. register 2-10: fiforstreg: fifo and reset mode configuration register (por: 0xca80) w-1 w-1 w-0 w-0 w-1 w-0 w-1 w-0 ccb<15:8> bit 15 bit 8 w-1 w-0 w-0 w-0 w-0 w-0 w-0 w-0 ffbc<3:0> sychlen ffsc fscf drstm bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11001010b ) are serially sent to the microcont roller to identify the bits to be written in the fiforstreg. bit 7-4 ffbc<3:0>: fifo fill bit count bits sets the received bits before generating an external interrupt to the host microcontroller to indicate the receive fifo is ready to be re ad. the maximum fill level is 15 (1) . bit 3 sychlen: synchronous character length bit this bit sets the synchronous character length to byte or word long. (2) 1 = byte long. user-programmable scl0 byte is used. 0 = word long. the character is composed of the scl1 and scl0 bytes. the scl1 byte value is fixed and is not configurable. the scl0 byte value is user-programmable through the synbreg. bit 2 ffsc: fifo fill start condition bit this bit sets the condition at which the fifo starts filling with data. 1 = the fifo will contin uously fill irrespective of noise or good data 0 = the fifo will fill when it recognizes the synch ronous character pattern as defined internally bit 1 fscf: fifo synchronous character fill bit 1 = the fifo starts filling with da ta when it detects the synchronous character pattern as defined in the ffsc bit 0 = the fifo fill stops to restart the synchronous character pattern recognition, just clear and set this bit (2) . bit 0 drstm: disable (sensitive) reset mode bit 1 = disables (3) 0 = enables system reset for any glitches above 0.2v in the power supply note 1: on register overrun, the data will be lost. therefore, the developer must take into account the processing time required to read-out data before a register overrun. it is recommended to set the fill value to half of the desired number of bits to be read to ensur e sufficient time for additional processing. see register 2-1 for the description of the txrxfifo and txurow bits, and register 2-9 for details on polling and interrupt driven fifo reads from the spi bus. 2: for synchronous character length selection, see ta b l e 2 - 8 . 3: for reset mode selection, see table 2-9 . ? 2009-2011 microchip technology inc. preliminary ds70590c-page 33 mrf49xa table 2-8: synchronous character selection sychlen scl1 scl0 synchronous character 1 na 0xd4 0xd4 (byte long) 0 0x2d 0xd4 0x2dd4 (word long) table 2-9: reset mode selection drstm reset mode condition 1 normal reset reset is triggered when v dd is below 250 mv 0 sensitive reset reset is triggered when v dd is below 1.6v and v dd glitch is greater than 600 mv note: see appendix a: ?read sequence and packet structures? for fifo packet structures. mrf49xa ds70590c-page 34 preliminary ? 2009-2011 microchip technology inc. register 2-11: synbreg: synchronou s byte configuration register (por: 0xced4) w-1 w-1 w-0 w-0 w-1 w-1 w-1 w-0 ccb<15:8> bit 15 bit 8 w-1 w-1 w-0 w-1 w-0 w-1 w-0 w-0 syncb<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11001110b ) are serially sent to the microcont roller to identify the bits to be written in the synbreg. bit 7-0 syncb<7:0>: synch byte configuration bits the synbreg assigns the value to scl0 of th e synchronous character in the fiforstreg. the value is valid for a byte or word long synchronous character. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 35 mrf49xa equation 2-4: equation 2-5: equation 2-6: register 2-12: drsreg: data rate value set register (por: 0xc623) w-1 w-1 w-0 w-0 w-0 w-1 w-1 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-1 w-0 w-0 w-0 w-1 w-1 drpe drpv<6:0> (1) bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11000110b ) are serially sent to the microcon troller to identify the bits to be written in the drsreg. bit 7 drpe: date rate prescaler enable bit 1 = enables the prescaler to obtain smaller values of expected data rates. the prescaler value when enabled is approximately 1/8 of the actual data rate. 0 = disables the prescaler bit 6-0 drpv<6:0>: data rate parameter value bits (1) these bits represent the decimal value of the 7-bi t parameter which is used to calculate the expected data rate. note 1: to calculate the expected data rate, use equation 2-4 . to calculate the drpv<6:0> decimal value for a given bit rate, use equation 2-5 . if the prescaler is not used, the data rates range from 2.694 kbps?344.828 kbps. with the prescaler enabled, the data rates range fr om 337 bps to 43.103 kbps. the slow clock recovery mode requires more accurate bit timing when setting the data rate. equation 2-6 is used to calculate the data rate accuracy for fast and slow modes. drex (kbps) = 10000/[29 x (drpv<6:0> + 1) x (1 + drpe x 7)] where: drpv<6:0> is the decimal value from 0 to 127 and the prescaler (drpe) is ? 1 ? (if on) or ? 0 ? (if off). drpv<6:0> = 10000/[29 x (1 + drpe x 7) x drex] ? 1 where: drex is the expected data rate. ? slow mode accuracy (sma) = dr/dr < 1/(29 x ln) ? fast mode accuracy (fma) = dr/dr < 3/(29 x ln) where: ln is the longest number of expected 1?s or 0?s in the data stream. dr is the difference in the actual data rate versus the set data rate in the transmitter. dr is the expected data rate set using drpv<6:0>. mrf49xa ds70590c-page 36 preliminary ? 2009-2011 microchip technology inc. register 2-13: pmcreg: power management configuration register (por: 0x8208) w-1 w-0 w-0 w-0 w-0 w-0 w-1 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-0 w-0 w-1 w-0 w-0 w-0 rxcen bbcen (1) txcen synen oscen lbden wuten (3) clkoen bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 10000010b ) are serially sent to the microcon troller to identify the bits to be written in the pmcreg. bit 7 rxcen: receiver chain enable bit the receiver chain consists of a baseband ci rcuit, synthesizer and crystal oscillator. 1 = enables receiver chain 0 = disables receiver chain bit 6 bbcen: baseband circuit enable bit (1) the baseband circuit, synthesizer and oscillator work together to demodulate and recover the data transmitted to the synthesizer (synen bit). the oscen bit must be enabled along with the baseband circuits in order to receive data. 1 = enables baseband circuit 0 = disables baseband circuit bit 5 txcen: transmit chain enable bit the transmit chain consists of power amplifier, synthesizer, oscillator and transmit register. 1 = enables the transmitter chain and starts transmission (if the tx register is enabled) 0 = disables transmitter chain bit 4 synen: synthesizer enable bit the synthesizer consists of a pll, oscillator and vco for controlling the channel frequency. 1 = enables the synthesizer 0 = disables the synthesizer bit 3 oscen: crystal oscillator enable bit 1 = enables the crystal oscillator 0 = disables the crystal oscillator bit 2 lbden: low battery detector enable bit the battery detector can be programmed to 32 different threshold levels (2) . 1 = enables the battery voltage detector circuit 0 = disables the battery voltage detector circuit bit 1 wuten: wake-up timer enable bit (3) 1 = enables the wake-up timer circuit 0 = disables the wake-up timer circuit note 1: this bit can be disabled to reduce current consumption. 2: see bcsreg ( register 2-16 ) for programming details. 3: see wtsreg ( register 2-14 ) for details on programming the wake-up timer value. 4: if the clkoen bit is cleared by enabling the clock ou tput, the oscillator continues to run even if the oscen bit is cleared. the device will not fully enter into the sleep mode. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 37 mrf49xa bit 0 clkoen: clock output enable bit on-chip reset or power-up clock output is enabled so that a processor can execute any special setup sequences as required by the designer (2) . 1 = disables the clock output 0 = enables the clock output (4) register 2-13: pmcreg: power management configuration register (por: 0x8208) (continued) note 1: this bit can be disabled to reduce current consumption. 2: see bcsreg ( register 2-16 ) for programming details. 3: see wtsreg ( register 2-14 ) for details on programming the wake-up timer value. 4: if the clkoen bit is cleared by enabling the clock output, the oscillator continues to run even if the oscen bit is cleared. the device will not fully enter into the sleep mode. mrf49xa ds70590c-page 38 preliminary ? 2009-2011 microchip technology inc. equation 2-7: register 2-14: wtsreg: wake-up time r value set register (por: 0xe196) w-1 w-1 w-1 w-0 w-0 w-0 w-0 w-1 ccb<15:13> wtev<4:0> bit 15 bit 8 w-1 w-0 w-0 w-1 w-0 w-1 w-1 w-0 wtmv<7:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 ccb<15:13>: command code bits the command code bits ( 111b ) are serially sent to the microcontrol ler to identify the bits to be written in the wtsreg. bit 12-8 wtev<4:0>: wake-up timer exponential value bits these bits define the exponential value to be used to set up the time interval. the value must be a decimal equivalent between 0 and 29 (1) . bit 7-0 wtmv<7:0>: wake-up timer multiplier exponential value bits these bits define the multiplier value to be used to set up the time interval. the value must be a decimal equivalent between 0 and 255 (1) . note 1: the wtsreg sets the wake-up inte rval for the device. after settin g the wake-up time, the wuten bit (pmcreg<1>) must be cleared and set at the end of every wake-up cycle. the wake-up duration can be calculated using equation 2-7 . wutime ( ms ) =[1.03 x wtmv<7:0> x 2 wtev<4:0> ] + 0.5 ms where: wtmv<7:0> = decimal value between 0 to 255 wtev<4:0> = decimal value between 0 to 29 ? 2009-2011 microchip technology inc. preliminary ds70590c-page 39 mrf49xa equation 2-8: register 2-15: dcsreg: duty cycle value set register (por: 0xc80e) w-1 w-1 w-0 w-0 w-1 w-0 w-0 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-0 w-0 w-1 w-1 w-1 w-0 dcmv<6:0> dcmen bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11001000b ) are serially sent to the microcon troller to identify the bits to be written in the dcsreg. bit 7-1 dcmv<6:0>: duty cycle multiplier value bits these bits are used to calculate the duty cycle or on time of the receiver after the wake-up timer has brought the mrf49xa out of sleep mode (1) . bit 0 dcmen: duty cycle mode enable bit 1 = enables the duty cycle mode 0 = disables the duty cycle mode note 1: for operation in duty cycle mode, the receiver must be disabled (rxcen = 0 ) and the wake-up timer must be enabled (wuten = 1 ) in pmcreg. the registers, dcsreg and wtsreg, can be used to reduce the current consumption of the receiver. t he dcsreg can be set up so that when the wake-up timer brings the mrf49xa out of sleep mode, the receiver is turned on for a short period to sample the signal presence before returning to sleep. the process in the duty cycle mode starts over. the duty cycle uses the multiplier value of the wake-up timer, in parts for its calculation, as shown in equation 2-8 . dc = [(dcmv<7:1> x 2 + 1)]/[wtmv<7:0> x 100%] where: wtmv is wtmv<7:0> bits of the wtsreg. mrf49xa ds70590c-page 40 preliminary ? 2009-2011 microchip technology inc. equation 2-9: register 2-16: bcsreg: battery threshold detect and clock output value set register (por: 0xc000) w-1 w-1 w-0 w-0 w-0 w-0 w-0 w-0 ccb<15:8> bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 cofsb<2:0> r lbdvb<3:0> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11000000b ) are serially sent to the microcont roller to identify the bits to be written in the bcsreg. bit 7-5 cofsb<2:0>: clock output frequency set bits these bits set the output clock frequency which can be used to run an external host microcontroller. 111 = 10 mhz 110 = 5 mhz 101 = 3.33 mhz 100 = 2.5 mhz 011 = 2 mhz 010 = 1.66 mhz 001 = 1.25 mhz 000 = 1 mhz bit 4 reserved: write as ? 0 ? bit 3-0 lbdvb<3:0>: low battery detect value bits these bits set the decimal value to calculate the battery detect threshold voltage level (1,2) . note 1: when the battery level goes down by 50 mv below this value, the lbtd bit (stsreg<10>) is set, indicating that the battery level is below the programmed threshold. this is useful in moni toring discharge-sensitive batteries, such as lithium cells. the low batt ery detect can be enabled by setting the lbden bit (pmcreg<2>) and can be disabled by clearing the bit. 2: the low battery threshold value is programmable from 2.2v ? 3.8v by using equation 2-9 . threshold voltage value = 2.25 +[0.1 x (lbdvb<3:0>)] where: lbdvb<3:0> is the decimal value from 0 to 15. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 41 mrf49xa register 2-17: pllcreg: pll config uration register (por: 0xcc77) w-1 w-1 w-0 w-0 w-1 w-1 w-0 w-0 ccb<15:8> bit 15 bit 8 w-0 w-1 w-1 w-1 w-0 w-1 w-1 w-1 ? cbtc<1:0> r pdds plldd r pllbwb bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 ccb<15:8>: command code bits the command code bits ( 11001100b ) are serially sent to the microcon troller to identify the bits to be written in the pllcreg. bit 7 unimplemented: write as ? 0 ? bit 6-5 cbtc<1:0>: clock buffer time control bits these bits control the rise and fall time for the clock buffer which is dependant on the output clock frequency from the bcsreg. 11 = 5 mhz - 10 mhz 10 = 3.3 mhz 01 = 2.5 mhz or less 00 = 2.5 mhz or less bit 4 reserved: masked to ? 1 ? bit 3 pdds: phase detector delay switch bit 1 = enables the phase detector delay function 0 = disables the phase detector delay function bit 2 plldd: pll dithering disable bit 1 = disables pll dithering 0 = enables pll dithering bit 1 reserved: write as ? 1 ? bit 0 pllbwb: pll bandwidth bit enabling the bit configures higher data rates, fast er settling and reduced phase noise; thus, resulting in a better rf performance. 1 = -102 dbc/hz, > 90 kbps (max 256 kbps) 0 = -107 dbc/hz, < 90 kbps (max 86.2 kbps) mrf49xa ds70590c-page 42 preliminary ? 2009-2011 microchip technology inc. table 2-10: control/command register map reg. name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por stsreg txrxfifo por txowrxof wutint lcexint lbtd fifoem atrssi dqdo clkrl afcct offsv offsb<3:0> 0x0000 gencreg 10 0 00000 txden fifoen fbs<1:0> lcs<3:0> 0x8008 afccreg 11 0 00100 automs<1:0> arfo<1:0> mfcs ham foren fofen 0xc4f7 txcreg 10 0 1100 modply modbw<3:0> ? otxpwr<2:0> 0x9800 txbreg 10 1 11000 txdb<7:0> 0xb8aa cfsreg 10 1 0 freqb<11:0> 0xa680 rxcreg 10 0 10 fintdio diort<1:0> rxbw<2:0 > rxlna<1:0> drssit<2:0> 0x9080 bbfcreg 11 0 00010 acrlc mcrlc ? ftype ? dqti<2:0> 0xc22c rxfiforeg 10 1 10000 rxdb<7:0> 0xb000 fiforstreg 11 0 01010 ffbc<3:0> sychlen ffsc fscf drstm 0xca80 synbreg 11 0 01110 syncb<7:0> 0xced4 drsreg 11 0 00110 drpe drpv<6:0> 0xc623 pmcreg 10 0 00010 rxcen bbcen txcen synen oscen lbden wuten clkoen 0x8208 wtsreg 11 1 wtev<4:0> wtmv<7:0> 0xe196 dcsreg 11 0 01000 dcmv<6:0> dcmen 0xc80e bcsreg 11 0 00000 cofsb<2:0> ? lbdvb<3:0> 0xc000 pllcreg 11 0 01100 ? cbtc<1:0> 1 pdds plldd ? pllbwb 0xcc77 ? 2009-2011 microchip technology inc. preliminary ds70590c-page 43 mrf49xa 3.0 functional description the mrf49xa is a low-power, zero-if, multi-channel fsk transceiver which operates in the 433, 868 and 915 mhz frequency bands. all the rf and baseband functions and processes are integrated in the mrf49xa. the device for its operation requires only a single, 10 mhz crystal as a reference source and an external, low-cost host microcontroller. the mrf49xa supports the following functions: ? reset ? pa and lna ? synthesizer (pll, vco and oscillator) ? i/q mixers and demodulators ? bbfs and amplifiers ? received signal strength indicator ? low battery detector ? wake-up timer/low duty cycle mode ?dqi the mrf49xa is the best option for fhss applications requiring frequency agili ty to meet federal communications commission (fcc), industry canada (ic) or european telecommunications standards institute (etsi) requirements. the communication link can be created by just using the mrf49xa along with a low-cost microcontroller. the device uses the different power-saving modes to reduce the overall current consum ption, and thereby, extends the battery life of the system or application. 3.1 reset the mrf49xa supports four types of reset: ? power-on reset ? power glitch reset ? software reset ? reset pin 3.1.1 power-on reset the mrf49xa has a built-in power-on reset circuitry which automatically resets all control registers when power is applied. a delay of 100 ms is recommended after a power-up sequence in order to allow the v dd to reach the correct voltage level and to get stabilized to recognize an active-low reset. in reset mode, the device does not accept the control commands through the spi. after power-up, the supply voltage starts to rise above 0v. the reset block has an internal ramping voltage reference level (reset ramp signal) which rises at a 100 mv/ms (typical) ra te. the device remains in the reset state until the voltage difference between the actual v dd and the internal reset ramp signal is higher than the reset threshold voltage level (typically 600 mv). the devi ce remains in reset mode as long as the v dd voltage level is less than 1.6v (typ- ical), irrespective of the voltage difference between the v dd and the internal ramp signal. figure 3-1 graphi- cally shows the por example for v dd with respect to time conditions. figure 3-1: power-on reset example v dd 1.6v h l reset threshold voltage (600 mv) reset ramp line (100 mv/ms) time the device stays in reset when v dd < 1.6v (even if the voltage difference is smaller than the reset threshold). reset output (pin 10) mrf49xa ds70590c-page 44 preliminary ? 2009-2011 microchip technology inc. 3.1.2 power glitch reset spikes or glitches are found on the v dd line if the power supply filtering is not satisfactory, or the internal resistance of the power supply is very high. so, in this case, the sensitive reset mode needs to be enabled. here, the device reset occurs due to the transients present on the v dd line. the internal reset block has two basic modes of operation: ? sensitive reset mode ? normal reset mode sensitive reset mode: enabling the sensitive reset, a reset is generated if: ? the positive going edge of the v dd has a rising rate greater than 100 mv/ms, and ? the voltage difference between the internal ramp signal and the v dd reaches the reset threshold voltage (600 mv). the sensitive reset mode is the default mode which can be changed using the drstm bit (fiforstreg<0>). figure 3-2 shows the sensitive reset mode. normal reset mode: the device enters this mode, when the power glitch detection circuit is disabled. figure 3-3 shows the normal reset mode. if the sensitive mode is disabled and the power supply is turned off, the v dd requires 250 mv to trigger a power-on reset when the supply voltage is reapplied. if the decoupling capacitors retain their charges for a longer duration, there might be no reset after power-up as the power glitch detector is disabled. figure 3-2: sensitive reset enabled note: negative change in the supply voltage does not cause a reset event unless the v dd level reaches the reset threshold voltage (i.e., 250 mv in normal reset mode, 1.6v in sensitive reset mode). note: the reset event reinitializes the internal registers, and thus, the sensitive mode is enabled again. v dd 1.6v h l reset threshold voltage (600 mv) reset ramp line (100 mv/ms) time reset output (pin 10) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 45 mrf49xa figure 3-3: sensiti ve reset disabled 3.1.3 software reset the software reset is initiated using the host microcontroller. the 0xfe00 command triggers this reset only if the sensitive reset mode is enabled. the hardware automatically clears the bit(s) to their power-on state. the software reset command is the same as por, but the duration of the reset event is much less than the actual por (0.25 ms, typical). 3.1.4 reset pin the mrf49xa has an open-drain reset output with an internal pull-up and input buffer (active-low). the host microcontroller resets the mrf49xa by asserting the reset pin to low (see figure 3-4 ). all control registers are reset to their por values. the reset pin consists of an internal weak pull-up resistor. in order to allow the rf circuitry to start-up and get stabilized, a delay of around 0.25 ms is recommended for accessing the mrf49xa after a hardware reset. figure 3-4: reset pin internal connection the registers associated with reset are: ?stsreg (see register 2-1 ) ? fiforstreg (see register 2-10 ) ? wtsreg (see register 2-14 ) 250 mv h l reset threshold voltage (600 mv) reset ramp line (100 mv/ms) time v dd reset output (pin 10) reset pin n v ss v dd 100k 10k to internal reset logic from por circuit to mcu reset (input/output*) * these pins can be left floating. mrf49xa ds70590c-page 46 preliminary ? 2009-2011 microchip technology inc. 3.2 v dd line filtering during the reset event (caus ed by power-on, glitch on the supply line or software reset), the v dd line should be kept clean. noise or a periodic disturbing signal superimposed on the supply voltage may prevent the device from getting out of the reset state. to avoid this, adequate filters should be m ade available on the power supply lines to keep the distorting signal level below 100 mvp-p, in the dc-50 khz range for 200 ms, from v dd ramp start. the usage of regulators or smps may sometimes introduce switching noise on the v dd line, so follow the power supply manufacturer?s recommendations on how to decrease the ripple of regulator ic and/or how to shift the switching frequency while using smps. the registers associated with power line filtering are: ?stsreg (see register 2-1 ) ? fiforstreg (see register 2-10 ) ? wtsreg (see register 2-14 ) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 47 mrf49xa 3.3 power and low noise amplifiers the pa is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching, can also drive a monopole antenna. an automatic antenna tuning circuit configured in the pa avoids the manual tuning during production and this offsets ?hand effects?. the registers associated with the pa are: ?txcreg (see register 2-4 ) ? pmcreg (see register 2-13 ) the input lna has selectable gain (0 db, -6 db, -14 db and -20 db) which is useful in environments with strong interferers. the lna has 250 ? of differential input impedance, which requires a matching circuit when connected to 50 ? devices. the registers associated with the lna are: ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) 3.4 crystal oscillator and clock output the mrf49xa has a single pin crystal oscillator circuit, which provides a 10 mhz reference signal for the on-chip pll. the clock fr equency is programmable from eight predefined frequencies, each being a prescaled value of a 10 mhz crystal reference. a programmable crystal load capacitor has been internally configured to reduce the external component count and to have a much simplified design. the internal load capacitor is programmable from 8.5 pf ? 16 pf in 0.5 pf steps as defined gencreg. this provides the advantage of accepting a wide range of crystals from different manufacturers with diff erent load capacitance requirements. for load capacitance values, see table 3-1 . these values are pr ogrammable through the bcsreg (see register 2-16 ). the crystal oscillator circuit is sensitive to parasitic capacitance for start-up. a small amount of parasitic capacitance is needed to facilitate oscillation. to achieve this, create a ground plane around the crystal and widen the connection to the mrf49xa. this is to adjust the reference frequency and to compensate for stray capacitance that might be introduced due to pcb layout. if the layout is not possible, a 0.5 pf ? 1 pf capacitor, soldered across the crystal, will initiate the start-up. also, see section 3.6, crystal selection guidelines for selecting the right crystal. the crystal oscillator provides a reference signal to the rf synthesizer, baseband circuits and digital signal processing parts. if receiver or transmitter blocks are used frequently, it is recommended to leave the oscillator running because the crystal might need a few milliseconds to start and stabilize. the stabilization time mainly depends on the crystal parameters. the clkoen bit (pmcreg<0>) is used to enable or disable the clock output. 3.4.1 clock tail feature the mrf49xa provides the clock signal for the microcontroller for accurate timing, and thus, removes the need for a second crystal for any board design. when the microcontroller turns off the crystal oscillator by clearing the oscen bit (pmcreg<3>), the mrf49xa provides a fixed number (192) of further clock pulses for the microcontroller to switch itself to idle or sleep mode (low-power cons umption modes). to use this feature, stsreg must be read before the oscen bit is set to ? 0 ?. if stsreg is not read, then the clock output will not shut down. if the clkout pin is not used, it is suggested to turn off the output buffer from pmcreg. the microcontroller clock so urce (if the clock is not supplied by the mrf49xa) should be stable enough over temperature and volt age ranges to ensure a minimum of 16 bits time delay under all operating circumstances. table 3-1: programmable load capacitance value cap3 cap2 cap1 cap0 load capacitance 0000 8.5 0001 9 0010 9.5 0011 10 0100 10.5 0101 11 0110 11.5 0111 12 1000 12.5 1001 13 1010 13.5 1011 14 1100 14.5 1101 15 1110 15.5 1111 16 note: leaving blocks needlessly turned on increases the current consumption, and thus, reduces the battery life. mrf49xa ds70590c-page 48 preliminary ? 2009-2011 microchip technology inc. 3.4.2 auto crystal oscillator when an interrupt occurs, irre spective of the oscen bit setting, the crystal oscilla tor automatically turns on to supply a clock signal to the microcontroller. after clearing all interrupts and reading the stsreg, the crystal oscillator is automatically tur ned off. the clock tail feature provides enough clock pulses for the microcontroller to enter the low-power mode. due to this automatic feature, it is not possible to turn off the crystal by clearing the oscen bit if any interrupt is active. for example, after power-on, the por interrupt must be cleared by reading stsreg and then writing ? 0 ? to the oscen bit puts the part in sleep mode. it is necessary to clear all interrupts before turning the oscen bit off as the extra current required for running the crystal oscillator can shorten the battery life significantly. on disabling the clock output (clkoen = 1 ), both the clock tail and auto crystal oscillator usage features are turned off. only the osce n bit controls the crystal oscillator (considering t hat both rxcen and txcen bits are cleared); the interrupts have no effect on it. the registers associated with the crystal oscillator and clock are: ?stsreg (see register 2-1 ) ? afccreg (see register 2-3 ) ? pmcreg (see register 2-13 ) ? bcsreg (see register 2-16 ) ? pllcreg (see register 2-17 ) 3.5 phase-locked loop the synthesizer consists of a pll, oscillator and vco for controlling the channel frequency. the synthesizer must be enabled when either the transmitter or the receiver is enabled. for faster rx/tx switching, the synthesizer block must be kept on. enabling the transmitter using the txcen bit (pmcreg<5>) will turn on the pa, and since the synthesizer is already up and running, the pa immediately produces the tx signal at the output. the oscillator must also be enabled to provide the reference frequency for the pll. on power-up, the synthesizer performs the calibration automatically. the synthesiz er also has an internal start-up calibration proced ure. if there are significant changes in voltage or temper ature, recalibration should be performed by simply disabling the synthesizer and re-enabling it. when set, the synen bit (pmcreg<4>) enables the synthesizer. the pll circuit automatic ally performs the fine adjustment of carrier frequenc y. this way, the receiver can minimize the offset between a transmit and receive frequency. the frequency control function can be enabled or disabled through afccreg. the range of offset can be programmed and the offset value is calculated and added to the frequency control word within the pll to incrementally change the carrier frequency. the mrf49xa can be programmed to automatically change and control the carrier frequency. the carrier frequency can also be manually activated by a strobe signal. the oscillator provides the reference signal to the rf synthesizer to set up the transmit or receive frequency. the crystal oscillator also provides a reference signal to the rf, baseband circuits and microcontroller interface. the pll configuration register configures the following: ? output clock buffer slew rate ? crystal start-up time ? phase detector delay ? pll dithering ? pll bandwidth the dithering reduces the noise error when calculating the fractional-n synthesizer code. when the plldd bit (pllcreg<2>) is cleared, dithering is enabled and the settling time is slightly increased. the pll bandwidth can accommodate higher data rates above 90 kbps. the reduced pll bandwidth allows faster settling time and reduced phase noise, and thus, results in a better rx performance. see register 2-17 for details on pll setting and configuration. the registers associated with the pll are: ?stsreg (see register 2-1 ) ? afccreg (see register 2-3 ) ? pmcreg (see register 2-13 ) ? bcsreg (see register 2-16 ) ? pllcreg (see register 2-17 ) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 49 mrf49xa 3.6 crystal selection guidelines the crystal oscillator of mrf49xa requires a 10 mhz parallel mode crystal. the circuit contains an integrated load capacitor in order to minimize the external component count. the internal load capacitance value is programmable from 8.5 pf ? 16 pf in 0.5 pf steps. with appropriate pcb layout, the total load capacitance value can be 10 pf ? 20 pf, so a variety of crystal types can be used. when the total load capacitance is not more than 20 pf, and a worst case 7 pf shunt capacitance (c s ) value is expected for the crystal, the oscillator is able to start-up with any crystal having less than 100 equivalent series loss resistance ( esr). however, the low c s and esr values ensure the faster oscillator start-up. the crystal frequency (f ref ) is used as the reference of the pll, which generates the local oscillator frequency (f lo ). therefore, f lo is directly proportional to f ref . the accuracy requirements for production tolerance, temperature drift and aging c an thus be determined from the maximum allowable local oscillator frequency error. whenever a low-frequency error is essential for the application, it is possible to ?pull? the crystal to the accurate frequency by changing the load capacitor value. the widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the ?midrange?; for example, 16 pf. the ?pull-ability? of the crystal is defined by its motional capacitance (c m ) and shunt capacitance. figure 3-5: maximum crystal tolerances includ ing temperature and aging (ppm) 30 45 60 75 90 105 120 433 mhz 15 30 50 70 80 100 100 868 mhz 8 152530405060 915 mhz 8 152530405050 deviation [ khz] bit rate: 9.6 kbps 30 45 60 75 90 105 120 433 mhz 20 30 50 70 90 100 100 868 mhz 10 20 25 30 40 50 60 915 mhz 10 15 25 30 40 50 50 deviation [ khz] bit rate: 2.4 kbps 30 45 60 75 90 105 120 433 mhz do not use 5 20 30 50 75 75 868 mhz do not use 3 10 20 25 30 40 915 mhz do not use 3 10 15 25 30 40 deviation [ khz] bit rate: 38.4 kbps 105 120 135 150 165 180 195 433 mhz do not use 3 20 30 50 70 80 868 mhz do not use do not use 10 20 25 35 45 915 mhz do not use do not use 10 15 25 30 40 deviation [ khz] bit rate: 115.2 kbps mrf49xa ds70590c-page 50 preliminary ? 2009-2011 microchip technology inc. 3.7 automatic frequency control the afc block operates in two modes and these modes depend on the strobe signals which are governed by the mfcs bi t (afccreg<3>). the two operating modes are as follows: ? manual mode ? automatic mode manual mode: in this mode, the microcontroller provides the manual freq uency control strobe signal. see register 2-3 (afccreg) for more details. one measurement cycle can compensate for around 50% ? 60% of the actual frequency offset. two measurement cycles can compensate fo r 80% and three measurement cycles can compensate for 92 % of the actual frequency offset. the afcct bit (stsreg<5>) is used to determine when the actual measurement cycle has been completed. automatic mode: in this mode, the strobe signal from the microcontroller is not required to update the frequency offset register block, as shown in figure 3-6 . the afc circuit is automatically enabled when the dio indicates the potential incoming signal during the entire measuremen t cycle and measures the same result in two subs equent cycles. without afc, the transmitter and the receiver need to be tuned precisely to the same frequency. the rx/tx frequency offset can lower the range. the units must be adjusted carefully during the production. to avoid drift, a stable and efficient crystal must be used or the output power needs to be increased to compensate for yield loss. the afc block calculates the tx/rx offset using the offsb bits (stsreg<3:0>). this value is used to pull the rx synthesizer close to the transmitter frequency. the benefits of the afc feature are: ? low-cost crystal can be used ? temperature or aging drift will not cause range loss ? production alignment is not needed figure 3-6 depicts the afc circuit for frequency offset correction. the automatic mode selection bits, automs<1:0> (afccreg<7:6>), select the type of operation (automatic or manual) for performing the afc based on the status of the mfcs bit (afccreg<3>). there are four types of operation modes for controlling the frequency: 1. (automs1 = 0 , automs0 = 0 ): automatic operation of afc is off. the mfcs bit is controlled by the microcontroller. 2. (automs1 = 0 , automs0 = 1 ): the circuit measures the frequency offset only once after power-up. hence, extended tx to rx distance can be achieved. in the actual application, when the user applies a battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. this method allows the use of a low-cost quartz crystal in the application and provides protection against interference. 3. (automs1 = 1 , automs0 = 0 ): the frequency offset is aut omatically calculated and the center frequency is corrected when the dio is high. when dio goes low, the calculated value is dropped. the two methods recommended for improving the accuracy of the afc calculation are as follows: ? the transmit package should start with a low effective baud rate pattern (i.e., 00110011b ) as it is easier to receive. th e circuit automatically measures the frequency offset during this initial pattern and changes the receiving frequency accordingly. the remaining part of the package will be received by the corrected frequency settings. ? the transmitter sends the first part of the packet with a higher deviation step than required during normal operation to help reception. after the frequency shift correction, the deviation can be reduced. in both methods, when the dio indicates poor receiving conditions (i.e., when dio goes low), the output register is automatically cleared. th is mode (drop offset mode) is used when the receiver communicates with more than one transmitter. 4. (automs1 = 1 , automs0 = 1 ): this mode (keep offset mode) is similar to drop offset mode, but is recommended for use when the receiver communicates with only one transmitter. after a complete measuring cycle, the measured value is kept independent of the state of the dio signal. in this mode, the drssi limit should be carefully selected to minimize the range hysteresis. the afc offset value (offsb< 3:0> bits in the status word) is represented as a two?s complement number. the actual frequency offset is calculated as the afc offset value multiplied by the current pll frequency step (see register 2-6 for more details). the actual rx/tx offset can be monitored by using the afc status report (i.e., afcct bit) included in the status word of the receiver. by reading out the status word, the actual measured offset fr equency can be derived. to get accurate values, the afc has to be disabled during read by clearing the fofen bit (afccreg<0>). the registers associated with afc are: ?stsreg (see register 2-1 ) ? afccreg (see register 2-3 ) ? cfsreg (see register 2-6 ) ? rxcreg (see register 2-7 ) ? pllcreg (see register 2-17 ) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 51 mrf49xa figure 3-6: afc circuit for frequency offset correction sel 11 10 y mux digital afc core logic digital limiter frequency offset register adder baseband signal in if in > maxdev then, out = maxdev if in < mindev then, out = mindev else, out = in output enable 7-bit 12-bit signals for auto operation modes strobe range limit por auto operation automs<1:0> dio enable calculation /4 ham 10 mhz clk clk fine fifoen arfo<1:0> mfcs foren freqb<11:0> output enable strobe clk clr f cor <11:0> corrected frequency parameter to synthesizer parameter from frequency control word 7 7 offsb <6:0> afcct stsig mrf49xa ds70590c-page 52 preliminary ? 2009-2011 microchip technology inc. 3.8 initialization certain control register values must be initialized for the basic operations of mrf49xa. these values differ from the power-on reset values and provide improved operational parameters. these settings are normally made once after a reset. after initialization, the mrf49xa device features can be configured for the application. here, accessing a register is implied as a command to the mrf49xa device through the spi port. the steps to be followed for the initialization of mrf49xa using the control registers are as follows: 1. set fiforstreg. 2. enable synchronous latch from fiforstreg. 3. program frequency band and crystal load capacitance from gencreg. 4. enable afc function from afccreg. 5. set center frequency through cfsreg for transmit or receive frequency. 6. set data rate through drsreg. 7. enable required functions (transmit, receive, etc.) from pmcreg. 8. configure rxcreg. 9. configure txcreg. 10. tune in the antenna. 11. turn off the transmitter and turn on the receiver. 12. enable fifo for data reception. 13. set fiforstreg. 14. enable synchronous latch from fiforstreg. 15. read stsreg. the following steps should be followed to tune in the antenna section: 1. turn on the transmitte r section from pmcreg. 2. wait for 5 ms for the oscillator to get stabilized. the registers associated with initialization are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? afccreg (see register 2-3 ) ?txcreg (see register 2-4 ) ?cfsreg (see register 2-6 ) ? rxcreg (see register 2-7 ) ? fiforstreg (see register 2-10 ) ? drsreg (see register 2-12 ) ? pmcreg (see register 2-13 ) 3.9 interrupts the advanced interrupt handler circuit is implemented in the mrf49xa to reduce the power consumption. as mentioned, the sleep mode is the lowest power consumption mode in which the mode clock and all functional blocks of the chip are disabled. however, the wut and lbd circuits can be active if enabled. in case of any interrupt, the device wakes up, switches to the active mode and an interrupt signal generated on the iro pin of the device indicates the change in state or occurrence of an interrupt to the host microcontroller. the source of the interrupt is determined by reading the status word of the device (see register 2-1 ). the receiver generates an ac tive-low interrupt request for the microcontroller at the following events: ? txbreg is ready to receive the next byte ? rxfiforeg has received the preprogrammed amount of bits ? rxfiforeg overflow/txbreg underrun ? negative pulse on interrupt input pin (int ) ? wake-up timer time-out (wutint) ? supply voltage below the preprogrammed value is detected ? power-on reset ? 2009-2011 microchip technology inc. preliminary ds70590c-page 53 mrf49xa 3.9.1 setting interrupts the device?s interrupt pin (iro ) signals one of eight interrupt events to the host microcontroller. the interrupt source in the microcontroller is read out from the transceiver through the sdo pin. the interrupt sources that are available are briefly described in the following subsections. 3.9.1.1 txrxfifo: transmit register or receive fifo bit 1. transmit mode: transmit register ready bit this interrupt is generated when the transmit register is empty. it is valid only when the txden bit (gencreg<7>) is set and the txcen bit (pmcreg<5>) is enabled. 2. receive mode: receive fifo empty bit this interrupt is generated when the bit level in the rxfiforeg has reached the preprogrammed level. an interrupt is triggered when the number of received data bits in the receiver fifo reaches the threshold set by the ffbc bits (fiforstreg<7:4>). this is valid only when the fifoen bit (gencreg<6>) is set and the rxcen bit (pmcreg<7>) is enabled. 3.9.1.2 por: power-on reset interrupt the por interrupt is generated when a change on the v dd line triggers an internal reset circuit or a software reset was issued. for details, see section 3.1, reset . 3.9.1.3 txowrxof: transmit overwrite receive overflow bit 1. transmit mode: transmit register underrun or overwrite bit this interrupt is gener ated when the automatic baud rate generator (brg) has completed the transmission of a byte in txbreg before the register write . it is valid only when the txden bit (gencreg<7>) is set and the txcen bit (pmcreg<5>) is enabled. 2. receive mode: receive fifo overflow bit this interrupt is generated when the bits received are more than the fifo capacity (16 bits). this is valid only when the fifoen bit (gencreg<6>) is set and the rxcen bit (pmcreg<7>) is enabled. 3.9.1.4 wutint: wake-up timer interrupt this interrupt occurs when the time specified by the wake-up timer has elapsed. it is valid only when the wuten bit (pmcreg<1>) is set. the device periodically wakes up and switches to receive mode. if valid fsk data is received, the device sends an interrupt to the microcontroll er and continues filling the rxfifo. after the completion of transmission, the fifo is read out completely and all other interrupts are cleared. the device returns to the low-power consumption mode. 3.9.1.5 lcexint: logic low-level change on external interrupt follows the level of the int pin if configured as an external interrupt by clearing the fintdio bit (rxcreg<10>). 3.9.1.6 lbtd: low battery threshold detect this interrupt occurs when v dd goes below the programmable low battery detector threshold level configured by the lbdvb bits (bcsreg<3:0>). it is valid only when the lbden bit (pmcreg<2>) is set. 3.9.2 clearing interrupts if any of the interrupt sources gets active, the iro changes to logic low level and the corresponding interrupt bit in the status byte goes high. clearing an interrupt implies: ? releasing the iro pin to return to logic high, and ? clearing the corresponding interrupt bit in the stsreg the clearing of each of the interrupts is briefly described in the following subsections. 3.9.2.1 txrxfifo 1. transmit mode the iro pin and its status bit remain active until the register is written (if underrun does not occur until the register write) or the transmitter and the tx latch are switched off. 2. receive mode the iro pin and its status bit remain active until the fifo is read (rec eive fifo interrupt threshold number of bits have been read). the receiver is switched off or the rxfifo is switched off. 3.9.2.2 por the iro pin and its status bit are cleared by reading the status read register. mrf49xa ds70590c-page 54 preliminary ? 2009-2011 microchip technology inc. 3.9.2.3 txowrxof 1. transmit mode in this mode, the txowrxof and txrxfifo bits are always set together. the iro pin and its status bit remain active until the transmitter and the tx latch are switched off. 2. receive mode in this mode, the txowrxof and txrxfifo bits are always set together and can be cleared by reading the stsreg. the iro pin and its status bit remain active until the fifo is read (a fifo interrupt threshold number of bits have been read), the receiver is switched off or the rx fifo is switched off. 3.9.2.4 wutint the iro pin and its status bit are cleared by reading the stsreg. 3.9.2.5 lcexint the iro pin and its status bit follow the level of the int pin. 3.9.2.6 lbtd the iro pin is released by reading the status bit of stsreg, but the status bit remains active until the v dd is below the threshold value. the mrf49xa interrupt generation logic is shown in figure 3-7 . a better way of interrupt handling is to first read the stsreg on an interrupt and then decide the action based on the status by te/word. it is important to note that any of the interrupt sources can wake-up the mrf49xa from sleep mode. this means that the crystal oscillator starts to supply a clock signal to the microcontroller even if the microcontroller has its own clock source. the mrf49xa will not enter sleep mode if any of the interru pt remains active, i rrespective of the state of the oscen bit in pmcreg. this way, the microcontroller can alwa ys have a clock signal to process the interrupt. to prevent high-current cons umption, which results in short battery life, it is hi ghly recommended to process and clear interrupts before entering sleep mode. the functions which are not neces sary should be turned off to avoid unwanted interrupts. before finalizing the microcontroller (application) code, a thorough testing must be conducted to make sure that all interrupt sources are handled before putting the transceiver in sleep mode. the oscen bit controls the crystal oscillator (considering that the rx cen and txcen bits are cleared) if the clkoen bit (pmcreg<0>) is set. the interrupts have no effect on it. on interrupt, the crystal oscillator turns on automatically to supply a clock signal to the microcontroller, irrespective of the oscen bit setting. the clock tail feature provides sufficient clock pulses for the microcontroller to enter the low-power consumption mode. due to this automatic f eature, it is not possible to turn off the crystal by clearing the oscen bit if any interrupt is active. for example, after power-on, the por interrupt must be cleared by a status read, and then by writing ? 0 ? in the oscen bit, puts the device into sleep mode. the registers associated with interrupts are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) ? bcsreg (see register 2-16 ) note: before turning the oscen bit off, clear all the interrupts, because the additional current required for running the crystal oscillator can shorten the battery life significantly. ? 2009-2011 microchip technology inc. preliminary ds70590c-page 55 mrf49xa figure 3-7: mrf49xa interrupt generation logic txrxfifo txcen txrxfifo rxcen txowrxof txcen txowrxof rxcen wutint wuten lcexint (int) fintdio lbtd lbden iro reset (ext./int.) mrf49xa ds70590c-page 56 preliminary ? 2009-2011 microchip technology inc. 3.10 baseband/data filtering the baseband receiver has several programming options to optimize the communication for a wide range of applications. the programmable functions are as follows: ? baseband analog filter ? baseband digital filter ? receive bandwidth ? receive data rate ? clock recovery a suitable bandwidth should be used to achieve various fsk deviation, data rate and crystal tolerance require- ments. the filter structure is a 7th order, butterworth low-pass with 40 db suppr ession at twice the bandwidth frequency. offset cancellation is done by using a high-pass filter, with a cutoff frequency below 7 khz, in order to achieve the best pos sible frequency response in baseband and a good flat response in the pass band. figure 3-8 shows the full baseband amplifier transfer function. this optimizes the chip area, cost and channel separation. figure 3-8: full baseband amplifier transfer function (bw = 67 khz) the receive bandwidth is programmable from 67 khz to 400 khz to accommodate various fsk modulation deviations. if the deviation is known for a given transmitter, good results are obtained with a bandwidth of at least twice the tr ansmitter fsk deviation. example 3-1 shows the method to calculate the recommended frequency deviation and bbbw for the given specifications. example 3-1: frequency devi ation and bbbw calculation -140 -120 -100 -80 -60 -40 -20 0 20 40 1 .0e+0 2 1 .0e+0 3 1 .0e+04 1.0e+05 1.0 e+06 frequency (hz) out put powe r leve l (db) ? data rate ? 9.6 kbps ? crystal accuracy ? 40 ppm ? frequency band ? 915 mhz ?f xerror by the crystal: 40 x (915000/1000000) = 36.6 khz deviation = data rate + 2 x f xerror + 10 = 9.6 + 2 x 36.6 + 10 = 92.8 khz the closest possible deviation is 90 khz. bbbw = deviation x 2 ? 10 kh z = 90 x 2 ? 10 = 170 khz the closest possible bbbw is 200 khz. the fsk modulated deviation for this example is shown in figure 3-9 . ? 2009-2011 microchip technology inc. preliminary ds70590c-page 57 mrf49xa figure 3-9: fsk modulated deviat ion ? maximum tx to rx offset the baseband filtering type can also be selected between an analog filter and a digital filter. 3.10.1 analog filtering mode for analog filtering, a simp le rc low-pass filter is used, along with a schmitt trigger circuit. the demodulator output is fed to the rclkout/fcap/fint pin over a 10 k resistor. the filter cut-off frequency is set by the external capacitor connected to this pin and v ss . a 10 k resistor and the schmitt trigger are integrated on the chip. an external capacitor for the rc filter has to be chosen in accordance with the required bit rate. the receiver can handle up to 256 kbps of data rate in analog operation. the receive data rate is programmable from 337 bps to 256 kbps. an internal prescaler can be used to give better resolution when setting up the receive data rate. the prescaler is optional and can be disabled through drsreg. the analog filtering does not use the fifo and the clock. the clock is not provided for the demodulated data, and hence, there is no need for setting the correct bit rate. 3.10.2 digital filtering mode a digital filter is used with a clock frequency at 29 times the data rate. for digital filtering, the synchronized clock to the data is provided by the clkrc. by using this clock, the received data can fill the fifo. if the fifo is not used, the reco vered clock can be accessed through rclkout/fcap/ fint pin. the clkrc operates in three modes: automatic mode, slow mode and fast mode. all three modes are configurable through bbfcreg. each mode is dependent on the type of signals it uses to determine the valid data and also the number of incoming preamble bits present at the beginning of the packet. in automatic mode, the cr clkrc automatically switches between the fast and slow mode. the noise immunity of the clkrc is very high in slow mode; however, it has slower settling time and requires more accurate data timing than in fast mode. the registers associated wi th baseband filtering are: ?stsreg (see register 2-1 ) ? rxcreg (see register 2-7 ) ? bbfcreg (see register 2-8 ) ? pmcreg (see register 2-13 ) 10 khz bbbw programmable rx center freq. baseband filter characteristic 2 x deviation amplitude 10 khz + data rate data rate tx-rx offset tx center freq. frequency mrf49xa ds70590c-page 58 preliminary ? 2009-2011 microchip technology inc. 3.11 data quality indicator the dqi is the digital proc essing part of the radio connected to the demodulator and functions when the receiver is on. this reports the reception of an fsk modulated rf signal. the dqi parameter setting defines how clean the incoming data stream would be stated as good data (valid fsk signal). the dio signal goes high if the internally calculated data quality value exceeds the dio threshold parameter, for five consecutive data bits, for both high and low periods. the dqi parameter (i.e., data quality threshold indicator (dqti) bit) valu e is calculated using the formula given in equation 3-1 . equation 3-1: the dqi parameter in bbfcreg should be chosen according to the following rules: ? the parameter should be > 4; otherwise, noise might be treated as a valid fsk signal ? the maximum value is 7 even during the on-time calculation in the low duty cycle mode, depending on the data quality threshold indicator, the device needs to receive a few valid data bits before the dqi signal indicates good signal condition (see register 2-8 ). selecting a short on-time can prevent the crystal oscill ator from starting, or the dqi signal will not go high, even when the quality of the received signal is good. the dio is an extension of the dqi. when incoming data is detected, it uses the dqi signal, the clock recovery lock signal and the digital rssi signal to determine if the incoming data is valid. the desired data rate and the acceptance criteria for valid data are user-programmable through the spi port. the dio has three modes of operation: slow, medium and fast. each mode is dependent on the signals it uses to determine the valid data and also on the number of incoming preamble bits present at the beginning of the packet. the dio can be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept only a preset range of data rates and data quality. the dio saves the battery power and the time for a host microcontroller because it will not wake-up the microcontroller unless there is valid data present. see register 2-7 (rxcreg) for setup details. the dio signal is valid when using the internal receive fifo or an external pin to capture baseband data. dio can be multiplexed to pin 16 for external usage. figure 3-10 depicts the dio logic block diagram. figure 3-10: dio logic block diagram dqipar = 4 x (deviation ? tx/rxoffset)/bit rate r/s flip/flop cr_lock drssi dqi drssi dqi cr_lock set q rxcen logic high slow medium fast diort1 diort0 dqi mux sel0 sel1 in0 in1 in2 in3 dio y clr clr ? 2009-2011 microchip technology inc. preliminary ds70590c-page 59 mrf49xa the dio signal response time setting is configured through rxcreg and has the following modes of operation: ? default mode: the dio is permanently connected to logic high . it always stays high independent of the receiving parameters. ? slow mode: the dio signal goes high if the digital rssi, dqi and clock recovery lock (cr_lock) signals are present. it stays high until any of these signals are present and goes low when all three input signals are low. ? medium mode: the dio signal is active when the cr_lock and the drssi or the dqi signals are high. it goes low when either the cr_lock becomes inactive or the drssi or dqi signals goes low. ? fast mode : the dio signal follows the level of the dqi signal. the registers associated with dqi are: ? stsreg (see register 2-1 ) ? rxcreg (see register 2-7 ) ? bbfcreg (see register 2-8 ) 3.12 programmable synchronous byte the internal synchronous pattern and the pattern length are user-programmable. the mrf49xa is configured to use a synchronous character to indicate the valid incoming data. the synchronous character selection is done through the fiforstreg. the character is divided into two bytes: scl1 and scl0. the scl0 byte is user-configurable, whereas scl1 is fixed to 2dh and is non-programmable. the synchronous character can also be configured as a byte character or a word character. a byte character uses only scl0, whereas the word character uses both scl1 and scl0. since scl0 is user-configurable, it is advantageous while operating under interferences and also while identifying the related transmitters. the registers associated with the programmable synchronous byte are: ? fiforstreg (see register 2-10 ) ? pmcreg (see register 2-13 ) 3.13 received signal strength indicator the received signal strength indicator (rssi) estimates the received signal power within the bandwidth of ism channels. the mrf49xa provides both analog rssi and digital rssi. a digital rssi output is provided to monitor the input signal level. the signal goes high if the received signal strength exceeds a given preprogrammed level. the digital rssi threshold is programmable through rxcreg, and is read and monitored only through stsreg. when an incoming signal is stronger than the pr eprogrammed threshold, the digital rssi bit in the stsreg is set. the settling time of digital rssi depends on the external filter capacitor. the drssit value is a 3-bit binary value ranging from 0 to 8. table 3-2 shows the mapping between the drssit value versus the received power level. the number of symbols to average can be changed by programming the drssit bits (rxcreg<2:0>). the digital rssi is basical ly a sensitive comparator behind an analog rssi block. the comparator threshold can be set using the three bits and the comparator output can be read out through the status read register. the curve in figure 3-11 shows the analog rssi output voltage versus signal strength. the analog rssi level is linear with input signal levels between -103 dbm and -73 dbm. the rssio pin in mrf49xa is used as an analog rssi output and better results can be achieved by using this pin with a sensitive comparator. these bits can be set to indicate the incoming signal strength above a preset limi t. the result enables or disables the dqdo bit (stsreg<7>). the rssi threshold depends on the lna gain and the real rssi threshold can be calculated by using the formula as given in equation 3-2 . equation 3-2: in transmit mode, the atrssi bit (stsreg<8>) indicates that the antenna tu ning circuit has detected a relatively str ong rf signal. in receive mode, the atrssi bit indicates that the incoming rf signal is above the preprogrammed digital rssi threshold. rssith = rssisetth + glna mrf49xa ds70590c-page 60 preliminary ? 2009-2011 microchip technology inc. figure 3-11: input power vs . analog rssi voltage 3.13.1 relationship between rssi and clock recovery the dio signal response time setting is configured through rxcreg and has the following modes of operation: ? normal mode ? slow mode ? medium mode ?fast mode these operation modes are configurable through bbfcreg. in medium mode, the dio signal is active when the cr_lock and the drssi or the dqi signals are high. the dio goes low when either the cr_lock turns inactive, or the drssi or dqi signals go low. for more details on dqi, see section 3.11, data quality indicator . 3.13.2 relationship between rssi and afc the keep offset mode of automatic configuration of afc (i.e., automs1 = 1 , automs0 = 1 ) is recommended to be used when a receiver operates with only one transmitter. after a complete measuring cycle, the measured value is kept independent from the state of the dio signal . in this mode, the drssi limit should be carefully selected to minimize the range hysteresis. the registers associated with rssi are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) table 3-2: digital r ssi threshold levels rssi threshold drssit2 drssit1 drssit0 reserved 111 reserved 110 -73 101 -79 100 -85 011 -91 010 -97 001 -103 000 0 0.2 0.4 0.6 0.8 1 1.2 -112 -102 -92 -82 -72 -62 -52 -42 input power (dbm) rssi (v) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 61 mrf49xa 3.14 power management the power management configuration register enables/disables the following functions: ? receiver ? transmitter ? baseband circuit ? synthesizer ? crystal oscillator ? low battery detect circuit ? wake-up timer ? clock output figure 3-12 shows the functions that are enabled using pmcreg. receiver: the rxcen bit, when set, enables the entire receiver chain. the re ceiver chain consists of a baseband circuit, synthesizer and crystal oscillator. transmitter: the txcen bit, when set, enables the entire transmit chain. the tran smit chain consists of a power amplifier, synthesizer, oscillator and transmit register. when the transmit chain and transmit register are enabled, any data in the transmit register is shifted out and a transmission is started. baseband circuit: the bbcen bit, when set, enables the baseband circuit. the baseband circuit, synthesizer and oscillator work together to demodulate and recover the data transmitted to the synthesizer (synen bit). if baseband circuits are enabled, then the oscillator (oscen bit) must be enabled in order to receive data. the bbcen bit can be disabled to reduce current consumption. synthesizer: the synen bit, when set, enables the synthesizer. the synthesizer is comprised of a pll, oscillator and vco for controlling the channel frequency. this bit must be enabled when either the transmitter or the receiver is enabled. the oscillator must also be enabled to provide the reference frequency for the pll. on power-up, the synthesiz er automatically performs the calibration. if there are significant changes in voltage or temperature, recalibration can be performed by disabling and re-enabling the synthesizer. crystal oscillator: the oscen bit, when set, enables the oscillator circuit. the oscillator provides the reference signal to the synthesizer when setting the transmit or receive frequency of use. low battery detect circuit: the lbden bit, when set, enables the battery vo ltage detect circuit. the battery detector can be programmed to 32 different threshold levels. see register 2-16 (bcsreg) for programming details. wake-up timer: the wuten bit, when set, enables the wake-up timer. see register 2-14 (wtsreg) for details on programming the wake-up timer interval. clock output: the clkoen bit, when set, disables the oscillator clock output. on device reset or power-up, the clock output is enabled so that a processor can begin execution of any special setup sequences as required by the designer. see register 2-16 (bcsreg) for programming details. the rf front end is comprised of the lna and the mixer. the synthesizer block has two main components: the vco and the pll. the baseband section consists of a baseband amplifier, low-pass filter, limiter and i/q demodulator. the synthesizer also has an internal start-up calibration procedure. if quick rx/tx switching is needed, leave this block on. enabling the transmitter using the txcen bit (pmcreg<5>) will turn on the pa, and since the synthesizer is already up and running, the pa immediately produces the tx signal at the output. to decrease the tx/rx turnaround time, keep the baseband section on. switching to receive mode means disabling the pa and enabling the rf front end. since the baseband block is already on, the internal start-up calibration is skipped, and thus, the turnaround time is shorter. the bbcen, synen and oscen bits are provided to optimize t he tx to rx or rx to tx turnaround time. the crystal oscillator provides a reference signal to the rf synthesizer, baseband circuit and digital signal processor. if the receiver or the transmitter is frequently used, it is recommended to leave the oscillator running as the crystal might need a few milliseconds to start. the start timing mainly depends on the crystal parameters. note: if bit 0 is cleared, and with the clock output enabled, the oscillator continues to run even if the oscen bit is cleared. the device will not fully enter sleep mode. note: leaving blocks unnecessarily turned on increases the current consumption, and thus, decreases the battery life. mrf49xa ds70590c-page 62 preliminary ? 2009-2011 microchip technology inc. from pmcreg, the following points are applicable when using the bit functionalities: ? the chip enters receive mode if both the txcen and rxcen bits are set. ? fsk/data/fsel input is equipped with an internal pull-up resistor. to achieve minimum current consumption, do not pull this input to logic low in sleep mode. ? to enable the rf synthesizer, the crystal oscillator must be turned on. ? to turn on the baseband circuits, the rf synthesizer and the crystal oscillator must be enabled. ? setting the rxcen bit automatically turns on the crystal oscillator, synthesizer, baseband circuits and rf front end. ? setting the txcen bit autom atically turns on the crystal oscillator, synthesizer and rf power amplifier. the clock tail and automatic crystal enable/disable features help in reducing the power consumption and are discussed in detail in section 3.4, crystal oscillator and clock output . the registers associated with power management are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 63 mrf49xa figure 3-12: logic connections between power control bits edge detector enable crystal oscillator enable baseband circuits (rf synthesizer must be on) enable rf front end enable rf synthesizer (crystal synthesizer must be on) (if tx latch is used) clear tx latch start tx enable power amplifier txcen synen rxcen bbcen oscen pa tx latch vco and pll crystal oscillator lna i/q demod. digital signal processing enable rf front end enable power amplifier enable rf synthesizer start tx clear tx latch enable crystal oscillator enable baseband circuits mrf49xa ds70590c-page 64 preliminary ? 2009-2011 microchip technology inc. 3.15 low duty cycle mode in low duty cycle mode, the receiver periodically wakes up for a short period and checks for the valid fsk transmission in progre ss. the fsk transmission is detected in the frequency range determined by cfsreg and the baseband filter bandwidth is determined by the rxcreg. the on time is automatically extended until the dqi indicates a good received signal condition. the following facts need to be considered while calculating the duty cycle on-time: ? the crystal oscillator, the synthesizer and the pll need time to start (see table 5-7 ). ? depending on the dqti, the device needs to receive few valid data bits before the dqi signal indicates a good signal condition (see register 2-8 ). selecting a short on-time can prevent the crystal oscillator from starti ng, or the dqi signal will not go high even when the received signal has a good quality. the mrf49xa is normally configured to work in fifo mode. however, when the device periodically wakes up from sleep mode, it switches to the receive mode. if valid fsk data is received, the device sends an interrupt to the microcontroller and continues filling the rxfifo. on completion of transmission, the fifo is read out completely and all other interrupts are cleared. the device then returns to the low-power consumption mode. figure 3-13 depicts the low-power duty cycle mode sequence. the low duty cycle is calculated by using the dcmv (dcsreg<7:1>) and wtmv (wtsreg<7:0>) bits, as shown in equation 3-3 . the time cycle is determined by the wtsreg. equation 3-3: the registers associated with low duty cycle mode are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? rcxreg (see register 2-7 ) ? bbfcreg (see register 2-8 ) ? pmcreg (see register 2-13 ) ? wtsreg (see register 2-14 ) figure 3-13: low-power duty cycle mode sequence note: in duty cycle mode, the rxcen bit must be cleared and the wuten bit must be set in pmcreg. dc = (dcmv<7:1> x 2 + 1)/wtmv<7:0> x 100% transmitter receiver receiving dqi iro microcontroller operation fifo read fifo read b. packet packet a packet a packet a packet a packet a t wake -up b. b. b. b. packet start/send start/send ? 2009-2011 microchip technology inc. preliminary ds70590c-page 65 mrf49xa 3.16 sleep, wake-up and battery operations the advanced interrupt handler circuit is configured in the transmitter to reduce the power consumption. as mentioned, the sleep mode is the lowest power consumption mode in which the clock and all functional blocks of the device are disabled. in case of any interrupt, the device wakes up, switches to active mode and an interrupt signal generated on the iro pin indicates the change in state to the host microcontroller. the source of the interrupt can be determined by reading the status word of the device (see register 2-1 ). to reduce current consumption, the mrf49xa should be placed in the low-power consuming sleep mode. in sleep mode, the 10 mhz main oscillator is turned off, disabling the rf and baseband circuitry. data is retained in the control and fifo registers and the transceiver is accessible through the spi port. the mrf49xa will not enter sleep mode if any of the interrupt remains active, irrespective of the state of the oscen bit in the pmcreg. this way, the microcontroller can always have a clock signal to process the interrupt. to prevent high-current consumption, which results in shorter battery life, it is highly recommended to process and clear interrupts before entering sleep mode. the functions which are not necessary should be turned off to avoid unwanted interrupts. to minimize the current consumption, the mrf49xa supports different power-saving modes, along with an integrated wake-up timer. active mode can be reinitiated by the following ways: ? by applying the wake-up events? negative logical pulse on int pin ? wake-up timer time-out ? low supply voltage detection ? on-chip fifo filled up ? on receiving a request through the serial interface to make the mrf49xa device enter into sleep mode, certain control register val ues must be initialized. the sequence to program the control registers for entering into sleep and wake-up modes is as follows: for sleep mode: 1. check the iro bit status 2. read stsreg 3. configure gencreg 4. configure pmcreg for oscillator and clock buffering for wake-up mode: 1. enter in tx/rx mode or 2. enable crystal or 3. set the int pin the device has the ability to wake itself up from sleep mode through a wake-up timer. the wtsreg sets the wake-up interval for the mrf49xa. after setting the wake-up interval, the wuten bit (pmcreg<1>) should be cleared and set at the end of every wake-up cycle. the wake-up duration time (wutime) is calculated as shown in equation 3-4 . equation 3-4: the battery threshold dete ct feature is useful in monitoring the discharge-sens itive batteries, such as lithium cells. the lbden bit (pmcreg<2>) is used to enable or disable the low battery detect feature. the bcsreg configures the following: ? output clock frequency ? low battery detect threshold the low battery threshold value is programmable from 2.2v to 3.8v and is calculated by using equation 3-5 . equation 3-5: when the battery level falls 50 mv below this value, the lbtd bit (stsreg<10>) is set, indicating that the battery level is below the programmed threshold. the registers associated with power-saving modes are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? txcreg (see register 2-4 ) ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) ? wtsreg (see register 2-14 ) ? bcsreg (see register 2-16 ) wutime = 1.03 x wtmv<7:0> x 2 wtev<4:0> + 0.5 ms where: wtmv<7:0> = decimal value between 0 to 255 wtev<4:0> = decimal value between 0 to 29 note: wutime is measured in ms. threshold voltage value = 2.25 + 0.1 x (lbdvb<3:0>) where: lbdvb<3:0> is the decimal value from 0-15 mrf49xa ds70590c-page 66 preliminary ? 2009-2011 microchip technology inc. 3.17 tx register buffered data transmission in data transmission mode (enabled by the txden bit (gencreg<7>)), the tx data is clocked into one of the two 8-bit data registers. the transmitter starts to send the data from the first register (with the given bit rate) when the txcen bit (pmcreg<5>) is set. the initial value of the data registers (0xaa) can be used to generate preamble. during this mode, the sdo pin is monitored to check whether the register is ready (sdo is high) to receive the next byte from the microcontroller. the block diagrams of the transmit register, before and during transmit, are shown in figure 3-14 and figure 3-15 , respectively. the transmitter fsk modulation parameters are used for calculating the resulting output frequency, as shown in equation 3-6 . equation 3-6: figure 3-14: tx register blo ck diagram (before transmit) f fskout = f 0 + (-1)sign x (mb + 1) x (15 khz) where: f 0 is the channel center frequency (see register 2-6 for f 0 calculation) mb is the 4-bit binary number (modbw<3:0>) sign = modply xor fsk 8-bit shift register (default: aah) 8-bit shift register (default: aah) serial bus data sclk clk sdi clk sdi sdo sdo tx_data txcen = 0 (register initial fill-up) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 67 mrf49xa figure 3-15: tx register blo ck diagram (during transmit) 8-bit shift register sclk serial bus data clk sdi clk sdi sdo sdo tx_data mux sel 11 10 y sel 11 10 y sel 11 10 y mux mux txcen = 1 (during tx) 8-bit shift register 1:8 bit rate divider note: the data registers? content is initialized by clearing the txcen bit. mrf49xa ds70590c-page 68 preliminary ? 2009-2011 microchip technology inc. the device transmit sequence should be performed as follows: 1. enable the tx register by setting txden = 1. 2. the tx register is automatically filled with 0xaaaa, which can be used to generate preamble. 3. enable the transmitter by setting txcen = 1 . 4. the synthesizer and the pll turns on, calibrates itself and the pa is automatically enabled. 5. the tx data transmission starts. 6. on completion of byte transmission, the iro pin goes high and the sdo pin goes low simultaneously. the iro pulse shows that the first 8 bits (the first byte by default, 0xaa) have been transmitted. there are still 8 bits in the transmit register. 7. the microcontroller recognizes the interrupt and writes a data byte to the txbreg. 8. repeat steps 6 and 7 until the last data byte is reached. 9. using the same method, transmit a dummy byte. the value of this dummy byte can be anything. 10. the next high-to-low transition on the iro line (or low-to-high on the sdo pin) shows that the transmission of the data bytes has ended. the dummy byte is still in the tx latch. 11. turn off the transmitter by setting the bit, txcen = 0 . this event probably happens while the dummy byte is being transmitted. since the dummy byte contains no useful information, this corruption will not cause any problem. 12. clearing the txden bit clears the register underrun interrupt. the iro pin goes high and the sdo pin goes low. the transmit sequence is illustrated in figure 3-16 . for details on transmit pin function configuration, see table 3-3 . the txden bit is in the gencreg register and enables the transmit data register. the transmit sequence can be performed without sending a dummy byte (step 1), but after loading the last data byte to the transmi t register, the pa turn off should be delayed for at least 16 bits time. the microcontroller clock source (if the clock is not supplied by the transceiver) should be stable enough over temperature and voltage ranges to ensure this minimum delay under all operating circumstances. when the dummy byte is us ed, the whole process is driven by interrupts. changing the tx data rate has no effect on the algorithm and no accurate delay measurement is needed. figure 3-17 shows the multi-byte transmit write sequence. the registers associated with transmission are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? txcreg (see register 2-4 ) ? txbreg (see register 2-5 ) ? pmcreg (see register 2-13 ) table 3-3: transmit pin function vs . operation mode mode bit setting function pin 6 pin 7 transmit txden = 0 internal tx data register disabled tx data input not used txden = 1 internal tx data register enabled fsel input (tx data register can be accessed) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 69 mrf49xa figure 3-16: tx register usage figure 3-17: multiple byte write with transmit register spi commands gencreg pmcreg tx latch tx latch pmcreg gencreg txden = 1 tx byte 1 dummy tx byte txcen = 0 txden = 0 txcen = 1 synt. pa t tx_xtal_on (1) txcen enable synthesizer/pa 0xaa fraction of the dummy byte 0xaa tx byte1 tx data sdo (2) do not switch the txcen off here, because the tx byte 1 is not transmitted out, it is only stored in the internal register enabling the transmitter preloads the tx latch with 0xaaaa (cs, sck, sdi) note 1: ttx_xtal_on is the start-up time of pll + pa with a running crystal oscillator. 2: sdo is a tri-state of cs. iro * the device is in transmit (tx) mode when the rxcen bit is cleared using the pmcreg. transmit register write tx byte 1 tx byte 2 tx byte n sdo (register interrupt in tx mode*) sck sdi cs mrf49xa ds70590c-page 70 preliminary ? 2009-2011 microchip technology inc. 3.18 rx fifo buffered data read in the receive operating mode, the incoming data is clocked into a 16-bit fifo buffer. the receive pin function configuration required for the fifo operation is given in table 3-4 . the fifoen bit is in the gencreg register and enables the receive fifo. the receiver starts to fill the fifo when the fintdio bit and the synchronous pattern recognition circuit indicates the potential real incoming data. this prevents the fifo from being filled with noise and avoids the overloading on the external microcontroller. the internal synchronous pattern and the pattern length are user-programmable. if the chip select (cs ) pin is low, the data bits on the sdi pin are shifted into the device on the rising edge of the clock on the sck pin. the serial interface is initialized every time if the cs signal is high. figure 3-18 shows a simple receiver fifo read over spi lines. in general, mrf49xa registers are read only. the rxfifo and the chip status can be read. during write only appropriate byte is written to the desired register. hence it is not desired to read/write all registers and there is no way reading back any of the other registers. to test the spi interface lines, the best is to set the lbd (low battery detector) threshold below the actual vdd and the device must generate an interrupt. figure 3-18: receiver fifo read sdo sck msb sdi lsb 0 txrxfifo 1 3 4 2 5 6 7 8 9 10 11 12 13 14 15 received bits out note: the transceiver is in receive (rx) mode when the rxcen bit is set using the pmcreg. cs (tx/rx mode) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 71 mrf49xa 3.18.1 interrupt mode the user can define the fifo interrupt level (the number of received bits) which generates the fint when the level is exceeded. in this case, the status bits report the changed fifo status. 3.18.2 polling mode when the fsel signal is low, the fifo output is connected directly to the sdo pin and its contents are clocked out by the sck pin. set the fifo interrupt level to 1. in this case, as long as fint indicates received bits in the fifo, the microcontroller continues to take the bits away. when fint goes low, no more bits need to be taken. an spi read command (receiver fifo read command) is also available to read out the contents of the fifo. see figure 3-19 for a simple receiver fifo read, in polling mode, on spi lines. figure 3-19: fifo read example with fint polling the registers associated with reception are: ?stsreg (see register 2-1 ) ? gencreg (see register 2-2 ) ? rxcreg (see register 2-7 ) ? fiforstreg (see register 2-10 ) ? pmcreg (see register 2-13 ) table 3-4: receive pin function vs . operation mode mode bit setting function pin 6 pin 7 receive fifoen = 0 receiver fifo disabled rx data output rx data clock output fifoen = 1 receiver fifo enabled fsel input (rx data fifo can be accessed) fint output fo + 2 fo + 3 fo + 1 fifo out fo + 4 fifo read out 0123 4 sck sdo fint fsel cs note: during fifo access, f sck cannot be higher than f ref /4, where f ref is the crystal oscillator frequency. if the duty cycle of the clock signal is not 50%, the shorter period of the clock pulse should be at least 2/f ref . mrf49xa ds70590c-page 72 preliminary ? 2009-2011 microchip technology inc. 3.19 rx-tx frequency alignment method the rx-tx frequency offset occurs due to the differences in the actual reference frequency. to minimize this error, the same crystal type and the same pcb layout should be used fo r the crystal placement on the rx and tx pcbs. also, see section 3.6, crystal selection guidelines . to verify the possible rx-tx offset, it is recommended to measure the clk output of both transceivers with a high level of accuracy. do not measure the output at the rfxtl pin as the measurem ent process itself might change the reference frequency. as the carrier frequencies are derived from the reference frequency, having identical reference frequencies, and nominal frequency settings at the tx and rx side, there should be no offset if the clk signals have identical frequencies. the crystal oscillator load capacitor bank value is to fine-tune the oscillator and minimize the offset. so the process is to measure the clock output and parallel change the value to minimize the offset. the actual rx-tx offset can be monitored by using the afc status data included in the stsreg of the receiver. by reading out the stsreg, the actual measured offset frequency can be reported. in order to get accurate values, the afc has to be disabled during the read by clearing the fofen bit in afccreg. the registers associated with rx-tx alignment procedures are: ?stsreg (see register 2-1 ) ? afccreg (see register 2-3 ) ? rxcreg (see register 2-7 ) ? pmcreg (see register 2-13 ) ? 2009-2011 microchip technology inc. preliminary ds70590c-page 73 mrf49xa 4.0 application details the application circuit of mrf49xa with a balun circuit is shown in figure 4-1 . figure 4-1: application circuit 4.1 antenna/balun a balun circuit for a 50 antenna is shown in figure 4-2 . if low tolerance components (i.e., 5%) are used with an appropriat e ground, the impedance remains close to the 50 measurement. figure 4-2: balun circuit 1 2 3 4 16 15 14 13 12 11 10 9 5 6 7 8 mrf49xa rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 osc1 pic ? mcu c4* 2.2 nf c1 2.2 uf v dd c3 0.01 uf c2 (see table 2-2) 50 ohm loop antenna x1 10 mhz * connections are optional. mclr _____ sdi sck sdo rclkout/fcap/fint* clkout* balun int/d io * iro cs fsk/data/fsel* reset* +3.3v c5 c6 50 ant j1 l1 l2 l3 rfn rfp freq. l1 l2 l3 c5 c6 c7 433 mhz 390 nh 33 nh 47 nh 68 pf 2.7 pf 5.1 pf 868 mhz 100 nh 8.2 nh 22 nh 1.2 pf 27 pf 2.7 pf 915 mhz 100 nh 8.2 nh 22 nh 1.2 pf 27 pf 2.7 pf c7 mrf49xa ds70590c-page 74 preliminary ? 2009-2011 microchip technology inc. 4.2 antenna design considerations the mrf49xa is designed to drive a differential output, such as a dipole antenna or a loop antenna. the loop antenna is ideally suited for applications where compact size is required. the dipole is typically not a good option for compact designs due to its inherent size at resonance, and it s space requirements around the ground plane, to be an efficient antenna. a monopole antenna can be used, along with a balun, or by using the matching circuit. 4.3 rf transmitter matching the rf pins are of high impedance and differential value. the optimum differential load for the rf port at a given frequency band is shown in ta b l e 4 - 1 . these load values in the table are expected by the rf port pins to have as an antenna load for maximum power transfer. antennas that are suited for such values would be a loop, dipole and folded dipole. for all antenna applications, eith er a bias, choke inductor or coils must be included during transmission since the rf outputs are of open-collector type. 4.4 general pcb layout design the guidelines in this section help the users in high-frequency pcb layout design. the printed circuit board is usually comprised of two or four basic fr4 layers. the two-layer printed circuit board has mixed signal/power/rf and common ground routed in both the layers. the four-layer printed circuit board is comprised of the following layers: ? signal layout ? rf ground ? power line routing ? common ground the four-layer pcb is shown in figure 4-4 . figure 4-3: two basic copper fr4 layers figure 4-4: four ba sic copper fr4 layers table 4-1: frequency band ? antenna admittance/impedance mrf49xa admittance (ms) impedance ( ) inductance (nh) 433 mhz 2?j5.9 52+j152 62 868 mhz 1.2?j11.9 7.8+j83 15.4 915 mhz 1.49?j12.8 9+j77 13.6 signal/power/rf and common ground dielectric constant = 4.5 signal/power/rf and common ground ground power line routing rf ground signal layout dielectric constant = 4.5 dielectric constant = 4.5 dielectric constant = 4.5 ? 2009-2011 microchip technology inc. preliminary ds70590c-page 75 mrf49xa the following guidelines explain the requirements of the above mentioned layers. ? it is important to keep the original pcb thickness, since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines? characteristic impedance. ? for good transmit and receive performance, the trace lengths at rf pins must be kept as short as possible. using small, surface mount components (in 0402/0603 package) yields good performance and keeps the rf circuit small. rf connections should be short and direct. ? except for the antenna layout, avoid sharp corners since they can act as an antenna. round corners will eliminate possible future emi problems. ? digital lines are prone to be very noisy when handling periodic waveforms and fast clock/switching rates. avoid rf signal layout close to any of the digital lines. ? a via filled ground patch underneath the ic transceiver is mandatory. ? power supply must be distributed to each pin in a star topology and low-esr capacitors must be placed at each pin for proper decoupling noise. ? thorough decoupling on each power pin is beneficial for reducing in-band transceiver noise, particularly when this noise degrades perfor- mance. usually, low value caps (27 pf ? 47 pf) combined with large value caps (100 nf) will cover a large spectrum of frequency. ? passive component (inductors) should be in the high-frequency category and the self resonant frequency (srf) should be at least two times higher than the operating frequency. ? the additional trace length affects the crystal oscillator by adding parasitic capacitance to the overall load of the crystal. to minimize this, place the crystal as close as possible to the rf device. ? setting short and direct connections between the components on board minimizes the effects of ?frequency pulling? that might be introduced by stray capacitance. it even allows the internal load capacitance of the chip to be more effective in properly loading the crystal oscillator circuit. ? long run tracks of clock signal may radiate and cause interference. this can degrade receiver performance and add harmonics or unwanted modulation to the transmitter. ? keep clock connections as short as possible and surround the clock trace with an adjacent ground plane pour. pouring helps in reducing any radiation or crosstalk due to long run traces of the clock signal. ? low value decoupling capacitors, typically 0.01 f ? 0.1 f, should be placed for v dd of the chip and for bias points of the rf circuit. ? high value decoupling capacitors, typically 2.2 f ? 10 f, should be placed at the point where power is applied to the pcb. ? power supply bypassing is necessary. poor bypassing contributes to conducted interference which can cause noise and spurious signals to couple into the rf sections, significantly reducing performance. mrf49xa ds70590c-page 76 preliminary ? 2009-2011 microchip technology inc. 4.5 mrf49xa schematic and bill of materials 4.5.1 schematic figure 4-5: mrf49xa schematic +3.3v +3.3v fint fsel rese t rssio int/dio sdo cs sck sdi c4 1000 pf c1 c2 0.01 uf c7 c5 c6 c3 2.2 uf 6.3v 50 ant j1 l1 l2 l3 tp1 clk tp2 gnd mrf49x a u1 sdi sck sdo iro fsk/d ata/ rclk out/fcap/fint clk out int/dio rssio vdd rfn rfp vss rfx tl/ex tref 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 x1 10 mhz freq. l1 l2 l3 c5 c6 c7 433 mhz 390 nh 33 nh 47 nh 68 pf 2.7 pf 5.1 pf 868 mhz 100 nh 8.2 nh 22 nh 1.2 pf 27 pf 2.7 pf c1 47 pf 220 pf 915 mhz 100 nh 8.2 nh 22 nh 1.2 pf 27 pf 2.7 pf 33 pf cs __ __ __ __ iro __ __ fsel ___ ___ rese t ____ ? 2009-2011 microchip technology inc. preliminary ds70590c-page 77 mrf49xa 4.5.2 bill of materials table 4-2: mrf49xa: 433 mhz bill of materials designator value description manufacturer manufacturer pn c1 200 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h201ja01d c5 2.7 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h2r7cz01d c6 68 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h680ja01d c7 5.1 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h5r1dz01d l1 390 nh inductor, ceramic, 5%, smt 0603 murata lqw18anr39j00d l2 33 nh inductor, multilayer, 5%, smt 0603 tdk corporation mlg1608b33nj l3 47 nh inductor, multilayer, 5%, smt 0603 tdk corporation mlg1608b47nj c4 1000 pf capacitor, ceramic, 50v, 10%, smt 0603, x7r murata grm188r71h102ka01d c2 10000 pf capacitor, ceramic, 50v, 10%, smt 0603, x7r murata grm188r71h103ka01d c3 2.2 f, 10v capacitor, tantalum, 10%, smt 3216-18 (a) kemet t491a225k010at u1 ? mrf49xa transceiver microchip mrf49xa-i/st x1 10 mhz crystal, 10 ppm, 10 pf, smt 5 x 3.2 mm abracon abm3b-10.000mhz-12-r8 0-b-1-u-t mrf49xa ds70590c-page 78 preliminary ? 2009-2011 microchip technology inc. table 4-3: mrf49xa: 868/915 mhz bill of materials designator value description manufacturer manufacturer pn c1 33 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h330ja01d c5 1.2 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h1r2cz01d c6 27 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h270ja01d c7 2.7 pf capacitor, ceramic, 50v, c0g, smt 0603 murata grm1885c1h2r7cz01d l1 100 nh inductor, multilayer, 5%, smt 0603 tdk corporation mlg1608br10j l2 8.2 nh inductor, multilayer, 5%, smt 0603 tdk corporation mlg1608b8n2d l3 22 nh inductor, multilayer, 5%, smt 0603 tdk corporation mlg1608b22nj c4 1000 pf capacitor, ceramic, 50v, 10%, smt 0603, x7r murata grm188r71h102ka01d c2 10000 pf capacitor, ceramic, 50v, 10%, smt 0603, x7r murata grm188r71h103ka01d c3 2.2 f, 10v capacitor, tantalum, 10%, smt 3216-18 (a) kemet t491a225k010at u1 ? mrf49xa transceiver microchip mrf49xa-i/st x1 10 mhz crystal, 10 ppm, 10 pf, smt 5 x 3.2 mm abracon abm3b-10.000mhz-12-r80- b-1-u-t ? 2009-2011 microchip technology inc. preliminary ds70590c-page 79 mrf49xa 5.0 electrical characteristics absolute maximum ratings (?) temperature under bias ...... .............. .............. .............. .............. ........... ........... ............ ......... .................. -40c to +85c storage temperature ............................................................................................................ .................. -55c to +125c lead temperature (soldering, max 10s) .......................................................................................... ..................... +260c voltage on v dd with respect to v ss ............................................................................................................... -0.3v to 6v voltage on any combined digital and analog pin with respect to v ss (except rfp, rfn and v dd ) ........................................................................................................... -0.3v to (v dd + 0.3v) voltage on open-collector outputs (rfp, rfn) (1) ........................................................................... -0.5v to (v dd + 1.5v) input current into pin (except v dd and v ss ).......................................................................................... -25 ma to 25 ma electrostatic discharge with human body model .................................................................................. .................. 1000v note: at maximum, voltage on rfp and rfn cannot be higher than 7v. ? notice: stresses above those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. mrf49xa ds70590c-page 80 preliminary ? 2009-2011 microchip technology inc. table 5-1: recommended operating conditions note 1: at minimum, v dd ? 1.5v cannot be lower than 1.2v. 2: at maximum, v dd + 1.5v cannot be higher than 5.5v. table 5-2: current consumption (1) note 1: typical values: t a = 25c, v dd = 3.3v. note 1: typical values: t a = 25c, v dd = 3.3v. 2: negative current is defined as the current sourced by the pin. parameters min typ max unit operating temperature -40 ? +85 c supply voltage for rf, analog and digital circuits 2.2 ? 3.8 v supply voltage for digital i/o 2.2 3.3 3.8 v dc voltage on open-collector outputs (rfp, rfn) (1,2) v dd ?1.5 ? v dd +1.5 v ac peak voltage on open-collector outputs (rfp, rfn) (1) v dd ?1.5 ? v dd +1.5 v chip mode condition min typ max unit sleep sleep clock disabled, all blocks disabled ? 0.3 1 a idle oscillator and baseband enabled, clock output disabled ?0.61.2ma tx power output ? 0 dbm, 50 ? load, 433 mhz ? 15 ? ma 868 mhz ? 16 ? ma 915 mhz ? 17 ? ma tx at maximum output power, 433 mhz ? 22 26 ma 868 mhz ? 23 27 ma 915 mhz ? 24 28 ma rx 433 mhz ? 11 13 ma 868 mhz ? 12 14 ma 915 mhz ? 13 15 ma low battery voltage detector current consumption ??0.51.7 a wake-up timer current consumption ??1.53.5 a table 5-3: i/o pin input specifications (1) symbol characteristic condition min typ max unit v il input low voltage ? ? ? 0.3xv dd v v ih input high voltage ? 0.7xv dd ??v i il input low leakage current (2) v il = 0v -1 ? 1 a i ih input high leakage current v ih = v dd , v dd = 3.8v -1 ? 1 a v ol digital low output voltage l ol = 2 ma ? ? 0.4 v v oh digital low output i oh = -2 ma v dd ?0.4 ? ? v v lbtd low battery threshold detect programmable in 0.1v steps 2.25 ? 3.75 v ? 2009-2011 microchip technology inc. preliminary ds70590c-page 81 mrf49xa note 1: typical values: t a = 25c, v dd = 3.3v. 2: ber = 10e ? 3, bw = 67 khz, f = 30 khz, baud rate = 1.2 kbps, digital filter with afc disabled. table 5-4: receiver ac characteristics (1) parameters condition min typ max unit receiver sensitivity 433 mhz band (2) ?-112?dbm 868 mhz band (2) ?-110?dbm 915 mhz band (2) ? -109 ? dbm maximum rf input power lna: high gain 0 ? ? dbm rf input capacitance ? ? 1 ? pf receiver spurious emission ???-60dbm receiver bw mode 0 ? 67 ? khz mode 1 ? 134 ? khz mode 2 ? 200 ? khz mode 3 ? 270 ? khz mode 4 ? 340 ? khz mode 5 ? 400 ? khz rssi range ? ? 46 ? db rssi error ? ? 6 ? db rssi power supply dependency when input signal level is lower than -54 dbm and greater than -100 dbm ?+35?mv/v filter capacitor for analog rssi ?1??nf rssi programmable level steps ??6?db digital rssi response time until the rssi signal goes high after the input signal exceeds the preprogrammed limit, carrsi = 4.7 nf ? 500 ? s input ip3 in band interferers in high bands (868 mhz, 915 mhz) ?-21?dbm iip3 (lna ? 6 db gain) in band interferers in low band (433 mhz) ?-15?dbm iip3 (lna ? 6 db gain) out of band interferers, l f-f o l > 4 mhz ?-12?dbm fsk bit rate with internal digital filters supported by design 0.6 ? 115.2 kbps fsk bit rate with internal analog filters supported by design ??256kbps afc locking range f fsk : fsk deviation in the received signal ? 0.8 ? f fsk ?? mrf49xa ds70590c-page 82 preliminary ? 2009-2011 microchip technology inc. note 1: typical values: t a = 25c, v dd = 3.3v. table 5-6: pll parameters ac characteristics (1) note 1: typical values: t a = 25c, v dd = 3.3v. table 5-5: transmitter ac characteristics (1) parameters condition min typ max unit rf carrier frequency 433 mhz band, 2.5 khz resolution 430.24 ? 439.75 mhz 868 mhz band, 5.0 khz resolution 860.48 ? 879.51 mhz 915 mhz band, 7.5 khz resolution 900.72 ? 929.27 mhz maximum rf output power 433 mhz @ 50 load ? 7 ? dbm 868 mhz @ 50 load ? 5 ? dbm 915 mhz @ 50 load ? 5 ? dbm rf output power control range in steps of 8 p max ? 17.5 ? p max dbm tx gain control resolution programmed in 8 steps ? 2.5 ? db harmonic suppression at maximum power, 50 load ? ? -35 dbc open-collector output dc current programmable 0.5 ? 6 ma spurious emission | f-f sp | > 1 mhz at maximum power, 50 load ? ? -55 dbc output capacitance (set by the automatic antenna tuning circuit) 433 mhz band 2 2.6 3.2 pf 868 mhz band 2.1 2.7 3.3 pf 915 mhz band 2.1 2.7 3.3 pf quality factor of the output capacitance 433 mhz band 13 15 17 ? 868 mhz band 8 10 12 ? 915 mhz band 8 10 12 ? output phase noise 100 khz from carrier ? -80 ? dbc/hz 1 mhz from carrier ? -103 ? dbc/hz fsk bit rate internal tx data register ? ? 172 kbps fsk bit rate tx data connected to the fsk input ? ? 256 kbps fsk frequency deviation programmable in 15 khz steps 15 ? 240 khz parameters condition/note min typ max unit pll reference frequency crystal related timing and fre- quency parameters change according to the pll reference frequency 91011mhz pll lock time frequency error <1 khz after 10 mhz step ?30? s pll start-up time with a running crystal oscillator and based on the design ? 200 300 s ? 2009-2011 microchip technology inc. preliminary ds70590c-page 83 mrf49xa table 5-7: other timing parameters ac characteristics (1) note 1: typical values: t a = 25c, v dd = 3.3v. 2: the crystal oscillator start-up time depends on the capa citance seen by the oscillator. low capacitance and low-esr crystal are recommended with low parasitic pcb layout design. 3: during the power-on reset period, commands are not acc epted by the chip. in case of software reset (see wtsreg ( register 2-14 )), the reset time-out is typically 0.25 ms. parameters condition min typ max unit transmitter switch on time synthe sizer off, crystal oscillator on with 10 mhz step ?250? s receiver switch on time synthe sizer off, crystal oscillator on with 10 mhz step ?250? s transmitter to receiver switch time synthesizer and crystal oscillator on during tx/rx change with 10 mhz step ?150? s receiver to transmitter switch time synthesizer and crystal oscillator on during rx/tx change with 10 mhz step ?150? s crystal load capacitance (see crystal selection guide) programmable in 0.5 pf steps, tolerance 10% 8.5 ? 16 pf crystal oscillator start-up time default capacitance bank setting, crystal esr <50 . crystal load capacitance = 16 pf. (2) ?2 7ms internal por time-out after v dd has reached 90% of the final value (3) ??100ms wake-up timer clock accuracy crystal oscillator must be enabled to ensure proper calibration at the start-up (2) ?10? % digital input capacitance ? ? ? 2 pf digital output rise/fall time 15 pf pure capacitive load ? ? 10 ns mrf49xa ds70590c-page 84 preliminary ? 2009-2011 microchip technology inc. 5.1 timing specification and diagram figure 5-1: spi timing diagram table 5-8: spi timing specification symbol parameter minimum value (ns) t ch clock high time 25 t cl clock low time 25 t ss select setup time (cs falling edge to sck rising edge) 10 t sh select hold time (sck falling edge to cs rising edge) 10 t shi select high time 25 t ds data setup time (sdi transition to sck rising edge) 5 t dh data hold time (sck rising edge to sdi transition) 5 t od data delay time 10 t ch t ss t cl t shi t ds t dh t cd sck sdi sdo bit 15 txrxfifo bit 14 bit 8 bit 13 bit 7 bit 1 bit 0 por txowrxof offsb(0) dqdo fifo out t sh cs atrssi ? 2009-2011 microchip technology inc. preliminary ds70590c-page 85 mrf49xa 5.2 typical performance characteristics figure 5-2: channel selectivity and blocking (1,2) 0 10 20 30 40 50 60 70 80 0123456789101112 cw interferer offset with respect to carrier (mhz) suppre ssi on (db) 434 mhz 868 mhz et si note 1: lna gain maximum, filter bandwidth 67 khz, data rate 9.6 kbps, afc switched off, fsk deviation 45 khz, v dd = 2.7v. 2: the etsi limit given in the figure is drawn by taking -106 dbm at 9.6 kbps typical sensitivity into account and corresponds to receiver class 2 requirements. mrf49xa ds70590c-page 86 preliminary ? 2009-2011 microchip technology inc. figure 5-3: ber cur ves in 433 mhz band figure 5-4: ber cur ves in 868 mhz band ber curves in 433 mhz band 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 -120 -115 -110 -105 -100 -95 -90 input power (dbm) ber 1.2k 9.6k 19.2k 115.2k ber curves in 868 mhz band 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 -115 -110 -105 -100 -95 -90 -85 input power (dbm) ber 1.2k 9.6k 19.2k 115.2k ? 2009-2011 microchip technology inc. preliminary ds70590c-page 87 mrf49xa table 5-9 shows the optimal receiver bbbw and transmitter deviation frequency ( f fsk ) settings for different data rates, considering no tx/rx offset frequency. if the tx/rx offset (for example, due to crystal tolerances) has to be taken into account, increase the bw accordingly. table 5-9: rx bw and tx deviation frequency for different baud rates baud rate 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps bw in khz bw ? 67 bw ? 67 bw ? 67 bw ? 67 bw ? 67 bw ? 134 bw ? 134 bw ? 200 tx in khz f fsk ? 45 f fsk ? 45 f fsk ? 45 f fsk ? 45 f fsk ? 45 f fsk ? 90 f fsk ? 90 f fsk ? 120 mrf49xa ds70590c-page 88 preliminary ? 2009-2011 microchip technology inc. figure 5-5: receiver sensitivi ty over ambient temperature (433 mhz, 2.4 kbps, f fsk : 45 khz, bw: 67 khz) figure 5-6: receiver sensitivi ty over ambient temperature (868 mhz, 2.4 kbps, f fsk : 45 khz, bw: 67 khz) receiver sensitivity over ambient temperature for 433 mhz -115 -112 -109 -106 -103 -100 -50 -25 0 25 50 75 100 temperature (c) power level (dbm) 2.2v 2.7v 3.3v 3.8v receiver sensitivity over ambient temperature for 868 mhz -115 -112 -109 -106 -103 -100 -50 -25 0 25 50 75 100 temperature (c) power level (dbm) 2.2v 2.7v 3.3v 3.8v ? 2009-2011 microchip technology inc. preliminary ds70590c-page 89 mrf49xa 6.0 packaging information 6.1 package marking information legend: xx...x product-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb -free jedec designator ( ) can be found on the outer packaging for this package. note: in the event, the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custom er-specific information. 3 e 3 e 16-lead tssop xxxxxxxx yyww nnn example 49xa/st 0910 017 3 e mrf49xa ds70590c-page 90 preliminary ? 2009-2011 microchip technology inc. 6.2 package details this section provides the technical details of the packages. 16-lead plastic thin shrink small outline (st) C 4.4 mm body [tssop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2009-2011 microchip technology inc. preliminary ds70590c-page 91 mrf49xa 16-lead plastic thin shrink small outline (st) C 4.4 mm body [tssop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging mrf49xa ds70590c-page 92 preliminary ? 2009-2011 microchip technology inc. 16-lead plastic thin shrink small outline (st) C 4.4 mm body [tssop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2009-2011 microchip technology inc. preliminary ds70590c-page 93 mrf49xa appendix a: read sequence and packet structures figure 1 shows the stsreg read sequence with fifo read as an example. figure a-1: stsreg read sequence note: 1. applicable when the rxcen bit is set using the pmcreg. 2. applicable when the rxcen bit is cleared using the pmcreg. 3. these bits are internally latched and the other bits are only multiplexed out. sck 0 1 3 4 2 5 6 7 8 9 10 11 12 13 14 15 16 17 por txrxfifo clkrl txowr xof wuti nt lce xint lbtd fifo em atrs si dqdo offsv afcct (latched) offsb <3> offsb <2> offsb <1> offsb <0> fo fo+1 fo+2 (latched) (latched) (latched) (latched) (sign) command fifo out status bits out interrupt bits out sdi sdo cs (1)(2)(3) (1,2,3) (1,2,3) table a-1: recommended fifo packet structures length preamble synchronous word/network id payload crc minimum length 4-8 bits (0x0a or 0x05) 0xd4 (programmable) ? 4-bit-1 byte recommended length 8-12 bits (e.g., 0xaa or 0x55) 0x2dd4 (d4 is programmable) ? 2 bytes mrf49xa ds70590c-page 94 preliminary ? 2009-2011 microchip technology inc. notes: ? 2009-2011 microchip technology inc. preliminary ds70590c-page 95 mrf49xa appendix b: revision history revision a (march 2009) this is the initial released version of this document. revision b (june 2009) major updates are done th roughout the document. revision c (november 2011) minor corrections such as figures, language and formatting updates are incorporated throughout the document. mrf49xa ds70590c-page 96 preliminary ? 2009-2011 microchip technology inc. notes: ? 2009-2011 microchip technology inc. preliminary ds70590c-page 97 mrf49xa index a absolute maximum ratings ................................................ 79 ac characteristics other timing parameters............................................ 83 pll parameters .......................................................... 82 receiver...................................................................... 81 transmitter.................................................................. 82 antenna design considerations ......................................... 74 antenna/balun .................................................................... 73 automatic frequency control (afc) ............................. 14, 50 b baseband features............................................................... 3 baseband/data filtering ..................................................... 56 bill of materials.................................................................... 77 block diagrams afc circuit for frequency offset correction .............. 51 analog rssi voltage vs. rf input power................... 15 application circuit ....................................................... 73 balun circuit................................................................ 73 dio logic .................................................................... 58 four basic copper fr4 layers .................................. 74 functional node............................................................ 8 logic connection between power control bits .......... 63 mcu to mrf49xa interface ......................................... 8 mrf49xa architectural .............................................. 10 mrf49xa interrupt generation logic......................... 55 reset pin internal connection.................................. 45 two basic copper fr4 layers ................................... 74 tx register before transmit ...................................... 66 tx register during transmit ...................................... 67 c clock output ....................................................................... 11 clock recovery circuit (clkrc) ........................................ 14 crystal oscillator ................................................................. 14 crystal oscillator and clock output .................................... 47 crystal selection guidelines ............................................... 49 current consumption .......................................................... 80 customer change notification service ............................... 99 customer notification service............................................. 99 customer support ............................................................... 99 d data data in ........................................................................ 11 data out...................................................................... 11 data filtering and clock recovery ..................................... 14 analog operation ........................................................ 57 digital operation ......................................................... 57 data indicator output (dio) ................................................ 15 data quality indicator (dqi).......................................... 15, 58 data validity blocks data indicator output.................................................. 15 data quality indicator ................................................. 15 receive signal strength indicator............................... 15 e electrical characteristics..................................................... 79 errata .................................................................................... 5 examples frequency deviation and bbbw calculation.............. 56 external reference input .................................................... 12 f fifo interrupt ..................................................................... 11 frequency shift keying data ............................................................................ 11 fifo select ................................................................ 11 functional description ........................................................ 43 g general pcb layout deign ................................................ 74 h hardware description ........................................................... 9 i i/o pin input specifications................................................. 80 initialization ......................................................................... 52 internet address ................................................................. 99 interrupt .............................................................................. 12 interrupt request output .................................................... 11 interrupts ............................................................................ 52 clearing ...................................................................... 53 lbtd .......................................................................... 53 lcexint .................................................................... 53 por............................................................................ 53 setting ........................................................................ 53 txowrxof............................................................... 53 txrxfifo.................................................................. 53 wutint...................................................................... 53 l low duty cycle mode................................................... 16, 64 low noise amplifier (lna).................................................. 13 low-battery voltage detector............................................. 16 m memory organization ......................................................... 18 microchip internet web site................................................ 99 o output filter capacitor ........................................................... 11 p packaging details......................................................................... 90 marking....................................................................... 89 packaging information ........................................................ 89 performance characteristics ber curves in 433 mhz band................................................ 86 in 868 mhz band................................................ 86 channel selectivity and blocking ............................... 85 receiver sensitivity ov er ambient temperature at 433 mhz......................................................... 88 at 868 mhz......................................................... 88 phase locked loop (pll) ............................................ 14, 48 pin description.................................................................... 11 pin diagram .......................................................................... 4 pins clkout ..................................................................... 11 cs ............................................................................... 11 data .......................................................................... 11 fsk/data/fsel ........................................................ 11 int /dio ...................................................................... 12 iro ............................................................................. 11 rclkout/fcap/fint............................................... 11 mrf49xa ds70590c-page 98 preliminary ? 2009-2011 microchip technology inc. reset ........................................................................ 12 rfn............................................................................. 12 rfp ............................................................................. 12 rfxtl/extref ......................................................... 12 rssio......................................................................... 12 sck............................................................................. 11 sdi .............................................................................. 11 sdo ............................................................................ 11 v dd .............................................................................. 12 v ss .............................................................................. 12 power and low noise amplifiers ........................................ 47 power management ............................................................ 61 power-saving modes low battery voltage detector ..................................... 16 low duty cycle mode ................................................. 16 wake-up timer ........................................................... 16 programmable synchronous byte ...................................... 59 r reader response ............................................................. 100 receive fifo ...................................................................... 17 receive signal strength indicator (rssi) ........................... 15 received signal strength indicator (rssi) ......................... 59 recommended operating conditions ................................. 80 recovery clock output ....................................................... 11 register map....................................................................... 42 registers afccreg (automatic frequency control configuration) 22 bbfcreg (baseband filter configuration)................ 29 bcsreg (battery threshold detect and clock output value set) ........................................................... 40 cfsreg (center frequency value set) .................... 26 dcsreg (duty cycle value set) ............................... 39 drsreg (data rate value set) ................................ 35 fiforstreg (fifo and reset mode configuration) 32 gencreg (general configuration) ........................... 21 pllcreg (pll configuration) ................................... 41 pmcreg (power management configuration) .......... 36 rxcreg (receive control)........................................ 27 rxfiforeg (receiver fifo read)........................... 31 stsreg (status read) .......................................... 19 synbreg (synchronous byte configuration) ........... 34 txbreg (transmit byte)............................................ 25 txcreg (transmit configuration) ............................. 23 wtsreg (wake-up timer value set)........................ 38 reset power glitch reset ..................................................... 44 power-on reset .......................................................... 43 reset pin.................................................................. 45 software reset ........................................................... 45 reset mode selection ......................................................... 33 reset pin .......................................................................... 13 revision history .................................................................. 95 rf crystal ........................................................................... 12 rf transmitter matching..................................................... 74 rf/analog features .............................................................. 3 rx fifo buffered data read ............................................. 70 rx-tx frequency alignment method ................................. 72 s schematics mrf49xa ................................................................... 76 serial peripheral interface (spi) ......................................... 17 sleep, wake-up and battery operations............................. 65 spi timing specification.................................................... 84 synchronous character selection ...................................... 33 t timing diagrams fifo read with fint polling...................................... 71 fsk modulated deviation (max. tx to rx offset)...... 57 low-power duty cycle mode sequence .................... 64 multiple byte write with transmit register ................. 69 power-on reset example ........................................... 43 receiver fifo read................................................... 70 sensitive reset disabled............................................ 45 sensitive reset enabled............................................. 44 spi .............................................................................. 84 stsreg read sequence .......................................... 93 tx register usage ..................................................... 69 transmit register ............................................................... 16 tx register buffered data transmission ........................... 66 typical applications .............................................................. 3 v v dd line filtering................................................................ 46 w wake-up timer ................................................................... 16 www address ................................................................... 99 www, on-line support ....................................................... 5 ? 2009-2011 microchip technology inc. preliminary ds70590c-page 99 mrf49xa the microchip web site microchip provides online support through our web site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support mrf49xa ds70590c-page 100 preliminary ? 2009-2011 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70590c mrf49xa 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2009-2011 microchip technology inc. preliminary ds70590c-page 101 mrf49xa product identification system to order or obtain information, e.g., on pricing or del ivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device mrf49xa: sub-ghz rf transceiver temperature range i = -40 c to +85 c (industrial) package st = tssop (lead plastic thin shrink small outline, no lead) t = tape and reel example: a) mrf49xa-i/st: industrial temperature, tssop package. b) mrf49xat-i/st: industrial temperature, tssop package, tape and reel. ds70590c-page 102 preliminary ? 2009-2011 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 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