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MPC9446 rev. 3, 08/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. 2.5 v and 3.3 v lvcmos clock fanout buffer the MPC9446 is a 2.5 v and 3.3 v compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. both 3.3 v, 2.5 v and dual supply voltages are supported for mixed-voltage applications. the MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. the outputs are configurable and support 1:1 and 1:2 ou tput to input frequency ratios. the MPC9446 is specified for the extended temperature range of ?40 c to 85 c. features ? configurable 10 outputs lvcmos clock distribution buffer ? compatible to single, dual and mixed 3.3 v/2.5 v voltage supply ? wide range output clock frequency up to 250 mhz ? designed for mid-range to high-performance telecom, networking and computer applications ? supports applications requiring clock redundancy ? maximum output skew of 200 ps (150 ps within one bank) ? selectable output configurations per output bank ? tristable outputs ? 32-lead lqfp package ? 32-lead pb-free package available ? ambient operating temperature range of ?40 to 85 c functional description the MPC9446 is a full static fanout buffer design supporti ng clock frequencies up to 250 mhz. the signals are generated and retimed on-chip to ensure minimal skew between the three outp ut banks. two independent lvcmos compatible clock inputs are available. this feature supports redundant cl ock sources or the addition of a test cloc k into the system design. each of the th ree output banks can be individually supplied by 2.5 v or 3.3 v suppo rting mixed voltage applications. the fselx pins choose be- tween division of the input reference frequency by one or two. t he frequency divider can be set individually for each of the th ree output banks. the MPC9446 can be rese,t and the outputs are disabled by deasserting the mr/oe pin (logic high state). assert- ing mr/oe will enable the outputs. all inputs accept lvcmos signals while the outputs provide lvcm os compatible levels with the capability to drive terminated 50 ? transmission lines. please consult the mpc9456 specification for a 1:10 mixed vo ltage buffer with lvpecl compatible in- puts. for series terminated transmission lines, each of the mpc9 446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. the dev ice is packaged in a 7x7 mm 2 32-lead lqfp package. fa suffix 32-lead lqfp package case 873a-04 ac suffix 32-lead lqfp package pb-free package case 873a-04 MPC9446 low voltage single or dual supply 2.5 v and 3.3 v lvcmos clock distribution buffer
advanced clock drivers devices 2 freescale semiconductor MPC9446 figure 1. MPC9446 logic diagram figure 2. pinout: 32-lead package pinout (top view) 0 1 0 1 0 1 0 1 clk 2 clk mr/oe cclk0 cclk1 fsela fselb fselc cclk_sel qa0 qa1 qa2 qb0 qb1 qb2 qc0 qc1 qc2 qc3 bank a bank b bank c 25k 25k 25k 25k 25k 25k 25k v cc v cc v cca qa2 gnd qa1 v cca qa0 gnd qc3 gnd qc2 v ccc qc1 gnd gnd qb0 v ccb qb1 gnd qb2 v ccb v ccc cclk_sel v cc cclk0 cclk1 fsela fselb fselc gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC9446 v ccb is internally connected to v cc qc0 v ccc mr/oe
advanced clock drivers devices freescale semiconductor 3 MPC9446 table 1. pin configuration pin i/o type function cclk0,1 input lvcmos lvcmos clock inputs fsela, fselb, fselc input lvcmos output bank divide select input mr/oe input lvcmos internal reset and output (high impedance) control gnd supply negative voltage supply (gnd) v cca , v ccb (1) , v ccc 1. v ccb is internally connected to v cc . supply positive voltage supply for output banks v cc supply positive voltage supply for core (vcc) qa0 ? qa2 output lvcmos bank a outputs qb0 ? qb2 output lvcmos bank b outputs qc0 ? qc3 output lvcmos bank c outputs table 2. supported single and dual supply configurations supply voltage configuration v cc (1) 1. v cc is the positive power supply of t he device core and input circuitry. v cc voltage defines the input threshold and levels. v cca (2) 2. v cca is the positive power supply of the bank a outputs. v cca voltage defines bank a output levels. v ccb (3) 3. v ccb is the positive power supply of the bank b outputs. v ccb voltage defines bank b output levels. v ccb is internally connected to v cc . v ccc (4) 4. v ccc is the positive power supply of the bank c outputs. v ccc voltage defines bank c output levels. gnd 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 0 v mixed voltage supply 3.3 v 3.3 v or 2.5 v 3.3 v 3.3 v or 2.5 v 0 v 2.5 v 2.5 v 2.5 v 2.5 v 2.5 v 0 v table 3. function table (controls) control default 0 1 cclk_sel 0 cclk0 cclk1 fsela 0 f qa0:2 = f ref f qa0:2 = f ref 2 fselb 0 f qb0:2 = f ref f qb0:2 = f ref 2 fselc 0 f qc0:3 = f ref f qc0:3 = f ref 2 mr/oe 0 outputs enabled internal reset outputs disabled (tristate) table 4. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to t he device may occur. exposure to these conditions or conditions beyond th ose indicated may adversely affect device re liability. functional operation under absolute-ma ximum-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.6 v v in dc input voltage ?0.3 v cc +0.3 v v out dc output voltage ?0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c
advanced clock drivers devices 4 freescale semiconductor MPC9446 table 5. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf table 6. dc characteristics (v cc = v cca = v ccb = v ccc = 3.3 v 5%, t a = ?40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.8 v lvcmos i in input current (1) 1. input pull-up / pull-down resi stors influence input current. 200 a v in = gnd or v in = vcc v oh output high voltage 2.4 v i oh = ?24 ma (2) 2. the MPC9446 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a te rmination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines. v ol output low voltage 0.55 0.30 v v i ol = 24 ma (2) i ol = 12 ma z out output impedance 14 ? 17 ? i ccq (3) 3. i ccq is the dc current consumption of the device with all outputs open and the input in its default state or open. maximum quiescent supply current 2.0 ma all v cc pins table 7. ac characteristics (v cc = v cca = v ccb = v ccc = 3.3 v 5%, t a = ?40c to +85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f ref input frequency 0 250 (2) 2. the MPC9446 is functional up to an input and output clock frequency of 350 mhz and is characterized up to 250 mhz. mhz f max maximum output frequency 1 output 2 output 0 0 250 (2) 125 mhz mhz fselx = 0 fselx = 1 t p, ref reference input pulse width 1.4 ns t r , t f cclk input rise/fall time 1.0 (3) 3. violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagat ion delay, device-to-device ske w, reference input pulse width, output duty cycle and maximum frequency specifications. ns 0.8 to 2.0 v t plh t phl propagation delay cclk0,1 to any q cclk0,1 to any q 2.2 2.2 2.8 2.8 4.45 4.2 ns ns t plz, hz output disable time 10 ns t pzl, lz output enable time 10 ns t sk(o) output-to-output skew within one bank any output bank, same output divider any output, any output divider 150 200 350 ps ps ps t sk(pp) device-to-device skew 2.25 ns t sk(p) dc q output pulse skew (4) output duty cycle 1 output 2 output 4. output pulse skew t sk(p) is the absolute difference of the propagation delay times: | t plh ? t phl |. output duty cycle is frequency dependent: dc q = (0.5 t sk(p) ? f out ). for example at f out = 125 mhz the output duty cycle limit is 50% 2.5%. 47 45 50 50 200 53 55 ps % % dc ref = 50% dc ref = 25%?75% t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4 v
advanced clock drivers devices freescale semiconductor 5 MPC9446 table 8. dc characteristics (v cc = v cca = v ccb = v ccc = 2.5 v 5%, t a = ?40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc + 0.3 v lvcmos v il input low voltage ?0.3 0.7 v lvcmos v oh output high voltage 1.8 v i oh = ?15 ma (1) 1. the MPC9446 is capable of driving 50 ? transmission lines on the inciden t edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines per output. v ol output low voltage 0.6 v i ol = 15 ma z out output impedance 17 ? 20 (2) 2. input pull-up / pull-down resi stors influence input current. ? i in input current (2) 200 a v in = gnd or v in = v cc i ccq (3) 3. i ccq is the dc current consumption of the device with al l outputs open and the input in its default state or open. maximum quiescent supply current 2.0 ma all v cc pins table 9. ac characteristics (v cc = v cca = v ccb = v ccc = 2.5 v 5%, t a = ?40c to +85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f ref input frequency 0 250 (2) 2. the MPC9446 is functional up to an input and output cloc k frequency of 350 mhz and is characterized up to 250 mhz. mhz f max maximum output frequency 1 output 2 output 0 0 250 (2) 125 mhz mhz fselx = 0 fselx = 1 t p, ref reference input pulse width 1.4 ns t r , t f cclk input rise/fall time 1.0 (3) 3. violation of the 1.0 ns maximum input rise and fall time limit will affect the device pr opagation delay, device-to-device ske w, reference input pulse width, output duty cycle and maximum frequency specifications. ns 0.7 to 1.7 v t plh t phl propagation delay cclk0,1 to any q cclk0,1 to any q 2.6 2.6 5.6 5.5 ns ns t plz, hz output disable time 10 ns t pzl, lz output enable time 10 ns t sk(o) output-to-output skew within one bank any output bank, same output divider any output, any output divider 150 200 350 ps ps ps t sk(pp) device-to-device skew 3.0 ns t sk(p) dc q output pulse skew (4) output duty cycle 1 or 2 output 4. output pulse skew t sk(p) is the absolute difference of the propagation delay times: | t plh ? t phl |. output duty cycle is frequency dependent: dc q = (0.5 t sk(p) ? f out ). for example at f out = 125 mhz the output duty cycle limit is 50% 2.5%. 45 50 200 55 ps % dc ref = 50% t r , t f output rise/fall time 0.1 1.0 ns 0.6 to 1.8 v table 10. ac characteristics (v cc = 3.3 v + 5%, v cca , v ccb , v ccc = 2.5 v + 5% or 3.3 v + 5%, t a = ?40c to +85c) (1) (2) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . 2. for all other ac specifications, refer to 2.5 v or 3.3 v tables according to the supply voltage of the output bank. symbol characteristics min typ max unit condition t sk(o) output-to-output skew within one bank any output bank, same output divider any output, any output divider 150 250 350 ps ps ps t sk(pp) device-to-device skew 2.5 ns t plh,hl propagation delay cclk0,1 to any q see 3.3 v table t sk(p) dc q output pulse skew (3) output duty cycle 1 or 2 output 3. output pulse skew t sk(p) is the absolute difference of the propagation delay times: | t plh ? t phl |. output duty cycle is frequency dependent: dc q = (0.5 t sk(p) ? f out ). 45 50 250 55 ps % dc ref = 50%
advanced clock drivers devices 6 freescale semiconductor MPC9446 applications information driving transmission lines the MPC9446 clock driver was designed to drive high- speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 ?, the drivers can drive either para llel or series terminated transmission lines. for more information on transmission lines the reader is referred to freescale application note an1091. in most high performance clock networks, point-to-point distribution of si gnals is the method of choice. in a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc 2. this technique draws a fairly high level of dc current, and thus, only a single terminated line can be driven by each output of the MPC9446 clock driver. for the series terminated case, however, there is no dc current draw; thus, the outputs can drive multiple series terminated lines. figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, the fanout of the MPC9446 clock driver is effectively doubled due to its capability to drive multiple lines. figure 3. single versus dual transmission lines the waveform plots in figure 4 show the simulation results of an output driving a single line versus two lines. in both cases, the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the mp c9446. the output waveform in figure 4 shows a step in the waveform. this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s (z 0 (r s + r 0 + z 0 )) z 0 = 50 ? || 50 ? r s = 36 ? || 36 ? r 0 = 14 ? v l = 3.0 (25 (18 + 14 + 25) = 1.31 v at the load end, the voltage will double, due to the near unity reflection coefficient, to 2.5 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). figure 4. single versus dual waveforms since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflec tions on the line. to better match the impedances when driving multiple lines, the situation in figure 5 should be used. in this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. figure 5. optimized dual line termination 14 ? in MPC9446 output buffer r s = 36 ? z o = 50 ? outa 14 ? in MPC9446 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1 voltage (v) outb t d = 3.9386 outa t d = 3.8956 in 246 8101214 time (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 z o = 50 ? z o = 50 ? 14 ? MPC9446 output buffer r s = 22 ? r s = 22 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ?
advanced clock drivers devices freescale semiconductor 7 MPC9446 figure 6. cclk0, 1 MPC9446 ac test reference for v cc = 3.3 v and v cc = 2.5 v figure 7. output transition time test reference figure 8. propagation delay (t pd ) test reference figure 9. output-t o-output skew t sk(lh, hl) figure 10. output pulse skew (t sk(p) ) test reference figure 11. output duty cycle (dc) figure 12. cycle-to-cycle jitter pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC9446 dut v tt v tt v cc = 3.3v v cc = 2.5v 2.4 1.8v 0.55 0.6v t f t r t (lh) v cc v cc 2 gnd v cc v cc 2 gnd cclk qx t (hl) the pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device. v cc v cc 2 gnd v cc v cc 2 gnd t sk(lh) t sk(hl) v cc v cc 2 gnd v cc v cc 2 gnd t (lh) cclk q x t (hl) t sk(p) = | t plh ? t phl | the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage. v cc v cc 2 gnd t p t 0 dc = t p /t 0 x 100% the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. t n t jit(cc) = | t n -t n+1 | t n+1
advanced clock drivers devices 8 freescale semiconductor MPC9446 package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3
advanced clock drivers devices freescale semiconductor 9 MPC9446 package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3
advanced clock drivers devices 10 freescale semiconductor MPC9446 package dimensions case 873a-04 issue c 32-lead lqfp package page 3 of 3
advanced clock drivers devices freescale semiconductor 11 MPC9446 notes
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