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[ ak1542 a ] m s1399 - e - 00 2012/3 - 1 - ak1542 a 20 to 600mhz integer - n frequency synthesizer 1. overview consisting a highly accurate charge pump that s upports current adjustment in 9 steps, a reference divider, a programmable divider and a dua l - modulus prescaler (p/p+1), the ak1542 a provides high performance, low consumption current and small footprint for a wide range of frequency conversions . this synthesizer also has two general - purpose output pins which allow it to be used to control the r f front end. an ideal phase locked loop (pll) can be achieved by combining the ak1542 a with the external loop filter and vco (voltage controlled oscillator). access to the regi sters is controlled via a 3 - wire serial interface. the opera ting supply voltage is from 2.7 to 5.5v; and the supply voltage for the charge pump and that for the serial interface can be driven separately. 2. features ? operating frequency: 20 to 600mhz ? programmable charge pump current: 158 to 25 28 ? a typical the c harge p ump current can b e changed in 9 steps; and the current range can be adjusted by the external resistance. two current settings can be specified with the register and switched over from one to another using the timer. ? supply voltage: 2.7 to 5.5 v (pvdd pin ) ? separate power su pply for the charge pump : pvdd to 5.5v (cpvdd pin) ? on - chip power - saving features ? on - chip lock detection feature of pll: direct output to the pfd ( p hase frequency detector) or digital filtering output can be selected. ? general - purpose output: it has t wo general - purpose output ports to control peripheral parts. ? very l ow c onsumption current: 2. 2 ma typical ? package: 24pin qfn ( 0.5mm pitch, 4mm ? 4mm ? 0.75mm) ? operating temperature: - 40 ? c to 85 ? c
[ ak1542 a ] m s1399 - e - 00 2012/3 - 2 - table of contents 1. overview ________________________________ ________________________________ ___________ 1 2. features ________________________________ ________________________________ ___________ 1 3. block diagram ________________________________ ________________________________ _______ 3 4. pin functional description ________________________________ ____________________________ 4 5. absolute maximum ratings ________________________________ ___________________________ 6 6. recommended operating range ________________________________ _______________________ 6 7. electrical characteristics ________________________________ ______________________________ 7 8. block functional descriptions ________________________________ ________________________ 11 9. register map ________________________________ ________________________________ _______ 18 10. register function description ________________________________ ________________________ 20 11. ic interface schematic ________________________________ _______________________________ 27 12. recommended schematic for off - chip component ________________________________ _______ 29 13. power - up sequence ________________________________ ________________________________ _ 31 14. typical evaluation board schematic ________________________________ ___________________ 33 15. block diagram by power supply ________________________________ _______________________ 34 16. outer dimensions ________________________________ ________________________________ ___ 35 17. marking ________________________________ ________________________________ ___________ 36 in this specification (draft version), the following notations are used for specific signal and register names: [name]: pin name : register group name (address name) { name}: register bit name
[ ak1542 a ] m s1399 - e - 00 2012/3 - 3 - 3. block diagram fig . 1 block diagram cp cpz phase freqency detector refin + - prescaler 8/9,16/17 , 32/33 programable counter 13 bit lock detect rfinp rfinn swin cpv dd cpvss pvdd vref dvss pvss ld clk data le register 24 bit n divider fast counter pdn1 test2 test1 ldo test3 pdn2 r counter 14 bit bias charge pump swallow counter 6 bit gpo1 gpo2
[ ak1542 a ] m s1399 - e - 00 2012/3 - 4 - 4. pin functional description table 1 pin functions no. n ame i/o pin functions power down remarks 1 cpvdd p power supply for charge pump 2 test3 di test pin 3 , this pin must be connected to ground. internal pull - down, schmidt trigger input 3 test1 di test pin 1 , this pin must be connected to ground. internal pull - down, schmidt trigger input 4 le di load e nable schmidt trigger input 5 data di serial data input schmidt trigger inpu t 6 clk di serial clock schmidt trigger input 7 ld do lock detect low 8 pdn2 di power down pin for pll schmidt trigger input 9 pdn1 di power down signal for ldo schmidt trigger input 10 refin ai reference input 11 test2 di test pin 2 , this pi n must be connected to ground. internal pull - down, schmidt trigger input 12 gpo1 do general - purpose output pin 1 low 13 gpo2 do general - purpose output pin 2 low 14 dvss g digital ground pin 15 vref ao connect to ldo reference voltage capaci tor low 16 rfinn ai prescaler input 17 rfinp ai prescaler input 18 pvdd p power supply for peripherals 19 bias aio resistance pin for setting charge pump current 20 pvss g ground pin for peripherals 21 cp ao charge pump output hi - z 2 2 cpz aio connect to the loop filter capacitor notes 1) & 2) 23 swin ai connect to resistance pin for fast lock up notes 1) & 2) 24 cpvss g ground pin for charge pump power supply note 1) for detailed functional descriptions, see the section cha rge pump and loop filter in 8 . block functional descriptions .
[ ak1542 a ] m s1399 - e - 00 2012/3 - 5 - note 2) the input voltage from the [ cpz ] pin is used in the internal circuit. the [ cpz ] pin must not be open even when the fast lock up featur e is unused. for the output destination from the [ cpz ] pin , see p.1 2 fig.5 loop filter schematic. the [ swin ] pin could be open when the f ast lock up feature is not used. note 3) power down refers to the state where [ pdn1 ] = [ pdn2 ] =low after power - on. no te 4) test1 to 3 must be connected to ground. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin fig. 2 package pin layout 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 top view 23 24 22 21 cpvdd test3 test1 data le clk ld pdn2 pdn1 refin test2 gp o1 gpo2 dvss vref rfinn rfinp pvdd bias pvss cp cpz swin cpvss
[ ak1542 a ] m s1399 - e - 00 2012/3 - 6 - 5. absolute maximum ratings table 2 absolute maximum ratings parameter symbol min. max. unit remarks supply voltage vdd1 - 0.3 6.5 v note 1 ) , applied to [ pvdd ] pin vdd2 - 0.3 6.5 v note 1 ) , applied to [ cpvdd ] pin ground level vss1 0 0 v voltage ground level , applied to [ pvss ] pin vss2 0 0 v voltage ground level , applied to [ cpvss ] pin vss3 0 0 v voltage ground level , applied to [ dvss ] pin analog input voltage vain1 vss1 - 0.3 vdd1+0.3 v notes 1 ) & 2 ) vain2 vss2 - 0.3 vdd2+0.3 v notes 1 ) & 3 ) digital input voltage vdin vss3 - 0.3 vdd1+0.3 v notes 1 ) & 4 ) input current iin - 10 10 ma storage temperature tstg - 55 125 c note 1) 0v reference for all voltages. note 2) applied to [ refin ] , [ rfinn ] and [ r finp ] pins. note 3) applied to [ cpz ] and [ swin ] pins. note 4) applied to [ clk ] , [ data ] , [ le ] , [ pdn1 ] , [ pdn2 ] , [ test1 ] , [ test2 ] and [ test 3 ] pins. exceeding these maximum ratings may result in damage to the ak15 42 a. normal operation is not guaranteed at th ese extremes. 6. recommended operating range table 3 recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta - 40 85 ? c supply voltage vdd1 2.7 3.3 5.5 v applied to [ pvdd ] pin vdd2 vdd1 5.0 5.5 v applied to [ cpvdd ] pin note 1) vdd1 and vdd2 can be driven individually within the recommended operating range. the specifications are applicable within the recommended operating range (su pply voltage /operating temperature).
[ ak1542 a ] m s1399 - e - 00 2012/3 - 7 - 7. electrical cha racteristics 1. digital dc characteristics table 4 digital dc characteristics parameter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8 ? vdd1 v note 1 ) low level input voltage vil 0.2 ? vdd1 v n ote 1 ) high level input current 1 iih1 vih = vdd1=5.5v - 1 1 a note 2 ) high level input current 2 iih2 vih = vdd1=5.5v 27 55 110 a note 3 ) low level input current iil vil = 0v, vdd1=5.5v - 1 1 a note 1 ) high level output voltage voh ioh = - 500 a vdd 1 - 0.4 v note 4 ) low level output voltage vol iol = 500 a 0.4 v note 4 ) note 1) applied to [ clk ] , [ data ] , [ le ] , [ pdn1 ] , [ pdn2 ] , [ test1 ] , [ test2 ] and [ test 3 ] pins. note 2) applied to [ clk ] , [ data ] , [ le ] , [ pdn1 ] and [ pdn 2] pins. note 3) applied to [ t est1 ] , [ test2 ] and [ test 3 ] pins. note 4) applied to [ ld ] , [gpo1] and [gpo2] pin s .
[ ak1542 a ] m s1399 - e - 00 2012/3 - 8 - 2. serial interface timing fig. 3 serial interface timing table 5 serial interface timing paramet er symbol min. typ. max. unit remarks clock l level hold time tcl 40 ns clock h level hold time tch 40 ns clock setup time tcsu 20 ns data setup time tsu 20 ns data hold time thd 20 ns le setup time tlesu 20 ns le pulse width tle 4 0 ns note 1 ) while [ le ] pin is setting at low , 24 iteration clocks have to be set with [ clk ] pin. i f 25 or larger clocks are set, the last 24 clocks synchronized data are valid. le (input) clk (input) data (input) tsu thd tcsu d19 d18 d0 a0 a1 a2 a3 tch t cl tlesu tle d19
[ ak1542 a ] m s1399 - e - 00 2012/3 - 9 - 3. analog circuit characteristics the resist ance of 27k ? is connected to the [ bias ] pin, vdd1 = 2.7 to 5.5v, vdd2=vdd1 to 5.5v, C 40c ta 85c parameter min. typ. max. unit remarks rf characteristics input sensitivity - 15 +5 dbm input frequency 100mhz - 5 +5 20mh input frequency < 100mhz 600 mhz refin characteristics input sensitivity 0.4 2 vpp input frequency 5 40 mhz maximum allowable prescaler output frequency 75 mhz phase detector phase detector frequency 3 mhz charge pump charge pump maximum value 25 28 a charge pump minimum value 158 a icp tri - state leak current 1 na 0. 7 vcpo vdd2 10 % vcpo = vdd2/2, ta= 25c icp vs. vcpo note 2 ) 15 % 0.5 vcpo vdd2 others vref rise time 50 s consumption current idd1 10 a [pdn1]= 1. 8 2.7 ma [pdn1]= 0. 4 0.9 ma [pdn1]= 0.5 1 ma [pdn1]= 2) see fig. 4 charge pump characteristics - voltage vs. current: icp vs. vcpo: [{1/2(|i1| - |i2|)}/{1/2(|i1|+|i2|)}]100 [%]
[ ak1542 a ] m s1399 - e - 00 2012/3 - 10 - note 3 ) idd3 doesn t include the current depending on phase detector frequency . idd3 is the current the charge pump circuit consumes constantly. note 4 ) in the case of [pdn1]=high and [pdn2]=high , the total current consumption = idd2 + idd3 . note 5 ) the s hipment test is done with the exposed pad at the center of backside connected to vss. resistance connected to the bias pin for setting charge pump output current parameter min. typ. max. unit remarks bias resistance 22 27 33 k? fig. 4 charge pump characteristics - voltage (vcpo) vs. current (icp) isink isource vcpo icp cpvdd - 0.5 cpvdd/2 0.5 i1 i1 i2 i2
[ ak1542 a ] m s1399 - e - 00 2012/3 - 11 - 8. block functional descriptions 1. frequency setup the following formula is used to calculate the frequency setting for ak1542 a . frequency setting (external vc o output frequency) = f pfd n n : dividing number n = [ (p b) + a ] f pfd : phase detector frequency f pfd = [refin] pin input frequency / r counter dividing number p : prescaler value (see < address2 > : { pre[1:0] } ) b : b (programmable) counter value (see < address1 > : { b[12:0] } ) a : a (swallow) counter value (see < address1 > : { a[5:0] } ) calculation examples when the [refin] pin input frequency is 10mhz, the phase detector frequency f pfd =5khz and the frequency setting = 460.1mhz; [ the ak1542 a settings] r=10000000/5000 = 2000 ( < address3 > : { r[13:0] } =2000dec ) p=32 ( < address2 > : { pre[1:0] } =10bin) b=2875 ( < address1 > : { b[12:0] } =2875dec) a=20 ( < address1 > : { a[5:0] } =20dec) frequency setting = 5000 [ (322875) + 20] = 460.1mhz lower limit for setting conse cutive dividing numbers in the ak154 2a , it is im possible to set consecutive dividing numbers below the lower limit . the lower limit is calculated by the following formula; n min =p 2 - p for example , in the case of p=16, it can be set 240 and over as consecuti ve dividing numbers .
[ ak1542 a ] m s1399 - e - 00 2012/3 - 12 - 2. charge pump and loop filter in ak1542 a , the fast lock up could be achieved by changing a charge pump current and enabling the loop filter. this is called fast lock up mode. for details, see 3. fast lock up mode on page 1 3 . the l oop filter is external and connected to [ cp ] , [ swin ] and [ cpz ] pins. the [ cpz ] pin should be connected to the r2 and c2 , which are intermediate nodes, even if the fast lock up is not used. therefore, r2 must be connected to the [ cp ] pin, while c2 must be c onnected to the ground. fig. 5 loop filter schematic c2 phase detector up down timer vco loop filter c1 c3 r2 r2' r3 cp cpz swin
[ ak1542 a ] m s1399 - e - 00 2012/3 - 13 - 3. fast lock up mode setting d[16]={f a sten} in < address4> to 1 enables the fast lock up mode for ak1542 a . changing a frequency setting ( the frequency is changed at the rising edge of [ le ] when and are accessed . ) or [pdn2] pin is set from low to high with { f a sten}=1 enables the fast lock up mode. the loop filter switch turns on during the timer period specified by the counter value in d[12:0] = { fa st[12:0]} in , and the charge pump for the fast loc k up mode (charge pump 2) set by d[ 9 :6] = { cp2[ 3 :0]} in is enabled. after the timer period elapsed, the loop filter switch turns off, the charge pump for normal operation (charge pump 1) set by d[ 3 :0] = { cp1[ 3 :0]} in is enabled and t hus normal operation returns. the register d[12:0] = {fast[12:0]} in is used to set the timer period for this mode. the following formula is used to calculate the time period: phase detector frequency cycle counter value set in {fast[12:0]} the charge pump current could be adjusted with 9 steps for both normal operation (charge pump 1) and the fast lock up operation (charge pump 2). the absolute value of the charge pump current is determined by the resistor value connected to the [bias] pin. the following formula shows the relationship between the resistance value, the register setting and the electric current value. charge pump mini mum current (icp_min) [a] = 8.55 / resistance connected to the [ bias ] pin ( ? ) charge pump current [a] = icp_min [a] (cp1 or cp2 setting + 1) the allowed range value for the resistance connected to the [ bias ] pin is from 22 to 33 [k ? ]. for details of current settings, see register functional description. fig. 6 timing chart for fast lock up mode fast lock u p mode charge p ump 2 on normal normal charge p ump 1 off charge p ump 1 off f as t lock up time specified by the timer operation mode charge pump l op filter switch the frequency is changed or [pdn2] pin is set to high when d[16]={f a sten} in is set to 1 .
[ ak1542 a ] m s1399 - e - 00 2012/3 - 14 - 4. lock detect (ld) signal in ak1542 a , the lock detect output can be selected by d[13] = { ld} in . when d[13] is set to 1", the phase detector outputs provide a phase detection as an a nalog level (compariso n result) . this is called analog lock detect . when d[13] is set to 0, the lock detect signal is output ac cording to the internal logic. this is called digital lock detect . 4.1 analog lock detect in analog lock detect, the phase detector output comes from the ld pin. fig. 7 analog lock detect operation reference clock pfd clock vco divide clock phase detector output ld output
[ ak1542 a ] m s1399 - e - 00 2012/3 - 15 - 4.2 digital lock detect in the digital lock detect , the [ ld ] pin outputs is low every time when the frequency is set. and the [ld] pin output s h igh (which means the locked state) when a phase error smaller than t is detected for n times consecutively. if the phase error larger than t is detected for n times consecu tively when the [ld] pin output s high , the [ld] pin outputs low (which means th e unlocked state). the threshold counts for lock detection n could be set b y d[18:17]={ldcntsel[1:0]} in . { ldcntsel[1:0]} settings and corresponding counts (n) are as follows: 00: n = 7 01: n = 15 10: n = 31 11: n = 63 the lock detect sign al is shown below: fig. 8 digital lock detect operations reference clock invalid pfd clock vco divide clock phase detector output ld output valid invalid va lid invalid when invalid is detected con secutively for n times, ld outputs high
[ ak1542 a ] m s1399 - e - 00 2012/3 - 16 - fig. 9 transition flow chart: unlock state to lock state fig. 10 transition flow chart: lock state to unlock state phase error < t flag=flag+1 lock(ld= high ) unlock(ld= low ) yes no flag>n flag=0 yes no phase error > t yes flag=0 flag=flag+1 flag>n no yes unlock(ld= low ) no lock(ld= high ) address2 write
[ ak1542 a ] m s1399 - e - 00 2012/3 - 17 - 5 . reference input the reference input could be set to a dividing number in the range of 4 to 16383 using { r [13:0] } , which is a 14 - bit a ddress of d[13:0] in . a dividing number f rom 0 to 3 could not be set. 6 . prescaler and swallow counter the dual modular prescaler (p/p+ 1) and the swallow counter are used to provide a large dividing ratio. the prescaler is set by { pre[1:0]}, which is a 2 - bit address of d[15:14 ] in . { pre[1:0]}=00: p=8, dividing ratio = 8/9 {pre[1:0]}=01: p=16, dividing ratio = 16/17 {pre[1:0]}=10: p=32, dividing ratio = 32/33 { pre[1:0]}=11: prohibited 7 . power save mode ak154 2 a can be operated in the power - down or power - save mode as necessary by using the external control pins [ pdn1 ] and [ pdn2 ] . power on see 13 . power - up sequence. it is necessary to bring [pdn1] to high first, then [pdn2]. bringing [pdn1] and [pdn2] to high simultaneously is p rohibited . normal operation pin name state pdn1 pdn2 low low power down low high prohibited high low power save mode note 1 ) and note 2 ) high high normal operation note 1 ) register setup can be made 50 s after [ pdn1 ] is set to h igh . the charge pump is in the hi - z state. note 2) register settings are maintained when [ pdn2 ] is set to low during normal operation.
[ ak1542 a ] m s1399 - e - 00 2012/3 - 18 - 9. register map name data address a/b d19 to d0 0 0 0 1 cp 0 0 1 0 ref/pres 0 0 1 1 function 0 1 0 0 gpo 0 1 0 1 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address a/b 0 b [12] b [11] b [10] b [9] b [8] b [7] b [6] b [5] b [4] b [3] b [2] b [1] b [0] a [5] a [4] a [3] a [2] a [1] a [0] 0x01 cp 0 0 0 0 0 0 0 0 0 0 cp2 [3] cp2 [2] cp2 [1] cp2 [0] 0 0 cp1 [ 3 ] cp1 [2] cp1 [1] cp1 [0] 0x02 ref/pres 0 0 0 0 pre [1] pre [0] r [13] r [12] r [11] r [10] r [9] r [8] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x03 function 0 ldcnt sel[1] ldcnt sel[0] fast en cp hiz cp pola ld fast [12 ] fast [11] fast [10] fast [9] fast [8] fast [7] fast [6] fast [5] fast [4] fast [3] fast [2] fast [1] fast [0] 0x04 gpo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpo 2 gpo 1 0x05
[ ak1542 a ] m s1399 - e - 00 2012/3 - 19 - notes for writing into registers (1) the data at addresses 0x02 and 0x03 are commi tted to all related circuits when address 0x01 is written, which means that the data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at the same time. (2) addresses 0x04 and 0x05 could be written individually from other address es. (3) t he initial register values are not defined. therefore, even after [ pdn1 ] is turned on, each bit value remains undefined. in order to set all register values, it is required to write the data in all addresses of the register. examples of writing into registers (ex. 1) power - on ? (1) write a charge pump current value to address 0x02. the data at address 0x02 is not committed to all related circuits at this time. instead, it is stored in the on - chip buffer. (2) write a d ivision number for the prescaler and a reference counter value to address 0x03. the data at the address 0x03 is not committed to all related circuits at this time. instead, it is stored in the on - chip buffer. (3) write values for a counter and b counter at the address 0x01. the data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at this time. (ex. 2) changing frequency settings (1) write values for a counter and b counter at the address 0x01. the data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at a time. the la st data written into addresses 0x02 and 0x03 are committed. (ex. 3) changing charge pump current ? (1) write a charge pump current value at the addre ss 0x02. the data in address 0x02 is not committed to all related circuits at this time. instead, it is stored in the on - chip buffer. (2) write values for a counter and b counter at the address 0x01. the data of these 3 addresses (0x01, 0x02 and 0x03) are com mitted to all related circuits at a time. the la st data written into address 0x03 is committed. (ex. 4) changing reference dividing number ? (1) write a division number for the prescaler and a reference counter value at the address 0x03. the data at the address 0x03 is not committed to all related circuits at this time. instead, it is stored in the on - chip buffer. (2) write values for a counter and b counter at the address 0x01. the data of these 3 addresses (0x01, 0x02 and 0x03) are committed to all related circuits at a time. the la st data written into address 0x03 is committed.
[ ak1542 a ] m s1399 - e - 00 2012/3 - 20 - 10. register function descriptio n < address1 : a/b > d19 d[18:6] d[5:0] address 0 b[12:0] a[5:0] 0001 b[12:0]: b (programmable) counters value d 18 d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec pr ohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 1 3 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec a[5:0]: a (swallow) counter value d5 d4 d3 d2 d 1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 0 1 0 2 dec 0 0 0 0 1 1 3 dec data 1 1 1 1 0 1 61 dec 1 1 1 1 1 0 62 dec 1 1 1 1 1 1 63 dec
[ ak1542 a ] m s1399 - e - 00 2012/3 - 21 - * requirements for a[5:0] and b[12:0] the data at a[5:0] and b[12:0] must meet th e following requirements: b[12:0] 3, b[12:0] a[5:0] see 1. frequency setup on page 1 1 for details of the relationship between a frequency division number and the data at a[5:0] and b[12:0]. < address2 : cp > d19 d18 d17 d16 d15 d1 4 d13 d12 d[11:10 ] d[9:6] d[5:4] d[3:0] address 0 0 0 0 0 0 0 0 0 cp2[ 3 :0] 0 cp1[ 3 :0] 0010 cp1[ 3 :0] : charge pump current for normal operation cp2[ 3 :0] : ch arge pump current for fast lock up mode in ak1542 a , two types of charge pump current cp1 and cp2 could be set. cp1 is the charge pump current setting for normal operation. cp2 is the charge pum p current setting for fast lock up mode. the following formula shows the relationship between the resistance value, the register setting and the electric current value. set ting 0~7; charge pump mini mum current (icp_min) [a] = 8.55 / resistance connected to the [ bias ] pin ( ? ) charge pump current [a] = icp_min [a] (cp1 or cp2 + 1) setting 8; charge pump current [a] = icp_min [a] 0.5 cp1[ 3 :0] cp2[ 3 :0] charge pump currents [ a] 22 k ? 27k ? 33 k ? 000 388 316 259 001 776 632 518 010 1 164 948 777 011 1552 1264 1036 100 1940 1580 1295 101 2328 1896 1554 110 2716 2212 1813 111 3104 2528 2072 1xxx 194 158 129
[ ak1542 a ] m s1399 - e - 00 2012/3 - 22 - < address3 : ref/pres > d19 d18 d17 d16 d[15:14] d[13:0] add ress 0 0 0 0 pre[1:0] r[13:0] 0011 pre[1:0] : prescaler division ratio (8/9, 16/17, 32/33) the following settings can be chosen for the prescaler division. d15 d14 function remarks 0 0 8/9 (p=8) 0 1 16/17 (p=16) 1 0 32/33 (p=32) 1 1 prohibited r[13:0]: reference clock division number the following settings can be chosen for the reference clock division. the allowed range is 4 (1/4 division) to 16383 (1/16383 division). 0 to 3 cannot be set. d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 funct ion remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/1 division prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/2 division prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1/3 division prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1/4 division data 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1/16381 division 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1/16382 division 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/16383 division
[ ak1542 a ] m s1399 - e - 00 2012/3 - 23 - < address4 : function > d19 d18 d17 d16 d15 d14 d13 d[12:0] address 0 ldcnt sel[1] ldcnt sel[0] fas t en cp hiz cp pola ld fast[12:0] 0100 ldcntsel[1:0] : counter value for lock detect the counter value for digital lock detect can be set. d18 d17 function remarks 0 0 counter value = 7 0 1 counter value = 15 1 0 counter value = 31 1 1 counter value = 63 fasten : the fast lock up mode enable/disable setting the fast lock up mode can be enabled or disabled. d16 function remarks 0 the data in cp2[ 3 :0] and fast[12:0] are disabled. 1 the data in cp2[ 3 :0] and fast[12:0] are enabled. cphi z: tri - state output setting for charge pumps 1 and 2 d15 function remarks 0 charge pump is activated. use this setting for normal operation. 1 tri - state note 1) note 1) the charge pump output is turned off and put in the hi - z state.
[ ak1542 a ] m s1399 - e - 00 2012/3 - 24 - cppola: selects p ositive or negative output polarity for cp1 and cp2. d14 function remarks 0 positive 1 negative fig. 11 charge pump output polarity ld: selects analog or digital for lock detect. d13 function remarks 0 digital lock detect mode 1 analog lock detect mode for detailed functional descriptions, see the section lock detect (ld) signal in 8 . block functional description. high high charge pump output voltage negative positive low lo w vco frequency
[ ak1542 a ] m s1399 - e - 00 2012/3 - 25 - fast[12:0] : fast counter value a decimal number from 1 to 8191 can be set. this value determines the time period during which the cp2 is on for the fast lock up mode. after the time period calculated by [phase detector frequency cycle { fast[12:0] } setting], the cp2 is turned off. 0 could not be set. d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec
[ ak1542 a ] m s1399 - e - 00 2012/3 - 26 - < address5 : gpo > d1 9 d1 8 d1 7 d1 6 d15 d14 d13 d12 d1 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpo2 gpo1 0101 gpo2: the state of the gpo2 pin this value controls the general - purpose output pin gpo2. the voltage applied to the pvdd pin determines the high level output. d1 function remarks 0 l ow output from the gpo2 pin 1 high output from the gpo2 pin gpo1: the state of the gpo1 pin this value controls the g eneral - p urpose output pin gpo1. the voltage applied to the pvdd pin determines the high level output. d0 function remarks 0 l ow output from the gpo1 pi n 1 high output from the gpo1 pin
[ ak1542 a ] m s1399 - e - 00 2012/3 - 27 - 11. ic interface schematic no. n ame i/o r0( ? ) cur( a) function 4 le i 300 digital input pins 5 data i 300 6 clk i 300 8 pdn2 i 300 9 pdn1 i 300 2 test3 i 300 digital input pins pull - down 3 test1 i 300 11 test2 i 300 7 ld o digital output pin 12 gpo1 o 13 gpo2 o 10 refin i 300 analog input pin 15 vref io 300 analog i/o pin 19 bias io 300 22 cpz io 300 r0 r0 100k r0 r0
[ ak1542 a ] m s1399 - e - 00 2012/3 - 28 - no. n ame i/o r0 ( ? ) cur( a) function 23 swin i analog input pin 21 cp o analog output pin 16 rfinn i 12k 20 analog input pin ( rf signal input ) 17 rfinp i 12k 20 r0
[ ak1542 a ] m s1399 - e - 00 2012/3 - 29 - 12. recommended sche matic for off - chip component 1. pvdd, cpvdd 2. vref 3. test [1,2,3] pvdd cpvdd lsi 100p f 10 ? f 0.01 ? f 0.01 ? f 100p f 10 ? f vref vref2 lsi 220nf 10% test 1, 2 , 3 lsi
[ ak1542 a ] m s1399 - e - 00 2012/3 - 30 - 4. refin 5. rfinp, rfinn 6. bias ref in lsi 100pf 10 % lsi rfinp vco output rfinn 100pf 10 % 100pf 10 % 5 1 lsi bias 22k ~33k
[ ak1542 a ] m s1399 - e - 00 2012/3 - 31 - 13. power - up sequence 1. pow er - up sequence (recommended ) fig. 12 recommended power sequence note 1) the initial register values are no t defined. therefore, even after [pdn1] is set to high , each bit value remains undefined. in order to set all register values, it is required to write the data in all addresses of the register. pvdd,cpvdd write to the register on - chip ldo (1.8v) pdn2(pll) internal resiter values are set cp output 0v 1.8v 50 ?
[ ak1542 a ] m s1399 - e - 00 2012/3 - 32 - 2. power - up sequence fig. 13 power sequence pvdd,cpvdd write to register on - chip ldo (1.8v) pdn2(pll) cp 0v 50 ? s hiz pdn1 refin d on t care input output(*1) registers can be written after more than 50 ? s from the [pdn1] is set to high he re [pdn1] is set to high after or at the same time as power - up. 1.8v refin must be input before setting [pdn2] to high *1 cp output is not defined before writing the data in all addresses of the register. after writing them, cp output can be controlled by register. h or l
[ ak1542 a ] m s1399 - e - 00 2012/3 - 33 - 14. typical evaluation board schematic fig. 14 typical evaluation board schematic note 1) the [cpz] pin should be connected to the r2 and c2 , which are intermediate nodes, even if the fast lock up is not used. therefore, r2 must be connected to the [cp] pin, while c2 must be connected to the ground. note 2) in fast lock up mode, r2 and r2 are connected in parallel by internal switching. for calculation of loop band width and phase margin at fast lock up mode, the resistance should be considered as parallel of r2 and r2 . note 3) it is recommended tha t t he exposed pad at the center of the backside should be connected to the ground. note 4) test pins (test1 to 3) should be connected to the ground. c2 ak1542 a loop filter c1 c3 r2 r2' r3 cp cpz swin rfout 51 ? 100pf rfinn vco bias rfinp 100pf 27k ? refin vref 220nf 100pf 100pf 18 ? 18 ? 18 ?
[ ak1542 a ] m s1399 - e - 00 2012/3 - 34 - 15. block diagram by power supply fig. 15 power supply block diagram pvdd cpvdd cp cpz phase freqency detector refin + - prescaler 8/9, 16/17, 32/33 programable counter 13 bit lock detect rfinp rfinn swin cpvdd cpvss pvdd vref dvss pvss ld clk data le register 24 bit n divider fast counter pdn1 test2 test1 ldo test3 pdn2 r counter 14 bit bias charge pump swallow counter 6 bit gpo1 gpo2
[ ak1542 a ] m s1399 - e - 00 2012/3 - 35 - 16. outer dimen sions fig. 16 package outer dimensions note) it is recommended to connect the exposed pad at the center of the backside to the ground, although it will not make any impact on the electrical characteristics if it is open. 0.05 s 2.40 2.40 0.400. 07 c0.30 1 13 18 19 24 12 7 4.000. 07 4 .000. 07 0.220.05 a 2.00 b 2.00 s part a 0.5 0.75max 0.70 0.05max 6 0.05 m s a b 0.00 ~ 0.05 0.12 ~ 0.18 0.17 ~ 0.27 detailed chart in part a
[ ak1542 a ] m s1399 - e - 00 2012/3 - 36 - 17. marking (a) style : qfn (b) number of pins : 24 (c) 1 pin marking: : (d) product number : 1542 a (e) date code : ywwl (4 digits) y : lower 1 digit of calendar year (year 20 1 2 2 , 20 1 3 3 ...) ww : week l : lot identification, given to ea ch product lot which is made in a week ? lot id is given in alphabetical order (a, b, c). fig. 17 marking ywwl (e) (c) 1542 a (d)
[ ak1542 a ] m s1399 - e - 00 2012/3 - 37 - important notice ? descriptions of externa l ci r cuits, application circuits, software and other related info r mation contained in this document are provided only to illustrate the operation and application examples of the semiconductor products . you are fully responsible for the incorporation of the se external circuits, application circuits, software and other related in formation in the design of your equipment. asahi kasei microdevices corporation (akm) assumes no responsibility for any loss e s incurr e d by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critic al components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: n ote1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ver y high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failur e to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm product s, who distributes, disposes of, or otherwise places the product with a third party , to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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