austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 austin semiconductor, inc. plastic encapsulated microcircuit 128mb, x8 and x16 q-flash memory even sectored, single bit per cell architecture features ? 100% pin and function compatible to intel?s mlc family ? nor cell architecture ? 2.7v to 3.6v vcc ? 2.7v to 3.6v or 5v vpen (programming voltage) ? asynchronous page mode reads ? manufacturer?s id code: 9 numonyx 0x89h ? industry standard pin-out ? fully compatible ttl input and outputs ? common flash interface [cfi] ? scalable command set ? automatic write and erase algorithms ? 5.6us per byte effective programming time ? 128 bit protection register 9 64-bit unique device identifier 9 64-bit user programmable otp cells ? enhanced data protection feature with use of vpen=vss ? security otp block feature ? 100,000 erase cycles per block ? automatic suspend options: 9 block erase suspend-to-read 9 block erase suspend-to-program 9 program suspend-to-read ? available operating ranges: 9 enhanced [- et ] -40 o c to +105 o c 9 mil-temperature [- xt ] -55 o c to +125 o c for in-depth functional product detail and timing diagrams, please reference numonyx?s full product datasheet: embedded flash memor y (j3vd) dated: december 2007 general description asi?s, as28f128j3a enhanced or mil-temp variant of numonyx?s q-flash family of devices, is a nonvolatile, electrically block-erasable (flash), programmable memory device manufactured using numonyx?s 0.15um process technology. this device containing 134,217,728 bits organized as either 16,777,218 (x8) or 8,388,608 bytes (x16). the device is uniformly sectored with one hundred and twenty eight 128kb erase blocks. this device features in-system block locking. they also have a common flash interface [cfi] that permits software algorithms to be used for entire families of devices. the software is device-independent, jedec id-independent with forward and backward compatibility. a22 ce1 a21 a18 a17 a16 vcc a10 a9 a7 a6 a5 a4 a1 a13 a12 we\ oe\ dq7 dq14 dq6 vss dq12 dq4 dq10 dq2 dq1 dq8 dq0 a0 ce2 nc sts dq5 vcc a23 dq15 dq13 dq9 byte\ vccq dq11 vss a20 a14 a8 a2 a19 a15 vss a3 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 dq3 28 27 26 25 24 23 ce0 rp\ vpen a11 22 21 20 19 18 17 16 15 14 13 12 10 11 a b c d e f g h 1 23456 78 a1 a2 a3 a4 a6 a8 a7 a5 a10 a11 a12 a13 a14 a15 vpen ce0 vss a9 rp\ dnu dnu dnu dnu dnu dnu dnu ce2 a18 a19 a20 a16 a17 a21 a22 ce1 vcc dnu dq4 dq3 dq9 dq1 dq8 dq15 sts byte\ dq0 dq10 dq11 dq12 oe\ a23 a0 dq2 vccq dq5 dq6 dq14 we\ vss vcc dq13 vss dq7 dnu pin assignment 64-ball fbga
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 austin semiconductor, inc. additionally, the scaleable command set [scs] allows a single, simple software driver in all host systems to work with all scs compliant flash memory devices. the scs provides the fastest system/device data transfer rates and minimizes the device and system-level implementation costs. to optimize the processor-memory interface, the device accommodates vpen, which is switchable during block erase, program, or lock bit configurations and in addition can be hard-wired to vcc all dependent on the end application(s). vpen is treated as an input pin to enable erasing, programming, and block locking. when vpen is lower than the vcc lockout voltage (vlko), all program functions are disabled. block erase suspend mode enables the user to stop block erase to read data from or program data to any other blocks. similarly, program suspend mode enables the user to suspend programming to read data or execute code from any un-suspended block(s). vpen serves as an input with 2.7v, 3.3v or 5v levels for application programming. vpen in this q-flash device can provide data protection when connected to ground. this pin also enables program or erase lockout functions/ controls during power transitions. this device is an even-sectored device architecture offering individual block locking that can lock and un-lock a block using the sector lock bits command sequence. status [sts] is a logic signal output that gives an additional indicator of the internal state machine [ism] activity by providing a hardware signal of both the status and status masking. this status indicator minimizes central processing unit overhead and system power consumption. in the default mode, sts acts as an ry/by\ pin. when low, sts indicates that the ism is performing a block erase, program, or lock bit configuration. when high, sts indicates that the ism is ready for a new command. f u n c t i o n a l b l o c k d i a g r a m : c o m m a n d e x e c u t i o n l o g i c [ c e l ] cex oe\ we\ rp\ wp\ clk i s m p o w e r ( c u r r e n t ) c o n t r o l b u s c o n f i g u r a t i o n r e g i s t e r [ b c r ] sts vpen wait i / o c n t l l o g i c a d d r b u f f e r / l a t c h a d d r . c o u n t e r v p p s w i t c h p u m p s t a t u s r e g i s t e r i d e n t i f i c a t i o n r e g i s t e r q u e r y 128kb memory block (0) 128kb memory block (1) 128kb memory block (2) 128kb memory block (3) 128kb memory block (n) o u t p u t b u f f e r i n p u t b u f f e r w r i t e b u f f e r y d e c . x d e c o d e b l o c k e r a s e c o n t r o l y - s e l e c t c o n t r o l s e n s e a m p l i f i e r s w r i t e / e r a s e b i t c o m p a r e a n d v e r i f y d q 0 - 8 o r d q 0 - 1 5
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 austin semiconductor, inc. three chip enable (cex) pins are used for enabling and disabling the device by activating the device?s control logic, input buffer, decoders, and sense amplifiers. byte\ enables the device to be used in x8 or x16 configuration. byte=low (logic 0) selects and 8-bit mode with address zero (a0) selecting the high or low byte and byte=high (logic 1) selects the 16-bit or word mode. when the device is in word mode, address one (a1) becomes the low order address bit and address zero (a0) becomes a no-connect (nc). rp\ is used to reset the device. when the device is disabled and rp\ is at vcc, the standby mode is enabled. a reset time (trwh) is required after rp\ switches to a high (logic 1) and the outputs become valid. likewise, the device has a wake time (trs) from rp\ high until writes to the command user interface [cui] are recognized, resets the ism and clears the status register. parameter/condition symbol typ max units input capacitance cin 5 8 pf cbyte 14 16 pf cout 5 12 pf output capacitance capacitance stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. chip enable truth table ce2 ce1 ce0 device vil vil vil enabled vil vil vih disabled vil vih vil disabled vil vih vih disabled vih vil vil enabled vih vil vih enabled vih vih vil enabled vih vih vih disabled absolute maximum ratings voltage min max units notes temperature under bias r 55 125 o c storage temperature r 65 125 o c short circuit current 100 ma 1 notes 1: all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on vcc and vpen pins. during transitions, this level may undershoot to -2.0v for periods austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 austin semiconductor, inc. bus operations mode rp\ ce0 ce1 ce2 oe \ we\ vpen d q notes address sts default mode read array vih enabled enabled enabled vil vih x dout 1,2,3 x high r z (voh with external pu) output disable vih enabled enabled enabled vih vhi x high r zx x standby vih disabled disabled disabled x x x high r zx x reset/power r down vil xxxxxx high r z x high r z (voh with external pu) read identifier codes vih enabled enabled enabled vil vih x 4 see table 31 of numonyx ds high r z (voh with external pu) read query vih enabled enabled enabled vil vih x 5 see cfi query of numonyx ds high r z (voh with external pu) read status (ism off) vih enabled enabled enabled vil vih x x x read status (ism on) vih enabled enabled enabled vil vih x dout x x write vih enabled enabled enabled vih vil vpenh din 3,6,7 x x notes 1 refer to dc characteristics. when vpen austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 austin semiconductor, inc. memory command set operations scalable or basic command command set [scs or bcs] bus cycles operation address data operation address data notes read array scs/bcs 1 write x ffh read identifier codes scs/bcs >/=2 write x 90h read ia id 1 read query scs write x 98h read qa qd read status register scs/bcs 2 write x 70h read x srd 2 clear status register scs/bcs 1 write x 50h write to buffer scs/bcs >2 write ba e8h write ba n 3,4,5 word/byte program scs/bcs 2 write x 40h or 10h write pa pd 6,7 block erase scs/bcs 2 write ba 20h write ba d0h 5,6 block erase/program suspend scs/bcs 1 write x b0h 7,8 block erase/program resume scs/bcs 1 write x d0h 7 configuration scs 2 write x b8h write x cc set block lock bits scs 2 write x 60h write ba 01h clear block lock bits scs 2 write x 60h write x d0h protection program 2 write x c0h write pa pd first bus cycle second bus cycle key: [ia] identifier code address [id] data read from identifier code [ba] address within a block [qa] query data base address [pa] address of memory location to be programmed [qd] data read from query data base [srd] data read from status register notes [1] following the read identifier codes command, read operations access manufacturer, device, and block lock codes. [2] if the ism is running, only dq7 is valid; dq15-dq8 and dq6-dq0 are placed in high-z [3] after the write-to-buffer command is issued, check the xsr to make sure a buffer is available for writing [4] the number of bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. count ranges on this de vice for byte mode are n=00h to n=1fh and for word mode, n=0000h to 000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n+1 write cycles; any other command at that point in the sequence aborts the write-to-buffer operation. [5] the write-to-buffer or erase operation does not begin until a confirm command (d0h) is issued [6] attempts to issue a block erase or program to a locked block will fail [7] etiher 40h or 10h is recognized by the ism as the byte/word program setup [8] program suspend can be issued after either the write-to-buffer or word/byte program operation is inititated. the clear block lock bits operation simultaneously clears all block lock bits.
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 austin semiconductor, inc. ac switching characteristics (vdd=3.0v ?5%/+10%, ta= min. / max. temperatures of operational range chosen) paramete r symbol units notes write operations min max rp\ high recovery to we\ (cex) going lo w trs 1.0 us 1 cex (we\) low to we\ (cex) going lo w tcs 0 ns write pulse width twp 70.0 ns data setup to we\ going high tds 50.0 ns address setup to we\ going high tas 55.0 us cex hold from we\ high tch 0 ns data hold from we\ high tdh 0 address hold from we\ high tah 0 write pulse width high twph 30 ns vpen setup to we\ going high tvps 0 ns 1 write recovery before read twr 35 ns we\ high to sts going lo w tsts 200 ns vpen hold from valid srd, sts going high tvph 0 ns 1 we\ high to status registry bus y twb 200 ns 1 block erase, program and lock bit performanc e typ max write buffer byte program time (program time 32 bytes/ 16 words) twed1 180 654 us byte/word program time twed2 125 630 us block program time twed3 0.70 2.4 sec block erase time twed4 1.00 5 sec set lock bits time twed5 50 75 us clear block lock bits time twed6 0.50 0.7 sec program suspend latency time to read tlps 25 30 us erase suspend latency time to read tles 25 35 us read only operation s min max read cycle time trc 115 ns address to output dela y taa 115 ns cex to output dela y tace 115 ns oe\ to non r array output dela y taoe 50 ns oe\ to array output dela y taoa 25 ns rp\ high to output dela y trwh 210 ns cex to output in low r z toec 0 ns 1 oe\ to output in low r z toeo 0 ns 1 cex high to output in high r z todc 35 ns 1 oe\ high to output in high r z todo 15 ns 1 output hold from address, cex, or oe\ change, whichever occurs firs t toh 0 ns 1 cex low to byte\ high or lo w tcb 10 ns 1 byte\ to output delay taby 1000 ns 1 byte\ to output in high r z todb 1000 ns 1 cex high to cex lo w tcwh 0.0 ns 1 page address access tapa 25 ns reset specifications min max rp\ pulse low time tplph 35 us rp\ high to reset during block erase, program, or lock bit configuratio n tphrh 100 ns 128mb notes to switching specifications: 1. sampled, not 100% tested
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 austin semiconductor, inc. mechanical diagram tsop, type 1, 56 pin (dimensions in mm) 20.00 +/- 0.25 18.40 +/- 0.08 14.00 +/- 0.08 0.15 +0.03, -0.02 0.10 1.20 max. 0.20 +/- 0.05 0.50 typ. see detail a detail a 0.50 +/- 0.10 0.80 typ. 0.10 + 0.10, -0.05 0.25 0.25 gage plane
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 austin semiconductor, inc. mechanical diagram pbga, 10mm x 13mm, 64 ball w/ 1.00 pitch (dimensions in mm) 10.00 +/-0.10 3.50 +/-0.05 7.00 13.00 +/-0.10 6.50 +/-0.05 1.00 typ. (bottom view) ball a1 id ball a1 7.00 0.10 c c seating plane ball a1 corner id alt. ball a1 id 1.20 max. solder ball material: 62% sn., 36% pb., 2% ag. 0.85 +/-0.075 x64 @ 0.45 diameter, post reflow lot code date code oeu86 xt as28f128j3 apbg-15 asi ordering information asi part numbe r configuration speed (ns) pkg. comments as28f128j3arg r 15/et 128mb, x8/x16 q r flash 115 tsop1 r 56 as28f128j3apbg r 15/et 128mb, x8/x16 q r flash 115 fbga r 64 consult factory, moq's apply as28f128j3arg r 15/xt 128mb, x8/x16 q r flash 115 tsop1 r 56 as28f128j3apbg r 15/xt 128mb, x8/x16 q r flash 115 fbga r 64 consult factory, moq's apply enhanced operating range ( r 40 o c to +105 o c) extended operating range ( r 55 0 c to +125 0 c)
austin semiconductor, inc. pem pem pem pem pem as28f128j3a q-flash as28f128j3a rev. 5.5 3/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 austin semiconductor, inc. document title plastic encapsulated microcircuit 128mb, x8 and x16 q-flash memory even sectored, single bit per cell architecture revision history rev # history release date status 5.5 updated with numonyx info march 2009 release
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