 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MP6902 fast turn-off intelligent controller MP6902 rev. 1. 13 www.monolithicpower.com 1 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology descri ption the mp690 2 is a low-drop diode emulator ic for flyback converters which comb ined with an external switch replace s schottky rectificat ion diodes for high efficie ncy. the chip regulate s the forward drop of an external switch to about 70mv and switches it off as soon as the voltage becomes n egative. MP6902 has a light-loa d sleep mode that redu ce s the quiescent current to <300ua. features ? supports dcm and qu asi-resona nt flyback converters ? works with 12v standard and 5v logic level fets ? compatible with energy star, 1w standby requiremen ts ? v dd range from 8v to 24v ? fast turn-of f total dela y of 20ns ? max 400khz switching f r equency ? <300 a qui e scent current at light load mode ? supports high-side and low-side rectification ? power savi ngs of up to 1.5w in a t y pical notebook adapter appli c ations ? industrial po wer syste m s ? distributed power systems ? battery powered systems ? flyback converters all m ps p ar t s ar e le ad- fre e an d adh er e to th e r ohs d i r e ctiv e. f o r m p s g r e e n sta t u s , plea se v isit mps w ebsite under quali t y assuran c e. ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. typical application http://
MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 2 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking MP6902ds soic8 MP6902ds * for tap e & reel, ad d suf f ix ?z (e.g. MP6902 ds?z ); for rohs co mpliant packaging, ad d su ffix ?lf; (e.g. MP6902 ds? l f?z ) package reference pgnd en ll v d v g nc v dd v ss 1 2 3 4 8 7 6 5 t op view absolute m a xi mum ratings (1) v dd to v ss ...................................... -0.3v to +27v pgnd to v ss ................................ -0.3v to +0.3v v g to v ss ......................................... -0.3v to v cc v d to v ss ..................................... -0.7v to +180v ll, en to v ss ............................... -0.3v to +6.5v maxi mum operating fre quency............ 400 khz continuous power dissipation (t a =+25 c) (2) ............................................................. 1.4w junction te mperature ............................... 150 c lead temperature (solder)....................... 260 c storage temperature .............. -55c to +150 c recommended operation conditions (3) v dd to v ss ............................................ 8v to 24v operating junction temp. (t j ) . ... -40c to +125c thermal resistance (4) ja jc soic8 ..................................... 90 ...... 45 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction tempe r ature t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the ma ximu m allow able cont inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . exceedi ng the m a ximum allow a ble po w e r dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on je sd51-7, 4 - la y e r pcb. MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 3 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. electri c al characteristi cs v dd = 12v, t a = +25 c, unless otherw ise noted . parameter sy mbol conditio ns min t y p max units v dd voltage ran g e 8 24 v v dd uvlo ri sing 5.0 6.0 7.0 v v dd uvlo hystere s i s 0.8 1 1.2 v operating cu rre nt i cc c load =5nf, f sw =1 00 kh z 8 10 ma quie scent current i q v ss -v d =0. 5 v 2 3 ma v dd =4v 210 255 shutdown cu rre nt v dd =20v, en=0v 375 440 a light-lo ad mo de cu rrent 290 380 a therma l shut down 150 o c therma l shut down hyste r e s is 30 o c enable uvlo risin g 1.1 1.5 1.9 v enable uvlo hysteresi s 0.2 0.4 v internal pull -up cu rrent o n en pin 10 15 a co ntr o l c i rc uitry s e ction v ss ?v d forward voltag e v fwd 55 70 85 mv t don c load = 5nf 150 ns turn -on dela y t don c load = 10nf 250 ns input bias cu rre nt on v d pin v d = 180v 1 a minimum on-time (5) t mi n c load = 5nf 1.6 s light-lo a d - ent er del a y t ll-dela y r ll =10 0 k ? 100 s light-lo a d - ent er pulse widt h t ll r ll =10 0 k ? 1.3 1.75 2.2 s light-lo a d - ent er pulse width hysteresi s t ll-h r ll =10 0 k ? 0.2 s light-lo ad re sisto r value r ll 30 300 k ? light-load mode exit pulse width th re sh old (v ds ) v ll-ds -400 -250 -150 mv light-lo ad m ode enter pulse width th re sh old (v gs ) (5) v ll-gs 1.0 v gate driver section v g (low) i load =1ma 0.05 0.1 v v dd >17v 13 14 15 v v g (high ) v dd <17v v dd -2.2 turn-off thr e shol d (v ss -v d ) 30 mv turn -off prop agation delay v d =v ss 15 ns t doff v d =v ss , c loa d =5nf, r gat e =0 35 ns turn-off total delay t doff v d =v ss , c loa d =10n f, r gat e =0 ? 45 ns pull down impeda nce 1 2 ? pull down cu rre nt (5) 3v MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 5 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v dd = 12v, unless otherwise noted. notes : 6) see figure 1 3 fo r the test circuit. MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 6 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. block diagram figure 1?function block diagram MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 7 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. operation the mp690 2 supports operation in dcm an d quasi-resonant flyback converters. the control circuitry con t rols the gate in forward mode an d will turn the gate off when the mosf et current i s fairly low. blanking the control circuitry con t ains a b l an king fun c tio n . when it pulls the mosf et on/off, it makes sur e that the on/ off state at least last s fo r some time. the turn o n blanking time is ~ 1 .6us, which determines the minimu m on-time. du ring the turn on blanking period, the turn off threshold is n o t totally blan ked, but changes t he thresho l d voltage to ~+50mv (i nstead of -30mv). th is assures tha t the part can always be turned off even during the turn on blanking p e riod. (albeit slower) vd clamp because v d can go a s high as 1 80v, a hig h - voltage jf et is u s ed at the inp u t. to avoid excessive currents when vg goes b e low -0.7v, a small resist or is re commended between v d and the drain of t he external mosfet. under-voltage lockout (uvlo) when the vdd is below uvlo thres hold, the par t is in sleep mode and the vg pin is pu lled low by a 10k resi st or. enable pin if en is pulled low, the part is in sle ep mode. thermal shutdow n if the junction temperat ure of the chip exceeds 170 o c, the vg will be pulled low and the par t stops switching. the part will return to normal function af t e r the jun c tion temp erature ha s dropped to 120 o c. thermal design if the dissipation of t he chip is higher than 100mw du e to switching frequencies above 100khz. turn-on ph ase when the synchronous mosfet i s conductin g , current will flow throu gh its body diode which generates a negative vds across it. because this body diode voltage drop (<-500mv) is much smaller than the turn on threshold o f the control circuitry (-70mv), whic h will then pull the gat e driver volta ge high to turn on the synchronous mosfet after about 150ns tu rn on delay (defined in figure 2). as soon a s the turn on threshold (-70mv) is triggered, a blanking t i me (minimum on-time : ~1.6us) will be added during which the turn off threshold will be change d from -30mv to +50mv. this blankin g time can help to avoid error trigger on turn off threshold caused by the turn on ringing of th e synchronous mosfet . v ds v gate t don t doff -7 0 m v -3 0 m v 2v to t a l t 5v figure 2?turn on and turn off dela y conducting phase when the synchronous mosfet is turned on, vds beco m es to rise according to its on resistance , as soon as vds rises a bove the turn on threshold (-70mv), the control circuitry sto p s pulling up t he gate dr i v er which l eads the g ate voltage is p u lled down by the inter nal pull-dow n resistance ( 10k ? ) to lar ger the on resistance o f synchronous mosfet to ease th e rise of v d s. by doing that, vds is adjusted to be around - 70mv even when the current through the mos i s fairly small, this function can ma ke the driver voltage fairly low when the synchronous mosfet is turned off t o fast t he t urn off sp ee d (this functio n is still act i ve during tu rn on blankin g time which means the gate driver could still b e turned off even with very s m all duty of the synchronous mosfet). MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 8 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. turn-off ph ase when vds r i ses to trigg er the turn o ff threshold ( - 30mv), the gate volta ge is pulle d to low af ter about 20ns turn off de la y (defined in figure 2) by the control circuitry. simi lar with turn-on phase, a 200ns bla nking time is adde d after the synchronous mosfet i s turned off to avoid error trigger. figure 3 shows synchronous rectif icat ion operation at heavy load condit i on. due to the high current , the gate driver will be saturated a t first, during which the g a te driver voltage is ke pt at ~2v lower than v dd (when v dd >16v, ga te driver will b e internal cl amped at 14v). after vds goes to a bove -70mv, gate dr iver voltage decreases t o adjust the vds to typical -70mv. figure 4 shows synchronous rectif icat ion operation at light load condition. due to the low current, the gate driver voltage never saturates but begins to decre ase as soon as th e synchronous mosfet is turne d on and adjust the vds. -70mv -30 m v vds isd vg s t 0 t1 t2 figure 3?sy nchronou s rectification operation at heavy load -70m v -3 0 m v vds is d vg s t0 t 1 t 2 figure 4 ? synchronous rectification operation at light load figure 5?drain-source and gate driver voltage on sr mofet figure 5 shows t he whole synchron ous rectificat ion waveform on drain-source volta g e v ds and gat e driver signal v gs . for safe operation of the ic, it is required: ou t i n d s _ spi k e v v / n v 180 v * k + +< where 180v is the maximum voltage rating on v d pin of MP6902, v in /v out is the in put/output dc voltage, n is the turn ratio from primary t o secondary of the powe r transformer, v ds_spike is the spike voltage on d r ain-source which is lea d by leakage inductance, while k is the de-ratin g factor which is usually selected as 0 . 7~0.8. light-load latch-off function the gate driver of mp69 02 is latched to save the driver loss at light-load condition to improve efficiency. when the synchronous mosfet?s conducting period keeps lower than light load timing (t ll ) for longer than the light-load-enter delay (t ll-delay ), MP6902 enters light-load mode and latches off the gate driver. here the synchronous mosfet?s conducting period is from turn on of the gate driver to the moment when v gs drops to below 1v (v ll_gs ). during light-load mode, MP6902 monitors the synchronous mosfet?s body diode conducting period by sensing the time duration of the v ds below -250mv(v ll_ds ). if it is longer than t ll +t ll- h (t ll-h , light-load-enter pulse width hysteresis), the light-load mode is finished and gate driver of MP6902 is unlatched to restart the synchronous rectification. MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 9 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. for MP6902, the light load enter timing (t ll ) is programmable by connecting a resistor (r ll ) on ll pin, by monitoring the ll pin current (the ll pin voltage keeps at ~2v internally), t ll is set as following: ll ll 2. 2 s tr ( k ) 100 k ? ? sr mosfet selection and driver ability the power mosfet sele ction proved to be a trad e off between ron and qg. in order to achieve hig h efficiency, t he mosfet with smaller ron is always preferred, while the qg is usually larger with smaller ron, which mak e s the turn-on/off spee d lower and lead to larger power loss. for MP6902 , because vd s is regu lat ed at ~-70mv during the driving period, the mosfet with too small ron is not recommend, because the gate driver ma y b e pulled down to a fairly low level with too small ron when t he mosfet current is still fairly high, which make the advantage of the low ron inconspicuo u s. figure 6 shows the typical wave form of qr flyback. assume 50% duty cycle and the output current is i out . to achieve fairly high usage of the mosfet?s ron, it is expected that the m o sfet be fu lly turned on at least 50% of the sr conduction period: ou t vd s i c ron 2 i ro n v f w d =? = ? ? ? where v ds is drain-source voltage of the mosfet and v fw d is the forward voltage threshold o f MP6902, wh ich is ~70m v. so the mosfet?s ron is recommen ded to be n o lower than ~35/i out (m ? ). (for example, for 5a application , the ro n of the mosfet is recommend ed to be no lower than 7m ? ) figure 7 shows the correspondin g total delay during turn-on period (t tot a l , see figure 2) wit h driving diffe rent qg mosfet by MP6902. from figure 7, w i th driving a 120nc qg mosfet, th e driver ability of MP6902 is able to pu ll up the gat e driver volta ge of the mosfet to ~5v in 300ns as soon as t he body diode of th e mosfet is conducting, which greatly save the t u rn-on power loss in t he mosfet?s bo dy diode. id ip e a k vg s r conduction period 50% s r co n d u c t i on p e r i o d ic ip e a k ? 4 i ou t ic ? 2 i ou t figure 6?sy nchronou s rectification ty pical w a v e forms in qr fl y b a c k t u r n- on d el ay v s . q g 0 50 100 150 200 250 300 350 0 20 40 60 80 1 00 12 0 14 0 qg ( n c ) t o t a l d e la y ( n s ) figure 7?total turn-on dela y vs. qg t y pical sy s t em implementations 6 1 5 8 3 4 mp 6 9 0 2 r1 r3 c1 c2 c3 vd vd d pg n d ll vs s vg en r2 2 figure 8? ic suppl y d e rived directl y from output voltage figure 8 shows the typical syst em implementat ion for the ic supply derived from output voltage, which is available in low-sid e rectificat ion and the output voltage is recommend ed to be in t he v dd range of MP6902 (from 8v to 24v). if output v o ltage is o u t of the v dd range of MP6902 or high-side r ectificat ion is used, it is recommended to use a n auxiliary winding fro m the power transformer for the ic supply, which is shown in figure 9 and figure.10. MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 10 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. 6 1 r3 5 8 3 c3 4 MP6902 c2 r1 r2 r4 c1 d1 vd vd d pg nd ll vs s vg en 2 figure 9? ic suppl y d e rived from auxiliary winding in low -side r ectification r1 r2 r3 c3 r4 c2 c1 d1 vd vss ll vg pgn d vd d en 2 m p 6902 1 3 5 8 4 6 figure 10? ic suppl y derived from auxiliary winding in high-side rectification there is another non-auxiliary win d ing solutio n for the ic supply, which uses an external ldo circuit from the secondary transformer windin g . see figure.11 and figure.12, co mpared with using auxilia ry winding for ic supply, this solutio n has a bit higher power loss which is dissipate on the ldo circuit esp e cia lly when the secondar y winding voltage is high. 6 1 r3 5 8 3 3 c 4 MP6902 2 c r4 r5 d1 d2 1 c r1 r2 pgn d vd d 2 ll vss vd en vg figure 11? ic suppl y derived from secondary winding through external ldo in low -side r ectification r4 r5 d1 d2 c2 c1 r1 r2 r3 c3 m p 6 902 vg ll vss pgn d v d d vd 2 en 1 6 3 5 4 8 figure 12? ic suppl y derived from secondary winding through external ldo in high-side rectification MP6902- f a s t t urn- off intelligent con t rolle r MP6902 rev. 1. 13 www.monolithicpower.com 11 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical application circuit figure 13?MP6902 for secondary sy nchrono us controller in 90w fl y back app lication MP6902- f a s t t urn- off intelligent con t rolle r notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP6902 rev. 1. 13 www.monolithicpower.com 12 1/11/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. package informati o n soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0. 0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0 . 013(0 .33) 0 . 020(0 .51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.0 53(1.3 5) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) cont rol d i mension is in in ches. d imension in bra cket is in millimeter s . 2) pac kage len gt h does not in cl ude mold fl ash, protru sion s or ga te bu rrs. 3) pac kage width does not in clu de int e rlea d fl ash or protru sion s. 4) l e a d copla nar ity (bottom of l e ads a f t e r formin g ) shal l be 0 . 004" in ches max. 5) dr awing conf or ms to jedec ms-012, va riat ion aa. 6) dr awing is not to scale. 0.010(0.25) bsc gauge plane |
Price & Availability of MP6902
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |