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september 2003 1/148 . ST92186B 8/16-bit mcu for tv applications with up to 32k rom and enhanced on-screen-display n register file based 8/16 bit core architecture with run, wfi, and halt modes n -10 to 70c operating temperature range n 24 mhz operation @5v+-10% n minimum instruction cycle time: 250ns at 16 mhz internal clock, 165ns at 24 mhz internal clock n 24 or 32 kbytes rom n 640 bytes of on-chip static ram n 256 bytes of register file n 256 bytes of display ram (osdram) n 32-pin shrink dip and 42-pin shrink dip packages n 26 (sdip42) or 17 (sdip32) fully programmable i/o pins n flexible clock controller for osd and core clocks, running from one single low frequency external crystal n enhanced display controller with rows of up to 63 characters per row C 50/60hz and 100/120 hz operation C 525/625 lines operation, 4/3 or 16/9 format C interlaced and progressive scanning C 18x26 or 9x13 character matrix C 256 (18x26) characters, 1024 (9x13) charac- ters definable in rom by user C 512 possible colors, in 4x16-entry palettes C 2 x 16-entry palettes for foreground, and 2 x 16-entry palettes for background C 8 levels of translucency on fast blanking C serial, parallel, and extended parallel at- tributes modes C 7 character sizes in 18x26 mode, 4 in 9x13 C rounding, fringe, scrolling, flashing, shad- owing, italics, semi-transparent n 5-channel (sdip42) or 3-channel (sdip32) analog-to-digital converter with 6-bit accuracy n 16-bit watchdog timer with 8-bit prescaler n 14-bit voltage synthesis for tuning reference voltage with 2 outputs (sdip42) for 2 tuners or 1 output (sdip32) for 1 tuner n 16-bit standard timer with 8-bit prescaler n 6 (sdip42) or 4 (sdip32) 8-bit programmable pwm outputs n nmi and 8 (sdip42) or 6 (sdip32) external interrupts n infra-red signal digital pre-processor n rich instruction set and 14 addressing modes n versatile development tools, including c- compiler, assembler, linker n source level debugger, emulator and real- time operating systems available from third- parties n windows based osd font and screen editor n eprom and otp devices available (st92e196a9 and st92t196a9) device summary device program memory package ST92186B3 24k sdip32/sdip42 ST92186B4 32k sdip32/sdip42 psdip32 psdip42 2
2/148 table of contents 148 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 i/o port reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 ST92186B register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.2 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.3 register pointing techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.4 paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.5 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.6 stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2.4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.1 addressing 16-kbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 addressing 64-kbyte segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.1 dpr[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.2 csr: code segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7.3 isr: interrupt segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8.1 normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.1 divide by zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.2 segment paging during interrupt routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1 priority level 7 (lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/148 table of contents 3.4.2 maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.3 simultaneous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.4 dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5.1 concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5.2 nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7 top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.8 on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.10 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 reset and clock control unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.1 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 4.4 reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 timing and clock controller (tcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1 frequency multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.1 pin declared as i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.2 pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.3 pin declared as an alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.7 configuration of unbonded i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1 timer/watchdog (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1.3 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1.4 wdt interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.2 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2.3 interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2.4 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4/148 table of contents 148 7.3 osdram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.3 osdram controller reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4 on screen display controller (osd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.2 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.4 horizontal and vertical sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.5 programming the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.6 programming the color palettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4.7 programming the row buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.5 ir preprocessor (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.5.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.6 voltage synthesis tuning converter (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.6.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 7.6.2 output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.6.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.7 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 28 7.7.2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.8 a/d converter (a/d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33 7.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.8.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 9.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5/148 ST92186B - general description 1 general description 1.1 introduction the ST92186B family brings the enhanced st9 register-based architecture to a new range of high- performance microcontrollers specifically de- signed for tv applications. their performance de- rives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. the intelligent on- chip peripherals offload the st9 core from i/o and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. the st9 mcu devices support low power consumption and low voltage operation for power-efficient and low-cost embedded sys- tems. 1.1.1 core architecture the nucleus of the ST92186B is the enhanced st9 core that includes the central processing unit (cpu), the register file and the interrupt con- troller. three independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register ad- dressing bus and a 6-bit interrupt bus which con- nects the interrupt controller in the on-chip periph- erals with the core. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off-chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. many opcodes specify byte or word operations, the hardware automatically handles 16-bit opera- tions and accesses. for interrupts or subroutine calls, the cpu uses a system stack in conjunction with the stack pointer (sp). a separate user stack has its own sp. the separate stacks, without size limitations, can be in on-chip ram (or in register file) or off-chip mem- ory. 1.1.2 instruction set the st9 instruction set consists of 94 instruction types, including instructions for bit handling, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats. instructions have been added to facilitate large program and data handling through the mmu, as well as to improve the performance and code density of c function calls. 14 address- ing modes are available, including powerful indi- rect addressing capabilities. the st9's bit-manipulation instructions are set, clear, complement, test and set, load, and various logic instructions (and, or, and xor). math func- tions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. 1.1.3 operating modes to optimize performance versus the power con- sumption of the device, st9 devices now support a range of operating modes that can be dynami- cally selected depending on the performance and functionality requirements of the application at a given moment. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). slow mode . power consumption can be signifi- cantly reduced by running the cpu and the periph- erals at reduced clock speed using the cpu pres- caler and ccu clock divider. wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (lp wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode.
6/148 ST92186B - general description introduction (contd) figure 1. ST92186B architectural block diagram (sdip42 package) watchdog timer 256 bytes register file 640bytes ram st9 core 8/16 bits cpu interrupt management memory bus rccu register bus a/d converter 32/24kbytes rom ain[4:0] extrg all alternate functions ( italic characters ) are mapped on ports 0, 2, 3, 4, and 5. oscin oscout reset reseti p0[4:3 ] p2[7:0] p3[7:4, 2:0] p4[7:6, 1:0] p5[6:5, 2:0] int[7:0] nmi fully prog. i/os osdram controller 256 bytes ram infra-red preprocessor pwm dac osd voltage synthesis ir pwm[7:6, 3:0] vso1 vso2 hsync vsync r/g/b/fb tslu pixclk frequency multiplier fcpu fosd standard timer
7/148 ST92186B - general description introduction (contd) figure 2. ST92186B architectural block diagram (sdip32 package) watchdog timer 256 bytes register file 640 bytes ram st9 core 8/16 bits cpu interrupt management memory bus rccu register bus a/d converter 32/24 kbytes rom ain[[4:3, 0] extrg all alternate functions ( italic characters ) are mapped on ports 0, 2, 3, 4, and 5. oscin oscout reset reseti p0[4:3 ] p2[7:3, 0] p3[6, 4, 2, 0] p4[7:6, 1:0] p5.0 int[7, 5:4, 2:0] nmi fully prog. i/os osdram controller 256 bytes ram infra-red preprocessor pwm dac osd voltage synthesis ir pwm[7:6, 1:0] vso2 hsync vsync r/g/b/fb tslu pixclk frequency multiplier fcpu fosd standard timer
8/148 ST92186B - general description introduction (contd) 1.1.4 on-chip peripherals osd controller the on screen display displays any text or menu data generated by the application. rows of up to 63 characters can be displayed with two user-de- finable fonts. colors, character shape and other attributes are software programmable. parallel i/o ports the st9 is provided with dedicated lines for input/ output. these lines, grouped into 8-bit ports, can be independently programmed to provide parallel input/output or to carry input/output signals to or from the on-chip peripherals and core. all ports have active pull-ups and pull-down resistors com- patible with ttl loads. in addition pull-ups can be turned off for open drain operation and weak pull- ups can be turned on to save chip resistive pull- ups. input buffers can be either ttl or cmos compatible. analog/digital converter the adc provides up to 5 (sdip42) or 3 (sdip32) analog inputs with on-chip sample and hold.
9/148 ST92186B - general description 1.2 pin description figure 3. 32-pin package pin-out figure 4. 42-pin package pin-out 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 reseti/ p5.0 test0 g b fb tslu/p3.0 int0/p3.2 int1/p3.4 ain4/p0.4 pixclk/int5/p2.7 nmi/p2.6 p2.5 int2/p2.4 p3.6 ain0/p0.3 reset p4.1/pwm1 vdd1 vss1 fcpu vdda fosd vsync hsync oscin p4.0/pwm0 p2.0/ir/int7 r oscout p2.3/vso2/ain3/int4 p4.6/pwm6 p4.7/pwm7/extrg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 40 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 test0 int0/p3.2 p3.5 p3.6 ain0/p0.3 pixclk/int5/p2.7 nmi/p2.6 p2.5 int2/p2.4 ain4/p0.4 int1/p3.4 g b tslu/p3.0 p3.1 fb r p5.0/reseti reset hsync p2.1/ain1/int6 p2.2/vso1/ain2/int3 p2.3/vso2/ain3/int4 oscout p4.1/pwm1 p4.6/pwm6 p4.7/pwm7/extrg oscin p4.0/pwm0 p2.0/ir/int7 vss1 fcpu fosd vsync vdda vdd1 pwm2/p5.5 pwm3/p5.6 p3.7 p5.2 p5.1 vss2
10/148 ST92186B - general description pin description (contd) table 1. power supply pins table 2. primary function pins name function psdip32 psdip42 v dd1 main power supply voltage 17 22 v ss1 v ss2 analog and digital circuit ground 18 23 -34 v dda analog circuit supply voltage 20 25 name function psdip32 psdip42 oscin oscillator input 27 35 oscout oscillator output 26 33 reset reset to initialize the st9 32 40 hsync video horizontal sync input (schmitt trigger) 23 28 vsync video vertical sync input (sch- mitt trigger) 22 27 r red video analog dac output 16 21 g green video analog dac output 15 20 b blue video analog dac output 14 19 fb fast blanking analog dac output 13 18 fcpu cpu frequency multiplier filter output 19 24 fosd osd frequency multiplier filter output 21 26 test0 test input (must be tied to v dd )22
11/148 ST92186B - general description pin description (contd) 1.2.1 i/o port configuration all ports can be individually configured as input, bi- directional, output, or alternate function. refer to the port bit configuration table in the i/o port chapter. no i/o pins have any physical weak pull-up capa- bility (they will show no pull-up if they are pro- grammed in the "weak pull-up" software mode). input levels can be selected on a bit basis by choosing between ttl or cmos input levels for i/ o port pin except for p2.(5:4,0), p3.(6:4,1:0), p4.(1:0) which are implemented with a schmitt trigger function. all port output configurations can be software se- lected on a bit basis to provide push-pull or open drain driving capabilities. for all ports, when con- figured as open-drain, the voltage on the pin must never exceed the v dd power line value (refer to electrical characteristics section). warning: some i/os are not bonded in the sdip32 pack- age. you must configure these unbonded i/os (i.e. p2.1, p2.2, p3.1, p3.5, p3.7, p5.1, p5.2, p5.5 and p5.6) as output push-pull at the very first begin- ning of your software and never change this con- figuration after initialization. this will avoid unpre- dictable software behavior. 1.2.2 i/o port reset state i/os are reset asynchronously as soon as the re- set pin is asserted low. all i/os are forced by the reset in "weak pull-up" configuration mode (but some are in high imped- ance due to the lack of physical pull-up) except p5.0 (refer to the reset section) which is forced into the "push-pull alternate function" mode until being reconfigured by software. warning: when a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always in- puts to the alternate function module declared as input. when any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. when a given pin is declared to be connected to an analog alternate function input (adc input for example) and if this pin is programmed in the "af-od" mode, the digit- al input path is disconnected from the pin to pre- vent any dc consumption. table 3. i/o port characteristics legend: od = open drain, af = alternate function input output weak pull-up reset state port 0[4:3] ttl/cmos push-pull/od no bidirectional port 2.0 port 2[3:1] port 2[5:4] port 2[7:6] schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od no no no no bidirectional bidirectional bidirectional bidirectional port 3[0:1] port 3.2 port 3[6:4] port 3.7 schmitt trigger ttl/cmos schmitt trigger ttl/cmos push-pull/od push-pull/od push-pull/od push-pull/od no no no no bidirectional bidirectional bidirectional bidirectional port 4[1:0] port 4[7:6] schmitt trigger ttl/cmos push-pull/od push-pull/od no no bidirectional bidirectional port 5.0 port 5[2:1] port 5[6:5] ttl/cmos ttl/cmos ttl/cmos push-pull/od push-pull/od push-pull/od no no no push-pull af out bidirectional bidirectional
12/148 ST92186B - general description table 4. ST92186B alternate functions port name general purpose i/o pin no. alternate function sdip32 sdip42 p0.3 all ports useable for general pur- pose i/o (in- put, output or bidirec- tional) 8 8 ain0 i a/d analog data input 0 p0.4 7 7 ain4 i a/d analog data input 4 p2.0 24 29 ir i ifr infrared input int7 external interrupt 7 p2.1 - 30 ain1 i a/d analog data input 1 int6 external interrupt 6 p2.2 - 31 int3 i external interrupt 3 ain2 a/d analog data input 2 vso1 o voltage synthesis converter output 1 p2.3 25 32 int4 i external interrupt 4 ain3 a/d analog data input 3 vso2 o voltage synthesis converter output 2 p2.4 3 3 int2 i external interrupt 2 p2.5 4 4 i/o p2.6 5 5 nmi i non maskable interrupt input p2.7 6 6 int5 i external interrupt 5 pixclk o pixel clock (after divide-by-2) output p3.0 12 17 tslu o translucency digital video output p3.1 - 16 i/o p3.2 11 15 int0 i external interrupt 0 p3.4 10 14 int1 i external interrupt 1 p3.5 - 13 i/o p3.6 9 12 i/o p3.7 - 11 i/o p4.0 28 36 pwm0 o pwm d/a converter output 0 p4.1 29 37 pwm1 o pwm d/a converter output 1 p4.6 30 38 pwm6 o pwm d/a converter output 6 p4.7 31 39 extrg i a/d converter external trigger input pwm7 o pwm d/a converter output 7 p5.0 1 41 reseti o internal delayed reset output p5.1 - 42 i/o p5.2 - 1 i/o p5.5 - 9 pwm2 o pwm d/a converter output 2 p5.6 - 10 pwm3 o pwm d/a converter output 3
13/148 ST92186B - general description 1.3 required external components v dd (+5v) 270 10k 1mf sw-push v dd (+5v) gnd gnd gnd gnd 56pf 56pf 1m 4mhz osc. 1.2k 47nf + warning: the decoupling capacitors between analog and digital +5v (v dda , v dd1 ) and ground (v ss1 , v ss2 ) are not shown. add a 100nf and a 4.7f capacitor close to the corresponding pins if needed. 100pf gnd 1.2k 47nf 100pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 40 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 test0 pwm2/p5.5 int0/p3.2 p3.5 p3.6 p3.7 ain0/p0.3 pixclk/int5/p2.7 nmi/p2.6 p2.5 int2/p2.4 pwm3/p5.6 p0.4/ain4 int1/p3.4 g b tslu/p3.0 p3.1 fb r p5.0/reseti reset hsync p2.1/ain1/int6 p2.2/vso1/ain2/int3 p2.3/vso2/ain3/int4 oscout p4.1/pwm1 p5.1 p4.6/pwm6 p4.7/pwm7/extrg oscin p4.0/pwm0 p2.0/ir/int7 vss1 fcpu fosd vsync vdda vdd1 p5.2 vss2
14/148 ST92186B - general description 1.4 memory map figure 5. ST92186B user memory map segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes 20f000h 20f27fh ram 640 bytes internal reserved segment 21h 64 kbytes 20ffffh 220000h 22ffffh 210000h segment 22h 64 kbytes 220000h 2200ffh 256 bytes osdram 32 kbytes page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh 24 kbytes 000000h 005fffh internal rom 007fffh
15/148 ST92186B - general description 1.5 interrupt vector table user isr program memory power-on reset divide-by-zero top level int. lo lo lo hi hi hi 000000h user main program user top level isr user divide-by-zero isr 0000ffh vector table isr address even odd int. vector register lo hi register file r240 r239 f page registers 000002h 000004h
16/148 ST92186B - general description 1.6 ST92186B register map table 6 contains the map of the group f peripheral pages. the common registers used by each peripheral are listed in table 5 . be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. C in particular, double-check that any registers with undefined reset values have been correct- ly initialised. warning : note that in the eivr and each ivr reg- ister, all bits are significant. take care when defin- ing base vector addresses that entries in the inter- rupt vector table do not overlap. table 5. common registers function or peripheral common registers adc cicr + nicr + i/o port registers wdt cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder
17/148 ST92186B - general description table 6. group f pages register map resources available on the ST92186B device: note 1: page 59, r242 and r243 are reserved on sdip32 register page 02311214243555962 r255 res. res. res. res. res res. res. res. vs res. r254 port 3 tcc r253 res. r252 wcr osd res. pwm r251 wdt res. r250 port 2 ir r249 res. r248 mmu ir r247 ext int res. res res. r246 port 5 extmi r245 res res. res r244 mmu r243 res. stim pwm 1) r242 port 0 port 4 rccu adc r241 res. res r240 rccu
18/148 ST92186B - general description table 7. detailed register map group f page dec. block reg. no. register name description reset value hex. doc. page n/a i/o port 0:5 r224 p0dr port 0 data register ff 62 r226 p2dr port 2 data register ff r227 p3dr port 3 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff core r230 cicr central interrupt control register 87 52 r231 flagr flag register 00 26 r232 rp0 pointer 0 register 00 28 r233 rp1 pointer 1 register 00 28 r234 ppr page pointer register 54 30 r235 moder mode register e0 30 r236 usphr user stack pointer high register xx 32 r237 usplr user stack pointer low register xx 32 r238 ssphr system stack pointer high reg. xx 32 r239 ssplr system stack pointer low reg. xx 32 0 int r242 eitr external interrupt trigger register 00 52 r243 eipr external interrupt pending reg. 00 53 r244 eimr external interrupt mask-bit reg. 00 53 r245 eiplr external interrupt priority level reg. ff 53 r246 eivr external interrupt vector register x6 54 r247 nicr nested interrupt control 00 54 wdt r248 wdthr watchdog timer high register ff 72 r249 wdtlr watchdog timer low register ff 72 r250 wdtpr watchdog timer prescaler reg. ff 73 r251 wdtcr watchdog timer control register 12 73 r252 wcr wait control register 7f 74 2 i/o port 0 r240 p0c0 port 0 configuration register 0 00 62 r241 p0c1 port 0 configuration register 1 00 r242 p0c2 port 0 configuration register 2 00 i/o port 2 r248 p2c0 port 2 configuration register 0 00 r249 p2c1 port 2 configuration register 1 00 r250 p2c2 port 2 configuration register 2 00 i/o port 3 r252 p3c0 port 3 configuration register 0 00 r253 p3c1 port 3 configuration register 1 00 r254 p3c2 port 3 configuration register 2 00
19/148 ST92186B - general description 3 i/o port 4 r240 p4c0 port 4 configuration register 0 00 62 r241 p4c1 port 4 configuration register 1 00 r242 p4c2 port 4 configuration register 2 00 i/o port 5 r244 p5c0 port 5 configuration register 0 00 r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 11 stim r240 sth counter high byte register ff 77 r241 stl counter low byte register ff 77 r242 stp standard timer prescaler register ff 77 r243 stc standard timer control register 14 77 21 mmu r240 dpr0 data page register 0 00 37 r241 dpr1 data page register 1 01 37 r242 dpr2 data page register 2 02 37 r243 dpr3 data page register 3 83 37 r244 csr code segment register 00 38 r248 isr interrupt segment register x0 38 r249 reserved extmi r246 emr2 external memory register 2 0f 55 42 osd r246 osdbcr2 border color register 2 x0 115 r247 osdbcr1 border color register 1 x0 115 r248 osder enable register 00 116 r249 osddr delay register xx 118 r250 osdfbr flag bit register xx 119 r251 osdslr scan line register xx 118 r252 osdmr mute register xx 120 43 ir r248 irpr infrared pulse register 00 122 r250 irscr infrared / sync control register 00 122 tcc r253 mccr main clock control register 00 61 r254 skccr skew clock control register 00 61 55 rccu r240 clkctl clock control register 00 56 r242 clk_flag clock flag register 48, 28 or 08 56 group f page dec. block reg. no. register name description reset value hex. doc. page
20/148 ST92186B - general description note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. note 1 : r242 and r243 are reserved on sdip32 59 pwm r240 cm0 compare register 0 00 130 r241 cm1 compare register 1 00 130 r242 cm2 1) compare register 2 00 130 r243 cm3 1) compare register 3 00 130 r244 reserved r245 r246 cm6 compare register 6 00 130 r247 cm7 compare register 7 00 130 r248 acr autoclear register ff 131 r249 ccr counter register 00 131 r250 pctl prescaler and control register 0c 131 r251 ocpl output complement register 00 132 r252 oer output enable register 00 132 vs r254 vsdr1 data and control register 1 00 127 r255 vsdr2 data register 2 00 127 62 adc r240 addtr channel i data register xx 135 r241 adclr control logic register 00 135 r242 adint ad interrupt register 01 136 group f page dec. block reg. no. register name description reset value hex. doc. page
21/148 ST92186B - device architecture 2 device architecture 2.1 core architecture the st9 core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt bus which connects the interrupt controller in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9 family devices highly efficient, both for numerical calculation, data handling and with re- gard to communication with on-chip peripheral re- sources. 2.2 memory spaces there are two separate memory spaces: C the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. C a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 6 . a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 7 ): C 224 general purpose registers (group 0 to d, registers r0 to r223) C 6 system registers in the system group (group e, registers r224 to r239) C up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 8 . figure 6. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132
22/148 ST92186B - device architecture memory spaces (contd) figure 7. register groups figure 8. page pointer for group f mapping f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234
23/148 ST92186B - device architecture figure 9. addressing the register file register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers
24/148 ST92186B - device architecture memory spaces (contd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 9 ). group d registers can only be ad- dressed in working register mode. note that an upper case r is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form rx , where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case r is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 2.3.3, and illustrated in figure 10 and in figure 11 . system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 2.3. paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these regis- ters therefore depends on the peripherals which are present in the specific st9 family device. in other words, pages only exist if the relevant pe- ripheral is present. table 8. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0
25/148 ST92186B - device architecture 2.3 system registers the system registers are listed in table 9 . they are used to perform all the important system set- tings. their purpose is described in the following pages. refer to the chapter dealing with i/o for a description of the port[5:2] and port0 data regis- ters. table 9. system registers (group e) 2.3.1 central interrupt control register please refer to the interrupt chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = reserved. this bit must be kept at 1. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bits 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) reserved r224 (e0h) port0 data reg. 70 - tlip tli ien iam cpl2 cpl1 cpl0
26/148 ST92186B - device architecture system registers (contd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in twos-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp
27/148 ST92186B - device architecture system registers (contd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the current st9 devices, the dp flag is only for compatibility with software developed for the first generation of st9 devices. with the single memory addressing space, its use is now redun- dant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form rxxx .
28/148 ST92186B - device architecture system registers (contd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bits 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0 = reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bits 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0 = reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0
29/148 ST92186B - device architecture system registers (contd) figure 10. pointing to a single group of 16 registers figure 11. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & register pointer 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8
30/148 ST92186B - device architecture system registers (contd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bit 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bit 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: C selection of internal or external system and user stack areas, C management of the clock frequency, C enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : oscin clock divided by 2 . this bit controls the divide-by-2 circuit operating on oscin. 0: clock divided by 1 1: clock divided by 2 bit 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on breq pin (where available). note: disregard this bit if breq pin is not availa- ble. bit 0 = himp : high impedance enable . when any of ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, ds, r/w) can be forced into the high impedance 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp
31/148 ST92186B - device architecture system registers (contd) state by setting the himp bit. when this bit is reset, it has no effect. setting the himp bit is recommended for noise re- duction when only internal memory is used. if port 1 and/or 2 are declared as an address and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the bottom of the stacks which are f illed using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is pushed in and post-incremented when data is popped out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix u . to use a stack in- struction for a word, the suffix w is added. these suffixes may be combined. when bytes (or words) are popped out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is popped from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: C interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. C subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. C link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 9 . stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group.
32/148 ST92186B - device architecture system registers (contd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 12. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 13. external stack mode 70 usp15 usp14 usp13 usp12 usp11 usp10 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 register file stack pointer (low) points to: stack 70 ssp15 ssp14 ssp13 ssp12 ssp11 ssp10 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) &
33/148 ST92186B - device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9 provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map.
34/148 ST92186B - device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 6 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 6 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of two 6-bit registers (csr and isr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory accesses during code execution (csr) and interrupts service routines (isr or csr). figure 14. page 21 registers isr emr2 reserved csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr reserved isr emr2 reserved csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr reserved isr emr2 reserved csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting) reserved
35/148 ST92186B - device architecture 2.6 address space extension to manage 4 mbytes of addressing space it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 15 ). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction popw dpr0 is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 15. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m s b 14 lsb
36/148 ST92186B - device architecture address space extension (contd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address program memory space during any code execution (normal code and interrupt routines). two registers are used: csr and isr. the 6-bit contents of one of the registers csr or isr define one out of 64 memory segments of 64 kbytes with- in the 4 mbytes address space. the register con- tents represent the 6 msbs of the memory ad- dress, whereas the 16 lsbs of the address (intra- segment address) are given by the virtual 16-bit address (see figure 16 ). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 14 . figure 16. addressing via csr and isr fetching program fetching interrupt instruction instruction 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr 1 2 1 2
37/148 ST92186B - device architecture mmu registers (contd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bits 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bits 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bits 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bits 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0_7 dpr0_6 dpr0_5 dpr0_4 dpr0_3 dpr0_2 dpr0_1 dpr0_0 70 dpr1_7 dpr1_6 dpr1_5 dpr1_4 dpr1_3 dpr1_2 dpr1_1 dpr1_0 70 dpr2_7 dpr2_6 dpr2_5 dpr2_4 dpr2_3 dpr2_2 dpr2_1 dpr2_0 70 dpr3_7 dpr3_6 dpr3_5 dpr3_4 dpr3_3 dpr3_2 dpr3_1 dpr3_0
38/148 ST92186B - device architecture mmu registers (contd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bits 7:6 = reserved, keep in reset state. bits 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bits 7:6 = reserved, keep in reset state. bits 5:0 = isr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines. these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space whenever an in- terrupt occurs: isr points to the 64-kbyte memory segment containing the interrupt vector table and the interrupt service routine code. see also the in- terrupts chapter. 70 00 csr_5 csr_4 csr_3 csr_2 csr_1 csr_0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0
39/148 ST92186B - device architecture mmu registers (contd) figure 17. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 16k
40/148 ST92186B - device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion.
41/148 ST92186B - interrupts 3 interrupts 3.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine. the st9 cpu can receive requests from the fol- lowing sources: C on-chip peripherals C external pins C top-level pseudo-non-maskable interrupt according to the on-chip peripheral features, an event occurrence can generate an interrupt re- quest which depends on the selected mode. up to eight external interrupt channels, with pro- grammable input trigger edge, are available. in ad- dition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the ex- ternal nmi pin (where available) to provide a non- maskable interrupt, or to the timer/watchdog. in- terrupt service routines are addressed through a vector table mapped in memory. figure 18. interrupt response n 3.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages. the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 3.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit
42/148 ST92186B - interrupts interrupt vectoring (contd) 3.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select whether the csr is saved or not when an interrupt occurs. for a description of the emr2 register, see page 55 . encsr = 0 if encsr is reset, for the duration of the interrupt service routine, isr is used instead of csr and only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. this mode ensures com- patibiliy with the original st9. encsr = 1 if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. 3.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: C the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). C the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 3.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests. if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 3.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 3.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. encsr bit 0 1 pushed/popped registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments
43/148 ST92186B - interrupts priority level arbitration (contd) 3.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel with the highest position in the chain, as shown in table 10 table 10. daisy chain priority note 1 : available on sdip42 only 3.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to modify dy- namically the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 19 figure 19. example of dynamic priority level modification in nested mode 3.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 3.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routines priority. this may cause undesirable interrupt response sequences. highest position lowest position inta0 inta1 intb0 intb1 intc0 intc1 intd0 intd1 int0/wdt int1/stim int2 int3 1) int4 /osd int5/adc int6 1) int7/ir 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program
44/148 ST92186B - interrupts arbitration modes (contd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 20 ) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 20. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request
45/148 ST92186B - interrupts arbitration modes (contd) example 2 in the second example, (more complex, figure 21 ), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 21. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei
46/148 ST92186B - interrupts arbitration modes (contd) 3.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C cpl is saved in the special nicr stack to hold the priority level of the suspended routine. C priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 22. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request
47/148 ST92186B - interrupts arbitration modes (contd) end of interrupt routine the iret interrupt return instruction executes the following steps: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. C if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 22 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 23 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level. figure 23. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei
48/148 ST92186B - interrupts 3.6 external interrupts the standard st9 core contains 8 external inter- rupt sources grouped into four pairs. table 11. external interrupt channel grouping note 1 : available on sdip42 only each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to 1, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 25 . the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2, prl1. for each pair, the even channel (a0,b0,c0,d0) of the group has the even priority level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 24. priority level examples n figure 24 shows an example of priority levels. figure 25 gives an overview of the external inter- rupt control bits and vectors. C the source of the interrupt channel a0 can be selected between the external pin int0 (when ia0s = 1, the reset value) or the on-chip timer/ watchdog peripheral (when ia0s = 0). C the source of the interrupt channel a1 can be selected between the external pin int4 (when ints = 1) or the on-chip standard timer. C the source of the interrupt channel intc0 can be selected between the int4 external pin (di- on=osde=0) or the display controller interrupt (all other cases) by programming the dion, osde bits in the osder register. C the source of the interrupt channel c1 can be selected between the external pin int5 (when the ad_int bit in the ad-int register=0) or the on-chip adc (when ad-int=1). C the source of the interrupt channel d1 can be selected between the external pin int7 (when the irwdis bit in the irsc register = 1) or the on-chip ir (when irwdis=0). warning: when using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. table 12. multiplexed interrupt sources external interrupt channel int7 int6 1) intd1 intd0 1) int5 int4 intc1 intc0 int3 1) int2 intb1 1) intb0 int1 int0 inta1 inta0 1001001 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priorit y source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr vr000151 0 100=4 101=5 channel internal interrupt source external interrupt source related pin sdip42 sdip32 inta0 timer/ watchdog int0 p3.2 inta1 stim timer int1 p3.4 intb0 int2 p2.4 intb1 int3 p2.2 - intc0 osd int4 p2.3 intc1 adc int5 p2.7 intd0 int6 p2.1 - intd1 ir int7 p2.0
49/148 ST92186B - interrupts external interrupts (contd) figure 25. external interrupts control bits and vectors n n int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 0 0 0 0 1 ia0s watchdog/timer end of count int 0 pin int a1 request int b0 request int 2 pin int b1 1) request int c0 request int c1 request int 5 pin int d0 1) request ted0 int 6 pin 1) int d1 request ted1 int 7 pin vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 0 1 v7 v6 v5 v4 0 1 0 0 v7 v6 v5 v4 0 1 1 0 v7 v6 v5 v4 1 0 0 0 v7 v6 v5 v4 1 0 1 0 v7 v6 v5 v4 1 1 0 0 v7 v6 v5 v4 1 1 1 0 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 * shared channels, see warning * ints std timer 0 1 tea0 teb0 pl2a pl1a 1 pl2c pl1c 0 pl2b pl1b 0 pl2a pl1a 1 pl2b pl1b 0 pl2c pl1c 0 pl2d pl1d 1 pl2d pl1d tea1 1 0 ad-int adc * 0 1 irdwis ir * tec1 * int 1 pin osd display teb1 tec0 int 3 pin 1) int 4 pin dion, odse * 0,0 * note 1 : available on sdip42 only
50/148 ST92186B - interrupts 3.7 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt, in any arbitration mode, not even by a subsequent top level inter- rupt request. warning : the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. 3.8 on-chip peripheral interrupts the general structure of the peripheral interrupt unit is described here, however each on-chip pe- ripheral has its own specific interrupt unit contain- ing one or more interrupt channels. please refer to the specific peripheral chapter for the description of its interrupt features and control registers. the on-chip peripheral interrupt channels provide the following control bits: C interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. C interrupt mask bit (im). if im = 0, no interrupt request is generated. if im =1 an interrupt re- quest is generated whenever ip = 1 and cicr.ien = 1. C priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) C interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. figure 26. top level interrupt structure n watchdog enable wden watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request
51/148 ST92186B - interrupts 3.9 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay.
52/148 ST92186B - interrupts 3.10 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = reserved this bit must be kept at 1. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generared when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bits 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event 70 - tlip tli ien iam cpl2 cpl1 cpl0 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0
53/148 ST92186B - interrupts interrupt registers (contd) external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bits 7:6 = pl2d, pl1d: intd0, d1 priority level. bits 5:4 = pl2c, pl1c : intc0, c1 priority level. bits 3:2 = pl2b, pl1b : intb0, b1 priority level. bits 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest)
54/148 ST92186B - interrupts interrupt registers (contd) external interrupt vector register (eivr ) r246 - read/write register page: 0 reset value: xxxx 0110b (x6h) bits 7:4 = v[7:4] : most significant nibble of exter- nal interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 25 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bits 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0
55/148 ST92186B - interrupts interrupt registers (contd) external memory register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bits 7, 5:0 = reserved, keep in reset state. refer to the external memory interface chapter. bit 6 = encsr : enable code segment register. this bit is set and cleared by software. it affects the st9 cpu behaviour whenever an interrupt re- quest is issued. 0: the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, isr is used instead of csr, and the in- terrupt stack frame is identical to that of the orig- inal st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. the drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service rou- tines is thus limited to 64k bytes. 1: isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service routines to access the entire 4 mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. 70 0encsr001111
56/148 ST92186B - reset and clock control unit (rccu) 4 reset and clock control unit (rccu) 4.1 introduction the reset and clock control unit (rccu) com- prises two distinct sections: C the clock control unit, which generates and manages the internal clock signals. C the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. 4.2 clock control registers mode register (moder) r235 - read/write system register reset value: 1110 0000 (e0h) *note : this register contains bits which relate to other functions; these are described in the chapter dealing with device architecture. only those bits relating to clock functions are described here. bit 5 = div2 : oscin divided by 2 . this bit controls the divide by 2 circuit which oper- ates on the oscin clock. 0: no division of the oscin clock 1: oscin clock is internally divided by 2 bits 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to pres- cale cpuclk from intclk. when these three bits are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. clock control register (clkctl) r240 - read write register page: 55 reset value: 0000 0000 (00h) bits 7:4 = reserved. must be kept reset for normal operation. bit 3 = sresen : software reset enable. 0: the halt instruction turns off the quartz, the pll and the ccu 1: a reset is generated when halt is executed bits 2:0 = reserved. must be kept reset for normal operation. clock flag register (clk_flag) r242 -read/write register page: 55 reset value: 0100 1000 after a watchdog reset reset value: 0010 1000 after a software reset reset value: 0000 1000 after a power-on reset warning : if this register is accessed with a logical instruction, such as and or or, some bits may not be set as expected. bit 7 = reserved. must be kept reset for normal operation. bit 6 = wdgres : watchdog reset flag. this bit is read only. 0: no watchdog reset occurred 1: watchdog reset occurred bit 5 = softres : software reset flag. this bit is read only. 0: no software reset occurred 1: software reset occurred (halt instruction) bits 4:0 = reserved. must be kept reset for normal operation. 70 - - div2 prs2 prs1 prs0 - - 70 - - - - sresen - - - 70 - wdg res soft res -----
57/148 ST92186B - reset and clock control unit (rccu) 4.3 oscillator characteristics because of the real time need of the application, it is assumed the ST92186B will be used with a 4 mhz crystal fed to the core by the frequency mul- tiplier output after it is started and stabilized. 4.3.1 halt state when a halt instruction is processed, it stops the main crystal oscillator preventing any derived clock into the chip. exit from the halt state can be obtained through a main system reset. it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied. figure 27. crystal oscillator table 13. crystal specification legend : c l1 , c l2 : maximum total capacitances on pins oscin and oscout (the value includes the external capaci- tance tied to the pin cl1 and cl2 plus the parasitic capac- itance of the board and of the device). note : the tables are relative to the fundamental quartz crystal only (not ceramic resonator). figure 28. internal oscillator schematic oscin oscout c l1 c l2 st9 crystal clock vr02116a 1m* *recommended for oscillator stability c 1 =c 2 = 56pf c 1 =c 2 = 47pf rs max (ohm) 200 260 vr02086a halt oscin oscout r in r out r
58/148 ST92186B - reset and clock control unit (rccu) 4.4 reset/stop manager the reset/stop manager resets the device when one of the three following triggering events occurs: C a hardware reset, consequence of a falling edge on the reset pin. C a software reset, consequence of an halt in- struction when enabled. C a watchdog end of count. the reset input is schmitt triggered. note : the memorized internal reset (called re- seti ) will be maintained active for a duration of 32768 oscin periods (about 8 ms for a 4 mhz crys- tal) after the external input is released (set high). this reseti internal reset signal is output on the i/o port bit p5.0 (active low) during the whole reset phase until the p5.0 configuration is changed by software. the true internal reset (to all macrocells) will only be released 511 reference clock periods after the memorized internal reset is released. it is possible to know which was the last reset triggering event, by reading bits 5 and 6 of register clk_flag. figure 29. reset overview n figure 30. recommended signal to be applied on reset pin build-up counter rccu true reset reseti memorized reset internal reset v reset v dd 0.7 v dd 0.3 v dd 20 s minimum
59/148 ST92186B - timing and clock controller (tcc) 5 timing and clock controller (tcc) 5.1 frequency multipliers two on-chip frequency multipliers generate the proper frequencies for: the core/real time periph- erals and the display related time base. they follow the same basic scheme based on an integrated vco driven by a three state phase comparator and a charge-pump (1 pin used for off- chip filtering components; a resistor in series with a capacitor tied to ground). for both the core and the display frequency mul- tipliers, a 4 bit programmable feed-back counter allows the adjustment of the multiplying factor to the application needs (a 4 mhz crystal is as- sumed). figure 31. timing and clock controller block diagram fosd fcpu synchronised clock to osdram controller pixclk to display controller fpixc skwen skwl [3:0] 4mhz real clock to ir, ds... wait for interrupt bus request memory wait state cpu clock control prescaler main clock controller div 2 (moder.5) fmsl frequency xtal osc multiplier by 2 by 2 div skdiv2 fml [3:0] fmen div by 2 div frequency multiplier prs [2:0] fmen intclk adc oscout oscin skew corrector cpuclk (core clock) clock) to timer, hsync (peripheral fosd div 2 (moder.5) by 2 div adc.
60/148 ST92186B - timing and clock controller (tcc) frequency multipliers (contd) off-chip filter components (to be confirmed) C core frequency multiplier (fcpu pin): 1.2k ohms; 47 nf plus 100 pf between the fcpu pin and gnd. C skew frequency multiplier (fosd pin): 1.2k ohms; 47 nf plus 100 pf between the fosd pin and gnd. the frequency multipliers are off during and upon exiting from the reset phase. the user must pro- gram the desired multiplying factor, start the multi- plier and then wait for its stability (refer to the elec- trical characteristics chapter for the specified de- lay). once the core/peripherals multiplier is stabilized, the main clock controller can be re-programmed through the fmsl bit in the mccr register to pro- vide the final frequency (cpuclk) to the cpu. the frequency multipliers are automatically switched off when the microprocessor enters halt mode (the halt mode forces the control register to its reset status). table 14. examples of cpu speed choices note: 24 mhz is the max. authorized frequency. caution : the values indicated in this table are the only authorized values. table 15. pixclk frequency choices crystal frequency fml (3:0) cpuclk skdiv2=0 4 mhz 4 10 mhz 5 12 mhz 6 14 mhz 7 16 mhz 8 18 mhz 9 20 mhz 10 22 mhz 11 24 mhz crystal frequency skw (3:0) fpixc pixclk skdiv2=0 4 mhz 6 0 14 mhz 7 0 16 mhz 8 0 18 mhz 9 0 20 mhz 10 0 22 mhz 11 0 24 mhz 6 1 28 mhz 7 1 32 mhz 8 1 36 mhz 9 1 40 mhz
61/148 ST92186B - timing and clock controller (tcc) 5.2 register description skew clock control register (skccr) r254 - read/ write register page: 43 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7= skwen: frequency multiplier enable bit. 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled providing clock to the skew cor- rector. the skwen bit must be set only after programming the skw(3-0) bits. bit 6 = skdiv2: skew divide-by-2 enable bit. 0: divide-by-2 disabled. 1: divide-by-2 enabled. this bit must be kept in reset state. bits 5:4 = reserved. these bits are forced to 0 by hardware. bits 3:0 = skw: skew counter. these 4 bits program the down-counter inserted in the feedback loop of the frequency multiplier which generates the internal multiplied frequency pixclk. the pixclk value is calculated as fol- lows : if fpixc=0 : f(pixclk)=crystal frequency * [ (skw(3:0)+1) ]/2 if fpixc=1 : f(pixclk)=crystal frequency * [ (skw(3:0)+1) ] note: to program the fpixc bit, refer to the de- scription of the osder register in the osd chap- ter. main clock control register (mccr) r253 - read/ write register page: 43 reset value: 0000 0000 (00h) the halt mode forces the register to its initializa- tion state. bit 7 = fmen: frequency multiplier enable bit . 0: fm disabled (reset state), low-power consump- tion mode. 1: fm is enabled, providing clock to the cpu. the fmen bit must be set only after programming the fml(3:0) bits. bit 6 = fmsl: frequency multiplier select bit. this bit controls the choice of the st9 core internal frequency between the external crystal frequency and the main clock issued by the frequency multi- plier. in order to secure the application, the st9 core in- ternal frequency is automatically switched back to the external crystal frequency if the frequency mul- tiplier is switched off (fmen =0) regardless of the value of the fmsl bit. care must be taken to reset the fmsl bit before any frequency multiplier can restart (fmen set back to 1). after reset, the external crystal frequency is al- ways sent to the st9 core. bits 5:4 = reserved. these bits are forced to 0 by hardware. bits 3:0 = fml: fm counter. these 4 bits program the down-counter inserted in the feed-back loop of the frequency multiplier which generates the internal multiplied frequency fimf. the fimf value is calculated as follows : fimf = crystal frequency * [ (fml(3:0) + 1) ] /2 7 6 5 4 3210 skwen skdiv2 0 0 skw3 skw2 skw1 skw0 7 6 5 4 3210 fmen fmsl 0 0 fml3 fml2 fml1 fml0
62/148 ST92186B - i/o ports 6 i/o ports 6.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). input buffers can be either ttl or cmos compatible. alternatively some input buffers can be permanently forced by hardware to operate as schmitt triggers. 6.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 6.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 32 . port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or accumulator locations. figure 32. i/o register map group e group f page 2 group f page 3 system registers ffh reserved reserved r255 feh p3c2 r254 fdh p3c1 r253 fch p3c0 r252 fbh reserved r251 fah p2c2 r250 f9h p2c1 r249 f8h p2c0 r248 f7h reserved r247 f6h p5c2 r246 e5h p5dr r229 f5h p5c1 r245 e4h p4dr r228 f4h p5c0 r244 e3h p3dr r227 f3h reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240
63/148 ST92186B - i/o ports port control registers (contd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 6.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 33 ) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit, except where the schmitt trigger option is assigned to the pin. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 6.5). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 34 . independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 35 ). C the output buffer is forced tristate. C the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. C the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin.
64/148 ST92186B - i/o ports input/output bit configuration (contd) figure 33. control bits n table 16. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) cmos (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input
65/148 ST92186B - i/o ports input/output bit configuration (contd) figure 34. basic structure of an i/o port pin n n figure 35. input configuration n n figure 36. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts
66/148 ST92186B - i/o ports input/output bit configuration (contd) when px.n is programmed as an output : ( figure 36 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : ( figure 37 ) C the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithmetic/logic and boolean instructions performed on a bidirec- tional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : ( figure 38 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 37. bidirectional configuration n n figure 38. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch
67/148 ST92186B - i/o ports 6.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: C data bus input/output C alternate function input C alternate function output 6.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 6.5.2 pin declared as an alternate function input a single pin may be directly connected to several alternate function inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is re- quired to enable an alternate function input, since the input buffer is directly connected to each alter- nate function module on the shared pin. as more than one module can use the same input, it is up to the user software to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is perma- nently assigned by hardware as an a/d bit. in this case , after software programming of the bit in af- od-ttl, the alternate function output is forced to logic level 1. the analog voltage level on the cor- responding pin is directly input to the a/d. 6.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 6.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. 6.7 configuration of unbonded i/os some i/os are not bonded in the sdip32 pack- age. you must configure these unbonded i/os (i.e. p2.1, p2.2, p3.1, p3.5, p3.7, p5.1, p5.2, p5.5 and p5.6) as output push-pull at the very first begin- ning of your software and never change this con- figuration after initialization. this will avoid unpre- dictable software behavior. mode i/o ports wfi not affected (clock outputs running) halt not affected (clock outputs stopped) reset bidirectional weak pull-up (high impedance when disabled in hardware).
68/148 ST92186B - on-chip peripherals 7 on-chip peripherals 7.1 timer/watchdog (wdt) 7.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: C generate periodic interrupts C measure input signal pulse widths C request an interrupt after a set number of events C generate an output signal waveform C act as a watchdog timer to monitor system in- tegrity the main wdt registers are: C control register for the input, output and interrupt logic blocks (wdtcr) C 16-bit counter register pair (wdthr, wdtlr) C prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: C wdin external clock input C wdout square wave or pwm signal output C int0 external interrupt input C nmi non-maskable interrupt input C hw0sw1 hardware/software watchdog ena- ble. figure 39. timer/watchdog block diagram int0 wdtpr 8-bit prescaler wdtrh, wdtrl 16-bit intclk/4 interrupt control logic end of count reset top level interrupt request iaos tlis inta0 request nmi wdgen downcounter
69/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) 7.1.2 functional description 7.1.2.1 external signals an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter is driven by an internal clock equal to intclk divided by 4. 7.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 7.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 7.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 7.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 7.1.3.1 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated.
70/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) 7.1.3.2 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 7.1.3.3 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp and s_c bits are ignored. hence, regardless of their status, the counter always runs in continuous mode, driven by the internal clock. figure 40. watchdog timer mode timer start counting wri te wdtrh,wdtrl wd en=0 write aah,55h into wdtrl reset software fail (e.g. infinite loop) or peripheral fail va00220 produce count reload value count g
71/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) 7.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 41 . note: software traps can be generated by setting the appropriate interrupt pending bit. table 17 below, shows all the possible configura- tions of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters . figure 41. interrupt sources table 17. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watchdog reset wdgen (wcr.6) inta0 request ia0s (eivr.1) mux 0 1 int0 mux 0 1 top level interrupt request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer
72/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) 7.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note: the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16 bit register (wdtlr, wdthr) is used to load the 16 bit counter value. the registers can be read or written on the fly. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = r[15:8] counter most significant bits. timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0
73/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h ) bit 7 = st_sp: start/stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c: single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:0 = reserved. must be kept in reset state. 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c 0 1 0 0 1 0
74/148 ST92186B - timer/watchdog (wdt) timer/watchdog (contd) wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 7 = reserved. must be kept in reset state. bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set anymore by the user program. at system reset, the watch- dog mode is disabled. bits 5:0 = reserved. must be kept in reset state. external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bits 7:4 = v[7:4] : most significant nibble of exter- nal interrupt vector . these bits are described in the interrupt section on page 54 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is described in the interrupt section on page 54 . bit 0 = ewen : external wait enable. this bit is described in the interrupt section on page 54 . 70 0wdgen111111 70 v7 v6 v5 v4 tltev tlis iaos ewen
75/148 ST92186B - standard timer (stim) 7.2 standard timer (stim) 7.2.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler is driven by an internal clock equal to intclk divided by 4. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 42. standard timer block diagram n external stp 8-bit prescaler sth,stl 16-bit standard timer clock interrupt control logic end of count ints interrupt request interrupt downcounter intclk/4
76/148 ST92186B - standard timer (stim) standard timer (contd) 7.2.2 functional description 7.2.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standard timer, the prescaler (stp) and counter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. it is only stopped by resetting the start/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 7.2.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to 1, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 7.2.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. std timer register register address stim sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h)
77/148 ST92186B - standard timer (stim) standard timer (contd) 7.2.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[15:8]: counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counters current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp: start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c: single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:3 = reserved. must be kept in reset state. bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bits 1:0 = reserved. must be kept in reset state. 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st-sp s-c 0 1 0 ints 0 0
78/148 ST92186B - osdram controller 7.3 osdram controller 7.3.1 introduction the osdram controller handles the interface be- tween the display controller, the cpu and the os- dram. the time slots are allocated to each unit in order to optimize the response time. the main features of the osdram controller are the following: n memory mapped in memory space (segment 22h of the mmu) n dma access for display control n direct cpu access 7.3.2 functional description the osdram controller manages the data flows between the different sub-units (display controller, cpu) and the osdram. a specific set of buses (16-bit data, 9-bit addresses) is dedicated to these data flows. the osdram controller accesses these buses in real time. the osdram controller has registers mapped in the st9 register file. as this osdram controller has also to deal with tv real time signals (on-screen-display), a spe- cific controller manages all exchanges: C its timing generator uses the same frequency generator as the display (pixel frequency multi- plier), C its controller can work in two tv modes: C single mode : all time slots are dedicated to the cpu. C shared mode : time slots are shared between the cpu and the display. the shared mode is controlled by the display controller. C its architecture gives priority to the tv real time constraints: whenever there is access contention between the cpu and the display (shared mode), the cpu is automatically forced in a wait configuration until its request is served. C its controller enables a third operating mode (stand-alone mode) which allows the application to access the osdram while the display is turned off. in this case, the osdram controller uses the cpu main clock. figure 43. display architecture overview 4 * 3 bits display controller osdram controller osd display ram cpu interface rom font matrix register buses memory buses address (6+4 bits) osd address (9 bits) osd data (16 bits) rgb fb translucency tslu data (8 bits) address (22 bits) data (8 bits)
79/148 ST92186B - osdram controller osdram controller (contd) 7.3.2.1 time sharing during display the time necessary to display a character on the screen defines the basic repetitive cycle of the os- dram controller. this whole cycle represents therefore 18 clock periods. this cycle is divided in 9 sub-cycles called slots. each slot is allocated in real-time either to the cpu or the display: C in single mode, this 9-slot cycle is repeated con- tinuously providing only cpu slots (single cycle), until the osdram controller is switched off by the main program execution. C in shared mode, this 9-slot cycle provides dis- play slots followed by cpu slots. each slot represents a two-byte exchange (read or write) between the osdram memory and the oth- er units: display reading slot (dis): 16 bits are read from the osdram and sent to the display unit, the ad- dress being defined by the display address gener- ator. direct cpu access slot (cpu): 16 bits are ex- changed (read or write) between the osdram and its controller but only 8 bits are exchanged with the cpu, the address being defined by the cpu memory address bus. figure 44. time sharing during display display reading is handled as follows: C dis(1) & dis(2) are dedicated to reading the character code, its parallel attributes & associat- ed palette pointer. C dis(3) provides the foreground palette. C dis(4) provides the background palette. in case of underline activation (refer to the osd control- ler paragraph for more details), the dis(4) slot is no longer provides the background palette con- tent (useless information) but recovers the un- derline color set data. the cpu write accesses are handled as follows: because of the 16-bit word width inside the os- dram matrix, it is obviously necessary to perform a cpu write access in 2 steps: C reading the osdram word C rewriting it with the same values except for the 8 modified bits. each time a cpu write operation is started, the next following cpu slot will be used as a read slot, the effective write to the osdram being complet- ed at the next cpu slot. 7.3.2.2 time sharing within the tv line at the beginning of each tv line, the osdram is accessed (read) by the display controller in order to get all the row attributes. when the tv line is recognized as the one where data have to be dis- played, the shared cycle is activated at the time the data has to be processed for display. cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) cpu (r/w) dis (1) cpu (r/w) dis (2) cpu (r/w) dis (3) cpu (r/w) dis (4) cpu (r/w) shared cycle single cycle one character display time
80/148 ST92186B - osdram controller osdram controller (contd) 7.3.3 osdram controller reset configuration during and after a reset, the osdram access is disabled. when the osdram controller is software disa- bled, it will: 1. complete the current slot. 2. complete any pending write operation (a few slots may elapse). 3. switch off any osdram interface activity. 7.3.3.1 osdram controller running modes 2 control bits called osde (osd enable) and dion (display on) are used to enable the os- dram controller. both are also shared by the dis- play controller. these 2 bits are located in the osder register. this register is described in the on screen display controller chapter. 7.3.3.2 cpu slowdown on osdram access as described above, the osdram controller puts priority on tv real time constraints and may slow- down the cpu (through wait cycle insertion) when any osdram access is requested. the ef- fective duration of the cpu slowdown is a complex function of the osdram controller working mode and of the respective pixclk frequency (os- dram frequency) and the core intclk frequen- cy. 7.3.3.3 osdram mapping the osdram is mapped in the memory space, segment 22h, starting from address 0000h to ad- dress 00ffh (256 bytes). the osdram mapping is described in the on screen display controller chapter.
81/148 ST92186B - on screen display controller (osd) 7.4 on screen display controller (osd) 7.4.1 introduction the osd displays character data and menus on a tv screen. each row can be defined through three different display configurations: C serial mode: each character is defined by an 8- bit word which provides the character address into the font rom memory. some codes are re- served for color controls and do not address any character description. they are displayed as spaces and as a direct consequence are active on a word basis. C basic parallel mode: each character is defined by a 16-bit word which provides the character ad- dress in the font rom memory and its color at- tribute. this mode is called parallel as the colors are definable on a per character basis. C extended parallel mode: each character is de- fined by a 24-bit word which provides the charac- ter address in the font rom memory and its color and shape attributes. this mode is called parallel as the attributes are definable on a per character basis. 7.4.2 general features n 50/60 hz and 100/120 hz operation n 525/625 lines operation, 4/3 or 16/9 format n interlaced or progressive scanning n 18x26 or 9x13 character matrix user definable in rom. both matrixes can be mixed. n up to 63 characters per row n 7 character sizes in 18x26, 4 in 9x13 n 512 possible colors in 4x16-entry palettes n 8 levels of translucency on fast blanking n basic parallel mode for character based color definition n extended parallel mode for character based color and shape definition n rounding, fringing, shadowing, flashing, scrolling, italics, and various underlining modes definition of terms used in this chapter C pixel : minimum displayed element that the dis- play controller can handle. its vertical physical size is always one tv line. its horizontal physical size is directly linked to the basic clock frequency (called pixel clock) which synchronizes the osd and is therefore independent of any magnifica- tion factor which may be applied to the displayed element. C dot : a dot defines the displayed element which corresponds to a single bit read from the font rom memory. a dot is represented on the screen by a "matrix" of pixels. the matrix size de- pends on the magnification factor applied. 7.4.3 functional description all characters are user definable by masking the font rom content (except the one corresponding to code 00h which is reserved for test). two differ- ent matrixes can be used and mixed: C 18x26 character matrix C 9x13 character matrix the hardware display system has the capability of displaying one character row and requires the cpu to update the next display buffer prior to dis- playing the next row. using a real time routine, the on screen display supports the display of as many character rows as the tv screen can physi- cally handle. the osd can display up to 63 characters per row, depending on the row ram buffer size (user defin- able, see section 7.4.5.1 ). a smart pixel processing unit provides extended features such as rounding, fringe, or shadowing for better picture quality. other smart functions such as flashing, scrolling, italics, underlining al- low the designing of a high quality display applica- tion. the screen insertion of the displayed characters is fully synchronized by the vertical and horizontal tv synchronizing signals. the osd controller generates the red, green, blue and fast blanking video signals through 8-level dac outputs. the fast blanking video signal can also be generated as a digital signal if needed.
82/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.3.1 display attributes n global screen attributes: C border color C border translucency C turn all background color into border color n row parameters and attributes: C row mode control (serial, basic parallel, extend- ed parallel) C row character count C horizontal and vertical shift C active range (used for vertical scrolling) C font matrix selection C size control (dot height and width definition) C flashing control C rounding control C fringe control n serial character attributes: C background color (16 user definable colors) C foreground color (16 user definable colors) C flashing control C italics control n palette parallel character attributes: C background color (16 user definable colors) C foreground color (16 user definable colors) n shape parallel character attributes: C character code extension C double height C double width C foreground palette extension (32 user definable colors) C background palette extension (32 user definable colors) C flashing control C shadowing control C fringe control 7.4.3.2 osd area when the display controller is turned on, the tv screen will show a specific color prior to any data display which is called the border color. the ef- fective border color is fully software programmable from a palette of 512 colors through 2 control reg- isters. the border area translucency can be chosen from 8 different levels, from fully transparent to fully opaque. the 3 translucency control bits are acces- sible through the border color control registers. when data are displayed by the osd, they form rows of characters. all characters of one row are horizontally aligned. for each displayed character, two kinds of colors must be programmed which are defined as: C background color C foreground color figure 45. osd area description 7.4.3.3 color processing further color elements may be generated by the display controller as a result of real time pixel cal- culations (they are not stored in the font rom memory). these are: C rounding pixels: they must be considered as calculated foreground pixels. C fringe pixels: they are always displayed with a black color and are never translucent. C underline pixels: they must be considered as calculated pixels. their colors are defined through independent underline color values. translucency levels are also programmable for underline pixels. a border color 1 character row 1 displayed character background color foreground color area a
83/148 ST92186B - on screen display controller (osd) osd controller (contd) all colors are taken from a double palette set (background and foreground) which are both os- dram mapped and thus definable in real-time. the priority of all color layers is, from highest to lowest: underline, foreground & rounding, fringe, back- ground and border. character code 00h is a test character and has no user customized content. it is always displayed with a border color and will appear as a non-dis- played character. 7.4.3.4 character matrix definition a character is described by a matrix of dots stored in the font rom memory. two matrix sizes are can be used to define each character pattern: ei- ther a 9x13 matrix or a 18x26 matrix. the matrix size can be redefined for each row display buffer; mixing the 2 matrix sizes on a same screen is therefore possible. refer to figure 54 , for an example of the font rom content. the 9x13 matrix is a compressed format where each bit represents a 2x2 pixel dot (with no magni- fication applied). in interlaced mode, for each dot, 2 pixels are generated on a field, the 2 others on the other field; each row of the matrix is used for both fields. the 18x26 matrix is an expanded format where each bit represents a 1x1 pixel dot (if no magnifi- cation). in interlaced mode, if no magnification is applied, each odd row of the matrix is displayed on a field, each even row on the other field. warning: as a result, when displaying the 18x26 matrix with no vertical magnification and in inter- laced mode, flicker may be visible on characters containing long single-pixel rows. to avoid this ef- fect, either use double pixel horizontal lines, if pos- sible, when designing the font (see figure 46 ). al- ternatively, use the double height attribute or choose the foreground and background colors for reduced contrast. figure 46. avoiding flicker on unmagnified 18x26 characters modified character design with visible flicker original character design
84/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.3.5 cursor & flash a cursor facility may be emulated under software control, using the flash attribute. this allows to have a flash-on-word in serial mode or a flash- on-character in extended parallel mode. the cursor facility first requires activating the flash on row control bit (refer to section 7.4.7.3 ), which acts as a general flash enable. then program the characters with flashing char- acter attribute(s) (serial or extended parallel) at the required locations. the flash effect is obtained by toggling the general flash enable bit. several flashing words or characters per screen can easily be implemented. 7.4.3.6 italic mode the italics attribute is a serial attribute; this means that italic mode is available in serial mode only. in the matrix description that follows, line 1 is at the top of the character, line 13 (or line 26) is at the bottom. the codes (seen as spaces) needed to activate and deactivate the italic attribute provide a con- venient method for solving border problems be- tween italic and non-italic characters. figure 47. italic character mode 18x26 26 1 21 20 17 16 13 12 9 8 5 4 9x13 shift row shift 5 4 3 2 1 0 2.5 2 1.5 1 0.5 0 normal italic 13 1 11 10 9 8 7 6 5 4 3 2 dot row dot
85/148 ST92186B - on screen display controller (osd) osd controller (contd) if the italic attribute is still active at the end of the row, the last character code to be displayed is truncated to the vertical position where it would have finished without the italic attribute. if the background color is changed while italics are enabled, then the color attribute (seen as a space) is not slanted. the right edge background corresponding to a control character is never slanted. when a background code follows an italic charac- ter, then the background color of the italic charac- ter extends half way into the displayed background code location, regardless of the background pal- ette m bit (refer to section 7.4.6.4 for a description of the m bit). in the case where a background code is followed by a second background code while italics are on, the first background color will extend half way into the second background location. the edges of the 00h code (test character seen as a border color) are never slanted. the right edge of the 00h code is never slanted. when a 00h code follows an italic character, then the background color of the italic character ex- tends half way into the 00h code location. in case a 00h code is followed by a background code while italics are on, the 00h code is never ex- tended into the following code location. 7.4.3.7 rounding and fringe rounding can be enabled or disabled row by row (see section 7.4.7.3 ). for a 18x26 matrix size, there is no rounding facil- ity when the character size is (1x,1y). for any other (x,y) size combinations, the round- ing facility is allowed for the 18x26 font matrix, and rounding is available in any of the 3 row modes (serial, basic parallel, extended parallel). the fringe mechanism can be enabled or disabled row by row (see row attributes description), but it can also be defined on a character basis in ex- tended parallel mode (see shape parallel at- tributes for more details). the fringe mechanism can be activated for any size and both matrix formats. please note that, for both matrixes, in the case of fringe usage in 1y vertical size and interlaced mode, a flicker may appear on the screen as the fringe information is built on a field basis. figure 48. rounding and fringe foreground dot size rounding dot size fringe dot size 9 x13 18 x 26 drawing conventions: partial details rounding and fringe in size (2x,2y) for 18x26 rounding and fringe (9x13 matrix only) partial details (9x13 matrix only) rounding and fringe partial details 9x13 matrix 18x26 matrix rounding and fringe in size (1x,1y) in size (1.5x,2y) in size (1.5x,1y) rounding and fringe in size (4x,4y) for 18x26
86/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.3.8 scrolling the row ram buffer architecture of the display al- lows all scrolling operations to be performed very easily by software: scroll up, scroll down, scroll left, scroll right and any horizontal/vertical mix. in addition to the character row scrolling, a vertical smooth scrolling has been implemented. it re- quires defining the active range for each dis- played row (refer to section 7.4.7.4 ). 7.4.3.9 color palettes the display controller provides 4 user-definable palettes: two 16-color foreground palettes (one ba- sic and one extended), and two 16-color back- ground palettes (one basic and one extended). each color is defined using 16 bits: C foreground palette: 3 bits for red level, 3 bits for green level, 3 bits for blue level, 3 bits for translucency, and 3 bits for the underline mode control. C background palette: 3 bits for red level, 3 bits for green level, 3 bits for blue level, 3 bits for translucency, and 1 bit for immediate color change control. two palettes are always available (one foreground palette and one background palette). the 2 other palettes are only accessible in extended parallel mode. the palettes available in serial and basic parallel modes depend on the value of the pasw bit in the osddr register. 7.4.3.10 underline mode control the osd is able to underline any character of the 9x13 or 18x26 matrix with 3 different colors select- ed from a palette, and 2 different dot lines. using 3 bits (see the color palettes paragraph above), it is possible to define the underline mode associated with each foreground palette entry. in 9x13 mode, single or double underline can be set on lines 12 and 13 with the foreground color or two specific colors defined in underline color sets 1 & 2. in 18x26 mode, single or double underline can be set on lines 23-24 and 25-26 with the foreground color or two specific colors defined in underline color sets 1 & 2. for more details please refer to section 7.4.6 .
87/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.3.11 translucency function the translucency feature is designed to provide a better osd quality while displaying rows in mixed mode. instead of forcing the background color of any character to any full intensity color, (which will pre- vent the viewer from seeing a significant amount of the video picture), or having a fully transparent background (i.e. no background) which makes the osd more difficult to read for the viewer, the trans- lucency provides a real time mix between both the video and the osd background information. this feature will appear as a boxing effect around all the displayed characters. the translucency can be handled in two different ways at application level, depending on the video processor used in the application. 1. when the video processor accepts an analog control of the fast switch osd signal (called fb), the translucency can be handled directly through the real time amplitude of the fb signal (refer to color attribute control for border, back- ground palette and underline color settings). 2. when the video processor accepts only a digital fb signal, the translucency function may be im- plemented on the chassis with the help of an additional digital output of the mcu, which is provided as an i/o pin alternate function. this digital output called tslu is active (set to 1) when the osd displays the background and foreground or when the mute is active (refer to the description of the lsm[2:0] bits in the osdmr reg- ister) and is inactive the rest of the time (during foreground or if no display), including character 00h. this tslu signal is controlled by the tsle bit in the osder register. when not used, (tsle=0), the tslu signal is held at 1 by hardware. application note in order to enable the translucency function (see example no. 2, above), the following procedure must be performed: C fast blanking must be set to digital mode. set bit difb (bit 7) of register osdbcr1 (r247, page 42) to 1. refer to section 7.4.8 register descrip- tion . C initialize port 3.0 as a push-pull type alternate function output. refer to section 6.5.3 pin de- clared as an alternate function output . C set bit tsle (bit 2) of register osder (r248, page 42) to 1. refer to section 7.4.8 register description . C for the selected colors (i.e. those which will ap- pear as transparent with contrast reduction), set bits bt[2:0] to 0. refer to section 7.4.6.4 back- ground palettes . figure 49. digital translucency output pin example a current displayed video line tlsu digital output fb (active high) no display foreground no display transparent background
88/148 ST92186B - on screen display controller (osd) osd controller (contd) figure 50. digital translucency display scheme using stv2238d in pqfp64 package figure 51. application example using stv224x/228x in sdip56 package video processor (stv2238d) contrast reduction internal red internal green internal blue rout gout bout rgb switch st9 mcu tslu r g fb b stv224x/228x chroma processor 2.2 k w 1.5 k w 1 k w 2.7 k w tslu fb fb osd st9 mcu
89/148 ST92186B - on screen display controller (osd) 7.4.4 horizontal and vertical sync 7.4.4.1 pixel clock control the pixel clock is issued from a frequency multipli- er which is locked to the main crystal frequency. the synthesized frequency is software program- mable (4-bit value defining the multiplying factor) which provides flexibility for supporting various ap- plication conditions, from a basic 4/3 screen for- mat and a 1h horizontal sweep to a 16/9 format with a 2h sweep, interlaced or progressive scan- ning. for more information, refer to the timing and clock controller chapter. note: it is recommended to wait for a stable clock (approx. 35 ms) from the frequency multiplier be- fore enabling the osdram controller .
90/148 ST92186B - on screen display controller (osd) osd controller (contd) vertical & horizontal sync pulse inputs a spike filter has been implemented on the vertical sync input. this circuit is inserted after internal po- larity compensation of the vsync input signal (see vpol bit of the delay register, osddr). it masks any spike on the vertical sync pulse with a duration smaller than 3s. the leading edge of the vsync pin is affected by the vertical sync pulse cleaner. the vsync edges are internally delayed by 3s. a schmitt trigger provides noise immunity on the horizontal sync pulse input and will add a delay between the deflection pulse and the effective count start of the osd line processing. 7.4.4.2 field detection in interlaced mode for tv sets working in interlaced mode, the dis- play controller has to retrieve the field information (some pixel information, like 18x26 matrix charac- ters, rounding or fringe, is field based). the display is synchronized to hsync and vsync inputs. the phase relationship of these signals may be different from one chassis type to another. therefore, in order to prevent vertical osd jitter, some circuitry is implemented to pro- vide a stable and secure field detection (osd jitter may appear if the rising edge of an external verti- cal sync pulse coincides with that of an external horizontal sync pulse). this circuitry delays the vertical sync leading edge internally. the delay ap- plied is software programmable through a 4-bit value (refer to bit dbls in the osddr register). the field information is then extracted by appropri- ate hardware logic. 7.4.4.3 display behaviour in 2h modes the 2h mode corresponds to a double scan dis- play mode: the line frequency is doubled (to 31.5 khz) compared to the traditional 60 hz field, 262.5 lines per field. this mode requires doubling the pixel frequency and also adjusting some timing op- erations (refer to section 7.4.4.1 and section 7.4.4.2 ). this feature is controlled by the dbls bit in the osder register. the double scan may be used in interlaced mode (100/120 hz field frequency) or in progressive scanning (non-interlaced mode, 50/60 hz field frequency). this feature is enabled by the nids bit in the os- der register. rgb-fb line start mute the r, g, b & fb outputs are muted after each horizontal sync pulse received on the hsync pin. the mute duration is controlled by software through a 3-bit value; these bits are called lsm(2:0) and are located in the mute register osdmr. when the display works in 1h mode (bit dbls re- set), the mute duration can be adjusted in 2s steps from 2 to 14 s. when the display works in 2h mode (bit dbls set), the mute duration can be adjusted in 1s steps from 1 to 7 s. when the 3-bit mute value is zero, the r, g, b & fb display outputs are muted during the duration of the horizontal sync pulse received on the hsync pin. for more details, refer to the dbls bit in the os- der and the lsm bits in the osdmr register. the hsy bit in the osdfbr register provides an image of the mute.
91/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.5 programming the display the row-wise ram buffer contains the description of the characters to display: C row and character attributes (color, shape etc.) C horizontal shift code C character codes (addressing the font rom) while one row buffer is displayed on the screen, the cpu has time to prepare the content of the next character row by filling up the second row buffer. at the time the next row must be displayed, the display controller will point to the second row buffer, allowing the cpu to start loading data into the first row buffer for the following row. an inter- rupt request is generated each time the buffer pointer toggles. the vertical location of the next character row on the screen is programmed by software through the event line value (refer to figure 57 ). the vertical position of the beam is memorized by the line counter which counts the tv horizontal synchroni- zation pulses (called here "scan line"). when the scan line counter matches the event line value the buffer toggle mechanism is activated. 7.4.5.1 osdram mapping the osdram is mapped in segment 22h of the memory space. in addition to row buffers, it is used to store color palettes. note: the reset value of the osdram contents is undefined. general overview the figure 52 gives a general overview of the os- dram mapping.
92/148 ST92186B - on screen display controller (osd) osd controller (contd) figure 52. osdram mapping 2n+b 2n 2p+a 2p row buffer 1 row buffer 2 8fh 00h buffer address & description section a & b values depend on the row mode and on the number of characters to display in the row segment 22h 0fh 08h 07h 06h 05h 04h 03h 02h 01h 00h free for user underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 8fh 70h 6fh 50h 4fh 30h 2fh 10h extended background palette extended foreground palette basic foreground palette basic background palette 2p+3 2p+2 2p+1 2p active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 2p+6 char (serial mode) 2p+4 2p+5 . . . . char + palette attrib. (basic parallel mode) char + palette attrib. + shape attrib. (extended parallel mode) osdram general features 00h to 4f, 6fh or 8fh depending on color palettes configured row buffer any even address between 50h and feh palette 2p is the start address of the first row buffer notes: active range
93/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.5.2 row buffer description the start address for each buffer must be even. starting from address 2p+6, write a string corre- sponding to the character codes and the possible attributes as in the example below: 7.4.5.3 osdram mapping example 1 the left column of figure 53 gives an example of osdram mapping for the following configuration: C the display uses basic parallel mode C only the two basic color palettes are used C 36 characters are displayed per row C the first buffer start address (to be stored in 0002h and 0003h) is 0050h C the next buffer start address to be stored in buffer 1 (address 0050h and 0051h) is 409eh (009eh is the address of buffer 2, and 40h is the code for basic parallel mode. refer to section 7.4.7.1 ). C the next buffer start address to be stored in buffer 2 (address 009eh and 009fh) is 4050h (0050h is the address of buffer 1, and 40h is the code for basic parallel mode. refer to section 7.4.7.1 for more details). 7.4.5.4 osdram mapping example 2 the right column of figure 53 gives an example of osdram mapping for the following configuration: C the display uses extended parallel mode C the four color palettes are used C 16 characters are displayed per row C the first buffer start address (to be stored in 0002h and 0003h) is 0090h C the next buffer start address to be stored in buffer 1 (address 0090h and 0091h) is 80c6h (00c6h is the address of buffer 2, and 80h is the code for extended parallel mode. refer to sec- tion 7.4.7.1 for more details). C the next buffer start address to be stored in buffer 2 (address 00c6h and 00c7h) is 8090h (0090h is the address of buffer 1, and 80h is the code for extended parallel mode. refer to sec- tion 7.4.7.1 for more details). note: to keep some osdram locations free, configure only those features that you really use (color palettes, underline palettes), as shown in the two examples. byte serial mode basic parallel mode extended parallel mode 1 char or attrib1 char1 char1 2 char or attrib2 paletteattrib1 paletteattrib1 3 char or attrib3 char2 shapeattrib1 4 char or attrib4 paletteattrib2 char2 5 char or attrib5 char3 paletteattrib2 6 char or attrib6 paletteattrib3 shapeattrib2 ... ... ... ...
94/148 ST92186B - on screen display controller (osd) figure 53. parallel mode mapping examples ffh 0fh 08h 07h 06h 05h 04h 03h 02h 01h 00h free for user underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 4fh 30h 2fh 10h basic foreground palette basic background palette 56h 57h 58h 59h character code 1 character code 2 palette attribute 1 9ch 9dh character code 36 palette attribute 36 53h 52h 51h 50h active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 54h 55h a4h a5h a6h a7h character code 1 palette attribute 2 palette attribute 1 character code 2 eah ebh character code 36 palette attribute 36 a1h a0h 9fh 9eh active range row attributes horizontal shift (low) horizontal shift (high) + row char. number next buffer start addr. (low) next buffer start addr. (high) + row mode a2h a3h free for user ech palette attribute 2 ffh 0fh 08h 07h 06h 05h 04h 03h 02h 01h 00h underline color set 2 (low) underline color set 2 (high) underline color set 1 (low) underline color set 1 (high) first buffer start address (low) first buffer start address (high) event line (low) event line (high) 8fh 70h 6fh 50h 4fh 30h 2fh 10h extended background palette extended foreground palette basic foreground palette basic background palette 96h 97h 98h 99h character code 1 character code 2 palette attribute 1 shape attribute 1 ffh 100h c5h character code 16 palette attribute 16 shape attribute 16 93h 92h 91h 90h active range row attributes horizontal shift (low) horizontal shift (high) + row char. count next buffer start addr. (low) next buffer start addr. (high) + row mode 94h 95h cch cdh ceh cfh character code 1 character code 2 palette attribute 1 shape attribute 1 f9h fah fbh character code 16 palette attribute 16 shape attribute 16 c9h c8h c7h c6h active range row attributes horizontal shift (low) horizontal shift (high) + row char. number next buffer start addr. (low) next buffer start addr. (high) + row mode cah cbh free for user fch second row buffer second row buffer first row buffer first row buffer basic parallel mode extended parallel mode free for user palettes palettes memory segment = 22h
95/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.5.5 font rom to address the characters in font rom, refer to figure 54 . to obtain the character code, add the line code to the column code. example 1: the code for the a character is: example 2: the code for the { character is: note: the two first 9x13 characters (address 00h and 01h) are the ST92186B control characters. they cannot be modified by the user. matrix line code + column code = character code 9x13 00h 41h 41h 18x26 60h 01h 61h matrix line code + column code = character code 9x13 82h 54h d6h 18x26 80h 1bh 9bh
96/148 ST92186B - on screen display controller (osd) figure 54. st92186 font rom contents 9x13 address 18x26 address 00h 01h 03h 04h 05h 02h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 13h 14h 15h 12h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 00h 01h 04h 05h 08h 09h 0ch 0dh 10h 11h 14h 15h 18h 19h 1ch 1dh 20h 21h 24h 25h 28h 29h 2ch 2dh 30h 31h 34h 35h 38h 39h 3ch 3dh 40h 41h 44h 45h 48h 49h 4ch 4dh 50h 51h 54h 55h 58h 59h 5ch 5dh 60h 61h 64h 65h 68h 69h 6ch 6dh 70h 71h 74h 75h 78h 79h 7ch 7dh
97/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.5.6 event line address in segment 22h: 00h (bits 15:8), 01h (bits 7:0) el[8:0] is a 9-bit number specifying at which tv line number the character row display should start. for more details refer to section 7.4.7.8 bits 15:8: are at address 00h in segment 22h. bits 7:0 are at address 01h bits 15:9 are reserved. 7.4.5.7 first buffer start address address in segment 22h: 02h (bits 15:8), 03h (bits 7:0) to handle the display properly, the user must store the start address of the first osdram row buffer (the row buffer containing the first row to be dis- played when the display controller is turned on). two bytes are reserved for this in the osdram. (see figure 52 ). bits 15:8 are at address 02h in segment 22h bits 7:0 are at address 03h bits 15:9 are reserved. as row buffer start addresses are always even ad- dresses, bit 0 is forced to 0 by hardware. 15 8 7 0 - - - - - - - el8 el7 el6 el5 el4 el3 el2 el1 el0 15 8 7 0 - - - - - - - fsa8 fsa7 fsa6 fsa5 fsa4 fsa3 fsa2 fsa1 0
98/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.6 programming the color palettes the palette attributes are coded inside the two palettes (basic background and foreground, and extended background and foreground); they are therefore accessible in all modes, parallel as well as serial. a palette contains 16 colors each defined with a 16-bit word. for each color, you can define the red level (1 of 8 values), the green level (1 value among 8), the blue level (1 value among 8), and the translucency level (1 value among 8). the color palettes also bring improvements in un- derline control to allow for windows-like buttons. once programmed, color palettes can be changed in real-time when the osd is running, that is to say when the software is filling one row buffer while the other one is displayed (but take care that the row currently displayed may be using some of the colors which you want to modify).
99/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.6.1 underline color set 1 (usc1) address in segment 22h: 04h (bits 15:8), 05h (bits 7:0) to support windows-like button effects, the color of the 2 (or 4 in 18x26 matrix) bottom dot lines of a character row may be defined using the underline attributes. two dedicated 2-byte words define 2 color sets, underline color set 1 called ucs1 and underline color set 2 called ucs2. they are used by the underline mode in addition to the current foreground color. this provides a four color choice for both rows 12 and 13 (9x13 character matrix) or pair of rows 23- 24 and 25-26 (18x26 character matrix): none (background), foreground, ucs1 or ucs2, as shown in table 18 . the ucs1 data is mapped in a fixed osdram lo- cation (see figure 52 ). bits 15:12 = free for the user bits 11:9 = u1t[2:0] underline color set 1 translu- cency these bits configure the background translucency level applied to the color (refer to section 7.4.3.11 for more details). u1t[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) u1t[2:0] = 0 means that this color will be fully transparent (the video is displayed instead of this color) bits 8:6 = u1r[2:0] underline color set 1 red color these bits configure the background red intensity for the color. u1r[2:0] = 0 means that no red is used to define the color. u1r[2:0] = 7 means that the maximum red intensi- ty is used in the color. bits 5:3 = u1g[2:0] underline color set 1 green color these bits configure the background green inten- sity for the color. u1g[2:0] = 0 means that no green is used to de- fine the color. u1g[2:0] = 7 means that the maximum green in- tensity is used in the color. bits 2:0 = u1b[2:0] underline color set 1 blue color these bits configure the background blue intensity for the color. u1b[2:0] = 0 means that no blue is used to define the color. u1b[2:0] = 7 means that the maximum blue inten- sity is used in the color. 15 8 7 0 u1t2 u1t1 u1t0 u1r2 u1r1 u1r0 u1g2 u1g1 u1g0 u1b2 u1b1 u1b0
100/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.6.2 underline color set 2 (ucs2) address in segment 22h: 06h (bits 15:8), 07h (bits 7:0) bits 15:12 = free for the user bits 11:9 = u2t[2:0] underline color set 1 translu- cency these bits configure the background translucency level applied to the color (refer to section 7.4.3.11 for more details). u2t[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) u2t[2:0] = 0 means that this color will be fully transparent (the video is displayed instead of this color) bits 8:6 = u2r[2:0] underline color set 1 red color these bits configure the background red intensity for the color. u2r[2:0] = 0 means that no red is used to define the color. u2r[2:0] = 7 means that the maximum red intensi- ty is used in the color. bits 5:3 = u2g[2:0] underline color set 1 green color these bits configure the background green inten- sity for the color. u2g[2:0] = 0 means that no green is used to de- fine the color. u2g[2:0] = 7 means that the maximum green in- tensity is used in the color. bits 2:0 = u2b[2:0] underline color set 1 blue color these bits configure the background blue intensity for the color. u2b[2:0] = 0 means that no blue is used to define the color. u2b[2:0] = 7 means that the maximum blue inten- sity is used in the color. warning : the ucs1 and ucs2 data may be used as row attributes providing more than 3 underline colors on screen. this requires taking some care when their contents are modified. the ucs1 and ucs2 contents are fetched for dis- play only when dot lines 12/13 of the character are being processed, but at that time (while dot lines 12 and 13 are processed) any change to ucs1 or ucs2 is forbidden. software should change the ucs1 or ucs2 while the display processes character dot lines 1 to 11. it is recommended to associate the ucs1 or ucs2 management of the currently displayed buffer with the routine which handles the next buffer prepara- tion. refer to section 7.4.7.9 . 15 8 7 0 - - - - u2t2 u2t1 u2t0 u2r2 u2r1 u2r0 u2g2 u2g1 u2g0 u2b2 u2b1 u2b0
101/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.6.3 foreground palettes the foreground palettes (basic and extended) both use the same principle: C the basic foreground palette is stored in os- dram (segment 22h) starting from 10h to 2fh (see figure 52 ). C the extended foreground palette is stored in os- dram (segment 22h) starting from 50h to 6fh (see figure 52 ). a 16-bit word is used to define each color in the palette, located at even addresses between 10h and 2eh (even value) for the basic foreground pal- ette, and between 50h and 6eh (even value) for the extended foreground one. figure 55. basic foreground palette mapping bit 15 = free for the user bits 14:12 = u[2:0] underline mode control bits . these bits configure the underline mode for the dot line 12 (lines 23 and 24 if using the 18x26 ma- trix) and line 13 (lines 25 and 26 if using the 18x26 matrix). see table 18 . bits 11:9 = ft[2:0] foreground translucency these bits configure the foreground translucency level applied to the color (refer to section 7.4.3.11 for more details). ft[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) ft[2:0] = 0 means that this color will be fully trans- parent (the video is displayed instead of this color) bits 8:6 = fr[2:0] foreground red color these bits configure the foreground red intensity for the color. fr[2:0] = 0 means that no red is used to define the color. fr[2:0] = 7 means that the maximum red intensity is used in the color. bits 5:3 = fg[2:0] foreground green color these bits configure the foreground green intensi- ty for the color. fg[2:0] = 0 means that no green is used to define the color. fg[2:0] = 7 means that the maximum green inten- sity is used in the color. bits 2:0 = fb[2:0] foreground blue color these bits configure the foreground blue intensity for the color. fb[2:0] = 0 means that no blue is used to define the color. fb[2:0] = 7 means that the maximum blue intensi- ty is used in the color. 15 8 7 0 u2 u1 u0 ft2 ft1 ft0 fr2 fr1 fr0 fg2 fg1 fg0 fb2 fb1 fb0 10h 2fh u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0] color 0 color 1 12h u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0] 14h color 15 u[2:0] ft[2:0] fr2 fr[1:0] fg[2:0] fb[2:0]
102/148 ST92186B - on screen display controller (osd) osd controller (contd) table 18. underline mode control bits description note: take care when changing (or stopping) un- derline mode for a character, when the back- ground color is displayed with underline mode change in the center of the character (m bit in background palette). in this case, the underline doesnt stop at the end of the character but stops in the middle of the fol- lowing character. the underline color used is the last background color displayed in the current pixel line. this always happens, when changing underline mode in the following ways: C from thick to thin or no underline C from one thin color to another when the under- lining is not on the same line. (thick underline, in a 9 x 13 matrix, is underlining on 2 lines and, in a 18 x 26 matrix, on 4 lines. thin underline, in a 9 x 13 matrix, is underlining on 1 line and, in a 18 x 26 matrix, on 2 lines.) u2 u1 u0 underline color for a 9x13 dot matrix underline color for a 18x26 dot matrix 0 0 0 no underline no underline 0 0 1 line 12: foreground color lines 23-24: foreground color 0 1 0 line 13: underline color set 1 lines 25-26: underline color set 1 0 1 1 line 13: underline color set 2 lines 25-26: underline color set 2 1 0 0 line 12-13: underline color set 1 lines 23-24-25-26: underline color set 1 1 0 1 line 12-13: underline color set 2 lines 23-24-25-26: underline color set 2 110 line 12: underline color set 1; line 13: underline color set 2 lines 23-24: underline color set 1; lines 25-26: underline color set 2 111 line 12: underline color set 2; line 13: underline color set 1 lines 23-24: underline color set 2; lines 25-26: underline color set 1
103/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.6.4 background palettes the background palettes (basic and extended) both use the same principle: the basic background palette is stored in os- dram (segment 22h) starting from 30h to 4fh (see figure 52 ). the extended background palette is stored in os- dram (segment 22h) starting from 70h to 8fh (see figure 52 ). a 16-bit word is used to define each color in the palette, located at even addresses between 30h and 4eh (even value) for the basic background palette, and between 70h and 8eh (even value) for the extended background one. figure 56. basic background palette mapping bit 15 = m background color change bit . this bit determines where the background color change occurs. 0: the background color change takes effect im- mediately. 1: the background color change occurs in the center of the character. notes : C when the preceding character is slanted (italics on, only available in serial mode), a background color change only occurs in the center of the character regardless of the m bit value. C if the m bit is used in parallel mode at the begin- ning of a row, it is strongly recommended to in- sert a space or null character before setting the m bit in order to control the first half background color. bits 14:12 = free for the user bits 11:9 = bt[2:0] background translucency these bits configure the background translucency level applied to the color (refer to section 7.4.3.11 for more details). bt[2:0] = 7 means that this color will be fully opaque (no video mixed in it on the display) bt[2:0] = 0 means that this color will be fully trans- parent (the video is displayed instead of this color) bits 8:6 = br[2:0] background red color these bits configure the background red intensity for the color. br[2:0] = 0 means that no red is used to define the color. br[2:0] = 7 means that the maximum red intensity is used in the color. bits 5:3 = bg[2:0] background green color these bits configure the background green inten- sity for the color. bg[2:0] = 0 means that no green is used to define the color. bg[2:0] = 7 means that the maximum green inten- sity is used in the color. bits 2:0 = bb[2:0] background blue color these bits configure the background blue intensity for the color. bb[2:0] = 0 means that no blue is used to define the color. bb[2:0] = 7 means that the maximum blue intensi- ty is used in the color. 15 8 7 0 m bt2 bt1 bt0 br2 br1 br0 bg2 bg1 bg0 bb2 bb1 bb0 30h 4fh color 0 color 1 32h 34h color 15 m bt[2:0] br2 br[1:0] bg[2:0] bb[2:0] m bt[2:0] br2 m bt[2:0] br2 br[1:0] bg[2:0] bb[2:0] br[1:0] bg[2:0] bb[2:0]
104/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7 programming the row buffers the 2 row buffers are based on the same structure ( figure 52 ): C next buffer start address C row mode C horizontal shift C row character count 7.4.7.1 next buffer start address and row mode address in segment 22h: 2p (bits 15:8), 2p + 1 (bits 7:0). see figure 52 . to display more than 1 character row on the screen, you must specify the start address of the next osdram row buffer (the row buffer contain- ing the next row to be displayed when the current row is completely processed). two bytes are re- served for this in the osdram. (see figure 52 ). as it is possible to display each row using different modes (serial, basic parallel, and extended paral- lel), the row mode has to be specified for the cur- rent row buffer. bits 15:14 = wm[2:1] serial/parallel row mode control these bits define the row mode for the buffer de- fined by the next buffer start address (nsa[8:0] bits). refer to table 19 for details. table 19. serial/parallel mode control bits 13:9 = free for the user bits 8:0 = nsa[8:0] next buffer start address these bits define the start address of the next row buffer. as row buffer start addresses are always even ad- dresses, the nsa0 is not implemented, and bit 0 is forced to 0 by hardware. 15 8 7 0 wm2 wm1 nsa8 nsa7 nsa6 nsa5 nsa4 nsa3 nsa2 nsa1 0 wm2 wm1 mode 1 1 (reserved) 1 0 extended parallel 0 1 basic parallel 0 0 serial
105/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7.2 horizontal shift and row character count address in segment 22h: 2p + 2 (bits 15:8), 2p + 3 (bits 7:0). see figure 52 . for each row to be displayed, the number of char- acters in the row, and the horizontal position of the row on the screen need to be specified. lets assume that the start address of the current row buffer is 2p (even address). bits 15:10 = rcn[5:0] row character count these bits define the number of characters to dis- play in the current row. the display controller allows to display from 1 to 63 characters (in parallel mode) or 61 (in serial mode, as the first 2 bytes are taken as attributes).. for example, a 36 character row requires pro- gramming rcn[5:0] = 24h. bits 9:0 = hs[9:0] horizontal shift these bits define the horizontal shift value. they specify, in terms of number of pixel clock periods, the horizontal shift applied from the leading edge of the hsync pulse to the beginning of the first dis- played character (1 st character in parallel modes, 3 rd character in serial mode). refer to figure 57 . loading any value smaller than 01h is forbidden. the result is given by the formula: horizontal shift = [hs[9:0]+ 47] * (2*pixclk) (where pixclk is the clock issued from the skew corrector). refer to the timing and clock control chapter for programming information. figure 57. row position 15 8 7 0 rcn5 rcn4 rcn3 rcn2 rcn1 rcn0 hs9 hs8 hs7 hs6 hs5 hs4 hs3 hs2 hs1 hs0 displayed row event line (vertical shift) horizontal shift st92186
106/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7.3 row attributes address in segment 22h: 2p + 4. see figure 52 . for each row to be displayed, specify the font ma- trix used (9x13 or 18x26), the size of the charac- ters, the rounding, the fringe and the flash mode. lets assume that the start address of the current row buffer is 2p (even address). bit 7 = fm font matrix this bit selects the 9x13 or the 18x26 font matrix for the current row. the fm bit is not an address extension bit but it af- fects how the font rom content is addressed. 0: the characters use a 9x13 font matrix. 1: the characters use an 18x26 font matrix bit 6 = uh upper half when 18x26 characters are displayed in double height (i.e. if the dbly parallel attribute is set), the uh bit defines if the current row displays the lower or upper half of the character. this bit has no effect when a 9x13 matrix is used or when the character has normal height (when dbly= 0). 0: the lower half of the double-height character is displayed. 1: the upper half of the double-height character is displayed. bit 5 = free for the user bit 4 = sy vertical size control bit this bit defines the character dot height refer to table 20 , table 21 , and table 22 for com- plete details. note : the dot height is also affected by dbly, de- fined in the parallel attribute section. bit 3 = sx horizontal size control bit this bit defines the character dot width refer to table 20 , table 21 , and table 22 for com- plete details. note : the dot width is also affected by dblx, de- fined in the parallel attribute section. table 20. 9x13 font matrix table 21. 18x26 font matrix (1) table 22. 18x26 font matrix (2) note : in 18x26 matrix mode, this mechanism pro- vides 7 different sizes which are: 1y-1x, 2y-2x, 4y-4x but also 2y-1x, 1y-2x, 4y-2x, 2y-4x. note : when the display controller works in basic parallel mode, the dblx and dbly bits are not ac- cessible, and are assumed to be always pro- grammed to 0. bit 2 = fon flash on control bit this bit is used to control the flashing period by software. it is only available in serial and extended parallel modes. this bit has no effect in basic par- allel mode. 0: the flashing mechanism is disabled for the whole row in all modes. 1: the flashing mechanism is enabled for the whole row. all characters described in the row with a serial or a parallel flash attribute are displayed as space with background color. underline also flashes. 70 fm uh sy sx fon rou fr sy sx dot height dot width matrix size 0 0 2 lines 2 pixels 1y-1x 0 1 2 lines 3 pixels 1y-1.5x 1 0 4 lines 3 pixels 2y-1.5x 1 1 4 lines 4 pixels 2y-2x sx character width dblx=0 dot width character width dblx=1 dot width 0 1x 1 pixel 2x 2 pixels 1 2x 2 pixels 4x 4 pixels sy vertical dot size dbly = 0 vertical dot size dbly = 1 0 1 line 2 lines 1 2 lines 4 lines
107/148 ST92186B - on screen display controller (osd) osd controller (contd) bit 1 = rou rounding control bit this bit enables or disables the rounding for the whole row. 0: the rounding is disabled 1: the rounding is enabled note : for a 18x26 matrix size, there is no rounding when the character size is (1x,1y). for any other (x,y) size combinations, the rounding is possible for the 18x26 font matrix. bit 0 = fr fringe control bit this bit enables or disables the fringe for the whole row. the fringe mechanism can be activated for any size and matrix format. 0: the character fringe is disabled 1: the character fringe is enabled. note : in case of fringe usage in 1y vertical size and interlaced mode, a flicker may appear on screen as the fringe information is built on a field basis. 7.4.7.4 active range address in segment 22h: 2p + 5. see figure 52 . the active range feature is useful for software con- trolled smooth vertical scrolling (up or down). for each row to be displayed, the first line (rs) and the last line (re) to be displayed for the cur- rent row have to be specified. the two values (rs[3:0] and re[3:0]) are com- pared to the row line counter value. if the value of the counter is outside the active range (less than rs[3:0] or greater than or equal to re[3:0]), the border color is displayed as defined by its at- tributes. otherwise, if the counter value is inside the active range, the normal character pixel processing and display is done (see figure 58 ). lets assume that the start address of the current row buffer is 2p (even address). bits 7:4 = rs[3:0] active range start value the rs[3:0] value range is 0h-ch (0-12) in all cas- es (9x13 or 18x26 character matrix). bits 3:0 = re[3:0] active range end value the re[3:0] value range is 1h-dh (1-13) in all cas- es (9x13 or 18x26 character matrix). note : for 18x26 matrix characters, the active range is calculated by pair of tv lines, i.e. the ac- tive range always starts on the first field and finish- es on the second field (in interlaced mode). in case of non-interlaced display mode, the active range is calculated by pair of tv lines. figure 58. active range example 70 rs3 rs2 rs1 rs0 re3 re2 re1 re0 0 1 2 3 4 5 6 7 8 9 10 11 12 rs = 0 ; re = 13 rs = 4 ; re = 9 active range example pixel not displayed
108/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7.5 serial mode in serial mode, only 1 byte is used to describe the character code or the attribute ( figure 52 ): C if the most significant bit (bit 7) of this byte is 0, the byte represents a character code. C if the most significant bit (bit 7) of this byte is 1, the byte represents a serial attribute. then the display controller uses bit 6 to determine wheth- er the attribute is a foreground serial attribute (bit 6 = 0) or a background serial attribute (bit 6 = 1). a consequence of this structure is that in serial mode, only the first 128 characters stored in the font rom can be accessed (the value of the 7 least significant bits of the character code = the character number in font rom). the first two bytes of the row buffer describing the row are displayed as border color. the first char- acter to be displayed in serial mode is in fact the 3 rd of the row buffer. all the attributes (background and foreground) are displayed as space with background color. lets assume that the start address of the current row buffer is 2p (even address). in this case the character codes and attributes are stored in the osdram at the address 2p+5+z, where z value is 1 to rcn (rcn is the row charac- ter count defined in section 7.4.7.2 ). character code in serial mode a ddress in segment 22h: 2p + 5 + z. see figure 52 . bits 6:0 = chc[6:0] character code in serial mode the chc[6:0] value points to one of the first 128 characters stored in the font rom. background serial attribute address in segment 22h: 2p + 5 + z. see figure 52 . bits 5:4 reserved bits 3:0 = bp[3:0] background palette pointer the bp[3:0] value points to one of the 16 prede- fined entries of the background palette for the background color and the translucency. for example, bp[3:0] = 0 points to the first back- ground palette entry, 30h & 31h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). note : the display of the background serial attribute is affected by the use of the italics (see the fore- ground serial attribute) and also by the m bit lo- cated in the background palette (see section 7.4.6.4 for further details). 70 0 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 1 1 x x bp3 bp2 bp1 bp0
109/148 ST92186B - on screen display controller (osd) osd controller (contd) foreground serial attribute address in segment 22h: 2p + 5 + z. see figure 52 bit 5 = fla flash control bit this bit controls the flashing feature (see section 0.2.4.2). 0: all the following characters in the row are not af- fected by the flashing mechanism. 1: all the following characters in the row follow the flashing mechanism. note : flashing characters are alternatively dis- played as spaces and in normal mode (non-flash- ing), depending on the value of the fon bit in the row attribute byte (see section 7.4.7.3 ). the flash rate is controlled by software by toggling the "fon" bit. bit 4 = it italics control bit this bit enables the italic feature for the row. (see section 7.4.3.6 ) 0: italics are disabled. 1: all the following characters, until the end of the row, or the next foreground serial attribute are displayed in italics. note : italics mode is only available in serial mode. bits 3:0 = fp[3:0] foreground palette pointer the fp[3:0] value points to one of the 16 prede- fined entries of the foreground palette for fore- ground color, translucency and underline style of all the following characters (see section 7.4.6.3 ). for example, fp[3:0] = 0 points to the first fore- ground palette entry, 10h & 11h if the palette swap bit pasw of the osddr register is reset. 7.4.7.6 basic parallel mode in basic parallel mode, each character code (1 byte) is followed by a palette attribute (1 byte). see figure 52 . lets assume that the start address of the current row buffer is 2p (even address). in this case the character codes are stored in os- dram at the address 2p+4+2z, and the palette at- tributes are stored in the osdram at the address 2p+5+2z, where z ranges from 1 to rcn (rcn is the row character count defined in section 7.4.7.2 ). the character code structure allows pointing to the first 256 characters of the font rom (the character code value = the character number in font rom). character code in basic parallel mode address in segment 22h: 2p+4+2z. see figure 52 . bits 7:0 = chc[7:0] character code in basic par- allel mode the chc[7:0] value points to one of the first 256 characters stored in the font rom. palette attribute address in segment 22h: 2p+5+2z. see figure 52 . bits 7:4 = fp[3:0] foreground palette pointer the fp[3:0] value points to one of the 16 prede- fined entries of the foreground palette for the fore- ground color, the translucency and the underline style of all the following characters (see section 7.4.6.3 for further details). for example, fp[3:0] = 0 points to the first fore- ground palette entry, 10h & 11h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). bits 3:0 = bp[3:0] background palette pointer the bp[3:0] value points to one of the 16 prede- fined entries of the background palette for the background color and the translucency. for example, bp[3:0] = 0 points to the first back- ground palette entry, 30h & 31h if the palette swap bit pasw of the osddr register is reset (see reg- isters description for more details). note : the background color of the character is af- fected by the use of the m bit located in the back- ground palette (see section 7.4.6.4 ). 70 1 0 fla it fp3 fp2 fp1 fp0 70 chc7 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 fp3 fp2 fp1 fp0 bp3 bp2 bp1 bp0
110/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7.7 extended parallel mode in extended parallel mode, each character code (1 byte) is followed by a palette attribute (1 byte) and a shape attribute (1 byte). refer to figure 52 . lets assume that the start address of the current row buffer is 2p (even address). the character codes are stored in the osdram at the address 2p+3+3z, the palette attributes are stored at the address 2p+4+3z, and the shape at- tributes are stored at the address 2p+5+3z, where z range value is 1 to rcn (rcn is the row charac- ter count defined in section 7.4.7.2 ). the character code structure, using the shape at- tribute, allows you to point to any of the font rom characters. the shape attribute definition depends on the font matrix used for the row (it depends on the fm bit, see section 7.4.7.3 ). character code in extended parallel mode address in segment 22h: 2p+3+3z. see figure 52 . bits 7:0 = chc[7:0] character code in extended parallel mode the chc[7:0] bits are used, combined with 3 or 1 bits of the shape attribute (for a 9x13 or 18x26 ma- trix), to point to any of the characters stored in the font rom (refer to the shape attribute description for more details). palette attribute address in segment 22h: 2p+4+3z. see figure 52 . refer to section 7.4.7.6 for the bit description. 70 chc7 chc6 chc5 chc4 chc3 chc2 chc1 chc0 70 fp3 fp2 fp1 fp0 bp3 bp2 bp1 bp0
111/148 ST92186B - on screen display controller (osd) osd controller (contd) shape attribute - 9x13 matrix address in segment 22h: 2p+5+3z. see figure 52 . bit 7 = codx character code extension this bit is used with spl[1:0] as the character ad- dress extension. thus it is possible to address any of the 9x13 characters of the font rom. (see the spl[1:0] bit description for more details) bits 6:5 = spl[1:0] character split control bits these character split bits are used with the codx bit as the character address extension. it is then possible to address any of the 9x13 charac- ters of the font rom. if the character code is chc[7:0] (1 byte), then the character addressed with this structure is: codx.spl1.spl0.chc[7:0] bit 4 = fxp foreground extended palette ad- dressing bit this bit is combined with the pasw bit in the os- ddr register to give the msb bit of the foreground palette address. it allows the foreground palette, (basic or extended), to be selected on a per-char- acter basis. see table 23 for details. table 23. foreground palette selection bit 3 = bxp background extended palette ad- dressing bit this bit is combined with the pasw bit in the os- ddr register to give the msb bit of the back- ground palette address. it allows the background palette, (basic or extended), to be selected on a per-character basis. see table 24 for details. bit 2 = foc flash on character control bit this bit enables the flash mechanism for the cur- rent character. 0: the flash mechanism is disabled. the current character is displayed, whatever the flash row attribute value (fon) is (see section 7.4.7.3 ). 1: the flash mechanism is enabled. if the flash row attribute (fon) is on (see section 7.4.7.3 ), the character is displayed as space using the back- ground color. bit 1 = sha shadow mode control bit this bit enables or disables a black shadow shape on the right and bottom edges of the current char- acter foreground. 0: no shadow is added 1: a black shadow is added on the current charac- ter. note : this shadow shape follows the same algo- rithm as the fringe (see section 7.4.3.7 for further details). bit 0 = frc fringe on character control bit this bit enables or disables a fringe on the current character foreground. 0: no fringe is added. 1: a fringe is added on the current character if the fringe row attribute bit fr is set (see section 7.4.7.3 for more details). note : the fringe follows the algorithm described in section 7.4.3.7 . 70 codx spl1 spl0 fxp bxp foc sha frc pasw fxp foreground palette used 0 0 basic 0 1 extended 1 0 extended 1 1 basic pasw bxp background palette used 0 0 basic 0 1 extended 1 0 extended 1 1 basic
112/148 ST92186B - on screen display controller (osd) osd controller (contd) shape attribute - 18x26 matrix address in segment 22h: 2p+5+3z. see figure 52 . bit 7 = codx character code extension this bit is used as the character address exten- sion. then it is possible to address any of the 18x26 characters of the font rom. lets assume that the character code is chc[7:0] (1 byte), then the character addressed with this structure is: codx.chc[7:0] bit 6 = dbly double height control bit this bit controls the double height feature applied on the current row height. 0: the character is displayed with the current row height, as defined by sy ( section 7.4.7.3 ). 1: the current character is displayed with a double height than defined by sy. the display of the lower or upper half of the character is controlled by the uh row attribute bit (refer to section 7.4.7.3 ). bit 5 = dblx double width control bit this bit controls the double width feature applied to the current row character width. 0: the character is displayed with the current width as defined by sx ( section 7.4.7.3 ). 1: the character is displayed in double width, ac- cording to the following rules: C it covers the next character location C the next character location is read and de- coded but not processed, C if the character is the last one in the row, it will be truncated to its left half. bit 4:0 = please refer to the bit descriptions in the 9x13 matrix shape attributes. 70 codx dbly dblx fxp bxp foc sha frc
113/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.7.8 row buffer management to start the display: 0. write the (dion, osde) bits to (1,0) to access the osdram with the cpu clock, 1. initialize the color palettes, 2. initialize the first buffer start address with the address of the first byte of the above row buffer (address 0002h & 0003h of the segment 22h), 3. fill up one of the row buffers with the data to display the desired row (only in case the te bit in the osder register has been set), 4. initialize the event line value to the desired one (address 0000h & 0001h of the segment 22h), 5. start the display controller by programming the mode control bits (dion, osde) and the trans- fer enable bit (te) to the desired working mode. it is mandatory to start the display following the algorithm below: 1 unsigned char tmp; spp(osd_pg); /* select the osd register page */ osdfbr &= ~0x06; /* reset dint & moit bits */ 5 while (osdfbr & osdm_vsy); /* wait a low to high transition on vsync */ while (!(osdfbr & osdm_vsy)); tmp= osdmr; /* save lsm bits */ 10 osdmr &= ~0x07; /* reset the lsm bits so that the hsy bit will be an image of the hsync pulse */ osder = 0x40; /* osdram interface enabled with pixel clock */ di(); /* disable all interrupts */ 15 while (osdfbr & osdm_hsy); /* wait a hsync pulse : low -> high -> low transition */ while (!(osdfbr & osdm_hsy)); while (osdfbr & osdm_hsy); 20 osdmr = tmp; /* recover old lsm bit value */ spp(osd_pg); /* select the osd register page */ osder |= 0xe0; /* start the display by setting the appropriate bits, set at least osde, dion, and te bits. then set the other bits as required 25 for your application. */ ei(); /* enable interrupts again*/
114/148 ST92186B - on screen display controller (osd) osd controller (contd) the real time control provides: C a continuous search of matching values be- tween scan line and event line (this condition being evaluated at each tv line start). C a display interrupt generation when the match condition is detected. C in full osd mode, if the te bit in the osder register is set, the switch from one row buffer to the second row buffer when the match occurs. if the te bit in the osder register is reset, when a matching condition occurs, the previous row buff- er will be kept. 7.4.7.9 handling the row buffers in continuous mode: C when the line match condition is detected, an in- terrupt is sent to the cpu. let us then assume the te bit in the osder reg- ister is set. when the interrupt is executed: C the event line value must be programmed to the next desired value. C the next row buffer content must be filled up by the data of the next row to display. the next row buffer is easily identified using the bufl bit in the osdfbr register. let us then assume the te bit in the osder reg- ister is reset. when the interrupt is fetched: C the event line value must be programmed to the next desired value. C the next row buffer content might be filled up by the data of the next row to display, if desired. C the content of the current row buffer is not displayed but simply ignored as it should have al- ready been displayed in a previous cycle. note : in case the te bit in the osder register is kept reset, there is no need to manage the second row buffer as it will never be used.
115/148 ST92186B - on screen display controller (osd) osd controller (contd) 7.4.8 register description to run the display controller properly, you need to program the 7 registers that configure the display border color register 2 (osdbcr2) r246 - read/write register page: 42 reset value: 0x00 0000 bit 7 = b2bc background to border color control bit . this bit allows to force the background color of all the characters to the border color. 0: all characters backgrounds are normally dis- played 1: all character backgrounds are forced to the cur- rent border color and translucency level. bit 6 = reserved bits 5:3 = bos[2:0] border color translucency these bits control the border color translucency. bos[2:0] = 7 means that the border color will be fully opaque (no video mixed in it on the display) bos[2:0] = 0 means that the border color will be fully transparent (the video is displayed instead of this color) bits 2:0 = bor[2:0] red border color these bits configure the red intensity for the bor- der color. bor[2:0] = 0 means that no red is used to define the border color. bor[2:0] = 7 means that the maximum red inten- sity is used in the border color. border color register 1 (osdbcr1) r247 - read/write register page: 42 reset value: 0x00 0000 bit 7 = difb digital fb control bit this bit selects the fast blanking (fb) output as analog or digital. 0: the fb dac works as an 8-level dac output from 0v up to 1v (with a 500ohms internal im- pedance to ground). 1: the fb dac works as a 2-level dac output, the high level providing an amplitude higher than 2.7 volts. all translucency control bits are man- aged as follows: - the code (0,0,0) generates a 0 output (0 volt), - all other codes generate a 1 output (>2.7 v). note : this applies to bt[2:0], ft[2:0], u2t[2:0], u2t[2:0] and bos[2:0] (refer to section 7.4.6.3 , section 7.4.6.4 and section 7.4.6.1 , and to the osdbcr2 register). bit 6 = reserved bits 5:3 = bog[2:0] green border color these bits configure the green intensity for the border color. bog[2:0] = 0 means that no green is used to de- fine the border color. bog[2:0] = 7 means that the maximum green in- tensity is used in the border color. bits 2:0 = bob[2:0] blue border color these bits configure the blue intensity for the bor- der color. bob[2:0] = 0 means that no blue is used to define the border color. bob[2:0] = 7 means that the maximum blue inten- sity is used in the border color. 70 b2bc bos2 bos1 bos0 bor2 bor1 bor0 70 difb - bog2 bog1 bog0 bob2 bob1 bob0
116/148 ST92186B - on screen display controller (osd) osd controller (contd) enable register (osder) r248 - read/write register page: 42 reset value: 0000 0000 (00h) bit 7 = dion display on this bit is used in combination with the osde bit to control the display working mode. see table 25 . warning : after a reset, a valid hsync signal is re- quired to write to the osdram, whatever the clock rate (cpu or pixel clock rate). bit 6 = osde osd enable this bit is used in combination with the dion bit to control the display working mode. see table 18 . note 1 : when the (dion,osde) bits switch from any other value to (1,1), i.e. when the controller is switched to a full osd function, the first buffer start address content is used to locate the first row buffer to process. while the full display function is running, the dion & osde bits remain set and the first buffer start address is not used again, even if both bits are re- written to 1. note 2 : it is strongly recommended to use state 3 only if the osdram has been initialized using state 2. warning 1: states 3 and 4 (refer to table 25 ) can only be used if hsync and vsync are applied on the external pins. warning 2 : after a reset, a valid hsync signal is required to write to the osdram, regardless of the clock rate (cpu or pixel clock rate). warning 3 : when the osd is displayed, it is ad- vised not to write to the osdram when a vsync pulse occurs. in normal operating mode, this con- figration will never happen. bit 5 = te transfer enable bit this bit controls the swap to next row buffer func- tion whenever the scan line counter content matches the event line parameter value. an interrupt request pulse is generated and for- warded to the core each time the match occurs re- gardless of the value of te. 0: row buffer swap disabled. the current row buff- er content is simply ignored and the screen will display the border color, as if the current buffer content was already processed. 1: a row buffer swap enabled note : refer to section 7.4.7.8 for more details about using the te bit. bit 4 = dbls double scan bit this bit defines if the display works in 1h or 2h mode. 0: the display works in single scan or 1h mode. 1: the display works in double scan or 2h mode. the 2h mode is used in progressive scan display (60hz field, 525 lines). note : the dbls bit acts on the display vertical de- lay for field determination (refer to the vd[3:0] bits of the delay register osddr). the dbls bit also acts on the line start mute (re- fer to the lsm[2:0] bits of the mute register osd- mr) and the hsy flag bit. bit 3 = nids non interlaced display control bit this bit selects interlaced or non-interlaced mode. 0: the display works in interlaced mode (line counting, fringe and rounding algorithms are 2- field based) 1: the display works in non-interlaced mode (line counting, fringe and rounding algorithms are 1- field based). bit 2 = tsle translucency enable bit this bit enables or disables the digital translucen- cy signal (tslu) generation. (refer to section 7.4.3.11 ). 0: the tslu signal built by the display controller remains continuously idle regardless of osd ac- tivity. 1: the tslu signal carries the real time back- ground information and can be output through the i/o pin alternate function. bit 1 = reserved. must be kept at reset. bit 0 = fpixc fast pixel clock control bit this bit handles the divide-by-2 prescaler inserted between the skew corrector output and the dis- play pixel clock input. 0: the skew corrector clock output is divided by 2 to provide the pixel clock. 1: the skew corrector clock output is directly tak- en as the pixel clock. 70 dion osde te dbls nids tsle - fpixc
117/148 ST92186B - on screen display controller (osd) osd controller (contd) note : for further information, refer to the timing and clock control chapter. table 25. osdram interface configuration dion osde osdram interface clock osd function detailed configuration state 0 0 off, no ram access off the osdram controller and the display are both disa- bled. the cpu has no access to the osdram. 1 1 0 on, cpu clock off the display is disabled. the osdram controller is run- ning using the cpu clock, allowing for cpu accesses. 2 0 1 on, pixel clock no osd, time control on the display is partially enabled. the osdram control- ler is running with the pixel clock, allowing cpu access- es. the osd pixel processing is disabled (rgb & fb outputs are turned off), the tv oriented time control is still running, such as event line control, interrupt genera- tion, flag bits and field calculation. the border control is inactive. 3 1 1 on, pixel clock fully on the osdram controller and the display are both ena- bled. the osdram controller is running with the pixel clock, allowing cpu accesses. the rgb & fb outputs are turned on. the border control is activated. 4
118/148 ST92186B - on screen display controller (osd) osd controller (contd) delay register (osddr) r249 - read/write register page: 42 reset value: 0xxx xxxx note : the display may flicker if you write to the delay register while osd is fully on. bit 7 = pasw palette swap bit the pasw bit is used in serial or basic parallel modes to provide access to the extended palettes. it is still active when you work in extended parallel mode, however it not needed as the fxp and bxp bits are available (refer to section 7.4.7.7 ). 0: the basic palette sets are used. 1: the extended palette sets are used. bit 6 = hpol hsync signal polarity selection bit this bit has to be configured according to the po- larity of the hsync input signal. 0: hsync input pulses are of positive polarity 1: hsync input pulses are of negative polarity bit 5 = vpol vsync signal polarity selection bit this bit has to be configured according to the po- larity of the vsync input signal. 0: vsync input pulses are of positive polarity 1: vsync input pulses are of negative polarity bit 4 = fbpol fast blanking signal polarity selec- tion bit this bit selects the polarity of the fast blanking (fb) output signal. 0: fb output pulses are of positive polarity (fb ac- tive high) 1: fb output pulses are of negative polarity (fb ac- tive low) note : the fb signal is kept active during the vsync vertical retrace. bits 3:0 = vd[3:0] vertical delay control bits this 4-bit value is used to program an internal de- lay on vertical sync pulses applied to vsync input pin. the purpose of the programmable delay is to pre- vent vertical osd jitter in case the rising edge of external vertical sync pulse coincides with thatofan external horizontal sync pulse. the delay applied is expressed by the following equations (4 mhz is the frequency issued directly from the crystal oscillator): for 2h display mode: [vd[3:0]+1] * 8*(1/4mhz) =< d =< [vd[3:0]+2] * 8*(1/4mhz) for 1h display mode: [vd[3:0]+1] *16*(1/4mhz) =< d =< [vd[3:0]+2] *16*(1/4mhz) note : programming the vertical delay to fh will freeze the scan line counter disabling any further rgb output. note : it is mandatory for the cpu to initialize the vertical delay register to avoid any problems. scan line register (osdslr) r251 - read only register page: 42 reset value: xxxx xxxx (xxh) bits 7:0 = sl[7:0] scan line counter value these bits indicate the current vertical position of the tv beam. the most significant bit sl8 of this counter is locat- ed in the flag bit register osdfbr (see below). this counter starts from 0 at the top of the screen (i.e. after the vsync pulse) and is incremented by hsync. 70 pasw hpol vpol fbpol vd3 vd2 vd1 vd0 70 sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0
119/148 ST92186B - on screen display controller (osd) osd controller (contd) flag bit register (osdfbr) r250 - read/write register page: 42 reset value: xxxx xxxx (xxh) bit 7 = bufl buffer flag bit this bit indicates which row buffer of the osd ram is being used by the display. the bufl flag is automatically re-evaluated each time the scan & event line matching condition is fulfilled. in case the te bit is reset (see the os- der register), the bufl flag remains un- changed as no row buffer change occurs. 0: the osd displays the content of the second row buffer (the one not pointed by the first buffer start address value). 1: the osd displays the content of the row buffer location pointed by the first buffer start address value. note : the bufl flag is automatically reset when the (dion,osde) bits are switching from any oth- er value to (1,1); it will be set at the first buffer transfer (scan & event match and te=1). bit 6 = vsy vsync status bit this bit gives the status of the vsync input signal. 0: the vsync input signal is inactive. 1: the vsync input signal is active. note : the vsync signal polarity is compensated to always provide vsy=1 during the vertical pulse. bit 5 = hsy hsync status bit this bit gives the status of the internal hs signal generated by the skew corrector and locked to the external hsync signal. 0: the hs signal is inactive. 1: the hs signal is active. note : the hsync signal polarity is compensated to provide hsy=1 during the horizontal pulse. note : hsy remains active during the whole line start mute timing which is software controlled through both the dbls bit and the lsm[2:0] value (see osder and osdmr registers). bit 4 = vsdl delayed vertical pulse status bit this bit indicates the status of the vdpls internal signal (it is the delayed vertical pulse issued from the programmable vertical delay unit as described by the osddr register bits vd[3:0]) 0: the vdpls internal signal is inactive 1: the vdpls internal signal is active note : the vdpls signal polarity is compensated to provide vsdl =1 during the vertical pulse. bit 3 = field field status bit this bit indicates the current tv field. 0: tv beam is in field 2 (even field) 1: tv beam is in field 1 (odd field) bit 2 = dint display interrupt flag bit this bit is set by hardware when an osd interrupt occurs. this bit must be reset by software. bit 1 = reserved. bit 0 = sl8 most significant bit of the scan line counter refer to the description of the osdslr register. 70 bufl vsy hsy vsdl field dint - sl8
120/148 ST92186B - on screen display controller (osd) osd controller (contd) mute register (osdmr) r252 - read/write register page: 42 reset value: 00xx x000 bits 7:3 = reserved bits 2:0 = lsm[2:0] line start mute value these bits are used to program the mute duration after the beginning of each tv line. when the display works in 1h mode the mute du- ration can be adjusted in 2s steps from 2 to 14 s. when the display works in 2h mode the mute du- ration can be adjusted in 1s steps from 1 to 7 s. the lsm bits also define the hsy flag duration. the mute duration is expressed by the following equation (the 1s is a frequency issued from the crystal oscillator): for 2h display mode: t mute = lsm[2:0] * (1 s) for 1h display mode: t mute = lsm[2:0] * 2*(1 s) in both 1h/2h modes, if lsm[2:0] = 0 then t mute = hsync width. 70 - - - - - lsm2 lsm1 lsm0
121/148 ST92186B - on screen display controller (osd) osd controller (contd) table 26. osd register map register number page 42 register name 765 4 3210 246 osdbcr2 reset value b2bc 0 - x bos2 0 bos1 0 bos0 0 bor2 0 bor1 0 bor0 0 247 osdbcr1 reset value difb 0 - x bog2 0 bog1 0 bog0 0 bob2 0 bob1 0 bob0 0 248 osder reset value dion 0 osde 0 te 0 dbls 0 nids 0 tsle 0 - 0 fpixc 0 249 osddr reset value pasw 0 hpol x vpol x fbpol x vd3 x vd2 x vd1 x vd0 x 250 osdfbr reset value bufl x vsy x hsy x vsdl x field x dint x - x sl8 x 251 osdslr reset value sl7 x sl6 x sl5 x sl4 x sl3 x sl2 x sl1 x sl0 x 252 osdmr reset value - 0 - 0 - x - x - x lsm2 0 lsm1 0 lsm0 0
122/148 ST92186B - ir preprocessor (ir) 7.5 ir preprocessor (ir) 7.5.1 functional description the ir preprocessor measures the interval be- tween adjacent edges of the demodulated output signal from the ir amplifier/detector. you can specify the polarity using the posed and neged bit in the irscr register the measurement is rep- resented in terms of a count obtained with a 12.5khz clock and stored in the irpr register. whenever an edge of specified polarity is detect- ed, the count accumulated since the previously detected edge is latched into an 8-bit register and an interrupt request irq is generated if the ir- wdis bit is reset in the irscr register. note: any count less than 255 stored in the latch register is over-written in case the p fails to exe- cute the read before the next edge occurs. in case an edge is not detected in about 20ms (the count reaches its maximum value of 255) the count is latched immediately and the irq flag is set. an overflow flag (not accessable) is also set internally. each time an interrupt is received, it must be ac- knowleged by writing any value in the irpr regis- ter. otherwise no further interrupts will be generat- ed. warning: the content of the latch cannot be changed as long as the overflow flag remains set. to clear the irq and internal overflow flags, just write any value in the irpr register. as long as the internal overflow flag is set, no interrupt is generat- ed. the ir input signal is preprocessed by a spike fil- ter. the flsel bit of the irscr register deter- mines the width of filtered pulse. 7.5.2 register description ir pulse register (irpr) r248 - read only register page: 43 reset value: 0000 0000 (00h) bits 7:0 = ir[7:0] : ir pulse width in terms of number of 12.5khz clock cycles. ir/sync control register (irscr) r250 - read/write register page: 43 reset value: 0000 0000 (00h) bits 7:6 = reserved. forced by hardware to 0. bit 5 = reserved. bit 4 = irwdis : external interrupt source. this bit is set and cleared by software. it selects the source of the interrupt assigned to the external interrupt channel. refer to the interrupt chapter. 0: the interrupt request from the ir preprocessor is forwarded to the cpu 1: the interrupt from the external interrupt pin is forwarded to the cpu bit 3 = flsel : spike filter pulse width selection this bit is set and cleared by software. it selects the spike filter width. 0: filter pulses narrower than 2s 1: filter pulses narrower than 160s bits 2:1 = posed , neged edge selection for the duration measurement bit 0 = reserved. 70 ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir 0 70 0 0 - irwdis flsel posed neged - neged posed count latch at ... 11 positive or negative transition of ir or when count reaches 255 10 negative transition of ir or when count reaches 255 01 positive transition of ir or when count reaches 255 0 0 only when count reaches 255
123/148 ST92186B - voltage synthesis tuning converter (vs) 7.6 voltage synthesis tuning converter (vs) 7.6.1 description the on-chip voltage synthesis (vs) converter al- lows the generation of a tuning reference voltage in a tv set application. the peripheral is com- posed of a 14-bit counter that allows the conver- sion of the digital content in a tuning voltage, avail- able at the vs output pin, by using pwm (pulse width modulation) and brm (bit rate modulation) techniques. the 14-bit counter gives 16384 steps which allow a resolution of approximately 2 mv over a tuning voltage of 32 v. this corresponds to a tuning resolution of about 40 khz per step in uhf band (the actual value will depend on the characteristics of the tuner). the tuning word consists of a 14-bit word con- tained in the registers vsdr1 (r254) and vsdr2 (r255) both located in page 59. coarse tuning (pwm) is performed using the sev- en most significant bits. fine tuning (brm) is per- formed using the the seven least significant bits. with all 0s loaded, the output is 0. as the tuning voltage increases from all 0s, the number of puls- es in one period increases to 128 with all pulses being the same width. for values larger than 128, the pwm takes over and the number of pulses in one period remains constant at 128, but the width changes. at the other end of the scale, when al- most all 1s are loaded, the pulses will start to link together and the number of pulses will decrease. when all 1s are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). 7.6.2 output waveforms included inside the vs are the register latches, a reference counter, pwm and brm control circuit- ry. the clock for the 14-bit reference counter is de- rived from the main system clock (referred to as intclk) after a division by 4. for example, using an internal 12 mhz on-chip clock (see timing & clock controller chapter) leads to a 3 mhz input for the vs counter. from the point of view of the circuit, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. from the application and software point of view, the 14 bits can be considered as one binary number. as already mentioned the coarse tuning consists of a pwm signal with 128 steps: we can consider the fine tuning to cover 128 coarse tuning cycles. the vs tuning converter is implemented with 2 separate outputs (vso1 and vso2) that can drive 2 separate alternate function outputs of 2 stand- ard i/o port bits. a control bit allows you to choose which output is activated (only one output can be activated at a time). note: on sdip32, only vso2 is available. when a vs output is not selected because the vs is disabled or because the second output is select- ed, it stays at a logical one level, allowing you to use the corresponding i/o port bit either as a nor- mal i/o port bit or for a possible second alternate function output. a second control bit allows the vs function to be started (or stopped) by software.
124/148 ST92186B - voltage synthesis tuning converter (vs) voltage synthesis (contd) pwm generation the counter increments continuously, clocked at intclk divided by 4. whenever the 7 least signif- icant bits of the counter overflow, the vs output is set. the state of the pwm counter is continuously compared to the value programmed in the 7 most significant bits of the tuning word. when a match occurs, the output is reset thus generating the pwm output signal on the vs pin. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. figure 59. typical pwm output filter figure 60. pwm generation c ext output voltage r ext pwm out 1k counter 127 7-bit pwm value overflow overflow overflow 000 t pwm output t intclk/4 x 128
125/148 ST92186B - voltage synthesis tuning converter (vs) voltage synthesis (contd) figure 61. pwm simplified voltage output after filtering (2 examples) v dd 0v 0v dd v v ripple (mv) v outavg "charge" "discharge" "charge" "discharge" 0v v v 0v outavg v (mv) ripple v vr01956 "charge" "discharge" "charge" "discharge" pwmout dd dd pwmout output voltage output voltage
126/148 ST92186B - voltage synthesis tuning converter (vs) voltage synthesis (contd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of fine-tuning the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t intclk / 4) are added to the beginning of the original pwm pulse and thus cause the pwm high time to be ex- tended by this time with a corresponding reduction in the low time. the pwm intervals which are add- ed to are specified in the lower 7 bits of the tuning word and are encoded as shown in the following table. table 27. 7-bit brm pulse addition positions the brm values shown may be combined togeth- er to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. figure 62. simplified filtered voltage output schematic with brm added fine tuning no. of pulses added at the following cycles 0000001 64 0000010 32, 96 0000100 16, 48, 80, 112 0001000 8, 24,... 104, 120 0010000 4, 12,... 116, 124 0100000 2, 6,... 122, 126 1000000 1, 3,... 125, 127 v dd pwmout 0v v dd output voltage 0v brm = 1 brm = 0 t intclk /4 brm extended pulse == =
127/148 ST92186B - voltage synthesis tuning converter (vs) voltage synthesis (contd) 7.6.3 register description vs data and control register 1 (vsdr1) r254 - read/write register page: 59 reset value: 0000 0000 (00h) bit 7 = vse : vs enable bit. 0: vs tuning converter disabled (i.e. the clock is not forwarded to the vs counter and the 2 out- puts are set to 1 (idle state) 1: vs tuning converter enabled. bit 6 = vswp : vs output select this bit controls which vs output is enabled to out- put the vs signal. 0: vso1 output selected 1: vso2 output selected note: this bit must be set to 1 on sdip32. bits 5:0 = vd[13:8] tuning word bits. these bits are the 6 most significant bits of the tuning word forming the pwm selection. the vd13 bit is the msb. vs data and control register 2 (vsdr2) r255 - read/write register page: 59 reset value: 0000 0000 (00h) bits 7:0 = vd[7:0] tuning word bits. these bits are the 8 least significant data bits of the vs tuning word. all bits are accessible. bits vd6 - vd0 form the brm pulse selection. vd7 is the lsb of the 7 bits forming the pwm selection. 76543210 vse vswp vd13 vd12 vd11 vd10 vd9 vd8 70 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0
128/148 ST92186B - pwm generator 7.7 pwm generator 7.7.1 introduction the pwm (pulse width modulated) signal genera- tor allows the digital generation of up to 6 (sdip42) or 4 (sdip32) analog outputs when used with an external filtering network. the unit is based around an 8-bit counter which is driven by a programmable 4-bit prescaler, with an input clock signal equal to the internal clock intclk divided by 2. for example, with a 12 mhz internal clock, using the full 8-bit resolution, a fre- quency range from 1465 hz up to 23437 hz can be achieved. higher frequencies, with lower resolution, can be achieved by using the autoclear register. as an ex- ample, with a 12 mhz internal clock, a maximum pwm repetition rate of 93750 hz can be reached with 6-bit resolution. figure 63. pwm block diagram. autoclear compare 7 compare 6 compare 3 compare 2 compare 1 compare 0 vr01765 pwm7 pwm0 8 bit counter 4 bit presc. control logic intclk/2 output logic st9 register bus pwm6 pwm3 1) pwm2 1) pwm1 note 1 : available on sdip42 only
129/148 ST92186B - pwm generator pwm generator (contd) up to 6 (sdip42) or 4 (sdip32) pwm outputs can be selected as alternate functions of an i/o port. each output bit is independently controlled by a separate compare register. when the value pro- grammed into the compare register and the counter value are equal, the corresponding output bit is set. the output bit is reset by a counter clear (by overflow or autoclear), generating the variable pwm signal. each output bit can also be complemented or dis- abled under software control. 7.7.2 register mapping the registers of the pwm generator are mapped in page 59. note 1 : available on sdip42 only figure 64. pwm action when compare register = 0 (no complement) figure 65. pwm action when compare register = 3 (no complement) register address register function r240 cm0 ch. 0 compare register r241 cm1 ch. 1 compare register r242 cm2 ch. 2 compare register 1) r243 cm3 ch. 3 compare register 1) r244 reserved r245 reserved r246 cm6 ch. 6 compare register r247 cm7 ch. 7 compare register r248 acr autoclear register r249 crr counter read register r250 pctlr prescaler/ reload reg. r251 ocplr output complement reg. r252 oer output enable register r253- r255 reserved vr0a1814 pwm clock pwm output counter=autoclear value counter=0 counter=1 vr001814 pwm clock pwm output counter=autoclear value counter=0 counter=3
130/148 ST92186B - pwm generator pwm generator (contd) 7.7.2.1 register description compare register 0 (cm0) r240 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 0. when the programmed content is equal to the counter content, a set operation is performed on pwm output 0 (if the output has not been com- plemented or disabled). bits 7:0 = cm0.[7:0] : pwm compare value chan- nel 0. compare register 1 (cm1) r241 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 1. compare register 2 (cm2) (sdip42 only) r242 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 2. compare register 3 (cm3) (sdip42 only) r243 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 3. compare register 6 (cm6) r246 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 6. compare register 7 (cm7) r247 - read/write register page: 59 reset value: 0000 0000 (00h) this is the compare register controlling pwm out- put 7. 70 cm0.7 cm0.6 cm0.5 cm0.4 cm0.3 cm0.2 cm0.1 cm0.0 70 cm1.7 cm1.6 cm1.5 cm1.4 cm1.3 cm1.2 cm1.1 cm1.0 70 cm2.7 cm2.6 cm2.5 cm2.4 cm2.3 cm2.2 cm2.1 cm2.0 70 cm3.7 cm3.6 cm3.5 cm3.4 cm3.3 cm3.2 cm3.1 cm3.0 70 cm6.7 cm6.6 cm6.5 cm6.4 cm6.3 cm6.2 cm6.1 cm6.0 70 cm7.7 cm7.6 cm7.5 cm7.4 cm7.3 cm7.2 cm7.1 cm7.0
131/148 ST92186B - pwm generator pwm generator (contd) autoclear register (acr) r248 - read/write register page: 59 reset value: 1111 1111 (ffh) this register behaves exactly as a 9th compare register, but its effect is to clear the crr counter register, so causing the desired pwm repetition rate. the reset condition generates the free running mode. so, ffh means count by 256. bits 7:0 = ac[7:0] : autoclear count value. when 00 is written to the compare register, if the acr register = ffh, the pwm output bit is always set except for the last clock count (255 set and 1 reset; the converse when the output is comple- mented). if the acr content is less than ffh, the pwm output bit is set for a number of clock counts equal to that content (see figure 2). writing the compare register constant equal to the acr register value causes the output bit to be al- ways reset (or set if complemented). example: if 03h is written to the compare regis- ter, the output bit is reset when the crr counter reaches the acr register value and set when it reaches the compare register value (after 4 clock counts, see figure 65 ). the action will be reversed if the output is complemented. the pwm mark/ space ratio will remain constant until changed by software writing a new value in the acr register. counter register (crr) r249 - read only register page: 59 reset value: 0000 0000 (00h) this read-only register returns the current counter value when read. the 8 bit counter is initialized to 00h at reset, and is a free running up counter. bits 7:0 = cr[7:0] : current counter value. prescaler and control register (pctl) r250 - read/write register page: 59 reset value: 0000 1100 (0ch) bits 7:4 = pr[3:0] pwm prescaler value . these bits hold the prescaler preset value. this is reloaded into the 4-bit prescaler whenever the prescaler (down counter) reaches the value 0, so determining the 8-bit counter count frequency. the value 0 corresponds to the maximum counter frequency which is intclk/2. the value fh corre- sponds to the maximum frequency divided by 16 (intclk/32). the reset condition initializes the prescaler to the maximum counter frequency. bits 3:2 = reserved. forced by hardware to 1 bit 1 = clr : counter clear. this bit when set, allows both to clear the counter, and to reload the prescaler. the effect is also to clear the pwm output. it returns 0 if read. bit 0 = ce : counter enable. this bit enables the counter and the prescaler when set to 1. it stops both when reset without affecting their current value, allowing the count to be suspended and then restarted by software on fly. 70 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 70 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 70 pr3 pr2 pr1 pr0 1 1 clr ce pr[3:0] divider factor frequency 0 1 intclk/2 (max.) 1 2 intclk/4 2 3 intclk/6 .. .. .. fh 16 intclk/32 (min.)
132/148 ST92186B - pwm generator pwm generator (contd) output complement register (ocpl) r251- read/write register page 59 reset value: 0000 0000 (00h) this register allows the pwm output level to be complemented on an individual bit basis. in default mode (reset configuration), each com- parison true between a compare register and the counter has the effect of setting the corresponding output. at counter clear (either by autoclear comparison true, software clear or overflow when in free run- ning mode), all the outputs are cleared. by setting each individual bit (ocpl.x) in this reg- ister, the logic value of the corresponding output will be inverted (i.e. reset on comparison true and set on counter clear). example: when set to 1, the ocpl.1 bit comple- ments the pwm output 1. bit 7 = ocpl.7 : complement pwm output 7. bit 6 = ocpl.6 : complement pwm output 6. bits 5:4 = reserved. must be kept in reset state. bit 3 = ocpl.3 1) : complement pwm output 3. bit 2 = ocpl.2 1) : complement pwm output 2. bit 1 = ocpl.1 : complement pwm output 1. bit 0 = ocpl.0 : complement pwm output 0. note 1 : available on sdip42 only. on sdip32, these bits are reserved and must be kept reset. output enable register (oer) r252 - read/write register page: 59 reset value: 0000 0000 (00h) these bits are set and cleared by software. 0: force the corresponding pwm output to logic level 1. this allows the port pins to be used for normal i/o functions or other alternate functions (if available). 1: enable the corresponding pwm output. example: writing 03h into the oe register will en- able only pwm outputs 0 and 1, while outputs 2, 3, 4, 5, 6 and 7 will be forced to logic level 1. bit 7 = oe.7 : output enable pwm output 7. bit 6 = oe.6 : output enable pwm output 6. bits 5:4 = reserved. must be kept in reset state. bit 3 = oe.3 1) : output enable pwm output 3. bit 2 = oe.2 1) : output enable pwm output 2. bit 1 = oe.1 : output enable pwm output 1. bit 0 = oe.0 : output enable pwm output 0. note 1 : available on sdip42 only. on sdip32, these bits are reserved and must be kept reset. 70 ocpl.7 ocpl.6 - - ocpl.3 ocpl.2 ocpl.1ocpl.0 70 oe.7 oe.6 - - oe.3 oe.2 oe.1 oe.0
133/148 ST92186B - a/d converter (a/d) 7.8 a/d converter (a/d) 7.8.1 introduction the 8-bit analog to digital converter uses a fully differential analog configuration for the best noise immunity and precision performance. the analog voltage references of the converter are connected to the internal av dd & av ss analog supply pins of the chip if they are available, otherwise to the ordi- nary v dd and v ss supply pins of the chip. the guaranteed accuracy depends on the device (see electrical characteristics). a fast sample/hold al- lows quick signal sampling for minimum warping effect and conversion error. 7.8.2 main features n 8-bit resolution a/d converter n single conversion time (including sampling time): C 138 internal system clock periods in slow mode (~5.6 s @25mhz internal system clock); C 78 intclk periods in fast mode (~6.5 s @ 12mhz internal system clock) n sample/hold: tsample= C 84 intclk periods in slow mode (~3.4 s @25mhz internal system clock) C 48 intclk periods in fast mode (~4 s @12mhz internal system clock) n up to 5 (sdip42) or 3 (sdip32) analog inputs n single/continuous conversion mode n external source trigger (alternate synchronization) n power down mode (zero power consumption) n 1 control logic register n 1 data register 7.8.3 general description depending on device, up to 5 (sdip42) or 3 (sdip32) analog inputs can be selected by soft- ware. different conversion modes are provided: single, continuous, or triggered. the continuous mode performs a continuous conversion flow of the se- lected channel, while in the single mode the se- lected channel is converted once and then the log- ic waits for a new hardware or software restart. a data register (addtr) is available, mapped in page 62, allowing data storage (in single or contin- uous mode). the start conversion event can be managed ei- ther: C by software, writing the start/stop bit of the control logic register C or by hardware using an external signal on the extrg triggered input (negative edge sensitive) connected as an alternate function to an i/o port bit. figure 66. a/d converter block diagram n st9 bus successive approximation register analog mux data register control logic s/h ain1 ainx ain0 extrg
134/148 ST92186B - a/d converter (a/d) a/d converter (contd) the conversion technique used is successive ap- proximation, with ac coupled analog fully differen- tial comparators blocks plus a sample and hold logic and a reference generator. the internal reference (dac) is based on the use of a binary-ratioed capacitor array. this technique allows the specified monotonicity (using the same ratioed capacitors as sampling capacitor). a pow- er down programmable bit sets the a/d converter analog section to a zero consumption idle status. 7.8.3.1 operating modes the two main operating modes, single and contin- uous, can be selected by writing 0 (reset value) or 1 into the cont bit of the control logic register. single mode in single mode (cont=0 in adclr) the str bit is forced to '0' after the end of channel i-th conver- sion; then the a/d waits for a new start event. this mode is useful when a set of signals must be sam- pled at a fixed frequency imposed by a timer unit or an external generator (through the alternate synchronization feature). a simple software rou- tine monitoring the str bit can be used to save the current value before a new conversion ends (so to create a signal samples table within the in- ternal memory or the register file). furthermore, if the r242.0 bit (register ad-int, bit 0) is set, at the end of conversion, a negative edge on the con- nected external interrupt channel (see interrupts chapter) is generated to allow the reading of the converted data by means of an interrupt routine. continuous mode in continuous mode (cont=1 in adclr) a con- tinuous conversion flow is entered by a start event on the selected channel until the str bit is reset by software. at the end of each conversion, the data register (adcdr) content is updated with the last conver- sion result, while the former value is lost. when the conversion flow is stopped, an interrupt request is generated with the same modality previously de- scribed. 7.8.3.2 alternate synchronization this feature is available in both single/continuous modes. the negative edge of external extrg sig- nal can be used to synchronize the conversion start with a trigger pulse. this event can be ena- bled or masked by programming the trg bit in the adclr register. the effect of alternate synchronization is to set the str bit, which is cleared by hardware at the end of each conversion in single mode. in continuous mode any trigger pulse following the first one will be ignored. the synchronization source must pro- vide a pulse (1.5 internal system clock, 125ns @ 12 mhz internal clock) of minimum width, and a period greater (in single mode) than the conver- sion time (~6.5us @ 12 mhz internal clock). if a trigger occurs when the str bit is still '1' (conver- sions still in progress), it is ignored (see electrical characteristics). warning : if the extrg signal is already active when trg bit is set, the conversion starts immedi- ately. 7.8.3.3 power-up operations before enabling any a/d operation mode, set the pow bit of the adclr register at least 60 s be- fore the first conversion starts to enable the bias- ing circuits inside the analog section of the con- verter. clearing the pow bit is useful when the a/d is not used so reducing the total chip power consumption. this state is also the reset configu- ration and it is forced by hardware when the core is in halt state (after a halt instruction execution).
135/148 ST92186B - a/d converter (a/d) a/d converter (contd) 7.8.4 register description a/d control logic register (adclr) r241 - read/write register page: 62 reset value: 0000 0000 (00h) this 8-bit register manages the a/d logic opera- tions. any write operation to it will cause the cur- rent conversion to be aborted and the logic to be re-initialized to the starting configuration. bits 7:5 = c[2:0] : channel address. these bits are set and cleared by software. they select channel i conversion as follows: note 1 : available on sdip42 only bit 4 = fs : fast/slow . this bit is set and cleared by software. 0: fast mode. single conversion time: 78 x intclk (5.75s at intclk = 12 mhz) 1: slow mode. single conversion time: 138 x intclk (11.5s at intclk = 12 mhz) note : fast conversion mode is only allowed for in- ternal speeds which do not exceed 12 mhz. bit 3 = trg : external trigger enable . this bit is set and cleared by software. 0: external trigger disabled. 1: a negative (falling) edge on the extrg pin writes a 1 into the str bit, enabling start of conversion. bit 2 = pow : power enable . this bit is set and cleared by software. 0: disables all power consuming logic. 1: enables the a/d logic and analog circuitry. bit 1 = cont : continuous/single mode select . this bit it set and cleared by software. 0: single mode: after the current conversion ends, the str bit is reset by hardware and the con- verter logic is put in a wait status. to start anoth- er conversion, the str bit has to be set by soft- ware or hardware. 1: select continuous mode, a continuous flow of a/d conversions on the selected channel, start- ing when the str bit is set. bit 0 = str : start/stop . this bit is set and cleared by software. it is also set by hardware when the a/d is synchronized with an external trigger. 0: stop conversion on channel i. an interrupt is generated if the str was previously set and the ad-int bit is set. 1: start conversion on channel i warning: when accessing this register, it is rec- ommended to keep the related a/d interrupt chan- nel masked or disabled to avoid spurious interrupt requests. a/d channel i data register (addtr) r240 - read/write register page: 62 reset value: undefined the result of the conversion of the selected chan- nel is stored in the 8-bit addtr, which is reloaded with a new value every time a conversion ends. bit 7:0 = r[7:0] : channel i conversion result . 70 c2 c1 c0 fs trg pow cont str c2 c1 c0 channel enabled 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 channel 0 channel 1 1) channel 2 1) channel 3 channel 4 reserved reserved reserved 70 r.7 r.6 r.5 r.4 r.3 r.2 r.1 r.0
136/148 ST92186B - a/d converter (a/d) a/d converter (contd) a/d interrupt register (adint) register page: 62 r242 - read/write reset value: 0000 0001 (01h) bits 7:1 = reserved. bit 0 = ad-int : ad converter interrupt enable . this bit is set and cleared by software. it allows the interrupt source to be switched between the a/d converter and an external interrupt pin (see inter- rupts chapter). 0: a/d interrupt disabled. external pin selected as interrupt source. 1: a/d interrupt enabled. 70 - - - - - - - ad-int
137/148 ST92186B - a/d converter (a/d) 8 electrical characteristics the ST92186B device contains circuitry to protect the inputs against damage due to high static volt- age or electric field. nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages. it is rec- ommended for proper operation that v in and v out be constrained to the range v ss ( v in or v out ) v dd to enhance reliability of operation, it is recom- mended to connect unused inputs to an appropri- ate logic voltage level such as v ss or v dd . all the voltages in the following table, are refer- enced to v ss . absolute maximum ratings * current is limited to |<200 m a| into the pin note : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended p eriods may affect device reliability. recommended operating conditions note 1. 1mhz when a/d is used symbol parameter value unit v dd 1 supply voltage v ss C 0.3 to v ss + 7.0 v v dda analog supply voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.3 to v dd +0.3 v v i input voltage v ss C 0.7 to v dd +0.7 * v v o output voltage v ss C 0.3 to v dd +0.3 v v o output voltage v ss C 0.7 to v dd +0.7 * v t stg storage temperature C 55 to + 150 c i inj pin injection current digital and analog input -5 to +5 ma maximum accumulated pin injection current in the device -50 to +50 ma symbol parameter value unit min. max. t a operating temperature -10 70 c v dd operating supply voltage 4.5 5.5 v v dda analog supply voltage 4.5 5.5 v f osce external oscillator frequency 4.0 mhz f intclk internal clock frequency 0 1 24 mhz
138/148 ST92186B - electrical characteristics dc electrical characteristics (v dd = 5v 10% t a = 0c + 70c, unless otherwise specified) note: all i/o ports are configured in bidirectional weak pull-up mode with no dc load external clock pin (oscin) is driven by square wave external clock. no peripheral working. symbol parameter test conditions value unit min. max. v ih input high level ttl 2 v cmos 0.7 v dd v v il input low level ttl 0.8 v cmos 0.3 v dd v v ihrs reset input high level 0.8 v dd v v ilrs reset input low level 0.3 v dd v v hyrs reset input hysteresis 0.5 v v ih p4[1:0], p3[6:4], p3[1:0], p2[5:4] and p2.0 input high level 0.8 v dd v v il p4[1:0], p3[6:4], p3[1:0], p2[5:4] and p2.0 input low level 0.3 v dd v v ihy p4[1:0], p3[6:4], p3[1:0], p2[5:4] and p2.0 input hysteresis 0.5 v v ihvh hsync/vsync input high level 0.8 v dd v v ilvh hsync/vsync input low level 0.3 v dd v v hyhv hsync/vsync input hysteresis 1.2 v v oh output high level push pull, iload = C 0.8ma v dd -0.8 v v ol output low level push pull or open drain, iload = 1.6ma 0.4 v i lkio i/o pin input leakage current hi-z input, 0v < v in < v dd 1 m a i lkrs reset pin input leakage current 0v < v in < v dd 1 m a i lka/d a/d pin input leakage current alternate function open drain 1 m a i lkos oscin pin input leakage current 0v < v in < v dd 1 m a
139/148 ST92186B - electrical characteristics ac electrical characteristics pin capacitance (v dd = 5v 10%; t a = -10c + 70c, unless otherwise specified) current consumption (v dd = 5v 10%; t a = -10c + 70c, unless otherwise specified) notes: 1. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss . the internal clock prescaler is in divide-by-1 mode. the external clock pin (oscin) is driven by a square wave external clock at 4 mhz. 2. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 28 mhz clock. all peripherals are working. 3. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss . external clock pin (oscin) and reset pins are held low. all peripherals are disabled. 4. all ports are configured in push-pull output mode (output is high). vsync and hsync are tied to v ss . all peripherals are disabled. 5. the cpu is fed by a frequency issued by the on-chip frequency multiplier. the skew corrector frequency multiplier provides a 14mhz clock. osd, a/d, pwm, std timer and wdg timer peripherals are running. symbol parameter conditions value unit typ. max c io pin capacitance digital input/output 810pf symbol parameter conditions value unit typ. max i cc1 run mode current (notes 1, 2) intclk=16mhz 80 100 ma i cc2 run mode current (notes 1, 2) intclk=24mhz 100 120 ma i cc3 run mode current (notes 1, 2) intclk=4mhz 25 30 ma i cc4 run mode current (notes 1, 5) intclk=16mhz 65 78 ma i cca analog current (v dda pin) freq. multipliers , a/d, osd & dacs off. 110 a i ilpr reset mode current (note 3) 10 100 a i halt halt mode current (note 4) 10 100 a
140/148 ST92186B - electrical characteristics ac electrical characteristics (contd) clock timing (v dd = 5v 10% t a = -10c + 70c, unless otherwise specified) external interrupt timing (rising or falling edge mode; v dd = 5v 10%; t a = -10c + 70c, unless otherwise specified) note: the value in the left hand two columns shows the formula used to calculate the minimum or maximum timing from the oscilla tor clock period, prescale value and number of wait cycles inserted. the value in the rignt hand two columns shows the minimum and maximu m for an external clock at 24 mhz divided by 2, prescale value of zero and zero wait status. external interrupt timing symbol parameter conditions value unit min max tpc oscin clock period intern. div. by 2 41.7 ns intern. div. by 1 83.3 ns trc oscin rise time 12 ns tfc oscin fall time 12 ns twcl oscin low width intern. div. by 2 17 ns intern. div. by 1 38 ns twch oscin high width intern. div. by 2 17 ns intern. div. by 1 38 ns n symbol parameter conditions unit oscin divided by 2 min. oscin not divided by 2 min. min max 1 twlr low level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 2 twhr high level minimum pulse width in rising edge mode 2tpc + 12 tpc + 12 95 ns 3 twlf low level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns 4 twhf high level minimum pulse width in falling edge mode 2tpc + 12 tpc + 12 95 ns intn 1 23 4 rising edge detection falling edge detection n = 0-7 va00112
141/148 ST92186B - electrical characteristics ac electrical characteristics (contd) skew corrector timing table (v dd = 5v 10%; t a = -10c + 70c, unless otherwise specified) the osd jitter is measured from leading edge to leading edge of a single character row on consecutive tv lines. the value is an envelope of 100 fields *max. value at all cpu operating frequencies symbol parameter conditions value max unit tjskw jitter on rgb output 28 mhz skew corrector clock frequency <12* ns
142/148 ST92186B - electrical characteristics ac electrical characteristics (contd) osd dac characteristics (v dd = 5v 10%; t a = -10c + 70c, unless otherwise specified) (*) output voltage matching of the r,g and b levels on a single device for each of the 8 levels (**) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in dac mode) (***) phase matching (50% point on both rise & fall time) on r, g, b, fb lines (fb in digital mode) (****) 95% of the signal amplitude is reached within the specified clock period symbol parameter conditions value unit min typ max output impedance fb,r,g,b 100 ohm output voltage fb,r,g,b cload = 20 pf rl=100k code = 111 code = 110 code = 101 code = 100 code = 011 code = 010 code = 001 code = 000 0.976 0.863 0.751 0.638 0.525 0.412 0.300 0.157 1.170 1.034 0.899 0.763 0.627 0.491 0.356 0.220 1.364 1.205 1.046 0.887 0.729 0.570 0.411 0.252 v fb = 1 fb = 0 v relative voltage accuracy (*) 5 % r/g/b to fb 50% point matching fb dac mode (**) 5ns r/g/b to fb 50% point matching fb digital mode (***) 5ns pixel frequency cload = 20 pf 20 (****) mhz. cload = 10 pf 40 (****) mhz.
143/148 ST92186B - electrical characteristics ac electrical characteristics (contd) a/d converter, external trigger timing table ( v dd = 5v +/-10%; t a = 0 to 70c, unless otherwise specified) a/d converter, external trigger timing table a/d converter. analog parameters table ( v dd = 5v +/-10% ; t a = 0 to 70c, unless otherwise specified)) notes: (*) the values are expected at 25 celsius degrees with v dd = 5v (**)'lsbs' , as used here, as a value of v dd /256 (1) @ 24 mhz external clock (2) including sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) dnl error= max {[v(i) -v(i-1)] / lsb-1}inl error= max {[v(i) -v(0)] / lsb-i} absolute accuracy= overall max conversion error n symbol parameter conditions value unit min max 1t low pulse width 1.5 intclk 2t high pulse distance 1.5 intclk 3t ext period/fast mode 79 intclk 4t str start conversion delay 0.5 1.5 intclk parameter value unit note typ (*) min max (**) analog input range v ss v dd v conversion time 138 intclk (1,2) sample time 87.51 intclk (1) power-up time 60 s resolution 8 bits differential non linearity 0.5 0.3 1.5 lsbs (4) integral non linearity 2 lsbs (4) absolute accuracy 2 lsbs (4) input resistance 1.5 kohm (3) hold capacitance 1.92 pf extrg 1 2 st (start conversion bit) 3 4 4 vr001401
144/148 ST92186B - general information 9 general information 9.1 package mechanical data figure 67. 32-pin shrink plastic dual in line package figure 68. 42-pin shrink plastic dual in-line package dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 pdip42s
145/148 ST92186B - general information 9.2 ordering information note: the eprom and otp versions are supported by the st92196a family. figure 69. package device types device rom (kbytes) ram (bytes) ST92186Bx3 24 640 ST92186Bx4 32 device package bk= psdip32 bj= psdip42 ST92186B3 ST92186B4
146/148 ST92186B - general information ST92186B option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. please confirm characteristics of device: device: [ ] ST92186B3 [ ] ST92186B4 24k rom 32k rom package: [ ] psdip32 [ ] psdip42 temperature range: -10c to 70 c osd code: [ ] osd filename _ _ _ _ _ _ _ _ _.osd special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 15 characters (sdip32) or 16 characters (sdip42). authorized characters are letters, digits, '.', '-', '/' and spaces only. quantity forecast: [ _ _ _ _ _ _ _] k units per year for a period of [ _ _ ] years. preferred production start date: [ _ _ _ _ _ _ _] ( yyyy/mm/dd) date . . . . . . . . . . . . . . . . . . . . . . . . . . . . customer signature . . . . . . . . . . . . . . . . . . . . .
147/148 ST92186B - summary of changes 10 summary of changes rev. main changes date 2.2 modification of vih levels in dc electrical characteristics table on page 139 9 march 2001
148/148 ST92186B - summary of changes information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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