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[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 1 - general description AK7601A is a high featur e audio proc essor with audi o codec (3ch adc, 6ch dac) and delay line memory ope rates 5.0v single pow er supply. the a nalog inputs support quas i-differential/single-end ed with 4:1 ster eo selector in front of 2-channel ed 97 db adc, and monaural a dc for guida nce sound. the digital inputs supports 3:1 input selecto r with asyn chronous sample rate con v erter (sr c ) for digital source such as dvd, blu- ray, digital br oadcas ting, etc. the high per forman ce 6-channel ed dac integrates full-rang e digital volume control and ac hieves 102db with single end outputs. the delay line memory covers 36ms in t o tal. time alignment of 6m or less is possi ble since the delay line memory can store for 18ms data for b o th left and right channels. the AK7601A can achiev e high pe rfo r mance car audio system easily by supportin g two ster eo 7-b and eq and time alignment functions. features 1. 2ch 24bit adc - quasi-differential/sin gle-ended i nputs w i th 4 : 1 stereo selector - s/(n+d): 9 0 db - dr, s/n: 97db - digital hpf for cancelling dc offset 2. 1ch 24bit adc for monaural audio input - single-end e d input - s/(n+d): 9 0 db - dr, s/n: 97db - digital hpf for cancelling dc offset 3. 6ch 24bit dac - single-end e d output - s/(n+d): 9 0 db - dr, s/n: 102db 4. asy nchronous sample rate co nverter(s r c) for digital input - 3:1 input selector - input sampling rate: 8khz 96khz - data format: msb justified, lsb ju stified, i 2 s c ompatible ( s lave mode onl y ) 5. digital processing - t w o stereo 7band eq (second-order iir-filter setting is also available) - digital de-emphasis filter - adjustable dela y mem ory control maximum d e la y time: lch 18ms, rch 18ms (for 1 stereo input / 3 stereo outputs) dela y resol u tion: 1/fs - x?over filter: front l, fro nt r: 2 nd order iir filter x 3 stages rear l, rear r, sub w o o f er l, sub w oofer r: 2 nd order iir filter x 2 stage s - spectrum anal y z er : variable 4-ban d - soft mute - zero detect function 6. smooth volume 7. master clock - master mode: 22.579 2 m hz 8. p interf ace: i 2 c bus (ver 1.0, 400khz mode) high feature digital audio processor with src a k7601a http://
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 2 - 9. po w e r suppl y - analog: avdd = 4.5 5.5v - digital: dvdd = 3.0 5. 5 v 10. po w e r consumption: 80ma 1 1 . t a = - 4 0 85c 12. package: 48lqfp(0 . 5mm pitch) block diagram 2ch adc 14band eq ( 2 nd iir x 14 ) delay control ao ut 1l ao ut 1r ao ut 2l ao ut 2r ao ut 3l ao ut 3r scl xti xto pdn dvdd avdd vss1 v s s2 vs s 4 dzf 4band spectrum analyser filter (2 nd iir x 1 st iir) x 4 ibick1 1 ibick2 monoin 2ch dac d-vol d-vol d-vol ibick3 ilrck1 1 ilrck2 ilrck3 sdti1 1 sdti2 sdti3 ai n l 4 ain l 1 g ndi n1 ain r1 ain l 2 g ndi n2 ain r4 ain r2 ain l 3 ainr 3 sda d-vol 1ch adc 2ch src i 2 c interface x?tal oscillator vcom vrefh ref18 vss3 mcko muten 2ch dac 2ch dac sdto1/sdto3 sdto2/sdti4 obick olrck clkmode 2 nd iir x 3 x2ch 2 nd iir x 2 x2ch 2 nd iir x 2 x2ch switch sw i t ch function fi gu re 1. b l oc k di ag ram
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 3 - ordering guide a k 7 6 0 1 a v q - 4 0 +8 5 c 48 pi n l qfp (0 . 5 m m pi t c h) a kd7 601 a ev alu a tion bo ar d fo r ak7 601a pin lay o ut vss3 xto 38 c lk m o d e 36 39 r e f1 8 40 v s s 4 41 monoin 42 a i n l 1 43 g n d i n 1 44 a i n r 1 45 ainl2 46 g n d i n 2 47 a i n r 2 48 xti 35 ilrck1 34 ilrck2 33 ilrck3 32 ibick1 31 ibick2 30 ibick3 29 sdti1 28 sdti2 27 sdti3 26 ainl3 1 ainr3 2 ainl4 3 ainr4 4 vcom 5 avdd 6 vss1 7 8 aout1l 9 aout1r 10 aout2l 11 23 22 21 20 19 18 17 16 15 14 13 sd t o 1 / sd t o 3 sd t o 2 / sd t i 4 o l rck ob i c k mc k o sc l sd a pd n dz f a out3r a out3l ak7 6 0 1 a vq t o p v i ew aout2r 12 24 vss2 dvdd 25 mu t e n 37 vrefh fi gu re 2. pi n l a y out
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 4 - pin function no . pi n nam e i/ o fu nct i on 1 a i n l 3 i lch single-ended input 3 pin 2 ai nr 3 i rch single-ended input 3 pin 3 a i n l 4 i lch single-ended input 4 pin 4 ai nr 4 i rch single-ended input 4 pin 5 vcom o vcom pin 6 av d d - analog power supply pin 4.5~5.5v 7 v s s1 - ground pin, 0v 8 vrefh - positive voltage reference input pin, avdd 9 ao ut 1l o dac1 lch output pin. 10 ao ut 1r o dac1 rch output pin 11 ao ut 2l o dac2 lch output pin 12 ao ut 2r o dac2 rch output pin 13 ao ut 3l o dac3 lch output pin 14 ao ut 3r o dac3 rch output pin 15 dzf o zero detect pin 16 pd n i po wer - d o wn & reset pin w h en ?l?, t h e a k 76 01a is po w e r e d - d o wn an d th e con t ro l reg i sters are reset to d e fau lt state. 17 sd a i/ o control data input pin : sda (i 2 c bus) ( note 2 ) 18 sc l i control data clock pin : scl (i 2 c bus) 19 m c ko o master clock output pin 20 ob ic k o output audio serial data clock pin 21 olr c k o output channel clock pin 22 sdt o 2/sdt i 4 i /o a u d io ser ial data i npu t 4 / ou tpu t 2 pin ( note 3 ) 23 sdt o 1/sdt o 3 o audio serial data output 1/3 pin 2 4 v s s2 - ground pin, 0v 25 dv d d - digital power supply 1 pin, 3.0 ~5.5v 2 6 sd ti 3 i audio serial data input 1 pin 2 7 sd ti 2 i audio serial data input 2 pin 2 8 sd ti 1 i audio serial data input 3 pin 29 ib ic k 3 i input audio serial data clock pin 3 pin 30 ib ic k 2 i input audio serial data clock pin 2 pin 31 ib ic k 1 i input audio serial data clock pin 1 pin 32 ilr c k 3 i input channel clock 3 pin 33 ilr c k 2 i input channel clock 2 pin 34 ilr c k 1 i input channel clock 1 pin 35 xti i x?tal input pin 36 xt o o x?tal output pin 37 m ute n i a k 76 01a m u te pin l: mute h: norm al operation 38 vss 3 (d vs s) - ground pin 0v 39 c l km o de i c l k m ode pi n (x ?t al / e xt ern a l c l k sel ect pi n ) l: x?tal m o d e h exter n al cl k in p u t m o de the pdn pin m u st set ?h? ?l? ? h ? bef o re cha n gi n g t h i s pi n ?l? ?h? . 40 r e f1 8 o internal regulator 1.8v output pin 4 1 v s s4 - ground pin, 0v 42 m on oi n i monaural adc input pin 43 ai nl 1 i lch differential input 1 pin 4 4 g ndi n1 i input ground 1 pin 45 ai nr 1 i rch differential input 1 pin 46 ai nl 2 i lch differential input 2 pin 4 7 g ndi n2 i input ground 2 pin 48 ai nr 2 i rch differential input 2 pin
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 5 - not e 1. al l di g i t a l i nput pi ns m u st not be al l o we d t o fl oat . not e 2. i n put p i n w he n po we r e d- d ow n. not e 3. o utp ut pi n w he n po w e red -d o wn handling of unused pin the u nuse d i/ o pi ns sh o u l d be pr ocesse d a p p r op ri at el y as bel o w c l assi fi cat i on pi n nam e set t i ng ai nl 1, g nd i n1 , ai nr1 , a inl 2, g n di n 2, a inr 2, ai nl 3, a inr 3, a inl 4, a i nr4 , m o n oi n ope n anal og ao ut 1l, a o u t 1 r, ao ut 2l, a o u t2r , ao ut 3l, ao ut 3r ope n ibick 1 , ib i c k2 , ibick 3 , ilrc k1 , ilrc k2 , ilrck3, sdti1, sdti2, sdti3, sdti4 connect to vss2 dig ital obic k, olr c k, m c ko , s d t o 1/s d t o 3 , s d t o 2 , xt o ope n
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 6 - absolute maxmum rating (vss 1=vss 2 = v ss 3= vss 4 = 0 v; no te 4 ) par a meter sym bol min max unit po wer s u p p lies anal og digital a vdd d vdd -0 .3 -0 .3 6. 0 6. 0 v v in p u t cu rre nt ( a ny pi ns e x ce p t fo r s u pplies) ii n - 10 ma anal og i n put vol t a ge ( no te 5 ) v i na - 0. 3 a vdd +0. 3 v dig ital in pu t vo ltag e ( note 6 ) v ind - 0. 3 d vdd +0. 3 v am bi ent tem p erat ure ( p owe r appl i e d ) ta -4 0 85 c st ora g e tem p erat ure tst g -6 5 15 0 c no te 4 . all indicated vo ltag e s are with r e sp ect to gr oun d vss1, v s s2 , vss3 and v s s4 m u st be conne cted to t h e anal og g r ou nd p lan e. not e 5. a n al o g i n p u t pi ns are ai nl 1- 4, a in r 1- 4, g nd i n 1 - 2 a n d m o n oi n. no te 6 . di g ital in pu t p i n s are sdti1-4 , ilr c k1 -3 , ibick 1 - 3 , m u te n, sd a, a n d scl . war n ing: op erating at o r beyo nd th ese limits m a y resu l t in p e rm an en t d a m a g e to th e d e v i ce. norm a l o p e ration is no t g u a ran t eed at t h ese critical co n d ition s . recommended operating co nditions (vss 1=vss 2 = v ss 3= vss 4 = 0 v; no te 4 ) par a meter sym bol min typ max unit power su pp lies ( note 7 ) anal og dig ital a vdd d vdd 4. 5 3. 0 5. 0 5. 0 5. 5 a vdd v v no te 7 . the power u p sequ ence b e t w ee n avdd an d dvdd is no t critical bu t t h e pdn p i n m u st b e ?l? u n til all power sup p lies are on, th en pu t th e pdn p in to ?h?. a ll pow er sup p lies of t h e ak 760 1a ar e mu st b e on . do n o t tu rn any p o we r s u p p l y of f (m eans t h e sam e vol t a ge as gr ou n d or fl oat i n g) i n de p e nde nt l y . whe n u s i n g t h e ak 76 0 1 a w ith i 2 c bu s, t h e p o w e r su pp l y o f th e ak 760 1a m u st no t b e turn ed of f un less th e pow er su pp lies o f t h e sur r o u n d i n g de vi ce are t u r n e d o ff. * akm assu mes no resp on si b ility fo r t h e u s ag e b e yon d th e con d ition s i n t h is d a tash eet.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 7 - analog c hara cter istics (ta=2 5 c; a v dd= 5. 0 v , d v d d =5 .0 v; vs s1= v ss 2= vs s3= v ss 4= 0v; vref h= av dd , fs=4 4. 1 k h z; sig n al fre que ncy = 1 k h z; 2 4 b i t dat a ; m easurem ent fre q uency = 20 hz 20khz at; unless ot herwi se speci fied) parameter min typ max unit adc analog inpu t characteristics (pseud o differential inputs) reso lu tion 2 4 bits -1 db fs 83 90 db s/(n+ d ) b w =2 0 k hz - 60d bfs 3 5 dr (- 60 db f s wi t h a - wei g ht ed) 90 97 db s/n (a -wei ghte d ) 90 97 db int e rc ha nnel is ol at i on 90 11 0 db int e rc ha nnel g a i n m i sm at ch 0 0. 5 db gain drift 2 0 - ppm / c input voltage ain=0.65xvrefh 3.09 3.25 3.41 vpp in p u t r e si st an ce ai nl 1, a inr 1, a inl 2, a i nr 2 22 45 k g ndi n1 , gnd in2 2 2 9 0 k power s u pply rejection ( no te 8 ) 55 db com m on mode rejection ra tio (cmrr) ( no te 9 ) 40 db adc analog input characteristics (single-ended inputs) reso lu tion 2 4 bits -1 db fs 83 90 db s/(n+ d ) b w =2 0 k hz - 60d bfs 3 5 dr (- 60 db f s wi t h a - wei g ht ed) 90 97 db s/n (a -wei ghte d ) 90 97 db int e rc ha nnel is ol at i on 90 11 0 db int e rc ha nnel g a i n m i sm at ch 0 0. 5 db gain drift 2 0 - ppm / c input voltage ain=0.65xvrefh 3.09 3.25 3.41 vpp in p u t r e si st an ce (a in l3 , a i nr 3, a i nl 4, ai nr 4 ) 22 45 k power s u pply rejection ( no te 8 ) 55 db adc analog input characteristics (monaural input) reso lu tion 2 4 bits -1 db fs 83 90 db s/(n+ d ) b w =2 0 k hz - 60d bfs 3 5 dr (- 60 db f s wi t h a - wei g ht ed) 90 97 db s/n (a -wei ghte d ) 90 97 db gain drift 2 0 - ppm / c input voltage ain=0.65xvrefh 3.09 3.25 3.41 vpp in p u t r e si st an ce 22 45 k power s u pply rejection ( no te 8 ) 55 db dac analog output characteristics (single outputs) reso lu tion 2 4 bits 0db fs 83 90 db s/(n+ d ) b w =2 0 k hz - 60d bfs 3 9 dr (- 60 db f s wi t h a - wei g ht ed) 93 10 2 db s/n (a -wei ghte d ) 93 102 db int e rc ha nnel is ol at i on 90 11 0 db interchannel gain mismatch 0 0.5 db gain drift 20 - ppm/ c output voltage aout=0.65xvrefh 3.09 3.25 3.41 vpp loa d resistanc e ( a c l o ad) 5 k loa d c a paci t a nce 30 pf power s u pply rejection ( no te 8 ) 55 db
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 8 - ad c t o da c ch arac teristic s (sin gle out p uts ) reso lu tion 2 4 bits -1 db fs 80 87 db s/(n+ d ) b w =2 0 k hz - 60d bfs 3 4 dr (- 60 db f s wi t h a - wei g ht ed) 87 96 db s/n (a -wei ghte d ) 87 96 db not e 8. psr i s appl i e d t o a v dd an d d vd d wi t h 1k hz, 50m vp p. th is is th e v a lu e o f co nvo lu ted sinu so id al v o ltag e of 1k hz a n d 50m vp p w h en t h e vr ef h pi n i s hel d + 5 v. not e 9. t h i s i s a val u e w h e n t h e fre que ncy r a nge i s 20 hz ~ 20khz a ssum i ng an exte rn al capacitor is 10uf30% a n d g dni n1 /2 amp litu d e is 100m v p p . src char acteristics (ta=2 5 c; a v dd= 5. 0 v , d v d d =5 .0 v; vs s1= v ss 2= vs s3= v ss 4= 0v; vref h= av dd , fs=4 4. 1 k h z; sig n al fre que ncy = 1 k h z; 2 4 b i t dat a ; m easurem ent fre q uency = 20 hz 20khz; unless othe rwise specified) par a meter sym bol min typ max unit src characteristics: reso lu tion 2 4 bits inpu t sam p le rate fsi 8 96 khz out put sam p l e r a t e fso 44 .1 khz thd + n (i npu t = 1kh z, 0d bfs, note 1 0 ) fsi =48 kh z - 130 - 100 d b dy nam i c r a ng e (i n put = 1 k h z, ? 6 0db f s , no te 10 ) f si = 48khz d y n a m i c ran g e (i npu t = 1kh z, - 60d bfs, a - w e igh t ed, note 1 0 ) f si = 48khz 136 140 120 db db ratio b etween inpu t and ou tpu t sam p le rate fso/fsi 4 4 .1 / 9 6 4 4 .1 / 8 - not e 1 0 . m eas ure d by au di o pr ecision syste m two cascade. parameter min typ max unit power s uppli e s pow e r su pp ly cu rr en t norm al operat ion (pdn pin = ?h? ) a vdd d vdd pow e r- dow n mo d e (pdn p in = ?l?) a vdd +dvdd ( note 12 ) 54 11 10 73 15 10 0 ma ma a note 11. powe r s u pply curre nt values are fo r wh en ad c, da c an d s rc a r e in operation. not e 1 2 . wh en t h e ak 7 6 0 1 a i s n o t i n o p erat i on. al l di gi t a l i n p u t pi ns i n cl udi ng cl oc k pi ns a r e hel d t o vss 2 .
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 9 - filter characteris tics (ta= -4 0 +85 c; a vdd =4. 5 5. 5v , dv dd= 3. 0 5. 5v ) parameter symbol min typ max unit adc digital filter (decimation lpf): passba n d ( no te 13 ) 0.1d b ? 0.2d b ? 3.0d b pb 0 - - - 18 .3 21 .1 17 .3 - - khz khz khz stopba nd ( note 13 ) sb 25 .7 - - khz passband ripple pr - - 0.04 db stopband attenuation sa 68 - - db group delay distortion gd - 0 - s gr oup delay ( note 14 ) gd - 16 - 1/fs adc digital filter (hpf): fre que ncy r e s p o n se ( note 1 3 ) ? 3d b ? 0.1d b fr - - 0. 86 5. 9 - - hz hz dac digital filter (lpf): p a s s b a n d ( note 1 3 ) 0.06d b ? 6.0d b pb 0 - - 22 .0 5 20 .0 - khz khz stopba nd ( note 13 ) sb 24 .1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 54 - - db group delay distortion gd - 0 - s gr oup delay ( note 14 ) gd - 20 - 1/fs dac digital filter + analog filter: frequency response ( note 15 ) 20~20khz fr - 0.1 - db not e 1 3 . the p a ssba n d an d st op ba nd f r eq ue nci e s scal e wi t h fs (sy s tem sam p ling rate). f o r exam ple, when fs= 44.1khz, d a c is pb=0 .4 541 2*f s ( @ 0 .0 6d b). note 14. the c a lculated delay tim e induce d by di gital filtering. t h is tim e is from the input of an anal og s i gnal to the settin g o f 24b it d a ta bo th ch ann e ls to th e adc ou tpu t reg i ster for adc . this ti m e is fro m th e set o f 24b it d a ta to th e inp u t reg i sters to th e ou tpu t of an alog si g n a l fo r dac. note 15. the refere nce fre quency of t h ese response s is 1khz. src digital f ilter sym bol min typ max unit passba n d - 0 . 0 1db 0. 98 5 fso /fsi < 5.513 pb 0 0 . 4 583 fsi k h z 0. 65 6 fso /fsi < 0.985 pb 0 0 . 4 167 fsi k h z 0. 49 2 fso /fsi < 0.656 pb 0 0 . 2 177 fsi k h z 0. 45 9 fso /fsi < 0.492 pb 0 0 . 1 948 fsi k h z st op ba nd 0. 98 5 fso /fsi < 5.513 sb 0 . 5 417 fsi k h z 0. 65 6 fso /fsi < 0.985 sb 0 . 5 021 fsi k h z 0. 49 2 fso /fsi < 0.656 sb 0 . 2 813 fsi k h z 0. 45 9 fso /fsi < 0.492 sb 0 . 2 604 fsi k h z passba n d ripple pr 0.01 db st op ba nd at t e nuat i o n 0. 98 5 fs o/ f s i < 5 . 5 1 3 sa 12 1. 2 db 0. 65 6 fs o/ f s i < 0 . 9 8 5 sa 12 1. 4 db 0. 49 2 fs o/ f s i < 0 . 6 5 6 sa 10 0. 2 db 0. 45 9 fs o/ f s i < 0 . 4 9 2 sa 10 3. 3 db g r ou p d e lay (ts=1 / f s ) ( no te 16 ) gd 64 ts not e 1 6 .t hi s d e l a y i s t h e pe ri od f rom t h e ri s i ng e d ge of il r c k, j u st after th e sdti d a ta is in pu t, t o th e risin g edg e of olr c k , just a ft e r t h e s d t o dat a i s out put , whe n t h ere i s n o pha se di ffe re nce bet w ee n i l r c k a n d ol r c k .
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 10 - dc cha ra cteristics (ta=- 4 0 c +85 c; a vdd = 4 . 5 5. 5 v, d v dd= 3. 0 5.5v ) parameter symbol min typ max unit hi g h -le v el in put v o l t a ge (p dn , s d a, s c l, s d ti 1 - 4 , ilrck 1- 3, ib ick 1 - 3 , m u te n, xt i pins ) (clkm o d e p i n) low-lev e l inpu t vo ltag e (p dn , s d a, s c l, s d ti 1 - 4 , ilrck 1- 3, ib ick 1 - 3 , m u te n, xt i pins ) (clkm o d e p i n) vi h vi h vil vil 7 0%dvd d 8 0%dvd d - - - - - - - - 3 0%dvd d 2 0%dvd d v v v v hig h -le v el ou tput voltage (s dto 1 -3 , ol rck, obic k, om cl k, sd a, dz f pins: io ut =- 10 0 a) lo w-le vel ou t put vol t a ge (s dto 1 -3 , ol rck, obic k, om cl k, dz f pi ns: io ut = 10 0 a) (s da pi n: iout= 3m a) vo h vo l vo l d vdd -0 .5 - - - - - - 0. 5 0. 4 v v v input leaka g e current pd n, sd a, s c l, s d ti 1 - 4 , ilrck 1- 3, ib ick 1 - 3 , m u te n, xt i iin - - 10 a
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 11 - switching chara ct eristics (ta=- 4 0 +8 5 c; a vdd =4. 5~5 .5 v ; dv dd=3 . 0 5. 5 v ; c l =2 0p f; un less o t h e rwise sp ecified ) parameter symbol min typ max unit master cloc k timing cry st a l re so n a t o r fre q uency fxt a l - - 22 .5 7 92 - - mh z mcko ou tp ut fre q uency m c ko 1 - 0 bi t = ?1 0? mcko 1-0 bit = ?01? d u ty cycle 512fs ( note 17 ) 256fs ( note 17 ) fm ck fm ck dmc k dmc k - - 40 45 22 .5 7 92 11 .2 8 96 50 50 - - 60 55 mh z mh z % % e x tern al cl oc k fre que ncy pul s e wi dt h l o w pul se wi dt h h i gh fcl k tcl k l tcl kh 22 .3 5 18 18 22 .5 7 92 22 .8 0 mh z ns ns mcko output f r eq ue ncy 51 2 f s duty cycle ( note 1 8 ) fm ck dmc k 22 .3 5 40 22 .5 7 92 50 22 .8 0 60 mh z % input lr ck (ilr ck1-3 ) fre que ncy duty cycle fsi duty 8 48 50 96 52 khz % output lrck (olrc k ) fre que ncy duty cycle fso duty - 44 .1 50 - khz % audi o i nter f ace timing obic k f r eq ue ncy obic k duty obic k ? ? to olrck obic k ? ? t o sdt o 1~3 sdt i 3-4 hol d tim e sdt i 3-4 set u p tim e inpu t p o rt ibick 1 -3 peri od ibick1 -3 p u lse w i dt h l o w p u ls e w i dt h high ilr c k 1- 3 e d ge t o ib ick 1 - 3 ? ? ( no te 19 ) ibick 1 -3 ? ? to ilrc k1-3 edge ( no te 19 ) sdt i1 - 3 hol d tim e from ibi c k1 -3 ? ? sdt i 1-3 set u p tim e to ibick1-3 ? ? fbck d bck tmblr tbsd tsdh tsdl tbck tbckl tbckh tlrb tblr tsdh tsds - - ? 20 ? 20 30 30 1/ 6 4 fs 65 65 30 30 30 30 64 fs 50 - - - - 20 20 hz % ns ns ns ns ns ns ns ns ns ns ns no te 17 . acco rd ing to th e cry s tal o s cillato r valu es in table 2 . n o te 18 . in th e case o f mc ko1-0 b its = ?10? (2 2.579 2 m hz) , t h ese a r e the value s whe n ex tern al clo c k du ty is 50 %. not e 1 9 . b i c k ri si n g e dge m u st not occ u r at t h e sam e t i m e as lr c k e d ge.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 12 - par a meter sym bol min typ max unit contr o l interface timing (i 2 c bus mo de): sc l c l oc k f re que ncy bus f r ee tim e between tra n sm issions st art c o ndi t i o n h o l d ti m e (pr i or t o fi rst cl oc k pul se ) c l ock l o w ti m e c l ock hi g h ti m e setu p tim e fo r rep eated start con d ition sd a hol d ti m e from scl falling ( note 20 ) sda set u p ti m e from scl rising rise tim e of b o th sda a n d s c l lines fall tim e of b o th sda a n d s c l lines setu p tim e fo r stop c o nd ition pu lse wid t h o f sp i k e no ise su ppressed b y in pu t filter cap acitiv e lo ad o n bu s fscl tbu f th d:st a tl o w th i gh ts u:st a th d:d a t ts u:d a t tr tf ts u:st o tsp c b - 1. 3 0. 6 1. 3 0. 6 0. 6 0 0. 1 - - 0. 6 0 - 400 - - - - - - - 0. 3 0. 3 - 50 400 khz s s s s s s s s s s ns pf power-down & rese t timi ng pd n p u lse wi dth ( note 2 1 ) tp d 15 0 ns no te 20 . data m u st b e h e ld lon g enough t o bridg e th e 300ns-tran s itio n time of scl. not e 2 1 . the ak 7 6 0 1 a ca n be reset by b r i ngi ng t h e pd n pi n = ?l? . note 2 2 . i 2 c-bu s is a tr adem a r k of n x p b.v.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 13 - timing diagram fi gu re 3. c l oc k ti m i ng tl r b lr c k 1 - 3 vi h bick1-3 vil vih vil tb l r ts d s sdti1-3 vih vil tsdh figure 4. audio inte rface ti ming (input port) 1/fclk tclkl vih tclkh xti vil 1/fmck 50%dvdd mcko tdmckl tdmckh dmck = tdmck h (or tdmckl) x fmck x 100 1/fbck tdbckl tdbckh bick 50%dvdd 1/fs lrck 50% dv dd tdlrkl tdlrkh dlrk = tdlrk h (o r tdlrkl ) x fs x 100 dbck = tdbckh (or tdbckl) x fs x 100
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 14 - ol r c k obick sdto1-3 tbsd tmblr 50 % d v d d 50 % d v d d 50%dvdd sd t i 4 tsdh tsds vih vil figure 5. audio interf ace ti ming (output port) fi gu re 6. i 2 c b u s m ode ti m i ng fi gu re 7. p o we r do w n & r e s e t tim i ng thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp tpd vil pdn vih
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 15 - operation overvie w s y s t em clock the e x t e r n al clock i n put o r x? t a l i nput i s avai l a bl e f o r mc l k cloc k so urce . ( figure 8 , fi gure 9 ) t h e req u ire d cloc k is 22 .5 7 9 m hz m c lk onl y . in t h e n o rm al operat i o n, i f t h e cl ock i s sto ppe d, cl i c k n o i s e m a y occur w h e n t h e cloc k s u p p l y i s rest art e d. it ca n be pre v e n t e d by e x t e r n al m u t e . olrck m c ko (m hz ) obic k (m hz) 44 .1 k hz 22 .5 7 92 2.8224 tabl e 1. sy st em cl ock e x am pl e clock source the cl ock f o r t h e xti pi n ca n be ge nerat e d b y t w o m e t hod s : 1) ext e r n al c l oc k (c l k m o de pi n= ? h ? ) xti xto ak7 6 0 1 a external cl oc k fi gu re 8. ext e r n al c l oc k m o d e no te. do no t in pu t th e clo c k o v e r dvdd. 2) x?tal (clkm o de p i n = ?l?) xti xto a k7 601 a fi gu re 9. x ? t a l m o de c0 l1 c1 r1 cl 0. 78 pf~ 1. 2 pf 20.475mh~11.8mh 2.428ff~4.2fh 24.1 ? ~16.0 ? 12pf~8pf table 2. recommended parameters of crystal oscillator r1 c1 l1 c0 cl cl fig u re 10 . equiv a len t circu it an d lo ad cap a citan ce of crystal oscillato r
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 16 - digital high pass filt er th e adc h a s a d i g ital h i g h pass filter for dc o f fset ca n cellatio n . th e cu t-o f f freq u e n c y o f th e hpf is 0.86 hz. master clock output pin the m c ko pi n i s t h e out put pi n f o r m a st er cl ock. m c k o 1 - 0 bi t s co nt r o l t h e m a st er cl ock fre que ncy . m c ko 1 bi t m c ko 0 bi t m ast e r c l ock spee d 0 0 ?l? output (default) 0 1 2 56f s ( 1 1 . 28 96mh z ) 1 0 5 12f s ( 2 2 . 57 92mh z ) 1 1 r e serve d tabl e 3. m a st e r c l oc k out put sel ect audio int e rface input format in all m o d e s t h e serial d a ta is msb-first, two?s co m p le me n t f or m at an d sd ti1- 4 ar e latch e d on t h e r ising edg e of ibick1 -3 an d obic k re spec tively . idif1 - 0 b its settin g is reflected o n sdti1-3 an d idif41-40 b its se ttin g is reflected o n sdit4. use olr c k , ob ic k a n d i d if w h en t h e s d ti 3 dat a i s i n put t o in p u t 2 i n st ead o f bei n g use d fo r sr c . m ode id if 1 bi t id if 0 bi t sdt i1 - 3 f o rm at ilrck1 - 3 pi ns ibick 1 -3 pi ns ibick1 -3 fre q 0 0 0 16 bi t , l s b j u st i fi e d 32~ 6 4 fs 1 0 1 24bit, lsb justified 48~64fs 2 1 0 24 bi t , m s b j us t i fi e d 48~ 64fs 24 or 16bit i 2 s compatible 48~64fs (default) 3 1 1 16 bi t , i 2 s c o mp atib le i npu t i npu t 32 fs table 4. sdt i 1~3 input audio interface form at mode id if 41 bit id if 40 bit sdt i 4 f o rm at olrck pi n obic k pi n obic k fre q 0 0 0 16 bi t , l s b j ust i fi e d 1 0 1 24 bi t , l s b j ust i fi e d 2 1 0 24 bi t , m s b j us t i f i e d 3 1 1 24 o r 1 6bi t i 2 s co m p atib le out put out put 64 fs (d efau lt) table 5. sdt i4 input audio interface format
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 17 - il r c k ib i c k ( 3 2 f s ) 0 11 0 2 3 9 1 11 2 1 3 1 41 5 0 12 3 1 0 10 9 1 1 1 2 1 31 41 5 sdti(i) don't care 1 0 15 14 13 21 0 15 14 1 3 12 12 do n ' t c a r e 15:msb, 0:lsb sdti(i) 15 14 13 76543 21 0 15 14 13 15 76543 21 0 ibick(64fs) 0 11 8 2 3 19 2 0 31 0 1 2 3 1 0 18 1 9 20 31 17 17 lch data rc h d a t a fi gu re 1 1 . m o de 0 ti m i ng ( 1 6bi t , lsb ju st i fi e d) i l rck i b i ck ( 64f s ) 0 1 224310 12 1 0 31 24 89 8 9 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 d o n 't c a r e 23 1 fi gu re 1 2 . m o de 1 ti m i ng ( 2 4bi t , lsb ju st i fi e d) il r c k ibi c k(6 4 f s ) 0 1 22 0 2 1 2 4 3 1 0 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data do n ' t ca r e 432 1 23 22 23 22 23 1 2 3 4 fi gu re 1 3 . m o de 2 ti m i ng ( 2 4bi t , m s b j u st i fi e d) il r c k ibi c k ( 6 4 f s ) 0 1 22 5 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rc h da t a don't care 432 1 23 22 23 22 1 2 3 4 fi gu re 1 4 . m o de 3 ti m i ng ( 2 4bi t i 2 s) no te : sdti rep r esen ts sdti1 , sdti2, sdti 3 an d sd ti 4, i l rck r e pr esen ts ilrck1 , ilrck2, ilrc k3 and olrc k, bick rep r ese n ts ibic k1 ibi c k2 , ib ick 3 and ob ick in the fi gu res a b o v e.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 18 - audio int e rface output format di f bi t sel ect s bet w ee n t w o seri al dat a m odes as s h o w n i n table 6 . in all m o d e s th e serial d a ta is msb-first, two ? s com p l e m e nt form at and s d t o 1 - 3 are l a t c h e d on t h e ri si n g e dge o f ob i c k. olrck obic k di f m ode sdt o 1-3 i/o i/o 0 24 bi t , le ft j u stified h/l o 64 fs o 1 24 bi t , i 2 s l/h o 64 fs o (de f ault) tabl e 6. a udi o dat a f o rm at ( s t e reo m ode) fi gu re 1 5 . m o de 0 ti m i ng ( l eft j u st i f i e d m ode) fi gu re 1 6 . m o de 1 ti m i ng ( i 2 s mode) olrck obick(64fs ) sdto (o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 lch data rch data 12 11 10 sdt o -23:msb, 0:lsb olrck obick(64fs ) sdto (o) 0 1 2 3 22 23 24 25 0 0 1 31 29 30 23 22 1 23:msb, 0:lsb lch data rch data 2 0 2 3 22 23 24 25 0 31 29 30 23 22 1 2 0 1
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 19 - zero detect function the a k 7 6 0 1 a has i n depe n d e n t zer os det ect fu nct i o n f o r ea ch dac . t h i s fu nct i o n is alw a y s ena b l e d. c h an nel gr o upi n g can be sel ect ed by dz d 1 - 3 bi t s of c ont 1 a nd i t s c ove rs 6- chan nel o u t p ut s. c o unt i n g on ?an d ? fo r zer o det ect ed fl ag s o f selected ch an n e ls, wh en t h e in pu t d a ta is co n tinuo usly zeros for 8192 l rck cycles, the dz f pi n g o es t o ? h ? i f d z l h bit (cont 1 ) is ?0?, the dz f pin goes t o ?l? if dzl h b it (cont 1) is ? 1 ? . t h e dzf pin immediately returns to ?l? ( d zl h b it ?0 ?) o r ?h ? (d z l h b it ?1 ?) if t h e in pu t d a ta is n o t zero after t h e zero d e tectio n. digital vo lume ak 7 6 0 1 a has a cha nnel - i nde pen d e n t di gi t a l at t e nuat o r (2 5 6 l e vel s , 0 .5 d b st eps) . at t e nu at i on l e vel of e ach c h an nel ca n be set by eac h t h e a tt7 - 0 bi t s ( table 7 ). att7 -0 atten u a tion lev e l 00h 0db 01 h - 0 . 5db 02 h - 1 . 0db : : 7d h -6 2.5db 7e h -6 3.0db 7f h -6 3.5db : feh - 127.0db ffh mute (- ) (d efau lt) tab le 7 . attenu atio n lev e l th e transitio n b e tw een set v a lu es is a soft tran sitio n o f 4096 le v e ls elim in atin g sw itch i ng no ise i n t h e t r an sition . it take s 4 096/fs (2 3.2m s) from 0 0 h(0d b) to ffh( m u te). if th e pdn p in go es to ?l?, th e att7-0 b its are in itialized to 00h. th e atts al so bec o m e 00h w h e n r stn bi t = ? 0 ?, an d fa de t o th eir cu rren t settin g v a lu e wh en rstn b it ret u rn s t o ?1 ?.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 20 - soft mute (mute1, mute2) ( figure 32 ) so ft m u t e o p er at i on i s per f o r m e d i n t h e di gi t a l dom ai n. w h en th e m u ten p i n is set t o ?l? o r sm ute b it is set ?0 ?, th e out put signal i s attenuated to - i n t h e ti m e set b y mcont b it. wh en the sm ute b it is return ed to ?1 ?, th e m u te is can celled an d t h e o u t p u t attenu atio n lev e l g r ad u a lly ch ang e s to 0d b in th e ti m e set b y mcont b it. if t h e so ft m u te is can celled b e fore attenu ating - , th e attenu atio n is d iscon tin u e d and th e atten u a tio n lev e l is ret u rn ed to 0d b b y t h e same cycle. soft m u te is effective for cha n ging the signal source without st o ppi ng t h e si g n al transm ission. mut e n pi n or smut en b i t att level dzf d- vol u m e1 f u ll le ve l - f aout 8192/fs gd gd (1 ) (4 ) (5 ) (6 ) (3 ) (2) (2 ) no te: (1) th e tran sitio n ti m e to atten u a te i n pu t d a ta to - in lin ear steps is set b y mcont b it. (2 ) t h ere i s del a y , whi c h i s set by t h e del a y b l ock, fr om a fal l i ng ed ge of t h e m u te n pi n or sm ute n b i t t o st art t h e atten u a tion. (3) th e tran sitio n tim e to return to th e fu ll scale of t h e i n pu t sign al t o lg1 , rg1 , lg2 and rg2 is set b y mcont b it. (4 ) anal og o u t put c o rres p on d i ng t o di gi t a l i n put has a gr ou p del a y ( g d). (5) if th e so ft m u te is can cell ed b e fore attenu atin g - after startin g th e o p eratio n, th e at t e nuat i o n i s di s c ont i n ue d an d th e d i g ital v o l ume is retu rn ed to th e fu ll scale lev e l b y t h e same cycle. (6) wh en th e in pu t d a ta for bo th ch ann e ls are co n tinuo u sly zero for 8192 lrck cycles and dzl h bit is ?0?, the dzf pin goes t o ? h ? (the dzf pin goes t o ?l? if the dzlh b it is ?1 ?). th e dzf p i n imm e d i a t ely retu rn s to ?l? if t h e in pu t d a ta are n o t zero after go ing to dzf ?h? (dzlh b it =?0 ? ). fi gu re 1 7 . so ft m u t e a n d zero det ect funct i on
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 21 - soft mute (fmute, r m ute, swmute, momu te) ( figure 32 ) so ft m u t e o p er at i on i s per fo r m e d i n t h e di gi t a l dom ai n. when the fmut e, rm ute, s w mu te or m o mute b it is set ?1?, th e ou tpu t sig n a l is attenuated to - i n 1024 lrck cycles. whe n t h es e bits a r e returned to ? 0 ?, t h e m u te is cancelled and th e ou tpu t atten u a tio n level g r adu a lly chan g e s to 0 d b in 10 24 lrck cycles. if th e so ft m u te is cancelled with i n t h e 1024 lrck cy cles after starting t h is oper ati o n, th e attenu atio n is d iscon tinu e d and th e atten u a tion lev e l i s return ed to 0db by the sam e cycle. soft m u te is eff ecti v e f o r changi n g t h e si gnal so urce wi t h o u t st op pi n g t h e si gnal t r a n s m i ssion. dzf - f aout 8192 /f s gd gd (1 ) (3) (4 ) (5 ) (2 ) fm u t e b i t rm u t e b i t s w m u t e b i t m o m u te b i t at t leve l d - vol u m e1 f u ll le ve l no te: (1) th e tran sitio n ti m e to atten u a te i n pu t d a ta to - in lin ear steps is 1 024 lrck cycles (1024/fs ) . (2) th e tran sitio n ti m e to return to t h e fu ll scale o f d i g ital vo lu m e o u t pu t sig n a l is 10 24 lrck cycles (10 2 4 / fs). (3 ) anal og o u t put c o rres p on d i ng t o di gi t a l i n put has g ro u p del a y ( gd ). (4) if th e so ft m u te is can cell ed b e fore attenu atin g - after startin g th e o p eratio n, th e at t e nuat i o n i s di s c ont i n ue d an d retu rn ed to att lev e l b y th e sam e cyc l e. (5) wh en th e in pu t d a ta for bo th ch ann e ls are co n tinuo u sly zero for 8192 lrck cycles and dzl h bit is ?0?, the dzf pi n g o es t o ?h ? (t he dz f pi n goe s t o ? l ? i f dzl h bi t i s ?1?). t h e dzf pi n immediately returns t o ?l? i f the i n put dat a are n o t zer o a f t e r goi ng t o dz f ? h ? ( d z l h bi t =?0? ). fi gu re 1 8 s o ft m u t e and ze r o det ect f unct i on
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 22 - pseudo-differential input (ainl1/ainr1, ainl2/ainr2) th e ak760 1a h a s two sets of p seudo -d ifferen tial in pu t chan n e ls. + - + - - + aaf aaf vco m =a vd d / 2 lin1 rin1 gnd1 fig ur e 19 . pseu do- d iff er en tial i npu t blo c k w h en pow e r - on th e ak7 601a , cap acitor s t h at conn ected t o th e pseudo -dif f e r e n tial in put p in ar e ch arged in h i g h sp eed (fast m ode) . t h i s fi rst m ode i s co nt r o l l e d by a re gi st er (fc h a 0 bi t ) . the char gi n g t i m e in fast m ode i s 40m s (t y p ) an d 10 0m s (m ax). (01h: d4 b it) fcha0 fast cha r ge 1 on (default) 0 off tabl e 8. fast c h ar ge input selector th e ak 760 1a h a s an an al o g in pu t selecto r fo r ad c an d a d ig ital in pu t selecto r for src. sel0 1-0 0 b its and sel11- 10 b its con t ro l th ese in pu t selectors. click no ise may o ccu r wh en se l0 1- 0 0 bi t s an d s el1 1 - 1 0 bi t s are c h a n ged . m u t e di gi t a l out put i f t h e cli c k noi se af fect s sy st em perfo r m ance. sel01 sel00 adc input 0 0 ainl 1/ a inr 1 (de faul t ) 0 1 ai nl 2/ a inr 2 1 0 ai nl 3/ a inr 3 1 1 ai nl 4/ a inr4 table 9. analog input selector sel11 s el10 src input 0 0 sdt i1 (de faul t ) 0 1 sdt i2 1 0 sdt i 3 1 1 r e serve d tab l e 1 0 . dig ital inpu t selecto r
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 23 - s y s t em r eset th e ak7 601 a sh ou ld b e powered -up wh en t h e pdn p in = ?l?. th e in t e rn al reg u lator will b e powered -up b y i n pu t tin g the m a s t er clock to the xti pin or c o nnect ing a x?tal afte r settin g th e pdn p i n to ?h?. in x?tal m o d e, th e in tern al regu lato r is powered -up in 5m s after th e pdn pi n bec o mes ?h?. in e x ternal cl o c k m o d e , th e in tern al regu lato r is po we red - u p i n 5m s aft e r cl ock i n put . whe n t h e re gul at o r i s po we red - u p , t h e i n t e r n al m a st er cl ock st art s by set t i ng r s t n b it to ?1 ?. po w e r dow n the adc an d dac pa rt s o f t h e ak 7 6 0 1 a are pl ace d i n t h e po wer - d o w n m ode by b r i ngi ng t h e pd n pi n ?l? a n d t h e d i g ital filter is also reset at the sam e t i m e. t h e intern al re g i sters are i n itiat ed to t h eir d efau lt v alu e b y the pdn p i n = ?l? . thi s reset s h o u l d al way s be m a de a f t e r po we r- up . in t h e p o w er -d o w n m ode, s d t o 1/ s d to 3, sdt o 2/ sdt i 4 , ob ic k, olr c k a n d dz f pi ns go t o ? l ? an d t h e a n al og o u t p ut i s v ss. whe n e x i t i ng t h e po wer - d ow n m ode, t h e ak7 6 0 1 a wi ll be in reset state since t h e rstn bit = ? 0 ?. figure 20 s h ows t h e power on/off seque n ce exam ple. pdn a dc i n t e r n a l st a t e nor m al operation power down rstn dac int e r n al st a t e n o rmal operation p o we r d o wn sdt o 1~ 3 a dc in ( a nalog ) gd(4) dac ou t ( a nalog ) gd(4) clock i n xt i ( ex ter nal) dzf dzlh= ?1? dzlh= ? 0 ? ?0? data ( 5) (7 ) (9) (6 ) (8 ) pd n i nte r nal 5ms(1 ) clock in x' t a l ( 10) (2) reg ulato r normal operation power down (3) no te: (1 ) after t h e pdn p i n = ?h?, th e in tern al pdn is ?l? u n til x? tal an d regu lator are po wered - u p . (reg ister writin g is n o t val i d fo r 5m s of t h i s pe ri o d ) (2 ) during th e rstn b it is ?0 ?, all circu its will b e p o we red d o wn ex cep t th e reg u lator an d x?tal ev en wh en th e in tern al pdn i s ?h?. (3 ) reg u l ator will b e po wered-up afte r t h e pdn p i n b eco m es ?h?. (4 ) the d ac an d sdt o 1- 3 out p u t s c o r resp o ndi ng t o t h e adc i n p u t ha s gr ou p del a y ( gd ). (5 ) th e sd tp1-3 o u t p u ts ar e ?0 ? wh en th e ak 76 01a is po w e red - do wn . (6 ) th e da c ou tpu t is v s s vo ltag e w h en t h e ak 760 1a is pow er ed -do w n . (7 ) click no ise o c cu rs at th e fallin g edg e of pdn. (8 ) in case of connectin g a x?tal, th e clo c k ou tpu t is ?l? wh en th e pdn p i n =?l?. th e x?ta l will b e powered up after t h e p d n pi n = ? h?. (9 ) in p o w er d o w n m ode (p d n pi n = ? l ?), t h e d z f pi n = ?l?. (1 0) th e dzf p i n ou tpu t will reflects th e dzlh b it settin g wh en in tern al pdn is ?h?. fi gu re 2 0 . po w e r up/ d o w n s e que nce exam pl e
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 24 - reset function w h en th e r s tn b it = ?0 ?, ad c and d a c par ts of th e a k 76 01a is pow ered dow n, bu t the in ter n al re gis t er values a r e not in itialized . th e an al o g ou tpu ts settle to vcom vo ltag e , s d to 1/sdt o 3, sdt o 2/sdt i 4 , ob ick a n d olr c k pi ns g o t o ?l? and t h e d z f pi n s f o r bot h cha n nel s g o t o ?h? or ?l? d e pen d i n g on t h e dzl h bi t set t i ng. c l i c k n o i s e occu rs at t h i s ti min g . m u te th e an alog o u t pu t ex tern ally if th e click n o i se in flu e n ces syst e m ap p licatio n . figu r e 21 s hows the exam ple of reset b y r s tn b it. rs t n b i t a dc in ternal state n ormal o peration power down dac inte r na l s t ate n ormal o peration power down sdt o 13~ a dc in ( a nalo g) gd(6) dac ou t (a nalog) gd(6) clock i n xt i( e x te rnal) d on' t care(11) dzf dzlh="0" "0" da t a ( 7 ) (9) (12) (9 ) i nter nal rs t n(ad c ) cl o ck in x'tal inter nal rst n ( i i r ) i nter nal rs t n(da c ) in it cycle 8/fs n o r m al op erat i o n init 1. 5~2. 5/f s normal op er ati on ii r i nter nal s t at e po w er down init 7~8/ f s n ormal o peration n o rmal operation 4~5/fs (1 ) (3) (4 ) (5) gd(6) (10) gd( 6 ) 9/fs ~1/fs(2) (8) (8 ) no te: (1 ) in tern al rstn will b e ?l?, 4~5 / fs after rstn b it ch ang e d to ?0 ?. (2 ) adc in tern al rstn will b e ?h?, with in 1 / fs fro m rstn bit = ?1 ?. (3 ) the reset cycle is 8/fs afte r adc internal r s tn becam e ?h?. (4 ) in tern al rstn fo r iir will b e ?h? after 7 ~ 8 / fs fro m rstn b it =?1 ?. (5 ) in tern al rstn fo r dac will b e ?h? afte r 1 . 5 ~ 2.5 / fs fro m rstn b it = ?1?. (6 ) the d a c , s d to 1/ sdt o 3 a n d s d t o 2/ s d ti4 o u t p ut s c o rres p on di n g t o t h e a d c i n p u t has gr o u p del a y (g d) . (7 ) the sdt o 1/ s d t o 3 an d sd to 2/ sdt i 4 ou t put s a r e ? 0 ? d a t a whe n t h e a k 7 6 0 1 a i s i n p o we re d do w n m ode. (8 ) click n o i se o c cu rs wh en th e in itializa tio n of adc b l o c k i s fin i sh ed . m u te d i g ital o u t pu t if click n o i se ad v e rsely affects system perform a nce. (9 ) click no ise o c cu rs at th e edge of in tern al r s tn. (1 0) an al o g ou tpu t is vcom vo ltag e (avdd/ 2 ) wh en rstn bit = ?0 ?. (1 1) in case o f i n p u t t i ng c l k fr o m t h e xti pi n, t h e cl oc k s h ou l d be i n p u t befo re t h e r s t n bi t i s c h an ge d t o ? 1 ? aft e r th e rstn b it was set t o ?0 ?. (1 2) th e dzf p i n reflects th e settin g of dzlh b i t. th is p i n ch a n g e s to ?l? o r ?h? 9 / fs after t h e rstn b it was set to ?0?. (1 3) reg ister setting s fo r p a t h switch ing ex cep t sel01 - 00 , sel1 1-1 0 and sw1 b its, and co mman d cod e ch an g e sh ou ld be m a de d u ri n g r st n bi t = ? 0 ?. figure 21. res et sequence e x am ple
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 25 - i 2 c bus interface (microcontroller interface) access to the AK7601A re gi sters and r a m is processe d by i2c bu s. th e form at o f th e i2c is co m p le m e n t with fast m o d e (m ax: 40 0k hz) . t h e ak 7 6 0 1 a doe s not s u p p o rt hs m ode. (m ax: 3.4m hz ). data tran sfer in orde r t o acc ess any ic devi ces on t h e i 2 c bus, inp u t a start cond itio n first, followe d by a single slave addres s whi c h in cl ude s t h e devi ce a d dres s. ic devi c e s on t h e bu s com p are this slave addre ss with th eir ow n ad dr esses and t h e ic devi ce wh i c h has a n i d e n t i cal address with t h e sl ave-a d dress ge n e r a tes an ackn ow ledg em en t. an i c device with t h e identical address the n e x ecut e s either a rea d or a write ope ratio n . after th e co mm an d ex ecu tio n, in pu t a st o p con d ition . 1-1. da ta ch ange ch ang e t h e d a ta on th e sda lin e wh ile scl lin e is ?l?. sda lin e con d ition m u st b e stab le and fix e d while th e clo c k is ?h?. ch ang e th e data lin e co nd itio n b e tween ?h? an d ?l? on ly wh en th e clo c k sig n a l on th e scl lin e i s ?l?. c h ang e t h e sda lin e cond itio n wh ile scl lin e is ?h? o n l y wh en th e start cond itio n o r stop con d itio n is i n pu t. fi gu re 2 2 . dat a tra n si t i on 1-2. start c onditi on and stop condition start con d ition is g e n e rated b y th e tr an sitio n of ?h? to ?l? on th e sda lin e wh ile th e scl lin e is ?h?. all in stru ction s are in itiated b y start con d ition. stop cond iti o n is g e n e rated b y th e tran sitio n of ?l? to ?h? o n sda lin e wh ile scl lin e is ?h?. al l in stru ction s en d b y stop co nd itio n . figu re 23 . start co nd itio n and st o p cond itio n scl sda data line stable : data valid change of data allo wed scl sda stop condition start condition
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 26 - 1-3. repea t e d start cond ition wh en a start co nd itio n is receiv ed ag ai n i n st ead of a st o p co nditio n, t h e bus ch ang e s t o rep eated start co nditio n. a rep eated start co nd itio n is functio n a lly th e same as a start co nd itio n. fig u re 24 . repeated start c o n d ition 1-4. ackno w l e dge an exte rnal de vice that is se nding da ta to t h e AK7601A re leases the sda line (? h?) afte r recei ving one -byte of data. an exte rnal device t h at receives da ta from the AK7601A the n sets t h e sda line to ? l? at the ne xt c l ock. t h is ope rat i o n is cal l e d ?ack n o wl e dgem e nt ? an d i t enabl e s ve ri fi cat i on t h at t h e dat a t r a n sfe r h a s bee n pr o p erl y execute d. the AK7601A ge nera tes an acknowle dgem ent upon recei pt of start condition and sla v e address. for a write inst ruction, a n ac knowle dgem e nt is ge nerated when e v er recei pt of ea ch byte is com p leted. for a re ad instruction, suc ceeded by ge ne ration of a n acknowledgem ent, the AK7601A releases the sda line after out putting d a ta at th e d e si g n a ted ad dress, and it m o n itors th e sda line con d ition . wh en th e master sid e g e n e rates an ack nowledg emen t withou t send ing a stop con d ition , t h e ak 760 1a ou tputs d a ta at th e nex t address l o catio n . whe n n o ac kn owl e dgem e nt i s ge nerat e d, t h e a k7 6 0 1 a e n ds dat a out put (n ot ac kn o wl e dge d ). fig u r e 25 . a c kn ow ledg e scl sda rep eated sta r t co nditio n start condition scl from master ackno w le dge data outp u t by t r ansmitte r dat a out p u t by receiver 1 9 8 start co nditio n clo ck p u ls e for ackn owl e dge not acknowledge
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 27 - 1-5. the firs t b y te the first byte whic h i n cludes the slave - address is i n pu t after th e start conditio n is set, an d a targ et ic d e vice th at will be accesse d on t h e bus is selected by the slave-a d dress. the sla v e-a d dress is config ure d with the uppe r 7-bits. d a ta o f th e upper 7 - b its is ?001 100 0 ? . th e add r ess b its th at select th e d e sir e d i c ar e f ix e d . w h en th e slave- add r ess is in pu tted , an ex tern al d e v i ce th at h a s th e iden tical device address ge nera tes an ac knowl e dgem e nt and in stru ction s are th en ex ecu ted . th e 8 th b it of t h e first byte (lowe s t bit) is all o cated as t h e r / w bit. whe n the r/ w bit is ?1 ?, th e read instru ction is ex ecu t ed, an d wh en it is ?0 ?, t h e write instru ction is ex ecu t ed . note 23. in thi s docum e nt, there is a case that descri b e s a ?w r ite s l av e - ad dr e ss as si gn me n t ? wh en b o t h ad dr e ss bits m a tch and a slave-a d dre ss at r/w bit = ?0? is rece ived. t h e r e is a case that describes ?rea d slave-a d dress assignm ent? when bo th a d dress bits m a tches and a slave - addre ss at r/w bit = ?1? is receive d. 0 0 1 1 0 0 0 r / w slav e a ddr ess is f i x e d 3 0 h( wr ite) or 31 h( r e ad ). figure 26. t he first byte structure 1-6. the sec ond and suc ceeding b y t es the data form a t of the sec o nd and s u cceedi n g bytes of t h e AK7601A tra n s f er / recei ve serial data (c ommand code , a d dress a n d data i n m i crocon troller inte rface form at) on the i 2 c b u s are all confi g ured with a m u lti p l e of 8-bits. whe n t r ansfe rri ng or receiving those data on t h e i 2 c b us , t h ey a re di vi de d i n t o a n 8 -bi t dat a st re am segm ent and they are tra n sfe r red / r eceive d with the msb side data first wi th an acknowle dgem e nt in-bet ween. whe n t r ans f erring / receivi ng a1b 2 c3 (he x ) 24-bit serial data in m i croprocessor interfac e form at: fi gu re 2 7 . di vi si on o f t h e dat a note 24. in t h is doc um ent, the r e is a case that descri bes a write instruction command c ode wh ic h is recei ved at t h e sec o nd byte as ? write command?. t h ere is a case t h at descri bes a read in stru ction co mm an d cod e wh ich is receiv ed at the sec o nd byte as ?read command? a1 b2 c3 a a 8bit 8bit 8bit a ac kn ow ledge (1)i 2 c format
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 28 - command code bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 8/16(*1)/16(*2)/32 flag area to be accessed (1 ) 8/1 6 ( * 1)/1 6 ( * 2 )/ 32 fla g wh en bit[7 : 6] b its are ?0 0 ? , th e fo llowi ng data will b e 8 b it. th e d a ta will be 16b it 1wo r d i n 2b yte transfer wh en ?01 ? , 16 bi t 1 w or d x 5 i n 1 0 b y t e t r a n sfe r w h en ?1 0 ? , an d 3 2bi t 1 w o r d x 5 i n 2 0 b y t e t r ans f er w h en ?1 1?. (2) accom p anying data to t h e access a r ea bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 co mman d an d co n ten t 0 0 0 0 0 0 0 1 01h control register cont1 setting 0 0 0 0 0 0 1 0 02h control register cont2 setting 0 0 0 0 0 0 1 1 03h control register cont3 setting 0 0 0 0 0 1 0 0 04h control register cont4 setting 0 0 0 0 0 1 0 1 05h control register cont5 setting 0 0 0 0 0 1 1 0 06h control register lout1vol setting 0 0 0 0 0 1 1 1 07h control register rout1vol setting 0 0 0 0 1 0 0 0 08h control register lout2vol setting 0 0 0 0 1 0 0 1 09h control register rout2vol setting 0 0 0 0 1 0 1 0 0ah control register lout3vol setting 0 0 0 0 1 0 1 1 0bh control register rout3vol setting 0 0 0 0 1 1 0 0 0ch control register monolvol setting 0 0 0 0 1 1 0 1 0dh control register monorvol setting 0 0 0 0 1 1 1 0 0eh control register swcont1 setting 0 0 0 0 1 1 1 1 0fh control register swcont2 setting 0 1 0 0 0 0 0 0 40h eq gain1 setting 0 1 0 0 0 0 0 1 41h eq gain2 setting 0 1 0 0 0 0 1 0 42h cross over fout gain setting 0 1 0 0 0 0 1 1 43h cross over rout gain setting 0 1 0 0 0 1 0 0 44h cross over swout gain setting 0 1 0 0 0 1 0 1 45h frontl1 delay setting 0 1 0 0 0 1 1 0 46h frontr1 delay setting 0 1 0 0 0 1 1 1 47h rearl2 delay setting 0 1 0 0 1 0 0 0 48h rearr2 delay setting 0 1 0 0 1 0 0 1 49h swl3 delay setting 0 1 0 0 1 0 1 0 4ah swr3 delay setting 0 1 0 1 0 0 0 0 50h read speana 1band (125hz) 0 1 0 1 0 0 0 1 51h read speana 2band (500hz) 0 1 0 1 0 0 1 0 52h read speana 3band (2khz) 0 1 0 1 0 0 1 1 53h read speana 4band (8khz)
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 29 - bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 co mman d an d co n ten t 1 0 0 0 0 0 0 0 80h input gain setting 1 0 0 0 0 0 0 1 81h function1 gain1 setting 1 0 0 0 0 0 1 0 82h function1 gain2 setting 1 0 0 0 0 1 0 0 84h function1 in filter coefficient setting preparation 1 0 0 0 0 1 0 1 85h function1 out filter coefficient setting preparation 1 0 0 0 1 0 0 0 88h function2 lpf2 filter coefficient setting preparation 1 0 0 0 1 1 0 0 8ch function2 gain1 setting 1 0 0 0 1 1 0 1 8dh funciotn2 gain low setting 1 0 0 1 0 0 0 0 90h function3 gain1 coefficient setting preparation 1 0 0 1 0 0 0 1 91h function3 gain2 coefficient setting preparation 1 0 0 1 0 0 1 0 92h function3 filter coefficient setting preparation 1 0 0 1 0 0 1 1 93h function4 gain coefficient setting preparation 1 0 0 1 0 1 0 0 94h function5 gain coefficient setting preparation 1 0 0 1 0 1 0 1 95h function5 filter coefficient setting preparation 1 0 0 1 0 1 1 0 96h eq bind2 coefficient setting preparation 1 0 0 1 0 1 1 1 97h eq band5 coefficient setting preparation 1 0 0 1 1 0 0 0 98h eq band6 coefficient setting preparation 1 0 0 1 1 0 0 1 99h eq band7 coefficient setting preparation 1 0 0 1 1 0 1 0 9ah eq band9 coefficient setting preparation 1 0 0 1 1 0 1 1 9bh eq band12 coefficient setting preparation 1 0 0 1 1 1 0 0 9ch eq band13 coefficient setting preparation 1 0 0 1 1 1 0 1 9dh eq band14 coefficient setting preparation 1 0 0 1 1 1 1 0 9eh x? over filter1-3 coefficient setting preparation 1 0 0 1 1 1 1 1 9fh speana3band coefficient setting preparation 1 0 1 0 0 0 0 0 a0h speana4band coefficient setting preparation 1 0 1 0 0 0 0 1 a1h fr gain setting 1 0 1 0 0 0 1 0 a2h sw gain setting
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 30 - bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 co mman d an d co n ten t 1 1 0 0 0 0 0 0 c0 h fu n c tion2 lpf0 filter co efficien t settin g preparation 1 1 0 0 0 0 1 0 c2h function4 filter coefficient setting preparation 1 1 0 0 0 0 1 1 c3h eq band1 coefficient setting preparation 1 1 0 0 0 1 0 0 c4h eq band3 coefficient setting preparation 1 1 0 0 0 1 0 1 c5h eq band4 coefficient setting preparation 1 1 0 0 0 1 1 0 c6h eq band8 coefficient setting preparation 1 1 0 0 0 1 1 1 c7h eq bnad10 coefficient setting preparation 1 1 0 0 1 0 0 0 c8h eq band11 coefficient setting preparation 1 1 0 0 1 0 0 1 c9h x? over filter1 -1 coefficient setting preparation 1 1 0 0 1 0 1 0 cah x? over filter2 -1 coefficient setting preparation 1 1 0 0 1 0 1 1 cbh x? over filter3 -1 coefficient setting preparation 1 1 0 0 1 1 0 0 cch x? over filter1 -2 coefficient setting preparation 1 1 0 0 1 1 0 1 cdh x? over filter2 -2 coefficient setting preparation 1 1 0 0 1 1 1 0 ceh x? over filter3-2 coefficient setting preparation 1 1 0 0 1 1 1 1 cfh speana1band coefficient setting preparation 1 1 0 1 0 0 0 0 d0h speana2band coefficient setting preparation 1 1 0 1 0 0 0 1 d1h speana sds coefficient setting preparation
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 31 - write seq u e n ce in the AK7601A, wh en a ?write-slave-address assi gnm ent? is received at the first byte, t h e write comm a n d at t h e second byte and data a t the third a n d succee ding bytes are receive d. at t h e data bl ock, a d dress and write data are receive d i n a single-byte unit each in accordance with a command code . the num b er of write data byte s (*1 in fi gu re 28 ) i s fi xe d by t he receive d c o mmand code. usa b le comm a n d codes in wri t e sequence are listed bel o w a s ? tabl e 1 1 . li st of u s abl e c o m m a nd c ode s i n wri t e sequence ?. figu re 2 8 . wri te seq u ence c o m m a nd c o d e dat a le ngt h c ont e n t 40h ~ 4ah 2-byte transferring 16bit coefficient data in 1-coefficient unit 80h ~ a2h 10-byte transferring 16bit coeffici ent data in 5-coefficient or 1-filter unit c0h ~ d1h 20-byte transferring 28bit coefficient data in 5-coefficient or 1-filter unit 01h ~ 0f 1byte writing control register tabl e 11 . li st of usa b l e c o m m a nd c odes i n wri t e seq u e n ce s slad w cmd data a stp a a repeat n times (*1)
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 32 - da ta forma t data write (1 ) c ontr o l re gister write sda (1) command 01h~0f (2) data d7~d0 (2) 1 6 b it co efficien t (1-co e ffi cien t un it) o r delay data write sda (1) command 40h~4ah (2) data1-1 d15~d8 (3) data1-2 d7~d0 (3)16b it co effi cien t (5 -co e fficien t un it) write sda (1) command 80h~a2h (2) data1-1 d15~d8 (3) data1-2 d7~d0 (4) data2-1 d15~d8 (5) data2-2 d7~d0 (6)~(11) (continues in 2byte unit from data3 to data5. in total 10byte data) (4)28b it co effi cien t data wri te sda (1) command c0h~d1h (2) data1-1 0 0 0 0 d27~d24 (3) data1-2 d23~d16 (4) data1-3 d15~d8 (5) data1-4 d7~d0 (6)~(21) (continues in 4byte unit from data2 to data5. in total 20byte data)
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 33 - rea d seque nce in t h e AK7601A, when a ?write- slave-a d dr e ss assignm e nt? is receive d at t h e fi rst byte, t h e comm and is send from m i cr o co n t ro ller in the secon d b y te. wh en th e slave ad dress is rece iv ed after th e start co nd itio n, th e ak 7601 a starts ou tpu ttin g t h e dat a re gard i ng t o c o m m a nd c ode . wh en can cellin g read op eratio n b e fo re t h e ak76 01a send s all d a ta, assu re th at a ?no t ack nowledg ed? sign al is receiv ed by the AK7601A. if t h is ?not ack nowledged? signal is not r eceived, the AK7601A continues to send data until specified num ber, and si nce it di d not release the bus, the stop c o ndi tion ca nnot be properly recei ved. usa b le comm a n d codes in rea d se quence are listed in tabl e 12 figure 29. rea d se quence c o m m a nd c o d e dat a le ngt h c ont e n t 40h ~ 4ah 2-byte reading 16bit coef ficient data in 1-coefficient unit 80h ~ a2h 10-byte reading 16bit coefficient data in 5-coefficient or 1-filter unit. c0h ~ d1h 20-byte reading 28bit coefficient data in 5-coefficient or 1-filter unit. 01h ~ 0f 1byte reading control register 50h ~ 53h 2-byte reading spectrum analyzer data tabl e 12 . li st of usa b l e r e a d c o m m a nd c ode s i n r ead s e que nce s slad w cmd rs data a a a slad r a repeat n times data na stp * canc el
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 34 - data read (1 ) c ont r o l r e gister r e a d sda (1 ) command 01h~0f (input) (2 ) data d7~d0 (2) 1 6 b it co efficien t (1-co e ffi cien t un it) o r delay ti m e rea d sda (1 ) command 40h~4ah (input) (2 ) data1-1 d15~d8 (output) (3 ) data1-2 d7~d0 (3)16b it co effi cien t (5 -co e fficien t un it) read sda (1 ) command 80h~a2h (input) (2 ) data1-1 d15~d8 (output) (3 ) data1-2 d7~d0 (4 ) data2-1 d15~d8 (5 ) data2-2 d7~d0 (6)~(1 1) (continues in 4byte unit from data3 to data5. in total 10byte data) (4)28b it co effi cien t data read sda ( 1) command c0h~d1 (input ) (2 ) data1-1 0 0 0 0 d27~d24 (output ) (3 ) data1-2 d23~d16 (4 ) data1-3 d15~d8 (5 ) data1-4 d7~d0 (6)~(2 1) (continues in 4byte unit from data2 to data5. in total 20byte data) (5) spectrum analyzer data read sda ( 1) command 50h, 51h, 52h, 53h (input) (2 ) data2 d15 d14 d13 d12 d11 d10 d9 d8 (output) (3 ) data1 d7 d6 d5 d4 d3 d2 d1 d0
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 35 - register map com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 01 h c ont 1 0 0 0 fc h a pmadc m pmadc pmdac rstn 02 h cont 2 dz d3 dz d2 dz d1 dzl h od if 0 mcont smuten 03 h cont 3 mom u te fmut e r mut e sw mut e id if 41 id if 40 idif1 idif0 04 h cont 4 lrck bick m c ko 1 m cko 0 do 2 1 do 2 0 do11 do10 05 h c ont 5 0 0 0 0 sel1 1 sel1 0 sel01 sel00 06h lout1 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 07h rout 1 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 08h lout2 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 09h rout 2 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 0ah lout3 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 0bh rout 3 vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att 0 0c h mo no in l vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att1 att0 0d h mo no in r vol um e c ont r ol att 7 att 6 att 5 att 4 att 3 att 2 att1 att0 0e h s w c ont 1 0 s w 51 s w 50 s w 4 s w 31 s w 30 sw2 sw1 0f h s w c ont 2 0 0 0 s w s w r s w fs w eqsw1 eqsw0 no te: all reg i sters are in itiali zed b y th e pdn p i n = ?l?. wh en r s tn bit b eco m e s ?0 ?, th e i n tern al timi n g is reset bu t th e reg i sters are n o t i n itializ ed . data m u st n o t b e written i n to ad dresses fro m 10 h to 1 f h. the bi t s de fi ne d as 0 m u st cont ai n a ? 0 ? val u e.
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 36 - register definitions com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 01 h c ont 1 0 0 0 fc h a pm a dc m pm a dc pm d ac rstn defa ul t 0 0 0 1 1 1 1 0 r/w rd rd rd r/w r/w r/w r/w r/w fc h a : hi gh s p eed c h a r ge m ode ena b l e 0: hi gh s p eed c h ar ge di sabl e 1: hi gh speed charge e n a b le (defa u lt) pmad cm: ad c mono power man a g e m e n t 0 : ad c pow e r do wn 1: norm al operation pm a d c : a d c po wer m a na gem e nt 0 : ad c pow e r do wn 1: norm al operation pm d a c : d a c 1- 3 p o wer m a nagem e nt 0: all dacs p o we r d o w n 1: norm al operation rstn: in tern al ti m i n g reset 0: r e set th e dzf p i n beco m es ?h? or ?l? d ep e nd ing o n dzlh b i t bu t reg i sters are n o t i n itialize d . 1: norm al operation
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 37 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 02h cont2 dzd3 dzd2 dzd1 dzlh dif 0 mcont smuten default 0 0 0 0 1 0 0 0 r/w r/w r/w r/w r/w r/w rd r/w r/w dz d3: dzf s e tting 0: t h e dzf pi n refl ect s t h e z e ro -det ect i o n o f dac 3 1: t h e dzf pi n i g n o res t h e z e ro -det ect i o n o f dac 3 dz d2: dzf s e tting 0: t h e dzf pi n refl ect s t h e z e ro -det ect i o n o f dac 2 1: t h e dzf pi n i g n o res t h e z e ro -det ect i o n o f dac 2 dz d1: dzf s e tting 0: t h e dzf pi n refl ect s t h e z e ro -det ect i o n o f dac 1 1: t h e dzf pi n i g n o res t h e z e ro -det ect i o n o f dac 1 dzl h: d zf pi n pol a rit y set t i ng 0: output ? h ? whe n t h e ze ro data is detected. 1: output ?l? whe n t h e ze ro data is detected d7 d6 d5 d4 dac 3 dac 2 dac 1 d zf pi n out pu t level 0 0 0 0 zero zero zero h 0 0 1 0 zero zero - h 0 1 0 0 zero - zero h 0 1 1 0 zero - - h 1 0 0 0 - zero zero h 1 0 1 0 - zero - h 1 1 0 0 - - zero h 1 1 1 0 - - - h 0 0 0 1 zero zero zero l 0 0 1 1 zero zero - l 0 1 0 1 zero - zero l 0 1 1 1 zero - - l 1 0 0 1 - zero zero l 1 0 1 1 - zero - l 1 1 0 1 - - zero l 1 1 1 1 - - - l tab l e 1 3 . zero detectio n contro l dif: di g ital ou tpu t format (dif mo d e settin g) 0 : left ju stified m o d e 1 : i 2 s m o d e ( d e f a u l t ) mcont: soft mu te tim e set tin g 0: 1 0 24/ fs (de f aul t ) 1: 2 2 / f s sm ute n : m u te 1, m u te 2 b l oc k m u te n pi n sm ute n bi t al l a n al o g ou t put s st at us 0 mute (default) l 1 m ute 0 mute (d efau lt) h 1 unm ut e table 14. s o ft m u t e c o nt r o l
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 38 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 03 h cont 3 m o m u te fm ute r m u te s w m u te id if 41 id if 40 id if 1 idif0 defa ul t 0 0 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w mo mu te: m o mu te blo c k 0: u n -m ut e (de faul t ) 1: m u t e (r efer t o p4 4; ds p b l oc k c o nst r uct i o n ) fmute: fmute bloc k 0: u n -m ut e (de faul t ) 1: m u t e (r efer t o p4 4; ds p b l oc k c o nst r uct i o n ) rmute: rmute bl ock 0: u n -m ut e (de faul t ) 1: m u t e (r efer t o p4 4; ds p b l oc k c o nst r uct i o n ) sw mu te: sw mu te blo c k 0: u n -m ut e (de faul t ) 1: m u t e (r efer t o p4 4; ds p b l oc k c o nst r uct i o n ) idif4 1 -idif40 : d i g ital input fo rm at, id if mo d e settin g (sdit4) 0 0 : 16 b it lsb ju stified mod e 0 1 : 24 b it lsb ju stified mod e 1 0 : 24 b it msb ju stified mode 1 1 : 16 b it/24 b i t i2 s m o d e (d efau lt) idif1 - idif0 : src dig ital in p u t form at, idif m o d e settin g (sdit1 , sdti 2, sdti3) 0 0 : 16 b it lsb ju stified mod e 0 1 : 24 b it lsb ju stified mod e 1 0 : 24 b it msb ju stified mode 1 1 : 16 b it/24 b i t i2 s m o d e (d efau lt)
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 39 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 04 h cont 4 lrck bick m c ko 1 m c ko 0 d o 2 1 d o 2 0 do 1 1 do10 defa ul t 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w lrck: lrck ou tpu t en ab le 0: t h e olr c k pi n o u t p ut s ? l ?. (d efau lt) 1: t h e olr c k pi n o u t p ut s lr c k ( 1 fs ). bick: bit clo c k ou tpu t enab le 0: t h e obick pin outputs ?l ?. (defa u lt) 1: t h e ob ic k pi n o u t p ut s 6 4 f s b i t cl oc k. m c ko 1- 0: m a st er c l oc k ou t put e n a b l e m c ko 1 m c ko 0 m a st er c l ock spee d 0 0 ?l? o u t p ut (de f aul t ) 0 1 256fs (11.2896mhz) 1 0 512fs (22.5792mhz) 1 1 reserved tabl e 3. m a st e r c l oc k out put sel ect do 2 1 - d o2 0: sdt o 2/ sdt i 4 i n / o ut p u t ena b l e d o 21 d o 20 sdto2 /sd ti4 p in 0 0 ?l? o u t p ut (de f aul t ) 0 1 sdt o 2 1 0 sd ti 4 (i npu t) 1 1 r e serve d tabl e 15 . s d t o 2/ s d t i 4 i n p u t / o ut put sel ect do 1 1 - d o1 0: sdt o 1/ sdt o 3 out put ena b l e do 1 1 do 1 0 sdt o 1/sdt o 3 pin 0 0 ?l? o u t p ut (de f aul t ) 0 1 sdto1 1 0 sdto3 1 1 r e serve d tabl e 16 . s d t o 1/ s d t o 3 ou t put sel ect
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 40 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 05h cont5 0 0 0 0 sel11 sel10 sel01 sel00 default 0 0 0 0 0 0 0 0 r/w rd rd rd rd r/w r/w r/w r/w sel11- 10 : sr c i npu t selecto r con t ro l sel11 sel10 s rc input 0 0 sdti1 (default) 0 1 sdt i2 1 0 sdt i3 1 1 r e serve d tab l e 1 0 . dig ital inpu t selecto r sel0 1 - 0 0 : an al og i n p u t sel e ct or c ont rol sel01 sel00 adc input 0 0 ainl1/ainr1 (default) 0 1 ai nl 2/ a inr 2 1 0 ai nl 3/ a inr 3 1 1 ai nl 4/ a inr 4 table 9. analog input selector
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 41 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 06 h lo ut1 v ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 07 h rout 1 v o l att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 08 h lo ut2 v ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 09 h rout 2 v o l att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 0a h lo ut3 v ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 0b h rout 3 v o l att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 0ch m o n o l v o l att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 0d h m o n o rv ol att 7 att 6 att 5 att 4 att 3 att 2 att 1 att0 defa ul t 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w att 7 - a tt 0: at t e nuat i o n le vel att7 -0 atten u a tion lev e l 00h 0db 01h -0.5db 02h -1.0db : : 7dh -62.5db 7eh -63.0db 7fh -63.5db : feh -127.0db ffh mute (- ) (d efau lt) table 7. attenuation level
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 42 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 0eh swcont1 0 sw51 sw50 sw4 sw31 sw30 sw2 sw1 default 0 0 0 0 0 1 0 0 r/w rd r/w r/w r/w r/w r/w r/w r/w s w51 - 50: sd to 3, sdt i 4 s e l ect or c o nt r o l m ode s w51 s w50 swi t c h a swi t c h b swi t c h c c o m m e nt mode1 0 0 gnd sdtoeq sdto delay no in/output mode2 0 1 sdto eq sdti4 sdto delay in/output before delay mode3 1 0 sdto delay sdtoeq sdti4 in/output after delay mode4 1 1 - - - reserved refer t o figure 32 tabl e 17 . s d t o 3/ s d t i 4 sel ect or c ont rol sd ti4 sd to3 a r1 l1 delay control c sd to d ela y sd t o e q b fi gu re 3 0 . sd to 3/ sdt i 4 b l ock di a g ram s w4: a o ut 3 l/ r pi n o u t p ut c o nt rol 0 : ou tpu t s aou t3l/r (d ef ault) 1 : ou tpu ts aou t2 l/r refer t o figure 32 s w 31 - 30: m g 2 sel ect o r c o n t rol refer t o figure 32 s w 31 s w 30 m g 2 i nput 0 0 sr c 0 1 adc (de faul t ) 1 0 sdt i3 1 1 - tabl e 18 . m g 2 sel ect or c o nt r o l s w 2: m g 1 se l ect or c o nt r o l 0: src (de f aul t ) 1: a dc refer t o figure 32 s w 1: de -em phasi s c ont r o l 0: dem - of f ( d efa u lt) 1: dem -o n ( 4 4. 1k hz ) refer t o figure 32
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 43 - com m a nd register nam e d7 d6 d5 d4 d3 d2 d1 d0 0f h s w c ont 2 0 0 0 s w s w r s w fs w eqs w1 eqsw0 defa ul t 0 0 0 0 0 0 0 0 r/w rd rd r/w r/w r/w r/w r/w r/w sw sw : sw inp u t s our ce s e lect 0: i n put 1 ( de f a ul t ) 1: i n put 2 refer t o figure 32 rsw : rear input source sel ect 0: i n put 1 ( de f a ul t ) 1: i n put 2 refer t o figure 32. fs w : front input source sel ect 0: i n put 1 ( de f a ul t ) 1: i n put 2 refer t o figure 32 eqs w2 - 1: e q ual i zer b l oc k set t i ng m ode eqs w2 eqs w1 swi t c h a swi t c h b c o m m e nt m ode 1 0 0 eqb a n d 2 eqb a n d 7 14 ba n d m ode (de faul t ) mode2 0 1 eqband9 eqband2 4 band + 5 band x 2 mode m ode 3 1 0 eqb a n d 2 eq gai n 2 7 ban d x 2 m ode1 m ode 4 1 1 eqb a n d 2 eq gai n 1 7 ban d x 2 m ode2 refer t o fig ur e 38 ab ou t sw itch a an d b tabl e 19 . e q s w m ode sel e c t 2b a n d m ode1 5band 2band 5b an d 2b a n d m ode2 2band 5band 5b an d 2b a n d m ode3 5band 2band 5b an d 2b a n d m ode4 5band 2band 5band fig u re 31. eqsw1 - 0 setting ex am p l es
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 44 - blocks and circuits construction of command setting src selector adc sdti1 sdti2 sdti3 ain1l/r de-emp ain2l/r ain3l/r ain4l/r <<2 lg1 rg1 <<2 <<2 lg2 rg2 <<2 function1 equalizer 14band function2 function3 function4 function5 l1 r1 l2 r2 delay sdt o 1/ 3 a sdto2/sdti4 xover xover xover a dc d-volume monoin sw 4 c b sw 3 sw 2 sw 1 dac dac dac cl k mc l k o ob i c k ol rck dz f ao ut 1 l ao ut 1 r ao ut 2 l ao ut 2 r ao ut 3 l ao ut 3 r sdto 1 sdto 2 * set by cont5-12(06h~0d) mute1 mute2 i n put 1 i npu t 2 momute fmute rmute swmute l1 v r1v l2 v r2 v l3 v r3v lm v rm v sdto1 sdto2 s pectr um an aly z e r *r efe r t o fi gu re 41 f o r del a y bl oc k. fi gu re 3 2 . ds p b l oc k c o nst r uct i on co mman d 8 0 h sh ift settin g r/w defau lt data 1 (2byte) lg1 2bit left x 4 r/w 0x 2000 data 2 (2byte) rg1 2bit left x 4 r/w 0x 2000 data 3 (2byte) lg2 2bit left x 4 r/w 0x 2000 data 4 (2byte) rg2 2bit left x 4 r/w 0x 2000 data 5 (2byte) dummy - - -
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 45 - functi on 1 (hi g h freque ncy exp a nsion) z - 1 z - 1 z - 1 z - 1 <<1 a 00 a0 1 a02 b01 b02 z - 1 z - 1 z - 1 z - 1 <<1 a10 a1 1 a12 b11 b12 z - 1 z - 1 z - 1 z - 1 <<1 a00 a 01 a02 b01 b02 z - 1 z - 1 z - 1 z - 1 <<1 a1 0 a11 a12 b1 1 b12 hi gho ut hi g h ga i n r << 1 << 1 thrgainr <<1 <<1 th rgai nl highgainl lch rch hi i n hi in highout s i ng l e p r e c is i on multiplier mu lt ip li er si ngl e pre c isi o n single precision sing le pr eci sio n fi gu re 3 3 . fu n c t i on1 b l oc k d i agram c o m m a nd 81 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) thr g ai n l 1bi t le ft x 2 r / w 0x 40 00 control register of lch through gain dat a 2 ( 2 by t e ) thr gai nr 1bi t le ft x 2 r / w 0x 40 00 control register of rch through gain data 3 ( 2 by te) dum m y - - - data 4 ( 2 by te) dum m y - - - data 5 ( 2 by te) dum m y - - - c o m m a nd 82 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) hi g h gai n l 1bi t le ft x 2 r / w 0x 00 00 control register of lch iir out gain dat a 2 ( 2 by t e ) hi g h gai n r 1bi t le ft x 2 r / w 0x 00 00 control register of rch iir out gain data 3 (2b y te) mu ltip lier1 - r/w 0x 40 00 control register of multiplier block data 4 (2b y te) mu ltip lier2 - r/w 0x 00 00 control register of multiplier block data 5 (2b y te) mu ltip lier3 - r/w 0x 00 00 control register of multiplier block c o m m a nd 84 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) hi i n_a 0 2 1bi t le ft x 2 r / w 0x 0 0 00 control register of hi in iir filter dat a 2 ( 2 by t e ) hi i n_a 0 1 1bi t le ft x 2 r / w 0x 00 00 control register of hi in iir filter dat a 3 ( 2 by t e ) hi i n_a 0 0 1bi t le ft x 2 r / w 0x 40 00 control register of hi in iir filter dat a 4 ( 2 by t e ) hi i n _ b 02 1bi t le ft x 2 r / w 0x 00 00 control register of hi in iir filter dat a 5 ( 2 by t e ) hi i n _ b 01 1bi t le ft x 2 r / w 0x 00 00 control register of hi in iir filter c o m m a nd 85 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) hi o u t _ a 12 1bi t le ft x 2 r / w 0x 00 00 control register of hi out iir filter dat a 2 ( 2 by t e ) hi o u t _ a 11 1bi t le ft x 2 r / w 0x 00 00 control register of hi out iir filter dat a 3 ( 2 by t e ) hi o u t _ a 10 1bi t le ft x 2 r / w 0x 40 00 control register of hi out iir filter dat a 4 ( 2 by t e ) hi o u t _ b1 2 1bi t le ft x 2 r / w 0x 00 00 control register of hi out iir filter dat a 5 ( 2 by t e ) hi o u t _ b1 1 1bi t le ft x 2 r / w 0x 00 00 control register of hi out iir filter
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 46 - functi on2 (compress o r) lch rch lpf z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a0 1 a02 b0 1 b02 double precision z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a0 1 a02 b0 1 b02 double precision lpf << 1 th r _ g thr _ g <<1 compresso r fi gu re 3 4 . fu n c t i on2 b l oc k d i agram co mman d c0 h sh ift settin g r/w defau lt co mmen t dat a 1 ( 4 by t e ) lpf _ a0 2 1bi t le ft x 2 r / w 0x 00 000 000 control register of lpf dat a 2 ( 4 by t e ) lpf _ a0 1 1bi t le ft x 2 r / w 0x 00 000 000 control register of lpf dat a 3 ( 4 by t e ) lpf _ a0 0 1bi t le ft x 2 r / w 0x 04 000 000 control register of lpf dat a 4 ( 4 by t e ) lpf _ b 0 2 1bi t le ft x 2 r / w 0x 00 000 000 control register of lpf dat a 5 ( 4 by t e ) lpf _ b 0 1 1bi t le ft x 2 r / w 0x 00 000 000 control register of lpf c o m m a nd 88 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) lpf _ a2 1 1bi t le ft x 2 r/w 0x 00 00 control register of compressor block dat a 2 ( 2 by t e ) lpf _ a2 0 1bi t le ft x 2 r / w 0x 00 00 control register of compressor block dat a 3 ( 2 by t e ) lpf _ b 2 1 1bi t le ft x 2 r / w 0x 00 00 control register of compressor block data 4 ( 2 by te) dum m y - - - control register of compressor block data 5 ( 2 by te) dum m y - - - control register of compressor block c o m m a nd 8c h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) thr _ g 1bi t le ft x 2 r / w 0x 40 00 control register of through gain data 2 ( 2 by te) dum m y - - - data 3 ( 2 by te) dum m y - - - data 4 ( 2 by te) dum m y - - - data 5 ( 2 by te) dum m y - - - c o m m a nd 8d h shi ft set t i ng r / w defa ul t c o m m e nt data 1 ( 2 by te) com p resso r1 - r/w 0x 00 00 control register of compressor block data 2 ( 2 by te) com p resso r2 - r/w 0x 00 00 control register of compressor block data 3 ( 2 by te) com p resso r3 - r/w 0x 00 00 control register of compressor block data 4 ( 2 by te) com p resso r4 - r/w 0x 00 00 control register of compressor block data 5 ( 2 by te) dum m y - - -
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 47 - functi on 3 (su rroun d effect) z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 s i ng l e p r ec i s i on z -n f3 th rg f3outr f3 ou t l f3 th rg lch rch f3 i n r f3 i n l f3 fb g f3 d m a x0 x2 d s a m p l e f 3 iir << 1 << 1 fi gu re 3 5 . fu n c t i on3 b l oc k d i agram c o m m a nd 90 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) f3t h r g 1bi t le ft x 2 r / w 0x 40 00 control register of through gain data 2 (2b y te) f3ou tl 1 b it left x 2 r/w 0x 00 00 control register of lch f3 iir out gain data 3 (2b y te) f3ou tr 1 b it left x 2 r/w 0x 00 00 control register of rch f3 iir out gain data 4 ( 2 by te) dum m y - - - data 5 ( 2 by te) dum m y - - - c o m m a nd 91 h shi ft set t i ng r / w defa ul t c o m m e nt data 1 ( 2 by te) f3 inl - r/w 0x 0000 data 2 ( 2 by te) f3 inr - r/w 0x 00 00 data 3 (2b y te) f3d - r/w 0x 00 00 data 4 (2b y te) f3 fb g - r/w 0x 00 00 data 5 ( 2 by te) dum m y - - - c o m m a nd 92 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) f3 iir _a0 2 1bi t le ft x 2 r/w 0x 0000 dat a 2 ( 2 by t e ) f3 iir _a0 1 1bi t le ft x 2 r / w 0x 00 00 dat a 3 ( 2 by t e ) f3 iir _a0 0 1bi t le ft x 2 r / w 0x 40 00 dat a 4 ( 2 by t e ) f3 iir _b 0 2 1bi t le ft x 2 r / w 0x 00 00 dat a 5 ( 2 by t e ) f3 iir _b 0 1 1bi t le ft x 2 r / w 0x 00 00
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 48 - functi on 4 (b a ss b o os t) z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b0 1 b02 double precision f4thrr f4 th rl lch rch f4 i n r f 4inl f 4 iir <<1 <<1 fi gu re 3 6 . fu n c t i on4 b l oc k d i agram c o m m a nd 93 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) f4t h r l 1bi t le ft x 2 r / w 0x 4000 control register of through gain dat a 2 ( 2 by t e ) f4t h rr 1bi t le ft x 2 r / w 0x 4000 control register of rch through gain data 3 ( 2 by te) f4 inl - r/w 0x 0000 control register of lch f4 iir input gain data 4 ( 2 by te) f4 inr - r/w 0x 0000 control register of rch f4 iir input gain data 5 ( 2 by te) dum m y - - - co mman d c2 h sh ift settin g r/w defau lt co mmen t dat a 1 ( 4 by t e ) f4 iir _a0 2 1bi t le ft x 2 r/w 0x 00000000 control register of f4iir filter dat a 2 ( 4 by t e ) f4 iir _a0 1 1bi t le ft x 2 r / w 0x 00000000 control register of f4 iir filter dat a 3 ( 4 by t e ) f4 iir _a0 0 1bi t le ft x 2 r / w 0x 04000000 control register of f4 iir filter dat a 4 ( 4 by t e ) f4 iir _b 0 2 1bi t le ft x 2 r / w 0x 00000000 control register of f4 iir filter dat a 5 ( 4 by t e ) f4 iir _b 0 1 1bi t le ft x 2 r / w 0x 00000000 control register of f4 iir filter
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 49 - functi on 5 (loudness ) z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 single precision f5outg f5thrg lch rch f 3 iir << 1 << 1 z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 single precision f5iir f 5 iir f5 th rg f5 o u t g fi gu re 3 7 . fu n c t i on5 b l oc k d i agram c o m m a nd 94 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) f5t h r g 1bi t le ft x 2 r / w 0x 40 00 control register of through gain dat a 2 ( 2 by t e ) f5 out g 1bi t le ft x 2 r / w 0x 00 00 control register of f5 iir out gain data 3 ( 2 by te) dum m y - - - data 4 ( 2 by te) dum m y - - - data 5 ( 2 by te) dum m y - - - c o m m a nd 95 h shi ft set t i ng r / w defa ul t c o m m e nt dat a 1 ( 2 by t e ) f5 iir _a0 2 1bi t le ft x 2 r/w 0x 00 00 control register of f5 iir filter dat a 2 ( 2 by t e ) f5 iir _a0 1 1bi t le ft x 2 r / w 0x 00 00 control register of f5 iir filter dat a 3 ( 2 by t e ) f5 iir _a0 0 1bi t le ft x 2 r / w 0x 40 00 control register of f5 iir filter dat a 4 ( 2 by t e ) f5 iir _b 0 2 1bi t le ft x 2 r / w 0x 00 00 control register of f5 iir filter dat a 5 ( 2 by t e ) f5 iir _b 0 1 1bi t le ft x 2 r / w 0x 00 00 control register of f5 iir filter
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 50 - equaliz er eqgain1 l1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a0 0 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a0 0 a 01 a02 b0 1 b02 z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b0 1 b02 z - 1 z - 1 z - 1 << 1 e qga i n 1 r1 <<1 z - 1 <<1 a0 0 a01 a02 b0 1 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a01 a02 b0 1 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 z - 1 z - 1 a0 0 a01 a02 b01 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 z - 1 z - 1 a 00 a0 1 a02 b01 b02 double precision z - 1 z - 1 <<1 a0 0 a01 a02 b 01 b02 single precision z - 1 z - 1 z - 1 z - 1 <<1 a0 0 a0 1 a02 b01 b02 z - 1 z - 1 <<1 a0 0 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a00 a0 1 a02 b0 1 b02 z - 1 z - 1 <<1 a 00 a01 a02 b01 b02 z - 1 z - 1 <<1 a0 0 a01 a02 b01 b02 z - 1 z - 1 z - 1 a e qga i n 2 l2 <<1 e qga i n 2 r2 <<1 b e q b a nz d1 e q b a nd2 e q b a nd1 e q b a nd2 e q b a nz d8 e q b a nd9 e q b a nd8 e q b a nd9 e q b anz d3 e q b a nd4 e q b anz d 5 e q b a nd6 e q b an z d7 e q b anz d3 e q b a nd4 e q b anz d 5 e q b a nd6 e q b an z d7 e q b anz d1 0 e qb a nd1 1 e qb anz d 12 e qb a nd1 3 e q b an z d14 e q b a nz d10 e q b and 11 e q b an z d12 e q b and 13 e q b anz d1 4 << 1 << 1 << 1 << 1 d o uble p r e c i s i on si n g l e pr e c i s i o n d o u b le p r ec i s io n s i ng l e p r ec i s i on double precision sin g le p r e c is io n d o ub l e p r e c is ion d o uble p r e c i s i o n d oub l e p r ec i s i on d o ub l e p r e c is io n d o ub l e p r e c is ion d o uble p r e c i s i o n d o ub l e p r e c is io n d o u b l e p r ec is io n s i ngle p r ec i s i o n s i ng l e p r e c i s i on s i ngle p r ec i s i on s i ngle p r ec i s i o n s i ng l e p r e c i s i on s i ng l e p r ec is i o n s i ng le p r e c is i o n s i n g l e p r e c is io n s i ng le p r e c is i o n s i ng le p r e c is ion s i n g le p r e c i s io n s i ng le p r e c is ion fi gu re 3 8 . e q u a l i zer b l ock di agram co mman d 4 0 h sh ift settin g r/w defau lt data 1 (2byte) eqgain1 1bit left x 2 r/w 0x 4000 co mman d 4 1 h sh ift settin g r/w defau lt data 1 (2byte) eqgain2 1bit left x 2 r/w 0x 4000 co mman d c3 h sh ift settin g r/w defau lt data 1 (4byte) eqband1_a2 1bit left x 2 r/w 0x 00000000 data 2 (4byte) eqband1_a1 1bit left x 2 r/w 0x 00000000 data 3 (4byte) eqband1_a0 1bit left x 2 r/w 0x 04000000 data 4 (4byte) eqband1_b2 1bit left x 2 r/w 0x 00000000 data 5 (4byte) eqband1_b1 1bit left x 2 r/w 0x 00000000 co mman d 9 6 h sh ift settin g r/w defau lt data 1 (2byte) eqband2_a2 1bit left x 2 r/w 0x 0000 data 2 (2byte) eqband2_a1 1bit left x 2 r/w 0x 0000 data 3 (2byte) eqband2_a0 1bit left x 2 r/w 0x 4000 data 4 (2byte) eqband2_b2 1bit left x 2 r/w 0x 0000 data 5 (2byte) eqband2_b1 1bit left x 2 r/w 0x 0000
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 51 - co mman d c4 h sh ift settin g r/w defau lt data 1 (4byte) eqband3_a2 1bit left x 2 r/w 0x 00000000 data 2 (4byte) eqband3_a1 1bit left x 2 r/w 0x 00000000 data 3 (4byte) eqband3_a0 1bit left x 2 r/w 0x 04000000 data 4 (4byte) eqband3_b2 1bit left x 2 r/w 0x 00000000 data 5 (4byte) eqband3_b1 1bit left x 2 r/w 0x 00000000 co mman d c5 h sh ift settin g r/w defau lt data 1 (4byte) eqband4_a2 1bit left x 2 r/w 0x 00000000 data 2 (4byte) eqband4_a1 1bit left x 2 r/w 0x 00000000 data 3 (4byte) eqband4_a0 1bit left x 2 r/w 0x 04000000 data 4 (4byte) eqband4_b2 1bit left x 2 r/w 0x 00000000 data 5 (4byte) eqband4_b1 1bit left x 2 r/w 0x 00000000 co mman d 9 7 h sh ift settin g r/w defau lt data 1 (2byte) eqband5_a2 1bit left x 2 r/w 0x 0000 data 2 (2byte) eqband5_a1 1bit left x 2 r/w 0x 0000 data 3 (2byte) eqband5_a0 1bit left x 2 r/w 0x 4000 data 4 (2byte) eqband5_b2 1bit left x 2 r/w 0x 0000 data 5 (2byte) eqband5_b1 1bit left x 2 r/w 0x 0000 co mman d 9 8 h sh ift settin g r/w defau lt data 1 (2byte) eqband6_a2 1bit left x 2 r/w 0x 0000 data 2 (2byte) eqband6_a1 1bit left x 2 r/w 0x 0000 data 3 (2byte) eqband6_a0 1bit left x 2 r/w 0x 4000 data 4 (2byte) eqband6_b2 1bit left x 2 r/w 0x 0000 data 5 (2byte) eqband6_b1 1bit left x 2 r/w 0x 0000 co mman d 9 9 h sh ift settin g r/w defau lt data 1 (2byte) eqband7_a2 1bit left x 2 r/w 0x 0000 data 2 (2byte) eqband7_a1 1bit left x 2 r/w 0x 0000 data 3 (2byte) eqband7_a0 2bit left x 4 r/w 0x 2000 data 4 (2byte) eqband7_b2 1bit left x 2 r/w 0x 0000 data 5 (2byte) eqband7_b1 1bit left x 2 r/w 0x 0000 co mman d c6 h sh ift settin g r/w defau lt data 1 (4byte) eqband8_a2 1bit left x 2 r/w 0x 00000000 data 2 (4byte) eqband8_a1 1bit left x 2 r/w 0x 00000000 data 3 (4byte) eqband8_a0 1bit left x 2 r/w 0x 04000000 data 4 (4byte) eqband8_b2 1bit left x 2 r/w 0x 00000000 data 5 (4byte) eqband8_b1 1bit left x 2 r/w 0x 00000000 co mman d 9 a h sh ift settin g r/w defau lt data 1 (2byte) eqband9_a2 1bit left x 2 r/w 0x 0000 data 2 (2byte) eqband9_a1 1bit left x 2 r/w 0x 0000 data 3 (2byte) eqband9_a0 1bit left x 2 r/w 0x 4000 data 4 (2byte) eqband9_b2 1bit left x 2 r/w 0x 0000 data 5 (2byte) eqband9_b1 1bit left x 2 r/w 0x 0000
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 52 - co mman d c7 h sh ift settin g r/w defau lt dat a 1 ( 4 by t e ) eqb a n d 1 0 _ a 2 1bi t le ft x 2 r / w 0x 00000000 dat a 2 ( 4 by t e ) eqb a n d 1 0 _ a 1 1bi t le ft x 2 r / w 0x 00000000 dat a 3 ( 4 by t e ) eqb a n d 1 0 _ a 0 1bi t le ft x 2 r / w 0x 04000000 d a ta 4 (4b y te) eq band1 0_b 2 1 b it lef t x 2 r/w 0x 00000000 d a ta 5 (4b y te) eq band1 0_b 1 1 b it lef t x 2 r/w 0x 00000000 co mman d c8 h sh ift settin g r/w defau lt dat a 1 ( 4 by t e ) eqb a n d 1 1 _ a 2 1bi t le ft x 2 r / w 0x 00000000 dat a 2 ( 4 by t e ) eqb a n d 1 1 _ a 1 1bi t le ft x 2 r / w 0x 00000000 dat a 3 ( 4 by t e ) eqb a n d 1 1 _ a 0 1bi t le ft x 2 r / w 0x 04000000 d a ta 4 (4b y te) eq band1 1_b 2 1 b it lef t x 2 r/w 0x 00000000 d a ta 5 (4b y te) eq band1 1_b 1 1 b it lef t x 2 r/w 0x 00000000 co mman d 9 b h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) eqb a n d 1 2 _ a 2 1bi t le ft x 2 r / w 0x 0000 dat a 2 ( 2 by t e ) eqb a n d 1 2 _ a 1 1bi t le ft x 2 r/w 0x 0000 dat a 3 ( 2 by t e ) eqb a n d 1 2 _ a 0 1bi t le ft x 2 r / w 0x 4000 d a ta 4 (2b y te) eq band1 2_b 2 1 b it lef t x 2 r/w 0x 0000 d a ta 5 (2b y te) eq band1 2_b 1 1 b it lef t x 2 r/w 0x 0000 co mman d 9 c h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) eqb a n d 1 3 _ a 2 1bi t le ft x 2 r / w 0x 0000 dat a 2 ( 2 by t e ) eqb a n d 1 3 _ a 1 1bi t le ft x 2 r / w 0x 0000 dat a 3 ( 2 by t e ) eqb a n d 1 3 _ a 0 1bi t le ft x 2 r / w 0x 4000 d a ta 4 (2b y te) eq band1 3_b 2 1 b it lef t x 2 r/w 0x 0000 d a ta 5 (2b y te) eq band1 3_b 1 1 b it lef t x 2 r/w 0x 0000 co mman d 9 d h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) eqb a n d 1 4 _ a 2 1bi t le ft x 2 r / w 0x 0000 dat a 2 ( 2 by t e ) eqb a n d 1 4 _ a 1 1bi t le ft x 2 r / w 0x 0000 dat a 3 ( 2 by t e ) eqb a n d 1 4 _ a 0 2bi t le ft x 4 r / w 0x 2000 d a ta 4 (2b y te) eq band1 4_b 2 1 b it lef t x 2 r/w 0x 0000 d a ta 5 (2b y te) eq band1 4_b 1 1 b it lef t x 2 r/w 0x 0000
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 53 - cross o v er foutgain rl <<1 xo2 i ir rr <<1 z - 1 <<1 a00 a01 a02 b01 b02 z - 1 z - 1 <<1 a10 a11 a12 b11 b12 z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 z - 1 z - 1 <<1 a10 a11 a12 b11 b12 z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 z - 1 z - 1 <<1 a10 a1 1 a12 b11 b12 z - 1 z - 1 <<1 a20 a21 a22 b2 1 b22 z - 1 z - 1 z - 1 z - 1 <<1 a00 a01 a02 b01 b02 double precision z - 1 z - 1 <<1 a10 a1 1 a12 b11 b12 z - 1 z - 1 <<1 a20 a21 a22 b2 1 b22 single precision z - 1 z - 1 z - 1 <<1 <<1 fou t gain rout ga i n rout ga i n fl fr xo2iir xo2 i ir xo2 i i r xo1 i ir xo1 i i r xo1 i ir xo1 i ir xo 1 i i r xo1 i ir xo3 i ir xo3 i i r a00 ~ c 0 2 a10 ~ b 1 2 s w o u t gai n sw l sw r d oubl e pr ec isi o n d oubl e pr e c is ion d o ubl e p r ecis ion d oubl e pr e c is ion d o ubl e p r ecis ion d oubl e pr e c is ion d o ubl e p r ecis ion d oubl e pr eci s i on d oubl e pr eci s i o n si ngl e p r eci s i o n fi gu re 3 9 . c r o ss o v e r b l oc k di ag ram co mman d 4 2 h sh ift settin g r/w defau lt data 1 (2byte) fout gain 1bit left x 2 r/w 0x 4000 co mman d 4 3 h sh ift settin g r/w defau lt data 1 (2byte) rout gain 1bit left x 2 r/w 0x 4000 co mman d 4 4 h sh ift settin g r/w defau lt data 1 (2byte) swout gain 1bit left x 2 r/w 0x 4000 co mman d c9 h sh ift settin g r/w defau lt data 1 (4byte) xo1iir_a02 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo1iir_a01 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo1iir_a00 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo1iir_b02 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo1iir_b01 1bit left x 2 r/w 0x 00000000
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 54 - co mman d cah sh ift settin g r/w defau lt data 1 (4byte) xo2iir_a02 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo2iir_a01 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo2iir_a00 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo2iir_b02 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo2iir_b01 1bit left x 2 r/w 0x 00000000 co mman d cbh sh ift settin g r/w defau lt data 1 (4byte) xo3iir_a02 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo3iir_a01 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo3iir_a00 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo3iir_b02 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo3iir_b01 1bit left x 2 r/w 0x 00000000 co mman d cch sh ift settin g r/w defau lt data 1 (4byte) xo1iir_a12 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo1iir_a11 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo1iir_a10 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo1iir_b12 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo1iir_b11 1bit left x 2 r/w 0x 00000000 co mman d cdh sh ift settin g r/w defau lt data 1 (4byte) xo2iir_a12 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo2iir_a11 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo2iir_a10 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo2iir_b12 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo2iir_b11 1bit left x 2 r/w 0x 00000000 co mman d ceh sh ift settin g r/w defau lt data 1 (4byte) xo3iir_a12 1bit left x 2 r/w 0x 00000000 data 2 (4byte) xo3iir_a11 1bit left x 2 r/w 0x 00000000 data 3 (4byte) xo3iir_a10 1bit left x 2 r/w 0x 04000000 data 4 (4byte) xo3iir_b12 1bit left x 2 r/w 0x 00000000 data 5 (4byte) xo3iir_b11 1bit left x 2 r/w 0x 00000000 co mman d 9 e h sh ift settin g r/w defau lt data 1 (2byte) xo1iir_a22 1bit left x 2 r/w 0x 0000 data 2 (2byte) xo1iir_a21 1bit left x 2 r/w 0x 0000 data 3 (2byte) xo1iir_a20 1bit left x 2 r/w 0x 4000 data 4 (2byte) xo1iir_b22 1bit left x 2 r/w 0x 0000 data 5 (2byte) xo1iir_b21 1bit left x 2 r/w 0x 0000
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 55 - spectr um analyz er z - 1 <<1 a0 0 a02 b0 1 b02 double precision z - 1 z - 1 z - 1 sa i i r1 sa i i r 4 a3 0 ~ c 32 a50 ~ b52 sa i i r 3 a20 ~ c 22 a50 ~ b52 sa i i r 2 a10 ~ c 12 a50 ~ b52 a5 0 a51 b51 z - 1 z - 1 sas i i r resister | x | >>3 lc h rch d oub l e p r ec i s i o n d o ub l e p r e c is ion d o ub l e p r e c is ion d o ub l e p r e c is ion d o u b l e p r e c is io n si ng l e pr ec i s i on s in g le p r e c is io n fi gu re 4 0 . spe c t r um anal y zer b l oc k di ag ra m co mman d cfh sh ift settin g r/w defau lt dat a 1 ( 4 by t e ) sa iir 1_a 0 2 1bi t le ft x 2 r / w 0x 0ffe2d4d dat a 2 ( 4 by t e ) sa iir 1_a 0 0 1bi t le ft x 2 r / w 0x 0001d2b3 dat a 3 ( 4 by t e ) sa iir 1_ b 02 1bi t le ft x 2 r / w 0x 0c009b92 dat a 4 ( 4 by t e ) sa iir 1_ b 01 1bi t le ft x 2 r / w 0x 07ff1150 data 5 ( 4 by te) dum m y - - - co mman d d0h sh ift settin g r/w defau lt dat a 1 ( 4 by t e ) sa iir 2_a 0 2 1bi t le ft x 2 r / w 0x 0ff51627 dat a 2 ( 4 by t e ) sa iir 2_a 0 0 1bi t le ft x 2 r / w 0x 000ae9d9 dat a 3 ( 4 by t e ) sa iir 2_ b 02 1bi t le ft x 2 r / w 0x 0c03a349 dat a 4 ( 4 by t e ) sa iir 2_ b 01 1bi t le ft x 2 r / w 0x 07f72d4d data 5 ( 4 by te) dum m y - - - co mman d d1h sh ift settin g r/w defau lt dat a 1 ( 4 by t e ) sas iir _a 51 - r / w 0x 00031773 dat a 2 ( 4 by t e ) sas iir _a 50 - r / w 0x 00031773 data 3 ( 4 by te) sas iir _ b 5 1 - r/w 0x 07fba0b8 data 4 ( 4 by te) dum m y - - - data 5 ( 4 by te) dum m y - - - co mman d 9 f h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) sa iir 3_a 2 2 1bi t le ft x 2 r /w 0x fd52 dat a 2 ( 2 by t e ) sa iir 3_a 2 0 1bi t le ft x 2 r / w 0x 02 ae dat a 3 ( 2 by t e ) sa iir 3_ b 22 1bi t le ft x 2 r / w 0x c0e5 dat a 4 ( 2 by t e ) sa iir 3_ b 21 1bi t le ft x 2 r / w 0x 79 fb data 5 ( 2 by te) dum m y - - - co mman d a0h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) sa iir 4_a 3 2 1bi t le ft x 2 r / w 0x f779 dat a 2 ( 2 by t e ) sa iir 4_a 3 0 1bi t le ft x 2 r / w 0x 0887 dat a 3 ( 2 by t e ) sa iir 4_ b 32 1bi t le ft x 2 r/w 0x c2d8 dat a 4 ( 2 by t e ) sa iir 4_ b 31 1bi t le ft x 2 r / w 0x 3449 data 5 ( 2 by te) dum m y - - -
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 56 - each data level rea d of spectrum analyzer. c om m a nd 50 h r / w data1 (2byte) 125hz (default) rd c om m a nd 51 h r / w data1 (2byte) 500hz (default) rd c om m a nd 52 h r / w data1 (2byte) 2khz (default) rd c om m a nd 53 h r / w data1 (2byte) 8khz (default) rd del a y b l oc k ( 1 /fs = 1 /441 00 = app r ox im a t ely 0 . 022 6 m s) = on e u n it c o m m a nd 45 h set t i ng uni t r / w defa ul t data 1 (2b y te) fro n t l1 ou t delay ti me set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0 c o m m a nd 46 h set t i ng uni t r / w default dat a 1 ( 2 by t e ) fr ont r 1 out d e l a y t i m e set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0 c o m m a nd 47 h set t i ng uni t r / w default data 1 (2b y te) rear l2 o u t d e lay ti me set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0 c o m m a nd 48 h set t i ng uni t r / w default data 1 (2b y te) rear r2 ou t d e lay ti me set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0 c o m m a nd 49 h set t i ng uni t r / w default data 1 (2b y te) sw l3 ou t d e lay ti m e set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0 c o m m a nd 4a h set t i ng uni t r / w default data 1 (2b y te) sw r 3 ou t d e l a y ti m e set range (0x0000~0x031a) delay ti m e : 1 / fs un it r/w 0 x 000 0
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 57 - co mman d a1h sh ift settin g r/w defau lt dat a 1 ( 2 by t e ) fr ont l gai n s e t t i ng c o e ffi ci ent 1bi t le ft x 2 r / w 0x 4000 dat a 1 ( 2 by t e ) fr ont r gai n s e t t i ng c o e ffi ci ent 1bi t le ft x 2 r / w 0x 4000 data 1 (2b y te) rear l gain settin g co e ffi ci ent 1bi t le ft x 2 r / w 0x 4000 data 1 (2b y te) rear r gain settin g co effici en t 1 b it left x2 r/w 0x 4000 data 1 ( 2 by te) dum m y - - - co mman d a2h sh ift settin g r/w defau lt data 1 (2b y te) sw l gain settin g c o efficient 1 b it left x2 r/w 0x 4000 dat a 1 ( 2 by t e ) s w r gai n set t i ng c o ef fi ci en t 1bi t le ft x 2 r / w 0x 4000 data 1 ( 2 by te) dum m y - - - data 1 ( 2 by te) dum m y - - - data 1 ( 2 by te) dum m y - - - no te: all d ata are r/ w . wh en t h e d elay ti m e is set o v er its li m it, it will b e set to t h e max i m u m v alu e. s w s w, r s w and fs w bi t s i n 0f h c ont rol i n p u t s o urce set t i ng. exam ple1. input1 l 1 , l2, l3 i npu t2 no d a ta d e l a y m e m o r y 1w o r d= 24 bi t 1 8m s dela y = 7 9 4 w or d ( 44 . 1 k h z x 0. 01 8) fl rl nl l1 ou t (fron t ) l2 ou t (r e a r) l3 ou t (s w ) l c h in pu t 1 << 1 << 1 << 1 exam ple2. input1 l2 , l3 i npu t2 l1 de l a y m e m o ry 1w o r d= 24 bi t 18m s del a y = 7 9 4 w ord (44 . 1 k hz x 0. 01 8) fl rl nl l 1 o u t (fron t ) l2 ou t (rear) l3 ou t (s w ) lch i n put 1 << 1 << 1 << 1 l c h i n pu t 2 fi gu re 4 1 . del a y am ount set t i ng e x am pl e
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 58 - system de sign figure 42 show s system co nn ectio n d iag r a m . a n ev alu a tio n bo ar d (akd760 1a) is availab l e for fast ev alu a tion as well as su ggest i o ns f o r pe ri p h eral ci rc ui t r y . 0.1 u p 0.1u xto mut en 37 38 39 40 41 42 43 44 45 47 46 vss3 re f 1 8 vss4 mono in a inl1 gndin1 a inr1 a i n l2 gn d i n 2 sd to1 / sdto 3 xti ilrck1 ibick1 ibick2 ibick3 sdti1 sdti3 ainl3 vss2 1 2 3 4 5 6 7 8 9 10 11 a inr4 a inr3 ainl4 vcom vss1 vrefh a out1l a out1r a out2l sd t o 2 / sdt i 4 olr ck ob i c k mc k o sc l sda pd n dz f ao u t 3 r a k 7601 a vq a vdd ilrck2 ilrck3 cl k m o d e 24 23 22 21 20 19 18 17 16 14 15 36 35 34 33 32 31 30 29 28 27 26 48 a in r 2 12 aout2 r ao u t 3 l 13 dvdd 25 sdti2 to p v i e w 0.1u 2.2u 0.1u 0.1 u muten digit a l 5 v 2.2u 10u mute mute mute mute mute mute ds p 4 10u analog 5v 10u dsp1 dsp2 dsp3 digital ground a nalog ground fig u r e 42 . syste m co nn ectio n d i agr a m ? x?t a l m ode ( c lkm o de pi n = ? l ?) ? sdt o 3, sdt i 4 sel ect m o de ( d o 2 1- 20 bi t s = ?1 0?, d o 1 1 - 1 0 bi t s = ? 10? ) no te: do no t t a k e cu rren t from th e ref18 pin .
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 59 - 1. groundin g and po w e r suppl y decoupling the a k 7 6 0 1 a re qui re s care f ul at t e nt i o n t o po we r s u p p l y a n d g r ou n d i n g a rra ngem e nt s. av d d a n d d v d d a re us ual l y su ppl i e d f r om t h e sy st em ?s an al og su p p l y . i f av d d a n d d v d d a r e s u ppl i e d se parat e l y , t h e p o w er -u p s e que nce i s n o t critical. v s s1, v s s2, vss3 and v s s4 of the a k 7601a sho u ld be co nnect ed t o the a n a log g r ound pla n e. system an alog g r ou nd an d d i g ital g r ou nd shou ld b e co nn ected tog e th er near to where th e supp lies ar e br oug h t on to t h e p r i n ted circuit board. decoupling ca p acitors s h ould be a s near t o t h e AK7601A a s possi ble, with the sm all value ce ram i c capacitor bei n g the nearest. 2. voltage reference inputs th e inpu t vo ltag e to t h e vrefh p i n sets th e an alog o u t p u t ra ng e. usu a lly th e vrefh p i n is co nn ected to th e avdd pin and a 0.1 f ceram ic capacitor is c o nnected betwee n th e av dd p in and t h e v s s1 p in. v com is a sign al gro und o f t h is chip (avdd/2). t h e elect ro lytic cap acito r aro und 2 . 2 f at t ached bet w een the vc om pin an t h e vss1 pin elim inates the effect s of hi g h fre que ncy noi s e . t h e ce ram i c cap acito r in p a rticu l ar shou ld be connecte d as close as possi ble to t h e pin. no l o ad c u rre nt m a y be t a ke n fr o m t h e vc om pi n. al l si gnal s , es peci al l y cl ock, sh o u l d be k e pt away fr om t h e vr e f h pi n and t h e vc o m pi n i n or de r t o av oi d u n wa n t e d c o upl i n g i n t o t h e ak 7 6 0 1 a . 3. analog in puts th e ad c su ppo r ts sing le- e nded an d pseudo -d if f e r e n tial in pu ts. it is b i ased to vcom vo ltag e (avdd/ 2 ) in tern ally b y 45k ? (typ). t h e inputs si gnal range scales wi th nom i nally at 0.65 x vrefh vpp (typ). t h e AK7601A c a n acce pt input vol t a ge f r om v ss1 t o a v d d . the o u t p ut c o de fo rm at i s 2' s com p l e m e nt . i n p u t dc of fset i s cancel e d by an i n t e g r at ed h igh -p ass filter. th e ak760 1a sam p les th e analo g i n pu t at 64 fs. a d i g ital fi lter rem o v es the no ise o v e r the stop b a nd atten u ation lev el, ex cep t for a b a n d of in tegral m u l tip licat io n o f 64 fs. ak760 1a h a s an in t e g r ated an ti-ali a s rc filter in o r d e r t o redu ce th e noi se at 6 4 f s . 4. analog o utput the dac o u t p ut i s si n g l e -e nd ed a nd o u t p ut r a nge i s 0 .6 5 x v r efh v pp (t y p ) ce nt ere d on vc om . the bi as v o l t a ge of t h e ex tern al su mmin g ci rcuit is sup p lied ex tern al ly. th e i n pu t data form at is t w o?s co m p li ment . po sitiv e full-scale o u t p u t cor r es po n d s t o 7ff fff h (@ 2 4bi t ) i n put code, neg a tive fu ll scale is 80 0000h (@24 b it) an d vc om v o ltag e id eally is 00 0 0 0 0 h ( @2 4bi t ) . the o u t - of -b an d noi se (sha pi n g noi se ) gene rat e d by t h e i n t e r n al del t a-si gm a m odul at or i s at t e nuat e d b y an in tegrated switch e d capacito r filter (scf) an d a co n t in uo us tim e fil t e r (ctf). dc of fset s on anal o g out put s are el i m i n at ed by ac co u p l i n g si nce a n al o g out put s has d c of fset of vc om .
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 60 - package 1 12 48 1 3 7.0 9.0 7.0 9.0 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0. 05 0.13 0.13 1.7 0 ma x 0 10 0.10 0.30 ~ 0.75 0.5 s s m materials and lead specification packa g e: epoxy lead fram e: copper lead -fin ish: so ld ering p l ate (pb free)
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 61 - marking ak 7 6 0 1 a vq xxxx xxx 1 1) pi n # 1 i ndi c a t i on 2) dat e c ode: xx x xx x x( 7 di gi t s) 3) m a r k i n g c o de: a k 7 6 0 1 a vq dat e ( y y/ m m / dd ) r e vi si on r eason page c ont e n t s 12/ 07/ 11 00 fi rst e di t i on revision h i story
[ ak7 601 a ] ms14 46 -e-0 0 2 012 /07 - 62 - impo rt an t noti ce z these products and thei r s p ecifications a r e s u bject t o c h ange without notice. w h en y o u consid er an y u s e or ap p licatio n of th ese p r od u c ts, p l ease m a k e in qu iries t h e sal e s office o f asah i kasei m i crode vi ces c o r p o r at i o n ( a km ) o r a u t h ori zed di st ri b u t o r s as t o cu rre nt st at us o f t h e pr od uct s . z descri p tio ns of ex tern al circu its, app licatio n ci rcu its, s o ft ware a n d ot he r rel a t e d i n f o r m at i on co nt ai ned i n t h i s d o c u m en t are p r ov id ed on ly to illu strate th e o p e ration and ap p licatio n ex am p les o f th e semico n d u c tor pro d u c ts. yo u are fu lly respon sib le fo r th e i n corp oratio n of t h ese ex tern al circu its, app licatio n ci rcu its, so ftware and o t h e r related in fo rm atio n in th e d e si g n of y o ur eq u i p m en t s . akm assu mes no respon sibilit y fo r an y lo sses in cu rred b y yo u or th ird p a rties arisin g fro m th e u s e of th ese informatio n h e rei n . akm assu m e s n o liab ility fo r in fring e m e n t o f an y p a ten t , i n t e l l ect ual pr o p ert y , or ot her ri g h t s i n t h e a p pl i cat i on or us e o f s u ch i n fo r m at i on co nt ai n e d herei n . z any e x po rt o f t h ese p r od uct s , or de vi ces or s y st em s cont ai n i ng t h em , m a y req u i re a n e x p o rt l i cense o r o t her of fi ci al app r oval u nde r t h e l a w an d re gul at i o ns of t h e co unt ry o f e x po rt pe rt ai ni n g t o cust om s and t a ri ffs , c u r r enc y excha n ge, or st rat e gi c m a t e ri al s. z akm products are neither int e nde d nor aut h orize d for use as critical compone n ts note1 ) in an y safety, life supp ort, o r othe r hazard related de vice or system no t e 2 ) , an d akm assu m e s n o respo n sib ility for su ch u s e, ex cept for th e u s e app r ove d wi t h t h e ex p r ess wri t t e n co nse n t by r e pre s ent a t i v e di rect or o f a k m . as use d h e re: note1 ) a c r i t i cal com pone nt i s o n e wh ose fa i l u re t o f u nct i o n or pe rf o r m m a y reaso n a b l y be e xpect e d t o resul t , wh et h er d i rectly or i n d i rectly, in th e loss of t h e safety or e ffe ctiveness of the de vice or sy st em cont ai ni ng i t , an d wh ich m u st therefo r e m eet ve ry h i gh stand a rd s o f p e rform a n ce and reliab i lity. note2 ) a h azar d r e lated d e v i ce or system is o n e d e sign ed or i n tend ed for l if e su ppo r t or main ten a n ce of saf e ty or fo r ap pl i cat i o n s i n m e di ci ne, aero s pace , n u cl ear ene r gy , or ot he r fi el ds , i n w h i c h i t s f a i l u re t o f u nct i on or p e rform m a y reason ab ly b e ex p ected t o resu lt in lo ss o f life o r in si g n i fi can t inju ry or d am ag e to p e rson o r pr o p ert y . z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or othe rwise places t h e p r o d u ct wi t h a t h i r d pa rt y , t o n o t i f y suc h t h i r d pa rt y i n a d vance o f t h e ab ove co nt ent a n d c o n d i t i ons , a n d t h e buy e r o r d i stribu tor ag rees t o assu me an y and all respo n s i b ility a n d liab ility for an d ho ld akm h a rm less fro m an y and all cl aim s ari si ng fr om t h e use of sai d pr o duct i n t h e ab sence o f s u ch n o t i f i cat i on.

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