document no. e0757e11 (ver. 1.1) date published february 2006 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2005-2006 preliminary data sheet 2g bits ddr2 sdram ede2104aase (512m words 4 bits) ede2108aase (256m words 8 bits) description the ede2104aase is a 2g bits ddr2 sdram organized as 67,108,864 words 4 bits 8 banks. the ede2108aase is a 2g bits ddr2 sdram organized as 33,554,432 words 8 bits 8 banks. they are packaged in 68-ball fbga package. features ? power supply: vdd, vddq = 1.8v 0.1v ? double-data-rate architecture: two data transfers per clock cycle ? bi-directional, differential data strobe (dqs and /dqs) is transmitted/received with data, to be used in capturing data at the receiver ? dqs is edge aligned with data for reads: center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge: data and data mask referenced to both edges of dqs ? 8 internal banks for concurrent operation ? data mask (dm) for write data ? burst lengths: 4, 8 ? /cas latency (cl): 3, 4, 5, 6 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average refresh period ? 7.8 s at 0 c tc + 85 c ? 3.9 s at + 85 c < tc + 95 c ? sstl_18 compatible i/o ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance ad justment and on-die- termination for better signal quality ? programmable rdqs, /rdqs output for making 8 organization compatible to 4 organization ? /dqs, (/rdqs) can be disabled for single-ended data strobe operation. ? programmable partial array self refresh ? fbga package with lead free solder (sn-ag-cu) ? rohs compliant
ede2104aase, ede2108aase preliminary data sheet e0757e11 (ver. 1.1) 2 ordering information part number mask version organization (words bits) internal banks speed bin (cl-trcd-trp) package ede2104aase-8g-e EDE2104AASE-6E-E ede2104aase-5c-e a 512m 4 8 ddr2-800 (6-6-6) ddr2-667 (5-5-5) ddr2-533 (4-4-4) 68-ball fbga ede2108aase-8g-e ede2108aase-6e-e ede2108aase-5c-e 256m 8 ddr2-800 (6-6-6) ddr2-667 (5-5-5) ddr2-533 (4-4-4) part number elpida memory density / bank 21: 2gb / 8-bank organization 04: x4 08: x8 power supply, interface a: 1.8v, sstl_18 die rev. package se: fbga (with back cover) speed 8g: ddr2-800 (6-6-6) 6e: ddr2-667 (5-5-5) 5c: ddr2-533 (4-4-4) product family e: ddr2 type d: monolithic device e d e 21 04 a a se - 8g - e environment code e: lead free
ede2104aase, ede2108aase preliminary data sheet e0757e11 (ver. 1.1) 3 pin configurations /xxx indicates active low signal. vdd 1 dq6 (nc)* vddq dq4 (nc)* vddl vss vdd 2 nu/ /rdqs (nc)* vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 3 vss dm/rdqs (dm)* vddq dq3 vss /we ba1 a1 a5 a9 a14 7 vssq dqs vddq dq2 vssdl /ras /cas a2 a6 a11 nc 8 /dqs vssq dq0 vssq ck /ck /cs a0 a4 a8 a13 9 vddq dq7 (nc)* vddq dq5 (nc)* vdd vdd vss (top view) 68-ball fbga note: ( )* marked pins are for 4 organization. ba2 odt ( 8, 4 organization) nc nc a b c d e f g h j k l m n p r t u v w nc nc nc nc nc nc pin name function pin name function a0 to a14 address inputs odt odt control ba0, ba1, ba2 bank select vdd supply voltage for internal circuit dq0 to dq7 data input/output vss ground for internal circuit dqs, /dqs differential data strobe vddq supply voltage for dq circuit rdqs, /rdqs differential data strobe for read vssq ground for dq circuit /cs chip select vref input reference voltage /ras, /cas, /we command input vddl supply voltage for dll circuit cke clock enable vssdl ground for dll circuit ck, /ck differential clock input nc* 1 no connection dm write data mask nu* 2 not usable notes: 1. not internally connected with die. 2. don?t use other than reserved functions.
ede2104aase, ede2108aase preliminary data sheet e0757e11 (ver. 1.1) 4 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
ede2104aase, ede2108aase preliminary data sheet e0757e11 (ver. 1.1) 5 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.
|
