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1. general description the PCT2075 is a temperature-to-digital converter featuring ? 1 ? c accuracy over ? 25 ? c to +100 ? c range. it uses an on-chip band gap temperature sensor and sigma-delta a-to-d conversion technique with an overtem perature detection output that is a drop-in replacement for other lm75 series thermal sensors. the device contains a number of data registers: configuration register (conf) to store the device settin gs such as device operation mode, os operation mode, os po larity and os fault queue; temperature register (temp) to store the digital temp read ing, set-point registers (tos and thyst) to store programmable overtemperature shutdown and hysteresis limits, and programmable temperature sensor sampling time tidle, that can be communi cated by a controller via the 2-wire serial i 2 c-bus fast-mode plus interface. the PCT2075 also includes an open-drain output (os) which becomes active when the temperature exceeds the programmed limits. the os output operates in either of two selectable modes: os comparator mode or os interrupt mode. its active state can be selected as either high or low. the fault queue that defines the number of consecutive faults in order to activate the os output is programmable as well as the set-point limits. the PCT2075 can be configured for different oper ation conditions. it can be set in normal mode to periodically monitor the ambient tem perature, or in shut-down mode to minimize power consumption. the temperature register always stores an 11-bit two?s complement data, giving a temperature resolution of 0.125 ? c. this high temperature resolu tion is particularly useful in applications of measuring precisely the t hermal drift or runaway. when the device is accessed the conversion in process is not interrupted (that is, the i 2 c-bus section is totally independent of the sigma-delta converter sect ion) and accessing the device continuously without waiting at leas t one conversion time between co mmunications will not prevent the device from updating the temp register wit h a new conversion result. the new conversion result will be available immediatel y after the temp register is upd ated. it is also possible to read just one of the temperature register bytes without lock-up. the PCT2075 powers up in the normal operation mode with the os in comparator mode, temperature threshold of 80 ? c and hysteresis of 75 ? c, so that it can be used as a stand-alone thermostat with those pre-defined temperature set points. the default set points can be modified during manufacture and ordered under custom part number. there are three selectable logic address pins with three logic states so that 27 8-pin devices or three 6-pin devices can be connected on the same bus without address conflict. PCT2075 i 2 c-bus fm+, 1 degree c accur acy, digital temperature sensor and thermal watchdog rev. 7 ? 6 march 2014 product data sheet
PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 2 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 2. features and benefits ? pin-for-pin replacement for lm75 series but allows up to 27 devices on the bus ? power supply range from 2.7 v to 5.5 v ? temperatures range from 55 q c to +125 q c ? frequency range 20 khz to 1 mhz with smbus time-out to prevent hanging up the bus ? 1 mhz fast-mode plus 30 ma sda drive allows more devices on the same bus but is backward compatible to fast-mode and standard-mode ? 11-bit adc that offers a temperature resolution of 0.125 q c ? temperature accuracy of: ? 1 q c (max.) from 25 q c to +100 q c ? 2 q c (max.) from 55 q c to +125 q c ? programmable temperature threshold and hysteresis set points during operation ? supply current of <1.0 p a in shut-down mode for power conservation ? stand-alone operation as thermostat at power-up ? esd protection exceeds 2000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? small 8-pin package types: so8, tssop8 and 2 mm u 3mmhwson8 ? small 6-pin package type: tsop6 3. applications ? system thermal management ? personal computers ? electronics equipment ? industrial controllers PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 3 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 4. ordering information [1] PCT2075dp/q900 is aec-q100 compliant. contact i2c.support@nxp.com for ppap. 4.1 ordering options table 1. ordering information type number topside mark package name description version PCT2075d PCT2075 so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCT2075dp p2075 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 PCT2075dp/q900 [1] p2075 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 PCT2075tp 075 hwson8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals, 2 ? 3 ? 0.8 mm sot1069-2 PCT2075gv 075 tsop6 plastic thin small outline package; 6 leads sot1353-1 table 2. ordering options type number orderable part number package packing method minimum order quantity temperature PCT2075d PCT2075d,118 so8 reel 13? q1/t1 *standard mark smd 2500 t amb = ? 55 ? c to +125 ?c PCT2075dp PCT2075dp,118 tssop8 reel 13? q1/t1 *standard mark smd 2500 t amb = ? 55 ? c to +125 ?c PCT2075dp/q900 PCT2075dp/q900j tssop8 reel 13? q1/t1 *standard mark smd 2500 t amb = ? 55 ? c to +125 ?c PCT2075tp PCT2075tp,147 hwson8 reel 7? q2/t3 *standard mark 4000 t amb = ? 55 ? c to +125 ?c PCT2075gv PCT2075gvh tsop6 reel 7? q3/t4 *standard mark 3000 t amb = ? 55 ? c to +125 ?c PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 4 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 5. block diagram 6. pinning information 6.1 pinning fig 1. block diagram of PCT2075 PCT2075 sda v cc scl a0 os a1 gnd a2 002aag634 bias reference band gap temp sensor oscillator power-on reset 11-bit sigma-delta a-to-d converter pointer register tidle/timer comparator/ interrupt counter logic control and interface configuration register thyst register tos register temperature register fig 2. pin configuration for so8 fig 3. pin configuration for tssop8 fig 4. pin configuration for hwson8 fig 5. pin configuration for tsop6 PCT2075d sda v cc scl a0 os a1 gnd a2 002aag635 1 2 3 4 6 5 8 7 PCT2075dp PCT2075dp/q900 sda v cc scl a0 os a1 gnd a2 002aag636 1 2 3 4 6 5 8 7 002aag637 terminal 1 index area 1sda PCT2075tp transparent top view 2scl 3 os 4 8 7 6 5 gnd v cc a0 a1 a2 PCT2075gv a0 sda gnd v cc scl 002aag638 1 2 3 6 os 5 4 PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 5 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 6.2 pin description [1] hwson8 package die supply ground is connected to both the gnd pin and the exposed center pad. the gnd pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the expos ed pad should be soldered to the board using a corresponding thermal pad on the board, and for proper head conduction through the board thermal vias need to be incorporated in the pcb in the thermal pad region. table 3. pin description fo r so8, tssop8 and hwson8 symbol pin description sda 1 digital i/o. i 2 c-bus serial bidirectional data line; open-drain. scl 2 digital input. i 2 c-bus serial clock input. os 3 overtemp shutdown output; open-drain. gnd 4 [1] ground. to be connected to the system ground. a2 5 digital input. user-defined address bit 2. a1 6 digital input. user-defined address bit 1. a0 7 digital input. user-defined address bit 0. v cc 8 power supply. table 4. pin description for tsop6 symbol pin description a0 1 digital input. user-defined address bit 0. gnd 2 ground. to be connected to the system ground. v cc 3 power supply. scl 4 digital input. i 2 c-bus serial clock input. os 5 overtemp shutdown output; open-drain. sda 6 digital i/o. i 2 c-bus serial bidirectional data line; open-drain. PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 6 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7. functional description 7.1 general operation the PCT2075 uses the on-chip band gap sensor to measure the device temperature with the resolution of 0.125 ? c and stores the 11-bit two?s complement digital data, resulted from 11-bit a-to-d conversion, into the device temp register. this temp register can be read at any time by a controller on the i 2 c-bus. reading temperature data does not affect the conversion in progress during the read operation. the PCT2075 can be set to operate in either mode: normal or shutdown. in normal operation mode, the temp-to-digital conver sion is executed every 100 ms or other programmed value and the temp register is updated at the end of each conversion. during each ?conversion period? (t conv ) of about 100 ms, the device takes only about 28 ms, called ?temperature conversion time? (t conv(t) ), to complete a temperature-to-data conversion and then becomes idle for the time remaining in the period. this feature is implemented to significantly reduce the device power dissipation. in shutdown mode, the device becomes idle, data conversion is disabled and the temp register holds the latest result; however, the device i 2 c-bus interface is still active and register write/read operation can be performed. the device operation mode is controllable by programming bit b0 of the configurati on register. the temperature conversion is initiated when the device is powered-up or put back into normal mode from shutdown. in addition, at the end of each conversion in normal mode, the temperature data (or temp) in the temp register is automatically co mpared with the overtemperature shutdown threshold data (or t ots ) stored in the tos register, and the hysteresis data (or t hys ) stored in the thyst register, in order to set the state of the device os output accordingly. the device tos and thyst registers are write/ read capable, and both operate with 9-bit two?s complement digital data. to match with this 9-bit operation, the temp register uses only the 9 msb bits of its 11-bit data for the comparison. t ots must always be higher than t hys . the way that the os output responds to th e comparison operation depends upon the os operation mode selected by configuration bit b1, and the user-defined fault queue defined by configuration bits b3 and b4. in os comparator mode, the os output behaves like a thermostat. it becomes active when the temp exceeds the t ots , and is reset when the temp drops below the t hys . reading the device registers or putting the device into shutdown does not change the state of the os output. the os output in this case can be used to control cooling fans or thermal switches. in os interrupt mo de, the os output is us ed for thermal interruption. when the device is powered-up, the os output is first acti vated only when the temp exceeds the t ots , then it remains active indefinitely unt il being reset by a read of any register. once the os output has been activated by crossing t ots and then reset, it can be activated again only when the temp drops below the t hys ; then again, it remains active indefinitely until being reset by a read of any register. the os interrupt op eration would be continued in this sequence: t ots trip, reset, t hys trip, reset, t ots trip, reset, t hys trip, reset, etc. putting the device into the shutdown mode by setting the bit 0 of the configuration register also resets the os output. PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 7 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog in both cases, comparator mode and interrupt mode, the os output is activated only if a number of consecutive faults, defined by th e device fault queue, has been met. the fault queue is programmable and stored in the two bits, b3 and b4, of the configuration register. also, the os output active state is selectable as high or low by setting accordingly the configuration register bit b2. at power-up, the PCT2075 is put into normal operation mode in os comparator mode, the t ots is set to 80 ? c, the t hys is set to 75 ? c, the os active state is selected low and the fault queue is equal to 1. the temp reading data is 0 ? c and not updated until the first conversion is completed in about 28 ms. the default t ots and t hys is set at the factory and can be modified on custom part number. the os response to the te mperature is illustrated in figure 6 . 7.2 i 2 c-bus serial interface the device can be connected to a compatib le 2-wire serial interface fast-mode plus i 2 c-bus as a slave device under the control of a controller or master device, using two device terminals, scl and sda. the controller must provide the scl clock signal and write/read data to/from the device through the sda terminal. notice that if the i 2 c-bus common pull-up resistors have not been installed as required for i 2 c-bus, then an external pull-up resistor, about 1.5 k ? , is needed for each of these two terminals. the bus communication protocols are described in section 7.10 . (1) os is reset by either reading register or putti ng the device in shutdown mode. it is assumed that the fault queue is met at each t ots and t hys crossing point. fig 6. os response to temperature 002aah455 (1) (1) (1) t ots t hys os reset os active os reset os active os output in comparator mode os output in interrupt mode reading temperature limits PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 8 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.2.1 bus fault time-out if the sda line is held low for longer than t to (25 ms minimum; guaranteed at 35 ms maximum), the device will reset to the idle state (sda releas ed) and wait for a new start condition. this ensures that the device will never hang up the bus shou ld there be conflicts in the transmission sequence. the bus fault time-out can be disabled during manufacture and shipped under custom part number. 7.3 slave address to communicate with the device, the master mu st first address slave devices via a slave address byte. the slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. the device features three address pins to allow up to 27 devices to be addressed on a single bus interface. ta b l e 5 describes the pin logic levels used to properly connect up to 27 8-pin devices. ta b l e 6 describes the pin logic levels used to properly connect up to three 6-pin devices. ?1? indicates the pin is connected to the supply (v cc ); ?0? indicates the pin is connected to gnd; ?float? indicates the pin is left unco nnected. the states of pins a0/a1/a2 are sampled only at power-up. after sampling the address is latched to minimize power dissipation associated with detection. table 5. PCT2075 address table (so8, tssop8, hwson8 packages) no. address pin coding slave address a2 a1 a0 1 0 0 0 1001 000 2 0 0 1 1001 001 3 0 1 0 1001 010 4 0 1 1 1001 011 5 1 0 0 1001 100 6 1 0 1 1001 101 71101001110 81111001111 9 floating 0 0 1110 000 10 floating 0 floating 1110 001 11 floating 0 1 1110 010 12 floating 1 0 1110 011 13 floating 1 floating 1110 100 14 floating 1 1 1110 101 15 floating floating 0 1110 110 16 floating floating 1 1110 111 17 0 floating 0 0101 000 18 0 floating 1 0101 001 19 1 floating 0 0101 010 20 1 floating 1 0101 011 21 0 0 floating 0101 100 22 0 1 floating 0101 101 23 1 0 floating 0101 110 PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 9 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.4 register list the PCT2075 contains four data registers beside the pointer register as listed in ta b l e 7 . the pointer value, read/write capability and default content at power-up of the registers are also shown in ta b l e 7 . 24 1 1 floating 0101 111 25 0 floating floating 0110 101 26 1 floating floating 0110 110 27 floating floating floating 0110 111 table 6. PCT2075 address table (tsop6 package) no. address pin coding slave address a0 1 float 1001 000 2 0 1001 001 3 1 1001 010 table 5. PCT2075 address table (so8, tssop8, hwson8 packages) ?continued no. address pin coding slave address a2 a1 a0 table 7. register table register name pointer value r/w por state description conf 01h r/w 00h configuration register: contains a single 8-bit data byte; to set the device operating condition; default = 0. temp 00h read only 0000h temperature register: contains two 8-bit data bytes; to store the measured temp data. tos 03h r/w 5000h overtemperature shutdown threshold register: contains two 8-bit data bytes; to store the overtemperature shutdown t ots limit; default = 80 ?c. thyst 02h r/w 4b00h hysteresis register: contains two 8-bit data bytes; to store the hysteresis t hys limit; default = 75 ?c. tidle 04h r/w 00h temperature conv ersion cycle default to 100 ms. PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 10 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.4.1 pointer register the pointer register contains an 8-bit data by te, of which the three lsb bits represent the pointer value of the other five registers, and the other five msb bits are equal to 0, as shown in ta b l e 8 and table 9 . the pointer register is not accessible to the user, but is used to select the data register for write/read operation by including the pointer data byte in the bus command. because the pointer value is latched into the pointer register when the bus command (which includes the pointer byte) is executed , a read from the device may or may not include the pointer byte in the statement. to read again a register that has been recently read and the pointer has been preset, the pointer byte does not have to be included. to read a register that is different from the one that has been recently read, the pointer byte must be included. however, a write to the dev ice must always include the pointer byte in the statement. the bus communication protocols are described in section 7.10 . at power-up, the pointer value is equal to 000 b and the temp register is selected; users can then read the temp data with out specifying the pointer byte. anything not shown in ta b l e 9 is reserved and should not be used. table 8. pointer register b7 b6 b5 b4 b3 b[2:0] 00000pointer value table 9. pointer value b2 b1 b0 selected register 0 0 0 temperature register (temp) 0 0 1 configuration register (conf) 0 1 0 hysteresis register (thyst) 0 1 1 overtemperature shutdown register (tos) 1 0 0 idle register (tidle) PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 11 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.4.2 configuration register the configuration register (conf) is a wr ite/read register and contains an 8-bit non-complement data byte that is used to configure the device for different operation conditions. ta b l e 1 0 shows the bit assignments of this register. 7.4.3 temperature register the temperature register (temp) holds the digital result of temperature measurement or monitor at the end of each analog-to-digital conversion. this register is read-only and contains two 8-bit data bytes consisting of one most significant byte (msbyte) and one least significant byte (lsbyte). however, only 11 bits of those two bytes are used to store the temp data in two?s complement format with the resolution of 0.125 ? c. ta b l e 11 shows the bit arrangement of the temp data in the data bytes. when reading register temp, all 16 bits of the two data bytes (msbyte and lsbyte) are provided to the bus and should be all collected by the controller for a valid temperature reading. however, only the 11 most significant bits should be used, and the five least significant bits of the lsbyte are zero and sh ould be ignored. one of the ways to calculate the temp value in ? c from the 11-bit temp data is: 1. if the temp data msbyte bit d10 = 0, then the temperature is positive and temp value ( ? c) = +(temp data) ? 0.125 ? c. 2. if the temp data msbyte bit d10 = 1, then the temperature is negative and te m p v a l u e ( ? c) = ? (two?s complement of temp data) ? 0.125 ? c. table 10. conf register legend: * = default value. bit symbol access value description b[7:5] reserved r/w 000* unused; any val ue written to these bits does not affect operation b[4:3] os_f_que[1:0] r/w os fault queue programming 00* queue value = 1 01 queue value = 2 10 queue value = 4 11 queue value = 6 b2 os_pol r/w os polarity selection 0* os active low 1 os active high b1 os_comp_int r/w os operation mode selection 0* os comparator 1 os interrupt b0 shutdown r/w device operation mode selection 0* normal 1 shutdown table 11. temp register msbyte lsbyte 7654321076543210 d10d9d8d7d6d5d4d3d2d1d0 x x x x x PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 12 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog examples of the temp data and value are shown in ta b l e 1 2 . for 9-bit temp data application in replacing the industry standard lm75, just use only 9 msb bits of the two bytes and disregard 7 lsb of the lsbyte. the 9-bit temp data with 0.5 ? c resolution of the device is defined exac tly in the same way as for the standard lm75 and it is here similar to the tos and thyst registers. a single byte read (msbyte) of the temp re gister is allowed. then the temperature resolution will be 1.00 ? c instead. 7.4.4 overtemperature shutdown threshold (tos) and hysteresis (thyst) registers these two registers, are write/r ead registers, and also called set-point registers. they are used to store the user-defined temperat ure limits, called overtemperature shutdown threshold (t ots ) and hysteresis temperature (t hys ), for the device wa tchdog operation. at the end of each conversion th e temp data will be compared with the data stored in these two registers in order to set the state of the device os output; see section 7.1 . each of the set-point registers contains two 8-bit data bytes consisting of one msbyte and one lsbyte in the same format as the temperature register. however, only 9 bits of the two bytes are used to store the set-point data in two?s complement format with the resolution of 0.5 ? c. ta b l e 1 3 and table 14 show the bit arrangement of the tos data and thyst data in the data bytes. notice that because only 9-bit data are used in the set-point registers, the device uses only the 9 msb of the temp data for data comparison. table 12. temp register value 11-bit binary (two?s complement) hexadecimal value decimal value value 011 1111 1000 3f8 1 016 +127.000 ?c 011 1111 0111 3f7 1 015 +126.875 ?c 011 1111 0001 3f1 1 009 +126.125 ?c 011 1110 1000 3e8 1000 +125.000 ?c 000 1100 1000 0c8 200 +25.000 ?c 000 0000 0001 001 1 +0.125 ? c 000 0000 0000 000 0 0.000 ?c 111 1111 1111 7ff ? 1 ? 0.125 ?c 111 0011 1000 738 ? 200 ? 25.000 ? c 110 0100 1001 649 ? 439 ? 54.875 ? c 110 0100 1000 648 ? 440 ? 55.000 ? c table 13. tos register msbyte lsbyte 7654321076543210 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 13 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog when a set-point register is read, all 16 bits are provided to the bus and must be collected by the controller for a valid temperature. however, only the 9 most significant bits should be used and the 7 lsb of the lsbyte are equal to zero and should be ignored. a single byte read of either tos or thyst is allowed. ta b l e 1 5 shows examples of the limit data and value. 7.4.5 tidle register for the device temperature sensor, the temper ature is measured periodically to save power. when the temperature is being measured, the device burns approximately 70 ? a active current. since the ambient temperature changes slowly, it is unnecessary to let the temperature measurement contin uously active. instead, the dev ice temperature sensor is set to idle for a user-specified time to save power after temperature measurement is done. the tidle register allows users to specify the sampling period to measure the temperature. the register is composed of 5-bi t values tidle[4:0] at pointer address 04h. the values of tidle[7:5] are ?don?t care ? and have no effect on the temperature measurement period. the temperature measurement period can be calculated by tidle[4:0] ? 100 ms. for example, if tidle[4:0] = 00001, the temperature sampling is ?00001? ? 100 ms = 100 ms. the temperature sensor allows a sampling period from 100 ms to 3.1 s by programming ti dle. if tidle is set to ?00000 ?, it will be treated the same as tidle = ?00001? and the temperature sensor will measure temperature at 100 ms period. table 14. thyst register msbyte lsbyte 7654321076543210 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x table 15. tos and thyst limit data and value 11-bit binary (two?s complement) hexadecimal value decimal value value 0 1111 1010 0fa 250 +125.0 ? c 0 0011 0010 032 50 +25.0 ?c 0 0000 0001 001 1 +0.5 ?c 0 0000 0000 000 0 0.0 ?c 1 1111 1111 1ff ? 1 ? 0.5 ?c 1 1100 1110 1ce ? 50 ? 25.0 ?c 1 1001 0010 192 ? 110 ? 55.0 ?c table 16. tidle - temperature idle register (address 04h) bit allocation temperature idle register contains the value of time in between temperature measurements. tidle[4:0] is the 5-bit tidle value. tidle ? 100 ms is the temperature sampling period. bit 7 6 5 4 3 2 1 0 symbol - - - tidle[4] tidle[3] tidl e[2] tidle[1] tidle[0] reset - - - 00001 access - - - r/w r/w r/w r/w r/w PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 14 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog the device temperature sensor powers up to measure temperature every 100 ms, with tidle = 00001 by default. for the PCT2075 with 11-bit accuracy, the adc conversion is about 28 ms. as a result, the PCT2075 will be id le for (100 ms ? 28 ms) = 72 ms between two temperature measurements. 7.5 os output and polarity the os output is an open-drain output and its state represents results of the device watchdog operation as described in section 7.1 . in order to observe this output state, an external pull-up resistor is needed. the resist or should be as large as possible, up to 1.5 k ? , to minimize the temp reading error due to internal heating by the high os sinking current. the os output active state can be selected as high or low by programming bit b2 (os_pol) of register conf: setting bit os_p ol to logic 1 selects os active high and setting bit b2 to logic 0 sets os active low. at power-up, bit os_pol is equal to logic 0 and the os active state is low. 7.6 os comparator and interrupt modes as described in section 7.1 , the device os output res ponds to the result of the comparison between register temp data and the programmed limits, in registers tos and thyst, in different ways depending on the selected os mode: os comparator or os interrupt. the os mode is selected by programming bit b1 (os_comp_int) of register conf: setting bit os_comp_int to logic 1 selects the os interrupt mode, and setting to logic 0 selects the os comparator mode. at power-up, bit os_comp_int is equal to logic 0 and the os comparator is selected. the main difference between the two modes is that in os comparator mode, the os output becomes active when temp has exceeded t ots and reset when temp has dropped below t hys , reading a register or putting the device into shutdown mode does not change the state of the os output; while in os interrupt mode, once it has been activated either by exceeding t ots or dropping below t hys , the os output will remain active indefinitely until reading a register, then the os output is reset. temperature limits t ots and t hys must be selected so that t ots > t hys . otherwise, the os output state will be undefined. PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 15 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.7 os fault queue fault queue is defined as the number of faults that must occur cons ecutively to activate the os output. it is provided to avoid false tripping due to noise. because faults are determined at the end of data conversions, fault queue is also defined as the number of consecutive conversions returning a temperature trip. the value of fault queue is selectable by programming the two bits b4 and b3 (os_f_que[1:0]) in register conf. notice that the programmed data and the fault queue value are not the same. ta b l e 1 7 shows the one-to-one relationship between them. at power-up, fault queue data = 0 and fault queue value = 1. 7.8 shutdown mode the device operation mode is selected by pr ogramming bit b0 (shutdown) of register conf. setting bit shutdown to logic 1 will put the device into shutdo wn mode. resetting bit shutdown to logic 0 will return the device to normal mode. in shutdown mode, the PCT2075 draws a small current of <1.0 ? a and the power dissipation is minimized; the temperature conversion stops, but the i 2 c-bus interface remains active and register write/read operat ion can be performed. when the shutdown is set, the os output will be unchanged in comp arator mode and reset in interr upt mode. 7.9 power-up defaul t and power-on reset the PCT2075 always powers-up in its default state with: ? normal operation mode ? os comparator mode ? t ots = 80 ? c (or as specified for the custom part number) ? t hys = 75 ? c (or as specified for the custom part number) ? os output active state is low ? pointer value is logic 000 (temp) ? smbus time-out enabled (or as spec ified for the custom part number) when the power supply voltage is dropped below the device power-on reset level of approximately 1.0 v (por) for over 2 ? s and then rises up again, the PCT2075 will be reset to its default condition as listed above. in some applications a higher or lower default t ots and t hys values or no smbus time-out may be required. please contact nxp for information on custom part number. table 17. fault queue table fault queue data fault queue value os_f_que[1] os_f_que[0] decimal 001 012 104 116 PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 16 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 7.10 protocols for writing and reading the registers the communication between the host and the de vice must strictly follow the rules as defined by the i 2 c-bus management. the protocols fo r device register read/write operations are illustrated in figure 7 to figure 12 together with the following definitions: 1. before a communication, the i 2 c-bus must be free or not busy. it means that the scl and sda lines must both be released by all devices on the bus, and they become high by the bus pull-up resistors. 2. the host must provide scl clock pulses necessary for the communication. data is transferred in a sequence of 9 scl clock pulses for every 8-bit data byte followed by 1-bit status of the acknowledgement. 3. during data transfer, except the start and stop signals, the sda signal must be stable while the scl signal is high. it means that the sda signal can be changed only during the low duration of the scl line. 4. s: start signal, initiated by the host to start a communication, the sda goes from high to low while the scl is high. 5. rs: re-start signal, same as the start signal, to start a read command that follows a write command. 6. p: stop signal, generated by the host to stop a communication, the sda goes from low to high while the scl is high. the bus becomes free thereafter. 7. w: write bit, when the write/read bit = low in a write command. 8. r: read bit, when the write/read bit = high in a read command. 9. a: device acknowledge bit, returned by th e device. it is low if the device works properly and high if not. the host must release the sda line during this period in order to give the device the control on the sda line. 10. a?: master acknowledge bit, not returned by the device, but set by the master or host in reading 2-byte data. during this clock period, the host must set the sda line to low in order to notify the device that the first byte has been read for the device to provide the second byte onto the bus. 11. na: not acknowledge bit. during this cloc k period, both the device and host release the sda line at the end of a data transfer, the host is then enabled to generate the stop signal. 12. in a write protocol, data is sent from th e host to the device and the host controls the sda line, except during the clock per iod when the device sends the device acknowledgement signal to the bus. 13. in a read protocol, data is sent to the bu s by the device and the host must release the sda line during the time that the device is providing data onto the bus and controlling the sda line, except during the clock per iod when the master sends the master acknowledgement signal to the bus. 14. for best temperature accuracy both temp erature bytes should be read as shown in figure 11 and figure 12 , but for a quick less accurate check/reduce bus transmission then only one byte, the msbyte, needs to be read as shown in figure 9 . PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 17 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog (1) see table 5 or table 6 for device address. fig 7. write configuration register (1-byte data) 002aah777 1 b6ssda scl b5b4b3b2b1b0wa 00000001a 000d4d3d2d1d0a p 23456789123456789123456789 start stop write device acknowledge device acknowledge device acknowledge device address (1) pointer byte configuration data byte (1) see table 5 or table 6 for device address. fig 8. read configuration register including pointer byte (1-byte data) 002aah778 scl sda (next) (next) 123456789123456789 device address (1) pointer byte start re-start write device acknowledge device acknowledge scl (cont.) sda (cont.) 123456789123456789 device address (1) data byte from device stop read master not acknowledged device acknowledge d7 d6 d5 d4 d3 d2 d1 d0 p b6 b5 b4 b3 b2 b1 b0 r a na 00000001a rs b6 s b5 b4 b3 b2 b1 b0 w a (1) see table 5 or table 6 for device address. fig 9. read configuration or temp register with preset pointer (1-byte data) 002aah779 start s scl sda 123456789123456789 device address (1) data byte from device stop read master not acknowledged device acknowledge d7 d6 d5 d4 d3 d2 d1 d0 p b6 b5 b4 b3 b2 b1 b0 r a na PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 18 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog (1) see table 5 or table 6 for device address. fig 10. write tos or thyst register (2-byte data) 002aah780 123456789123456789 d7 sda (cont.) scl (cont.) d6 d5 d4 d3 d2 d1 d0 a d7 d6 d5 d4 d3 d2 d1 d0 a p b6ssda scl b5 b4 b3 b2 b1 b0 w a 0 0 0 0 0 0 p1 p0 a (next) (next) 123456789123456789 device address (1) pointer byte msbyte data lsbyte data start write device acknowledge device acknowledge stop device acknowledge device acknowledge (1) see table 5 or table 6 for device address. fig 11. read temp, tos or thyst register including pointer byte (2-byte data) 123456789 123456789123456789 123456789 b6 b5 b4 b3 b2 b1 b0 r a d7 d6 d5 d4 d3 d2 d1 d0 a' d7 d6 d5 d4 d3 d2 d1 d0 na p 1234567890 b6s b5 b4 b3 b2 b1 b0 w a 0 0 0 0 0 0 p1 p0 a (next) (next) sda scl sda (cont) scl (cont) rs 002aah781 device address (1) pointer byte device address (1) msbyte from device lsbyte from device start re-start write device acknowledge device acknowledge read master acknowledge master not acknowledged device acknowledge stop (1) see table 5 or table 6 for device address. fig 12. read temp, tos or thyst register with preset pointer (2-byte data) 123456789123456789123456789 b6 s b5b4b3b2b1b0 r a d7d6d5d4d3d2d1d0 a' d7d6d5d4d3d2d1d0na p sda scl 002aah782 device address (1) msbyte from device lsbyte from device start read master acknowledge master not acknowledged device acknowledge stop PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 19 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 8. application design-in information 8.1 typical application 8.2 temperature accuracy because the local channel of the temperature sensor measures its own die temperature that is transferred from its body, the temperat ure of the device body must be stabilized and saturated for it to provide the stable readings. because the device operates at a low-power level, the thermal gr adient of the device package has a minor effect on the measurement. the accuracy of the measuremen t is more dependent upon the definition of the environment temperature, which is affect ed by different factors: the printed-circuit board on which the device is mounted; the air flow contacting the device body (if the ambient air temperature and the printed-circ uit board temperature are much different, then the measurement may not be stable because of the different thermal paths between the die and the environment). the stabilized temperature liq uid of a thermal bath will provide the best temperature environment when the device is completely dipped into it. a thermal probe with the device mounted inside a sealed-end metal tube located in consistent temperature air also provides a good method of temperature measurement. 8.3 noise effect the device design includes the implementation of basic features for a good noise immunity: ? the 50 ns low-pass filter on both the bus pins scl and sda; ? the hysteresis of the threshold voltages to the bus input signals scl and sda, about 500 mv minimum; ? all pins have esd protection circuitry to prevent damage during electrical surges. the esd protection on the address, os, scl and sda pins it to ground. the latch-back based device breakdown voltage of addres s/os is typically 11 v and scl/sda is typically 9.5 v at any supply voltage but will vary over process and temperature. since fig 13. PCT2075 typical application 002aag640 0.1 f 1.5 k digital logic PCT2075 detector or interrupt line bus pull-up resistors i 2 c-bus 8 2 scl sda a2 a1 a0 5 6 1 7 4 3 os v cc power supply gnd 1.5 k 1.5 k PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 20 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog there are no protection diodes from scl or sda to v cc , the device will not hold the i 2 c lines low when v cc is not supplied and therefore allow continued i 2 c-bus operation if the device is de-powered. however, good layout practices and extra noise filters are recommended when the device is used in a very noisy environment: ? use decoupling capacitors at v cc pin. ? keep the digital traces away from switching power supplies. ? apply proper terminations for the long board traces. ? add capacitors to the scl and sda lin es to increase the low-pass filter characteristics. 9. limiting values 10. recommended operating conditions table 18. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage ? 0.3 +6.0 v v i input voltage at input pins ? 0.3 +6.0 v i i input current at input pins ? 5.0 +5.0 ma i o(sink) output sink current on pin os - 60 ma v o output voltage on pin os ? 0.3 +6.0 v t stg storage temperature ? 65 +150 ?c t j junction temperature - 150 ?c table 19. recommended operating characteristics symbol parameter conditions min typ max unit v cc supply voltage 2.7 - 5.5 v t amb ambient temperature ? 55 - +125 ?c PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 21 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 11. static characteristics [1] typical values are at v cc = 3.3 v and t amb =25 ? c. table 20. static characteristics v cc = 2.7 v to 5.5 v; t amb = ? 55 ? c to +125 ? c; unless otherwise specified. symbol parameter conditions min typ [1] max unit t acc temperature accuracy t amb = ? 25 ? c to +100 ?c ? 1- +1 ?c t amb = ? 55 ? c to +125 ?c ? 2- +2 ?c t res temperature resolution 11-bit digital temp data - 0.125 - ?c t conv(t) temperature conversion time normal mode - 28 - ms t conv conversion period normal mode - 0.1 3.2 s v por power-on reset voltage - - 2.6 v i cc(av) average supply current normal mode: i 2 c-bus inactive - 125 300 ? a normal mode: i 2 c-bus active; f scl = 1000 khz -200400 ? a shutdown mode t amb =25 ?c- < 0 . 1 - ? a t amb =85 ?c- < 1 - ? a t amb =125 ?c- - 2 0 ? a v ih high-level input voltage digital pins (scl, sda, a2 to a0) 0.7 ? v cc -v cc +0.3 v v il low-level input voltage digital pins ? 0.3 - 0.3 ? v cc v v i(hys) hysteresis of input voltage scl and sda pins - 300 - mv a2, a1, a0 pins - 150 - mv i ih high-level input current digital pins; v i =v cc t amb =25 ?c- < 0 . 1 - ? a t amb =85 ?c (PCT2075d, dp and tp only) -<1- ? a t amb =85 ? c (PCT2075gv only) - <2 - ? a t amb =125 ?c (PCT2075d, dp and tp only) --10 ? a t amb =125 ? c (PCT2075gv only) - - 20 ? a i il low-level input current digital pins; v i = 0 v ? 1.0 - +1.0 ? a v ol low-level output voltage os pin; i ol =20ma - - 0.4 v sda pin; i ol =20ma - - 0.4 v i lo output leakage current sda and os pins; v oh =v cc --20 ? a n fault number of faults programmable; conversions in overtemperature-shutdown fault queue 1-6 t ots overtemperature shutdown temperature default value - 80 - ?c t hys hysteresis temperatur e default value - 75 - ?c c i input capacitance digital pins - 20 - pf PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 22 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog fig 14. average supply current versus temperature; i 2 c-bus inactive fig 15. average supply current versus temperature; i 2 c-bus active fig 16. shutdown mode supply current versus temperature fig 17. low-level output voltage on os pin versus temperature; i ol =4ma fig 18. low-level output current on os pin versus temperature; v ol =0.4v fig 19. low-level input current versus temperature; digital pins 100 150 50 200 250 i dd (a) 0 t amb (c) ?75 125 75 ?25 25 002aah437 v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 0 300 200 100 400 002aah438 i dd (a) v dd = 5.5 v 4.5 v 3.3 v 2.7 v 4 6 2 8 10 i dd (a) 0 t amb (c) ?75 125 75 ?25 25 002aah439 v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 0 0.30 0.20 0.10 0.40 002aah440 v ol (v) v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 0 60 40 20 80 002aah441 i ol (ma) v dd = 5.5 v 4.5 v 3.3 v 2.7 v ?0.2 0.2 ?0.6 0.6 1.0 i il (a) ?1.0 t amb (c) ?75 125 75 ?25 25 002aah442 v dd = 5.5 v 4.5 v 3.3 v 2.7 v PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 23 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog fig 20. high-level input current versus temperature; digital pins fig 21. low-level output voltage on sda pin versus temperature; i ol =20ma fig 22. low-level output current on sda pin versus temperature; v ol =0.4v fig 23. temperature accuracy versus temperature; v cc =2.8v to 5.5v fig 24. power-on reset threshold voltage versus temperature; rising v cc fig 25. power-on reset voltage versus temperature; falling v cc 4 6 2 8 10 i ih (a) 0 t amb (c) ?75 125 75 ?25 25 002aah443 v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 0 0.30 0.20 0.10 0.40 002aah453 v ol (v) v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 0 60 40 20 80 002aah454 i ol (ma) v dd = 5.5 v 4.5 v 3.3 v 2.7 v t amb (c) ?75 125 75 ?25 25 ?2.0 1.0 0 ?1.0 2.0 002aah444 t acc (c) 1.0 2.0 3.0 v th(por) (v) 0 t amb (c) ?75 125 75 ?25 25 002aah451 1.0 2.0 3.0 v por (v) 0 t amb (c) ?75 125 75 ?25 25 002aah452 PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 24 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 12. dynamic characteristics [1] these specifications are guaranteed by design and not tested in production. [2] this is the sda time low fo r reset of serial interface. [3] holding the sda line low for a time greater than t to will cause the device to reset sda to the idle state of the serial bus communication (sda set high). table 21. i 2 c-bus interface dynamic characteristics [1] v cc = 2.7 v to 5.5 v; t amb = ? 55 ? c to +125 ? c; unless otherwise specified. symbol parameter conditions min typ max unit f scl scl clock frequency see figure 26 20 - 1000 khz t high high period of the scl clock 0.26 - - ? s t low low period of the scl clock 0.5 - - ? s t hd;sta hold time (repeated) start condition 0.26 - - ? s t su;dat data set-up time 50 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.26 - - ? s t f fall time sda and os outputs; c l = 450 pf; i ol =30ma -120-ns t to(smbus) smbus time-out time [2] [3] 25 - 35 ms fig 26. timing diagram sda scl 002aah456 t f s sr p s t hd;sta t low t r t su;dat t f t hd;dat t high t su;sta t hd;sta t sp t su;sto t r t buf 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc PCT2075 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 7 ? 6 march 2014 25 of 37 nxp semiconductors PCT2075 i 2 c-bus fm+ digital temperature sensor and thermal watchdog 13. package outline fig 27. package outline sot96-1 (so8) 8 1 , 7 $ p d [ $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5 ( ) ( 5 ( 1 & |