? semiconductor components industries, llc, 2014 june, 2014 ? rev. 1 1 publication order number: NCS325/d NCS325 50 v offset, 0.25 v/ c, 35 a, zero-drift operational amplifier the NCS325 is a cmos operational amplifier providing precision performance. the zero?drift architecture allows for continuous auto?calibration, which provides very low offset, near?zero drift over time and temperature, and near flat 1/f noise at only 35 a (max) quiescent current. these benefits make it ideal for precision dc applications. the NCS325 provides rail?to?rail input and output performance and is optimized for low voltage operation as low as 1.8 v and up to 5.5 v. the NCS325 is available in the space?saving sot23?5 package. features ? low offset voltage: 14 v typ, 50 v max at 25 c ? zero drift: 0.25 v/ c max ? low noise: 1 vpp, 0.1 hz to 10 hz ? quiescent current: 21 a typ, 35 a max at 25 c ? supply voltage: 1.8 v to 5.5 v ? rail?to?rail input and output ? internal emi filtering ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? battery powered instruments ? temperature measurements ? transducer applications ? electronic scales ? medical instrumentation ? current sensing tsop?5 (sot23?5) sn suffix case 483 marking diagram 5 4 (top view) pin connections http://onsemi.com a = assembly location y = year w = work week = pb?free package (note: microdot may be in either location) 1 5 32a ayw 1 5 device package shipping ? ordering information NCS325sn2t1g tsop?5 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. out vss in+ vdd in? ? + 2 1 3
NCS325 http://onsemi.com 2 absolute maximum ratings over operating free?air temperature, unless otherwise stated. parameter rating unit supply voltage 6 v input and output pins input voltage (note 1) (vss) ? 0.3 to (vdd) + 0.3 v input current (note 1) 10 ma output short circuit current (note 2) continuous temperature operating temperature ?40 to +150 c storage temperature ?65 to +150 c junction temperature ?65 to +150 c esd ratings (note 3) human body model (hbm) 4000 v machine model (mm) 200 v other ratings latch?up current (note 4) 100 ma msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. input terminals are diode?clamped to the power?supply rails. in put signals that can swing more than 0.3 v beyond the supply r ails should be current limited to 10 ma or less 2. short?circuit to ground. 3. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (jedec standard: jesd22?a114) esd machine model tested per aec?q100?003 (jedec standard: jesd22?a115) 4. latch?up current tested per jedec standard: jesd78. thermal information thermal metric symbol sot23?5 unit junction to ambient (note 5) ja 235 c/w 5. as mounted on an 80x80x1.5 mm fr4 pcb with 650 mm 2 and 2 oz (0.034 mm) thick copper heat spreader. following jedec jesd/eia 51.1, 51.2, 51.3 test guidelines operating conditions parameter symbol range unit supply voltage (v dd ? v ss ) v s 1.8 to 5.5 v specified operating range t a ?40 to 125 c input common mode voltage range v icmr v ss ?0.1 to v dd +0.1 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
NCS325 http://onsemi.com 3 electrical characteristics: v s = 1.8 v to 5.5 v at t a = +25 c, r l = 10 k connected to midsupply, v cm = v out = midsupply, unless otherwise noted. boldface limits apply over the specified temperature range, t a = ?40 c to 125 c, guaranteed by characterization and/or design. parameter symbol conditions min typ max unit input characteristics offset voltage v os v s = +5v 14 50 v offset voltage drift vs temp v os / t t a = ?40 c to 125 c 0.02 0.25 v/ c input bias current i ib 50 pa input offset current i os 100 pa common mode rejection ratio cmrr v ss +0.3 < v cm < v dd ? 0.3, v s = 1.8 v 85 108 db v ss +0.3 < v cm < v dd ? 0.3, v s = 5.5 v 90 110 v ss ?0.1 < v cm < v dd + 0.1, v s = 1.8 v 80 v ss ?0.1 < v cm < v dd + 0.1, v s = 5.5 v 92 input resistance r in 15 g input capacitance c in differential 1.8 pf common mode 3.5 pf output characteristics output voltage high v oh output swing within v dd 12 100 mv output voltage low v ol output swing within v ss 8 100 mv short circuit current i sc 5 ma open loop output impedance z out?ol f = 350 khz, i o = 0 ma, v s = 1.8 v 1.4 k f = 350 khz, i o = 0 ma, v s = 5.5 v 2.7 capacitive load drive c l see figure noise performance voltage noise density e n f in = 1 khz 100 nv / hz voltage noise e p?p f in = 0.01 hz to 1 hz 0.3 v pp f in = 0.1 hz to 10 hz 1 v pp current noise density i n f in = 10 hz 0.3 pa / hz dynamic performance open loop voltage gain a vol r l = 10 k , v s = 5.5 v 114 db gain bandwidth product gbwp c l = 100 pf, r l = 10 k 350 khz phase margin m c l = 100 pf 60 gain margin a m c l = 100 pf 20 db slew rate sr g = +1, c l = 100 pf, vs = 1.8 v 0.10 v/ s g = +1, c l = 100 pf, vs = 5.5 v 0.16 power supply power supply rejection ratio psrr 100 107 db t a = ?40 c to 125 c 95 turn?on time t on v s = 5 v 100 s quiescent current i q no load 21 35 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCS325 http://onsemi.com 4 12 10 8 6 4 2 0 frequency offset voltage ( v) figure 1. offset voltage distribution 03 30 27 24 69 21 18 12 15 v s = 5 v v cm = midsupply t a = 25 c sample size = 31 100 gain (db) frequency (hz) figure 2. gain and phase vs. frequency 80 60 40 20 0 ?20 ?40 ?60 ?80 90 60 30 0 ?30 ?60 ?90 ?120 ?150 ?180 phase ( c) gain, v s = 1.8 v gain, v s = 5.5 v phase, v s = 1.8 v phase, v s = 5.5 v phase figure 3. cmrr vs. frequency figure 4. psrr vs. frequency figure 5. output voltage swing vs. output current iib+ iib? 500 input bias current (pa) common mode voltage (v) ?1 ?0.8 ?0.6 ?0.4 0.8 1 400 300 200 100 0 ?100 ?200 ?300 ?400 ?500 ?0.2 0 0.6 0.4 0.2 figure 6. input bias current vs. common mode voltage, v s = 1.8 v v s = 1.8 v t a = 25 c gain 100 cmrr (db) frequency (hz) 10 100k 90 80 70 60 50 40 30 20 10 0 100 1000 10k v s = 1.8 v v s = 5 v 100 psrr (db) frequency (hz) 90 80 70 60 50 40 30 20 10 0 10 100k 100 1000 10k 1m t a = 25 c v ss v dd v s = 5 v r l = 10 k t a = 25 c t a = 25 c 3 output swing (v) output current (ma) 010 123 2 1 0 ?1 ?2 ?3 456789 10 100k 100 1000 10k 1m v oh , v s = 1.8 v v ol , v s = 5 v v oh , v s = 5 v v ol , v s = 1.8 v
NCS325 http://onsemi.com 5 500 input bias current (pa) common mode voltage (v) figure 7. input bias current vs. common mode voltage, v s = 5.5 v ?3 ?2.5 2.5 2 1.5 ?2 ?1.5 1 0.5 ?1 0 input bias current (pa) temperature ( c) figure 8. input bias current vs. temperature ?50 ?25 0 100 125 150 figure 9. input bias current vs. input differential voltage figure 10. large signal step response figure 11. small signal step response 3 voltage (v) time ( s) ?100 200 figure 12. positive over voltage recovery iib+ iib? 400 300 200 100 0 ?100 ?200 ?300 ?400 ?500 3 3.5 iib+ iib? v s = 5.5 v 500 400 300 200 100 0 ?100 ?200 ?300 ?400 ?500 25 50 70 1.0 input bias current (pa) differential voltage (v) ?1 ?0.75 1 0.75 0.5 0.25 0 ?0.25 ?0.5 ?0.75 ?1 ?0.5 ?0.25 0 0.25 0.5 0.75 iib+ iib? t a = 25 c output voltage (v) time ( s) ?200 ?100 0 300 400 500 3 100 200 2 1 0 ?1 ?2 ?3 v s = 5.0 v r l = 10 k c l = 10 pf av = 1 v/v 0.2 output voltage (v) time ( s) ?200 ?100 500 0 100 200 300 400 0.1 0 ?0.1 ?0.2 v s = 5.0 v r l = 10 k c l = 10 pf av = 1 v/v 2 1 0 ?1 ?2 ?3 0 ?50 50 100 150 input output v s = 5.0 v r l = 10 k c l = 10 pf av = ?10 v/v v s = 5.5 v t a = 25 c
NCS325 http://onsemi.com 6 3 voltage (v) time ( s) figure 13. negative over voltage recovery 700 setting time ( s) gain (db) figure 14. setting time vs. closed loop gain 1 10 100 figure 15. small signal overshoot vs. load capacitance figure 16. 0.1 hz to 10 hz noise figure 17. voltage noise spectral density vs. frequency 1000 current noise (pa/ hz ) frequency (hz) figure 18. current noise spectral density vs. frequency input output v s = 5.0 v r l = 10 k c l = 10 pf av = ?10 v/v 2 1 0 ?1 ?2 ?3 ?100 200 0 ?50 50 100 150 600 500 400 300 200 100 0 v s = 5.0 v r l = 10 k output = 4 v step 70 overshoot (%) load capacitance (pf) 10 100 1000 60 50 40 30 20 10 0 r l = 10 k input = 50 mv v s = 1.8 v v s = 5.5 v voltage (500 nv/div) time (1 s/div) 1000 voltage noise (nv/ hz ) frequency (hz) 10 100 1000 100 10 1 v s = 1.8 v v s = 5.5 v 100 10 1 0.1 0.01 10 100 1000 10k 0.1 1 v s = 1.8 v v s = 5.5 v
NCS325 http://onsemi.com 7 0.2 slew rate (v/ s) temperature ( c) figure 19. slew rate vs. temperature figure 20. quiescent current vs. temperature figure 21. turn?on response ?40 140 0 ?20 20 100 120 0.18 0.16 0.14 0.12 0.1 0.08 0.06 40 60 80 v s = 5.0 v v in = 5 v pp r l = 10 k c l = 100 pf av = ?10 v/v v s = 1.8 v v in = 1.5 v sr+ sr? sr? sr+ 30 quiescent current ( a) temperature ( c) 25 20 15 10 5 0 v s = 5.5 v v s = 1.8 v 6 v dd voltage (v) time ( s) ?20 120 0 20 100 40 60 80 5 4 3 2 1 0 ?1 v dd pulse output r l = 10 k t a = 25 c ?40 140 0 ?20 20 100 120 40 60 80 5 4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.90 4.89 4.88 4.87 4.86 output voltage (v)
NCS325 http://onsemi.com 8 applications information offset correction the NCS325 uses an auto zero architecture to establish low input offset voltage and noise. with an internal clock of 125 khz, the amplifier offset is calibrated automatically every 8 s. the amplifier requires approximately 100 s to achieve the specified offset voltage. input voltage the NCS325 has a rail?to?rail common mode input voltage range. the typical input bias current of the NCS325 is 50 pa. in an overdriven condition, the output is driven to a supply rail. in this case, the feedback path cannot achieve in? = in+. there are no clamp diodes between in+ and in? to limit this differential voltage. diodes between the inputs and the supply rails keep the input voltage from exceeding the rails. 10 k 10 k + ? vdd vss in+ in? figure 22. equivalent input circuit emi susceptibility and input filtering op amps have varying amounts of emi susceptibility. semiconductor junctions can pick up and rectify emi signals, creating an emi?induced voltage offset at the output, adding another component to the total error. input pins are the most sensitive to emi. the NCS325 integrates a low?pass filter to decrease its sensitivity to emi. application circuits low?side current sensing the goal of low?side current sensing is to detect over?current conditions or as a method of feedback control. a sense resistor is placed in series with the load to ground. typically, the value of the sense resistor is less than 100 m to reduce power loss across the resistor. the op amp amplifies the voltage drop across the sense resistor with a gain set by external resistors r1, r2, r3, and r4 (where r1 = r2, r3 = r4). precision resistors are required for high accuracy, and the gain is set to utilize the full scale of the adc for the highest resolution. + ? load vdd adc microcontroller control r sense r 1 r 2 r 3 r 4 vdd vdd v load figure 23. low?side current sensing
NCS325 http://onsemi.com 9 differential amplifier for bridged circuits sensors to measure strain, pressure, and temperature are often configured in a wheatstone bridge circuit as shown in figure 24. in the measurement, the voltage change that is produced is relatively small and needs to be amplified before going into an adc. precision amplifiers are recommended in these types of applications due to their high gain, low noise, and low offset voltage. figure 24. bridge circuit amplification + ? vdd vdd general layout guidelines to ensure optimum device performance, it is important to follow good pcb design practices. place 0.1 f decoupling capacitors as close as possible to the supply pins. keep traces short, utilize a ground plane, choose surface?mount components, and place components as close as possible to the device pins. these techniques will reduce susceptibility to electromagnetic interference (emi). thermoelectric effects can create an additional temperature dependent offset voltage at the input pins. to reduce these effects, use metals with low thermoelectric?coefficients and prevent temperature gradients from heat sources or cooling fans.
NCS325 http://onsemi.com 10 package dimensions tsop?5 case 483?02 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimension a. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 m 0 10 s 2.50 3.00 123 54 s a g b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 c seating plane 0.05 k m detail z detail z top view side view a b end view on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCS325/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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