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1 characteristics subject to change without notice 2048 3.3 10/03/01 smp9210, -11, -12 summit microelectronics, inc. ?summit microelectronics, inc., 2001 ? 300 orchard city dr., suite 131 ? campbell, ca 95008 ? phone 408-378-6461 ? fax 408- 378-6586 ? www.summitmicro.com preliminary ! ! ! ! ! two 10-bit nonvolatile dacs " " " " " inl 1lsb " " " " " dnl 1lsb ! ! ! ! ! programmable configuration ! ! ! ! ! programmable power on reset options " " " " " recall full scale value " " " " " recall zero scale value " " " " " recall mid-scale value " " " " " recall nv register value dual 10-bit nonvolatile dac simplified application drawing features c apc 1nf in+ in? apcset modmon md imod laser driver ibias gnd modset biasset v cc apc monitor diode r filt r damp laser diode 3.3v smp9210 smp9210 vout1 vout1 vout2 i 2 c 2048 sad applications ! ! ! ! ! ate set and forget calibration ! ! ! ! ! laser biasing ! ! ! ! ! tandem or independent operation of dacs ! ! ! ! ! programmable power down mode (short vout to gnd or float vout) ! ! ! ! ! i2c interface ! ! ! ! ! low noise outputs ! ! ! ! ! 2.7v to 5.5v operation ! ! ! ! ! C40 o c to 85 o c temperature range ! ! ! ! ! rfpa biasing
2 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary gnd v dd 13 7 6 v out 2 9 scl 12 cs 8 2048 bd10 2.2 configuration register interface & control logic a0 3 a1 2 a2 1 sda 14 volatile control register 10-bit dac non- volatile register volatile control register 10-bit dac non- volatile register v ref h2 4 5 11 10 v ref h1 v ref l2 v ref l1 v out 1 smp9210 functional block diagrams note: pinouts for these three drawings reflect the 14 pin soic package. introduction the smp9210, -11, -12 trio are serial input, voltage output, dual 10-bit digital to analog converters. they can operate from a single 2.7v to 5.5v supply. internal precision buffers swing rail-to-rail with an input reference range from ground to the positive supply. they integrate two 10-bit dacs and their associated circuits: an enhanced unity gain operational amplifier output, a 10-bit volatile data latch, a 10-bit nonvolatile data register and an industry standard 2-wire serial interface. programming of configuration, control and calibration values by the user can be simplified with the interface adapter and windows gui software obtainable from summit microelectronics. recommended operating conditions temperature C40 o c to 85 o c. voltage 2.7v to 5.5v
3 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary gnd v dd 13 7 6 v out 2 9 scl 12 2048 bd11 2.2 configuration register interface & control logic a0 3 a1 2 a2 1 sda 14 volatile control register 10-bit dac non- volatile register volatile control register 10-bit dac non- volatile register v ref h2 4 5 11 10 v ref h1 v ref l2 v ref l1 v out 1 smp9211 mute# 8 gnd v dd 13 7 6 v out 2 9 scl 12 v ref 8 2048 bd12 3.0 configuration register interface & control logic a0 3 a1 2 a2 1 sda 14 volatile control register 10-bit dac non- volatile register volatile control register 10-bit dac non- volatile register v ref h2 4 5 11 10 v ref h1 v ref l2 v ref l1 v out 1 precision reference smp9212
4 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary v dd power supply input. gnd power supply return. v out 1 , v out 2 the voltage output of the dacs. it is buffered by a unity- gain follower that can slew up to 1v/s. v ref l1, v ref l2 the lower of the voltage reference inputs. v ref l must be equal to or greater than ground and less than v ref h. v ref h1, v ref h2 the higher of the voltage reference inputs. v ref h must be equal to or less than v cc and greater than v ref l. a0, a1, a2 the address inputs for the serial interface logic. bias- ing the address inputs will determine the devices bus address that is contained within the serial data stream when communicating over the serial bus. pin descriptions scl the serial interface clock. it is used to clock the data in and out. when writing to the device data must remain stable while scl is high. when reading from the device data is clocked out on the falling edge of scl. sda the bidirectional pin used to transfer data in and out of the device. cs chip select input (v ih = selected) in the 9210. see the block diagrams. mute# mute input (v il = mute) in the 9211. see the block diagrams. v ref v ref output (1.25v) in the 9212. see the block diagrams. note: nc pins are not connected. pin configurations a2 a1 a0 v ref h2 v ref l2 v out 2 gnd sda v dd scl v ref h1 v ref l1 v out 1 mute# 14-pin soic 2048 14-pcon 1 2 3 4 5 6 7 14 13 12 11 10 9 8 a2 a1 a0 v ref h2 v ref l2 v out 2 gnd sda v dd scl v ref h1 v ref l1 v out 1 cs 1 2 3 4 5 6 7 14 13 12 11 10 9 8 a2 a1 a0 v ref h2 v ref l2 v out 2 gnd sda v dd scl v ref h1 v ref l1 v out 1 v ref 1 2 3 4 5 6 7 14 13 12 11 10 9 8 smp9210 smp9211 smp9212 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2048 16-pcon 16-pin ssop a2 nc a1 a0 v ref h2 v ref l2 v out 2 gnd sda nc v dd scl v ref h1 v ref l1 v out 1 mute# smp9210 smp9211 smp9212 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 a2 nc a1 a0 v ref h2 v ref l2 v out 2 gnd sda nc v dd scl v ref h1 v ref l1 v out 1 cs 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 a2 nc a1 a0 v ref h2 v ref l2 v out 2 gnd sda nc v dd scl v ref h1 v ref l1 v out 1 v ref
5 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ...................... C55c to 125c storage temperature ........................... C65c to 150c lead solder temperature (10 secs) .................. 300 c terminal voltage with respect to gnd: v dd ................................ C0.3v to 6.0v all others ...................... C0.3v to 6.0v j a .................. 14 pin = 88, 16 pin = 115 j c .................. 14 pin = 37, 16 pin = 40 dc operating characteristics absolute maximum ratings* ( over recommended operating conditions; voltages are relative to gnd ) 2048 elect tablea 3.1 (1) v ref l = 0.5v, v ref h = 4.5v l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u ) 1 ( e c n a m r o f r e p c i t a t s nn o i t u l o s e r0 1s t i b l n iy c a r u c c a e v i t a l e r2 ? 1 2 b s l l n dy t i r a e n i l n o n l a i t n e r e f f i dc i n o t o n o m d e e t n a r a u g1 ? 5 . 0 1b s l e s z vr o r r e e l a c s o r e z0 0 0 = a t a d x e h 00 2v m s f ve g a t l o v e l a c s l l u ff f 3 = a t a d x e h v f e r h b s l 1 ? v v c t e r u t a r e p m e t e l a c s l l u f t n e i c i f f e o c 5 1 m p p r o r r e t e s f f o3 . 0 ? 3 . 0s f v % r o r r e n i a g5 . 0 ? 5 . 0% e c n a m r o f r e p g n i h c t a m r o r r e g n i h c t a m y t i r a e n i l 5 b s l t u p t u o g o l a n a i t u o t n e r r u c t u p t u o 0 0 2 = a t a d x e h , ? v t u o , b s l 3 5 a m g e r d le l a c s f l a h @ n o i t a l u g e r d a o l0 0 2 = a t a d x e h k 1 = l r , ? o t 14 b s l c l d a o l e v i t i c a p a cn o i t a l l i c s o o n0 0 5f p s e g a t l o v e c n e r e f e r v f e r hv f e r v > h f e r lv d d v v f e r lv f e r v < l f e r hd n gv v f e r t u o2 1 2 9 p m s5 2 . 1v
6 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary 2048 elect tableb l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u r e w o p i d d t n e r r u c y l p p u s r e w o p v e t i r w v n d d v 5 . 5 =3a m v e t i r w v n d d v 7 . 2 =3a m t n e c s e i u q r o y b d n a t s h g u o r h t t n e r r u c g n i d u l c x e v s c a d d d v 5 . 5 = 1a m h g u o r h t t n e r r u c g n i d u l c x e v s c a d d d v 7 . 2 = 1a m n w o d r e w o p c a d g n i d u l c n i t n e r r u c l a t o t v d d v 5 . 5 = 1a m c a d g n i d u l c n i t n e r r u c l a t o t v d d v 7 . 2 = 1a m v d d e g a t l o v y l p p u s7 . 25 . 5v v h i l c s , a d s 7 . 0 v d d v v l i l c s , a d s3 . 0 v d d v v l o a d si l o a m 3 =4 . 0v i i l e g a k a e l t u p n iv n i o t 0 =v d d 0 0 1a i o l e g a k a e l t u p t u o v t u o h g i h n i n w o d d e r e w o p e d o m e c n a d e p m i 0 1a w d n e e c n a r u d n e e t i r ws n o i t a r e p o e r o t s v n f o r e b m u n1 0 1 6 s e r o t s v n t r d n o i t n e t e r a t a dd v nn o i t n e t e r a t a0 0 1s r a e y
7 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary introduction the device has two 10-bit digital to analog converters that are comprised of a resistor network that converts a digital input into an equivalent analog output voltage in proportion to the applied reference voltage. the voltage differential between each of the v ref l and v ref h input pairs sets the full-scale output voltage for their respective dac. each dac has a 10-bit volatile register that holds the current digital value. the register can be set to any value by the serial interface; commanded to load the zero scale value, full scale value or mid-scale value; or can recall a preset value stored in a nonvolatile register. each dac has a 10-bit nonvolatile register that can hold a set-and-forget value that can be recalled whenever the device is powered-on. the device also has a nonvolatile configuration register that is accessible over the 2-wire bus. the configuration register is used to select the device type identifier, the function of pin 8 and the dac power-on state. device operation accessing the dacs the device uses the industry standard 2-wire serial proto- col. the bus is designed for two-way, two-line serial communication between different integrated circuits. the two lines are the scl (serial clock) and sda (serial data) and both lines must be tied to the positive supply through a pull-up resistor. the protocol defines devices as being either masters or slaves. the smp9210, -11, or -12 will always be a slave because it does not initiate any communications or provide a clock output. data transfers are initiated when a master issues a start condition, which is a high to low transition on sda while scl is high (see figure 1). the start is immediately followed by an eight bit transmission: bits 7 through 1 comprise the device type identifier and bus device bus address; bit 0 is the read/write bit indicating the action to follow. if the intended device receives the byte and recognizes its address it will return an acknowledge during the 9 th clock cycle. some data transfers will be concluded with a stop condition, which is a low to high transition on sda while scl is high. note: a stop condition must be performed for all nonvolatile write operations. timing for all i 2 c operations are summarized in figure 2 and table 1. the dac device type identifier default is 0101 bin . in order to accommodate more than eight devices on a single bus the device type identifier can be modified by the end user by writing to the configuration registers. (see page 10) figure 1. start and stop timing figure 2. data/clock timing 2048 fig01 scl sda in start condition stop condition t f t r t low t high t hd:sta t su:sta t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2048 fig02
8 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary table 2. command structure 2048 table02 3.0 table 1. data/clock timing 2048 table01 2.0 note (1) these values are guaranteed by design. b s m 7 d 6 d5 d4 d3 d2 d1 d b s l 0 d d n a m m o cn o i t c n u f 10 0 1 xx 9 d8 d 1 c a d e t i r w1 c a d o t e u l a v t i b - 0 1 e t i r w 10 10 xx 9 d8 d 2 c a d e t i r w2 c a d o t e u l a v t i b - 0 1 e t i r w 10 1 1 xx 9 d8 d s c a d h t o b e t i r ws c a d h t o b o t e u l a v t i b - 0 1 e t i r w 110 11110 2 c a d f 3v ( e l a c s l l u f o t 2 c a d t e s f e r ) h 11011101 1 c a d f 3v ( e l a c s l l u f o t 1 c a d t e s f e r ) h 11011111 s c a d h t o b f 3v ( e l a c s l l u f o t s c a d h t o b t e s f e r ) h 1110 1110 2 c a d o r e zv ( e l a c s o r e z o t 2 c a d t e s f e r ) l 1110 110 1 1 c a d o r e zv ( e l a c s o r e z o t 1 c a d t e s f e r ) l 1110 1111 s c a d h t o b o r e zv ( e l a c s o r e z o t s c a d h t o b t e s f e r ) l 1111 xx 10 2 c a d l l a c e re l l a c e r 2 2 c a d o t 1111 xx 01 1 c a d l l a c e re l l a c e r 2 1 c a d o t 1111 xx 11 s c a d h t o b l l a c e re l l a c e r 2 s c a d h t o b o t 1000 xx 10 2 c a d d p2 c a d n w o d r e w o pv ( t u o d n g o t) 1000 xx 01 1 c a d d pv ( 1 c a d n w o d r e w o p t u o ) d n g o t 1000 xx 11 s c a d h t o b d pv ( s c a d h t o b n w o d r e w o p t u o ) d n g o t l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b ) 1 ( e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a ) 1 ( t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s3 . 05 . 3s t h d ) 1 ( e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s3 . 0s t r ) 1 ( e m i t e s i r a d s d n a l c s 0 0 0 1s n t f ) 1 ( e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s ) 1 ( e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h ) 1 ( e m i t d l o h n i a t a d 0s n i t) 1 ( a d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m
9 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary the command structure is illustrated in table 2. of special note is the ability to write individually to either of the two dacs, or write to them both. the first three commands are three bytes in length and can either be volatile or nonvolatile. ack and nack a device that is receiving data will respond with an acknowledge by pulling the sda line low (ack) after each byte is transmitted. the transmitting device will recog- nize this and continue to transmit. when the master has received the data it expects it will hold the sda line high (nack) and the transmitting device will end transmis- sion. sequence the sequence is to issue a start, followed by the device type and bus address with the read/write bit set to zero. the device will respond with an acknowledge and the master will then issue the command and follow-on data. in figure 3 the write is to dac1 where the command = 1001 bin ; d9 and d8 are the msbs of the dac value being written. the device will then respond with an acknowl- edge followed by the master writing the last eight bits. if no stop is generated after the device acknowledge the write is only to the register. if the device acknowledge is followed by a stop the data is written to both the dac register and to the nonvolatile register. reading the device reading the dacs requires setting the r/w bit to one. then the host supplies clocks and the device will output data as shown in figure 4. pd is the power down mode indicator: 1 = power down, 0= dac active. both dacs provide their data for a single read operation. special configurations the smp9210 can be configured by the end user or by summit prior to shipment (see page 10). reading the configuration register can also be performed if it has not already been locked. see figure 5. there is one configuration register and it is accessed through the serial interface using 1001 bin as the device type address, consequently the dac address should never be set to 1001 bin . the register is shown in table 3. figure 3. dac1 write operation (see table 2) figure 4. read dac1 (see dac2 differentiator & table 2) a c k d 9 d 8 a c k a c k s t o p master sda slave 0 1 0 1 r/ w 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x a 2 a 1 a 0 1 0 0 1 nonvolatile write only x 2048 fig03 a c k master sda slave 0 1 0 1 r/ w 1 a 2 a 1 a 0 2048 fig04 dac #1 dac #2 s t o p d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k 1 p d d 9 d 8 1 0 0 1 (1 0 1 0) data from master data to master n a c k
10 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary table 3. configuration register 2048 table03 3.1 figure 5. configuration register (see table 3) * note: never set the dac address to 1001 bin . the slave address for the configuration register is 1001 bin , and a collision will occur on the i 2 c bus. configuration register note: all parts are normally shipped with the configura- tion register locked. unlocked user configurable parts are available on a special order basis. contact the factory. b s m 7 c 6 c5 c4 c3 c2 c1 c b s l 0 c n o i t c n u f xxxx x xx 0 e l b i s s e c c a r e t s i g e r n o i t a r u g i f n o c xx 1 d e k c o l r e t s i g e r n o i t a r u g i f n o c 00 x s 0 l l a o t t e s s c a d : l l a c e r n o r e w o p 01 s 1 l l a o t t e s s c a d : l l a c e r n o r e w o p 10 e l a c s d i m o t t e s s c a d : l l a c e r n o r e w o p 11 r e t s i g e r v n o t t e s s c a d : l l a c e r n o r e w o p 0 xx v n w o d r e w o p t a t u o e c n a d e p m i w o l = 1 v n w o d r e w o p t a t u o e c n a d e p m i h g i h = * 3 a d p* 2 a d p* 1 a d p* 0 a d p xs s e r d d a c a d e l b m m a r g o r p c 2 c 4 a c k a c k s t o p master sda slave 1 0 0 1 r/ w a 2 a 1 a 0 optional 2048 fig05 command byte 1 c 7 c 6 c 5 c 3 c 1 c 0
11 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary ordering information programming connection figure 6. programming connection hardware the end user can use the summit smx3200 programming cable and software that have been developed to operate with a standard personal computer. the programming cable interfaces directly between a pcs parallel port and the target application. the applications values are entered via an intuitive graphical user interface employing drop-down menus. after the desired settings for the application are deter- mined the software will generate a hex file that can be transferred to the target device or downloaded to summit. if it is downloaded to summit a customer part number will be assigned and the file will be used to customize the devices during the final electrical test operations. smp9210 s base part number package s = soic g = ssop 2048 tree smp9211 s base part number package s = soic g = ssop smp9212 s base part number package s = soic g = ssop pin 9, 5v pin 7, 10v pin5, reserved pin3, gnd pin 1, gnd pin 10, reserved pin 8, reserved pin 6, reserved pin 4, sda pin 2, scl top view of straight 0.1" 0.1" closed side connector smx3200 interface positive supply negative supply v dd gnd a0 a1 a2 sda scl 9 7 5 3 1 10 8 6 4 2 smp92xx 2048 fig06 c1 0.1f
12 smp9210, smp9211, smp9212 2048 3.3 10/03/01 summit microelectronics, inc. preliminary packages 14 pin soic package 0.150 - 0.157 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.01 (0.10 - 0.25) 0.337 - 0.344 (8.55 - 8.75) 0.228 - 0.244 (5.80 - 6.20) 0.053 - 0.069 (1.35 - 1.75) 0.016 - 0.050 (0.40 - 1.27) (1.27) 0.0075 - 0.01 (0.19 - 0.25) 0.01 - 0.02 (0.25 - 0.50) (3.80 - 4.00) 14 pin soic 45 o 0.016 - 0.050 0.05 0 to 8 typ 1 ref. jedec ms-012 inches (millimeters) 0.007 - 0.010 (0.18 - 0.25) 0.150 - 0.157 (3.81 - 3.99) 0.025 (0.635) 0.016 - 0.050 (0.41 - 1.27) 0.008 - 0.012 (0.20 - 0.31) 0.189 - 0.197 (4.80 - 5.00) 0.228 - 0.244 (5.79 - 6.20) pin 1 0 o to 8 o 0.004 - 0.010 (0.10 - 0.25) 0.059 (1.50) 0.053 - 0.069 (1.35 - 1.75) max 16 pin ssop ref. jedec mo-137 inches (millimeters) 16 pin ssop package
13 2048 3.3 10/03/01 smp9210, smp9211, smp9212 summit microelectronics, inc. preliminary notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a users specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. power management for communications? ? copyright 2001 summit microelectronics, inc. this document supersedes all previous versions. i 2 c is a trademark of philips corporation. part marking n = package type (p or s) l = lot number yy = year ww = work week 9210: zz = blank 9211: zz = 11 9212: zz = 12 . summit smp9210 n l yy ww zz

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