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| preliminary technical data mixed-signal control processor with arm cortex-m4 ADSP-CM402F / cm403f/cm407f / cm408f rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2013 analog devices, inc. all rights reserved. system features 100 mhz to 240 mhz arm cortex-m4 with floating-point unit 128k byte to 384k byte zero-wait-state l1 sram with 16k byte l1 cache up to 2m byte flash memory 16-bit asynchronous exte rnal memory interface enhanced pwm units four 3rd/4th order sinc filters for glueless connection of iso- lated adcs harmonic analysis engine 10/100 ethernet mac full speed usb on-the-go (otg) two can (controller area network) 2.0b interfaces three uart ports two serial peripheral interface (spi-compatible) ports eight 32-bit general-purpose timers four encoder interfaces, 2 with frequency division single power supply 176-lead (24 mm 24 mm) rohs compliant lqfp package 120-lead (14 mm 14 mm) rohs compliant lqfp package analog subsystem features adc controller (adcc) and dac controller (dacc) two 16-bit sar adcs with up to 24 multiplexed inputs, supporting dual simultaneous co nversion in 380 ns (16-bit, no missing codes, 3.5lsb inl) two 12-bit r-string dacs, with output rate up to 50 khz two 2.5 v precision voltage reference outputs (for details, see adc/dac specifications on page 36 .) figure 1. block diagram up to 2m byte flash l1 cache 16k byte l1 instruction cache system control blocks peripherals hardware functions l3 memory system fabric 1 emac with ieee 1588 (optional) 2x sport 2 can static memory controller async interface 2 spi 4 quadrature encoder 8 timer 12 pwm pairs 1 twi usb fs otg (optional) l1 memory up to 384k byte parity-enabled zero-wait-state sram coresight? test & control pll & power management fault management event control system watchdogs 3 uart adcc dacc harmonic analysis engine (hae) analog subsystem gpio (40 or 91) adc dac ctx-m4 sinc filters
rev. pre | page 2 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data table of contents system features ....................................................... 1 analog subsystem features ........................................ 1 general description ................................................. 3 analog subsystem ................................................. 4 arm cortex-m4 core ........................................... 7 embeddedice ...................................................... 7 processor infrastructure ......................................... 7 memory architecture ............................................ 8 security features ................................................ 10 processor reliability features ................................. 10 additional processor peripherals ............................ 11 general-purpose counters .................................... 12 serial peripheral interface (spi) ports ...................... 12 uart ports ...................................................... 12 twi controller interface ...................................... 12 controller area network (can) ............................ 13 10/100 ethernet mac .......................................... 13 usb 2.0 on-the-go dual-role device controller ....... 13 clock and power management ............................... 14 system debug .................................................... 15 development tools ............................................. 15 related documents .............................................. 15 related signal chains ........................................... 16 ADSP-CM402F/adsp-cm403f si gnal descriptions . ..... 17 ADSP-CM402F/adsp-cm403f multiplexed pins ......... 22 adsp-cm407f/adsp-cm408f si gnal descriptions . ..... 24 adsp-cm407f/adsp-cm408f multiplexed pins ......... 31 specifications ........................................................ 34 operating conditions ........................................... 34 electrical characteristics ....................................... 35 adc/dac specifications ...................................... 36 flash specifications .............................................. 43 absolute maximum ratings ................................... 44 esd sensitivity ................................................... 44 package information ............................................ 44 timing specifications ........................................... 45 output drive currents ......................................... 72 environmental conditions .................................... 73 120-lead lqfp lead assignments ............................. 74 176-lead lqfp lead assignments ............................. 77 outline dimensions ................................................ 81 pre-release products ............................................... 82 revision history 09/13revision prd to revision pre updated the specifications section to include flash information and timing data for all interfaces. see specifications ....... 34 preliminary technical data rev. pre | page 3 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f general description the adsp-cm40x family of mixed- signal control processors is based on the arm ? cortex-m4 tm processor core with floating- point unit operating at frequencies up to 240 mhz and integrat- ing up to 384kb of sram memory, 2mb of flash memory, accelerators and peripherals optimized for motor control and photo-voltaic (pv) inverter cont rol and an analog module con- sisting of two 16-bit sar-type adcs and two 12-bit dacs. the adsp-cm40x family operates from a single voltage supply (vdd_ext/vdd_ana), generating its own internal voltage supplies using internal voltage re gulators and an external pass transistor. this family of mixed-signal cont rol processors offers low static power consumption and is produced with a low-power and low- voltage design methodology, delivering world class processor and adc performance with lower power consumption. by integrating a rich set of indu stry-leading system peripherals and memory (shown in table 1 ), the adsp-cm40x mixed-sig- nal control processors are th e platform of choice for next-generation applications that require risc programmabil- ity, advanced communications and leading-edge signal processing in one integrated pac kage. these applications span a wide array of markets including power/motor control, embed- ded industrial, instrumentation, medical and consumer. each adsp-cm40x family memb er contains the following modules. ? 8 gp timers with pwm output ? 3-phase pwm units with up to 4 output pairs per unit ?2 can modules ? 1 two-wire interface (twi) module ?3 uarts table 1 provides the additional product features shown by model. table 1. adsp-cm40x family product features generic ADSP-CM402F adsp-c m403f adsp-cm407f adsp-cm408f package 120-lead lqfp 176-lead lqfp gpios 40 91 ebiu 16-bit asynchronous/5 address 16-bit asynchronous/24 address adc enob (no averaging) 11+ 13+ 11+ 13+ adc inputs 24 16 dac outputs 2 n/a sports 3 half-sports 4 half-sports ethernet n/a 1 n/a n/a 1 n/a usb n/a 1 1 n/a 1 1 external spi 1 2 general-purpose counters 2 4 (2 with dual-outputs) feature set code efcefabdab l1 sram (kb) 128 128 384 128 128 384 384 128 384 384 flash (kb) 512 256 2048 512 256 2048 2048 1024 2048 2048 core clock (mhz) 150 100 240 150 100 240 240 150 240 240 model adsp-cm402bswz-ef adsp-cm402bswz-ff adsp-cm403bswz-cf adsp-cm403bswz-ef adsp-cm403bswz-ff adsp-cm407bswz-af adsp-cm407bswz-bf adsp-cm407bswz-df adsp-cm408bswz-af adsp-cm408bswz-bf rev. pre | page 4 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data analog subsystem the processors contain two adcs and two dacs. control of these data converters is simplified by a powerful on-chip ana- log-to-digital conversion cont roller (adcc) and a digital-to- analog conversion controller (dacc). the adcc and dacc are integrated seamlessly into th e software programming model, and they efficiently manage the configuration and real-time operation of the adcs and dacs. for technical details, see adc/dac specifications on page 36 . the adcc provides the mechanis m to precisely control execu- tion of timing and analog sampling events on the adcs. the adcc supports two-channel (one eachadc0, adc1) simul- taneous sampling of adc inputs with tbd ps time offset accuracy (aperture delay), and can deliver 16 channels of adc data to memory in 3 s. conver sion data from the adcs may be either routed via dma to me mory, or to a destination regis- ter via the processor. the adcc can be configured so that the two adcs sample and convert both analog inputs simultane- ously or at different times and may be operated in asynchronous or synchronous modes. the best performance can be achieved in synchronous mode. likewise, the dacc interfaces to two dacs and has purpose of managing those dacs. conversion data to the dacs may be either routed from memory th rough dma, or from a source register via the processor. functional operation and programming for the adcc and dacc are described in detail in the adsp-cm40x mixed-signal control processor with arm co rtex-m4 hardware reference . adc and dac features and performance specifications differ by processor model. simplified block diagrams of the adcc, dacc and the adcs and dacs are shown in figure 2 and figure 3 . figure 2. cm402f/cm403f analog subsystem block diagram dac1 dac0 adc0 adc1_vin00 . . . adc1_vin01 adc1_vin02 adc1_vin11 dac1 adc0_vin00 . . . adc0_vin01 adc0_vin02 adc0_vin11 dac0 mux mux adcc dacc control control micro controller dma sram memory data vref1 vref0 refcap buf buf buf buf buf buf dac1_vout dac0_vout ~ ~ ~ adc1 buf buf band gap adc/dac local controller preliminary technical data rev. pre | page 5 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f figure 3. cm407f/cm408f analog subsystem block diagram dac1 dac0 adc1 adc0 adc1_vin00 . . . adc1_vin01 adc1_vin02 adc1_vin07 dac1 adc0_vin00 . . . adc0_vin01 adc0_vin02 adc0_vin07 dac0 mux mux adcc dacc control control micro controller dma sram memory data vref1 vref0 refcap buf buf buf buf buf buf ~ ~ not pinned out buf buf band gap adc/dac local controller rev. pre | page 6 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data considerations for best converter performance as with any high performance analog/digital circuit, to achieve best performance, good circuit design and board layout prac- tices should be followed. the power supply and its noise bypass (decoupling), ground return paths and pin connections, and analog/digital routing channel paths and signal shielding, are all of first-order consideration. for application hints of design best practice, see figure 4 and the adsp-cm40x mixed-signal con- trol processor with arm co rtex-m4 hardware reference . adc module the adc module contains two 16-bit, high speed, low power successive approximat ion register (sar) adcs, allowing for dual simultaneous sampling with each adc proceeded by a 12-channel multiplexer. see adc specifications on page 36 for detailed performance specifications. input multiplexers enable up to a combined 26 analog inpu t sources to the adcs (12 ana- log inputs plus 1 dac loopback input per adc). the voltage input rang e requirement for thos e analog inputs is from 0 v to 2.5 v. all analog in puts are of single-ended design. as with all single-ended inputs, signals from high impedance sources are the most difficult to control, and depending on the electrical environment, may requ ire an external buffer circuit for signal conditioning ( figure 5 ). an on-chip buffer between the multiplexer and adc reduces the need for additional signal conditioning external to the pr ocessor. additionally, each adc has an on-chip 2.5 v re ference that can be overdriven when an external voltage reference is preferred. dac module the dac is a 12-bit, low power, string dac design. the output of the dac is buffered, and can drive an r/c load to either ground or v dd_ana . see dac specifications on page 38 for detailed performance specifications. it should be noted that on some models of the processor, the dac outputs are not pinned out. however, these outputs are always available as one of the multiplexed inputs to the adcs. this feature may be useful for functional self-check of the converters. figure 4. typical power supply configuration figure 5. equivalent single -ended input (simplified) vdd_ext vdd_vreg vdd_int byp_d0 gnd vdd_ana0 gnd_ana0 byp_a0 vref0 vref_gnd0 refcap vref1_gnd vref1 byp_a1 gnd_ana1 vdd_ana1 vreg circuit gnd_ana 3.3v connected at one point gnd_dig plane gnd_ana plane gnd_dig gnd_ana2 gnd_ana3 vreg_base adsp-cm40x analog source to adc v in vdd_ana c tbd optional external buffer c hold r track c in r in tbd tbd adsp-cm40x preliminary technical data rev. pre | page 7 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f harmonic analysis engine (hae) the harmonic analysis engine (hae) block receives 8 khz input samples from two source signals whose frequencies are between 45 hz and 65 hz. the hae will then process the input samples and produce output results. the output results consist of power quality measurements of the fundamental and up to 12 additional harmonics. sinc filter the sinc module processes four bit streams using a pair of configurable sinc filters for each bitstream. the purpose of the primary sinc filter of each pair is to produce the filtered and decimated output for the pair. the output may be decimated to any integer rate betw een 8 and 256 times lo wer than the input rate. greater decimation allows greater remova l of noise and therefore greater enob. optional additional filtering outside the sinc module may be used to further increase enob. the primary sinc filter output is accessible through transfer to processor memory, or to another peripheral, via dma. each of the four channels is al so provided with a low-latency secondary filter with programmabl e positive and negative over- range detection comparators. th ese limit detection events can be used to interrupt the core, generate a trigger, or signal a sys- tem fault. arm cortex-m4 core the arm cortex-m4, core shown in figure 6 , is a 32-bit reduced instruction set computer (r isc). it uses a single 32-bit bus for instruction and data. the length of the data can be eight bits, 16 bits, or 32 bits. the leng th of the instruction word is 16 or 32 bits. the controller has the following features. cortex-m4 architecture ? thumb-2 isa technology ? dsp and simd extensions ? single cycle mac (up to 32 32 + 64 -> 64) ? hardware divide instructions ? single-precision fpu ? nvic interrupt controlle r (129 interrupts and 16 priorities) ? memory protection unit (mpu) ?full coresight tm debug, trace, breakpoints, watchpoints, and cross-triggers microarchitecture ? 3-stage pipeline with branch speculation ? low-latency interrupt processing with tail chaining configurable for ultra low power ? deep sleep mode, dynamic power management ? programmable clock generator unit embeddedice embeddedice ? provides integrated on-chip support for the core. the embeddedice module contains the breakpoint and watch-point registers that allow code to be halted for debugging purposes. these registers are cont rolled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters debug state. once in a debug state, the proces- sor registers can be inspected as well as the flash/ee, sram, and memory mapped registers. processor infrastructure the following sections provid e information on the primary infrastructure components of the adsp-cm40x processors. dma controllers (ddes) the processor contains 17 periph eral dma channels plus two mdma streams. dde channel nu mbers 0C16 are for peripher- als and channels 17C20 are for mdma. system event controller (sec) the sec manages the enabling and routing of system fault sources through its integrat ed fault management unit. trigger routing unit (tru) the tru provides system-level sequence contro l without core intervention. the tru maps trigge r masters (generators of trig- gers) to trigger slaves (receivers of triggers). slave endpoints can be configured to respond to triggers in various ways. common applications enabled by the tru include: ? automatically triggering the start of a dma sequence after a sequence from another dma channel completes ? software triggering ? synchronization of concurrent activities pin interrupts every port pin on the processor can request interrupts in either an edge-sensitive or a level-sensitive manner with programma- ble polarity. interrupt functionality is decoupled from gpio operation. six system-level in terrupt channels (pint0C5) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins . the assignment from pin to interrupt is not performed on a pi n-by-pin basis. rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab le half-port assignment and interrupt management. this includes masking, identification, and clearing of requests. these re gisters also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address entries to write-one-to-set or write-one-to-clear them individually. rev. pre | page 8 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data general-purpose i/o (gpio) each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C a write one to mod- ify mechanism allows any combination of individual gpio pins to be mo dified in a single instruction, without affecting the level of any other gpio pins. ? gpio interrupt mask register s C allow each individual gpio pin to function as an interrupt to the processor. gpio pins defined as inputs ca n be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C specify whether indi- vidual pins are level- or ed ge-sensitive and specifyif edge-sensitivewhether just the rising edge or both the ris- ing and falling edges of th e signal are significant. pin multiplexing the processor supports a flexible multiplexing scheme that mul- tiplexes the gpio pins with various peripherals. a maximum of 4 peripherals plus gpio functionality is shared by each gpio pin. all gpio pins have a bypass path featurethat is, when the output enable and the input en able of a gpio pin are both active, the data signal before the pad driver is looped back to the receive path for the same gpio pin. see ADSP-CM402F/adsp- cm403f multiplexed pins on page 22 and adsp- cm407f/adsp-cm408f multiplexed pins on page 31 . memory architecture the internal and external memo ry of the adsp-cm40x proces- sor is shown in figure 7 and described in the following sections. arm cortex-m4 memory subsystem the memory map of the adsp-cm40x family is based on the cortex-m4 model from arm. by retaining the standardized memory mapping, it becomes easier to port applications across m4 platforms. only the physical implementation of memories inside the model differ s from other vendors. adsp-cm40x application develo pment is typically based on memory blocks across code/sram and external memory regions. sufficient internal me mory is available via internal sram and internal flash. additi onal external memory devices may be interfaced via the smc asynchronous memory port, as well as through the spi0 serial memory interface. code region accesses in this region (0x 0000_0000 to 0x1fff_ffff) are per- formed by the core on its ic ode and dcode interfaces, and they target the memory and ca che resources within the adi cortex-m4f platform component. ? boot rom. a 32k byte boot rom executed at system reset. this space supports read-only access by the m4f core only. note that rom memory co ntents cannot be modified by the user. ? internal sram code region. this memory space con- tains the application instructions and literal (constant) data which must be executed real time. it supports read/write access by the m4f core and read/write dma access by sys- tem devices. internal sram can be partitioned between figure 6. cortex-m4 block diagram 1 9 , & 1 ( 6 7 ( ' 9 ( & 7 2 5 ( ' , 1 7 ( 5 5 8 3 7 & 2 1 7 5 2 / / ( 5 $ 5 0 & 2 5 7 ( ; 0 ) 3 5 2 & ( 6 6 2 5 & 2 5 ( : , 7 + ) 3 8 ( 7 0 ( 0 % ( ' ' ( ' 7 5 $ & ( 0 $ & 5 2 & ( / / 0 3 8 0 ( 0 2 5 < 3 5 2 7 ( & 7 , 2 1 8 1 , 7 ' : 7 ' $ 7 $ : $ 7 & + 3 2 , 1 7 7 5 $ & ( ) 3 % ) / $ 6 + 3 $ 7 & + % 5 ( $ . 3 2 , 1 7 & 2 5 7 ( ; , 1 7 ( 5 1 $ / % 8 6 0 $ 7 5 , ; , 7 0 , 1 6 7 5 8 0 ( 1 7 $ 7 , 2 1 7 5 $ & ( 0 $ & 5 2 & ( / / $ 3 $ & & ( 6 6 3 2 5 7 ' 3 ' ( % 8 * 3 2 5 7 % 8 6 0 $ 7 5 , ; , 1 7 ( 5 5 8 3 7 $ 1 ' 3 2 : ( 5 & 2 1 7 5 2 / 6 : ' ' ( % 8 * , 1 7 ( 5 ) $ & ( ( 7 0 7 5 $ & ( , 1 7 ( 5 ) $ & ( , 7 0 7 5 $ & ( , 1 7 ( 5 ) $ & ( 3 3 % ' ( % 8 * % 8 6 , 1 7 ( 5 ) $ & ( 3 3 % 6 < 6 ' & 2 ' ( , & 2 ' ( preliminary technical data rev. pre | page 9 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f code and data (sram region in m4 space) in 64k byte blocks. access to this region occurs at core clock speed, with no wait states. ? integrated flash. this contains the 2m byte flash memory space interfaced via the spi2 port of the processor. this memory space contains the application instructions and lit- eral (constant) data. reads from flash memory are directly cached via internal code cache. direct memory-mapped reads are permitted via spi memory-mapped protocol. ? internal code cache. a zero-wait-state code cache sram memory is available internally (not visible in the memory map) to cache instruction access from internal flash as well as any externally connected serial flash and asynchronous memory. ? mem-x/mem-y. these are virtual memory blocks which are used as cacheable memory for the code cache. no phys- ical memory device resides inside these blocks. the application code must be compiled against these memory blocks to utilize the cache. sram region accesses in this region (0x 2000_0000 to 0x3fff_ffff) are per- formed by the arm cortex-m4f co re on its sys interface. the sram region of the core can otherwise act as a data region for an application. ? internal sram data region. this space can contain read/write data. internal sram can be partitioned between code and data (sram region in m4 space) in 64k byte blocks. access to this region occurs at core clock speed, with no wait states. it suppo rts read/write access by the m4f core and read/write dma a ccess by system devices. it supports exclusive memory acce sses via the global exclusive access monitor within the adi cortex-m4f platform. bit- banding support is also available. external (memory-mapped) peripheral region ? external spi flash support. up to 16m byte of external serial quad flash memory opti onally connected to the spi0 port of the processor. reads from flash memory are directly cached via internal code cache. direct memory-mapped reads are permitted via spi memory-mapped protocol. ? system mmrs. various system mmrs reside in this region. bit-banding support is available for mmrs. external sram region ? l2 asynchronous memory. up to 32m byte 4 banks of external memory can be optionally connected to the asyn- chronous memory port (smc). code execution from these memory blocks can be optionally cached via internal code cache. direct r/w data access is also possible. figure 7. adsp-cm40x memory map 0 h p ; 6 3 , ) o d v k 0 % [ rev. pre | page 10 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data system region accesses in this region (0xe 000_0000 to 0xf7ff_ffff) are per- formed by the arm cortex-m4f co re on its sys interface, and are handled within the adi cortex-m4f platform. the mpu may be programmed to limit access to this space to privileged mode only. ? coresight rom. the rom table entries point to the debug components of the processor. ? arm ppb peripherals. this space is defined by arm and occupies the bottom 256k byte of the sys region (0xe000_0000 to 0xe004_0000). the space supports read/write access by the m4f co re to the arm cores inter- nal peripherals (mpu, itm, dwt, fpb, scs, tpiu, etm) and the coresight rom. it is not accessible by system dma. ? platform control registers. this space has registers within the adi cortex-m4f platform component that con- trol the arm core, its memory, and the code cache. it is accessible by the m4f core vi a its sys port (but is not accessible by system dma). static memory controller (smc) the smc can be programmed to control up to four banks of external memories or memory-ma pped devices, with very flexi- ble timing parameters. each bank occupies a 32m byte segment regardless of the size of the device used. booting the processor has several mechan isms for automatically loading internal and external memory af ter a reset. the boot mode is defined by the sys_bmode input pins dedicated for this pur- pose. there are two categories of boot modes. in master boot modes, the processor actively lo ads data from a serial memory. in slave boot modes, the processo r receives data from external host devices. the boot modes are shown in table 2 . these modes are imple- mented by the sys_bmode bits of the rcu_ctl register and are sampled during power-on re sets and software-initiated resets. security features the processor provides a combination of hardware and soft- ware protection mechanisms that lock out access to the part in secure mode, but grant access in open mode. these mechanisms include password-protected slave boot modes (spi and uart), as well as password-protected jtag/swd debug interfaces. processor reliability features the processor provides the following features which can enhance or help achieve certain le vels of system safety and reli- ability. while the level of safety is mainly dominated by system considerations, the following feat ures are provided to enhance robustness. multi-parity-bit-protected l1 memories in the processors sram and ca che l1 memory space, each word is protected by multiple parity bits to detect the single event upsets that occur in all rams. cortex mpu the mpu divides the memory map into a number of regions, and allows the system programmer to define the location, size, access permissions, and memory attributes of each region. it supports independent attribute settings for each region, over- lapping regions, and export of me mory attributes to the system. for more information, refer to http://infocenter.arm.com/ system protection all system resources and l2 memo ry banks can be controlled by either the processor core, memory-to-memory dma, or the debug unit. a system protecti on unit (spu) enables write accesses to specific resources th at are locked to a given master. system protection is enabled in greater granularity for some modules through a global lock concept. watchpoint protection the primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. when enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user -defined addre sses. watchdog events can be configured such that they signal the events to the core or to the sec. software watchdog the on-chip watchdog timer can provide software-based super- vision of the adsp-cm40x core. signal watchdogs the eight general-purpose timers feature two modes to monitor off-chip signals. the watchdog period mode mo nitors whether external signals toggle with a period within an expected range. the watchdog width mode monitors whether the pulse widths of external signals are in an expe cted range. both modes help to detect incorrect undesired toggling (or lack thereof) of system-level signals. table 2. boot modes sys_bmode[1:0] setting description 00 no boot/idle. the processor does not boot. rather the boot kernel executes an idle instruction. 01 flash boot. boot from integrated flash memory through the spi2. for derivatives with no flash, the processor boots through the spi0 peripheral configured as a master. 10 spi slave boot. boot through the spi0 peripheral configured as a slave. 11 uart boot. boot through the uart0 peripheral configured as a slave. preliminary technical data rev. pre | page 11 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f oscillator watchdog the oscillator watchdog monitors the external clock oscillator, and can detect the absence of clock as well as incorrect har- monic oscillation. the oscillator watchdog detection signal is routed to the fault management portion of the system event controller. low-latency sinc filter over-range detection the sinc filter units provide a lo w-latency secondary filter with programmable positive and negative limit detectors for each input channel. these may be used to monitor an isolation adc bitstream for over- or under-range conditions with a filter group delay as low as 0.7 s on a 10 mhz bitstream. the sec- ondary sinc filter events can be used to interrupt the core, to trigger other events directly in hardware using the trigger rout- ing unit (tru), or to signal the fault management unit of a system fault. up/down count mismatch detection the gp counter can monitor external signal pairs, such as request/grant strobes. if the ed ge count mismatch exceeds the expected range, the up/down counte r can flag this to the proces- sor or to the sec. fault management the fault management unit is part of the system event controller (sec). most system events can be defined as faults. if defined as such, the sec forwards the event to its fault management unit which may automatically reset the entire device for reboot, or simply toggle the sys_fault output pin to signal off-chip hardware. optionally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chance for the core to resolve the crisis and to prevent the fault action from being taken. additional processor peripherals the processor contains a rich set of peripherals connected to the core via several concurrent hi gh-bandwidth buses, providing flexibility in system configurat ion as well as excellent overall system performance (see the block diagram on page 1 ). the processor contains high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power manage- ment control functions to tail or the performance and power characteristics of the processor and system to many application scenarios. the following sections describe additional peripherals that were not described in the previous sections. timers the processor includes several ti mers which are described in the following sections. general-purpose timers the gp timer unit provides ei ght general-purpose programma- ble timers. each timer has an external pin that can be configured either as a pulse width modulato r (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be syn- chronized to an external clock input on the tmrx pins, an external signal on the tm0_clk input pin, or to the internal sysclk. the timer unit can be used in conjunction with the uarts and the can controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timer can generate interrupts to the processor core, provid- ing periodic events for synchron ization to either the system clock or to external signals. timer events can also trigger other peripherals via the tru (for in stance, to signal a fault). watchd og timer the core includes a 32-bit timer, which may be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state, via generation of a hardwa re reset, nonmaskable interrupt (nmi), or general-purpose interrup t, if the timer expires before being reset by software. the programmer initializes the count value of the timer, enables th e appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to ze ro from the programmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can dete rmine if the watchdog was the source of the hardware reset by in terrogating a status bit that is set only upon a watchdog generated reset. 3-phase pwm units the pulse width modulator (pwm) unit provides duty cycle and phase control capabilities to a resolution of one system clock cycle (sysclk). the heightened precision pwm (hppwm) module provides in creased performance to the pwm unit by increasing its resolu tion by several bits, resulting in enhanced precision levels. additional features include: ? 16-bit center-based pwm generation unit ? programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ?twos-complement implementa tion which permits smooth transition to full on and full off states ? dedicated asynchronous pwm shutdown signal each pwm block integrates a flexible and programmable 3-phase pwm waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase volt- age source inverter for ac induction motor (acim) or permanent magnet synchronous motor (pmsm) control. in addition, the pwm block contains special functions that con- siderably simplify the genera tion of the required pwm rev. pre | page 12 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data switching patterns for control of the electronica lly commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for swit ched reluctance motors (srm). the eight pwm output signals (p er pwm unit) consist of four high-side drive signals and four low-side drive signals. the polarity of a generated pwm signal can be set with software, so that either active hi or ac tive lo pwm patterns can be produced. each pwm unit features a dedi cated asynchronous shutdown pin which (when brought low) in stantaneously places all pwm outputs in the off state. serial ports (sports) the synchronous serial ports pr ovide an inexpe nsive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices audi o codecs, adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ? multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ?left-justified mode general-purpose counters the 32-bit counter can operate in general-purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. count direction is either controlled by a level-sensitive input pin or by two edge detectors. a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins ha ve a programmable debouncing circuit. the gp counter can also support a programmable m/n fre- quency scaling of the cnt_cud and cnt_cdg pins onto output pins in quadrature encoding mode. internal signals forwarded to ea ch general-purpos e timer enable these timers to measure the intervals between count events. boundary registers enable auto-z ero operation or simple system warning by interrupts when programmable count values are exceeded. serial peripheral interface (spi) ports the processor contains the spi-co mpatible port that allows the processor to communicate with multiple spi-compatible devices. in its simplest mode, the spi inte rface uses three pins for trans- ferring data: two data pins master output-slave input and master input-slave output (spi_mosi and spi_miso) and a clock pin, spi_clk. a spi chip select input pin (spi_ss ) lets other spi devices select the proces sor, and seven spi chip select output pins (spi_seln) let the processor select other spi devices. the spi select pins ar e reconfigured general-purpose i/o pins. using these pins, the spi provides a full-duplex, syn- chronous serial interface, whic h supports both master and slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has integrated dma channels for both transmit and rece ive data streams. uart ports the processor provides full-du plex universal asynchronous receiver/transmitter (uart) ports, which are fully compatible with pc-standard uarts. each uart port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-support ed, asynchronous transfers of serial data. a uart port includes suppo rt for five to eight data bits, and none, even, or odd parity. optionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminated by one, one and a half, two or two and a half stop bits. the uart ports support automa tic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmab le assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processor includes a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi modu le is compatible with the widely used i 2 c bus standard. the tw i module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (twi_scl) and data (twi_sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compati- ble with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functi onality for easier control of various cmos camera sensor devices. preliminary technical data rev. pre | page 13 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f controller area network (can) the can controller implements the can 2.0b (active) proto- col. this protocol is an asynchronous communications protocol used in both industrial and au tomotive contro l systems. the can protocol is well suited for control applications due to its capability to commun icate reliably over a network. this is because the protocol incorporat es crc checking, message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (id) message formats. ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error and global. an additional crystal is not required to supply the can clock, as the can clock is derived from a system clock through a pro- grammable divider. 10/100 ethernet mac the processor can directly connec t to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 et hernet mac peripheral on the processor is fully compliant to the ieee 802.3-2002 standard. it provides programmable features designed to minimize supervi- sion, bus use, or message processi ng by the rest of the processor system. some standard features are: ? support for rmii protocols for external phys ? full duplex and half duplex modes ? media access management (in half-duplex operation) ?flow control ? station management: generation of mdc/mdio frames for read-write access to phy registers some advanced features are: ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes ? 47 mac management statistics counters with selectable clear-on-read behavior and pr ogrammable interrupts on half maximum value ? advanced power management ? magic packet detection and wakeup frame filtering ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ieee 1588 support the ieee 1588 standard is a pr ecision clock synchronization protocol for networked measurement and control systems. the processor includes hardware support for ieee 1588 with an integrated precision time protoc ol synchronization engine. this engine provides hard ware assisted time stamping to improve the accuracy of clock synchron ization between ptp nodes. the main features of the engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? 64-bit hardware assi sted time stamping for transmit and receive frames capable of up to 10 ns resolution ? identification of ptp message type, version, and ptp pay- load in frames sent directly over ethernet and transmission of the status ? coarse and fine correction me thods for system time update ? alarm features: target time can be set to interrupt when system time reaches target time ? pulse-per-second output for ph ysical representation of the system time. flexibility to control the pulse-per-second (pps) output signal including control of start time, stop time, pps output width and interval ? automatic detection and time stamping of ptp messages over ipv4, ipv6 and ethernet packets ? multiple input clock sources (sysclk, rmii clock, exter- nal clock) ? auxiliary snapshot to time stamp external events usb 2.0 on-the-go dual-role device controller the usb 2.0 otg dual-role device controller provides a low- cost connectivity solution for th e growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digi tal still cameras, and mp3 play- ers. the usb 2.0 controller is a full-speed-only (fs) interface that allows these devices to transfer data using a point-to-point usb connection without the need for a pc host. the module can operate in a traditional usb peripheral-only mode as well as the host mode presented in th e on-the-go (otg) supplement to the usb 2.0 specification. rev. pre | page 14 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data clock and power management the processor provides three operating modes, each with a dif- ferent performance/power profile. control of clocking to each of the processor peripherals al so reduces power consumption. see table 3 for a summary of the power settings for each mode. crystal oscillator (sys_xtal) the processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external cl ock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. this signal is connected to the proc essors sys_clkin pin. when an external clock is used, the sys_xtal pin must be left uncon- nected. alternatively, because th e processor includes an on-chip oscillator circuit, an exte rnal crystal may be used. oscillator watchdog a programmable oscilla tor watchdog unit is provided to allow verification of proper startup and harmonic mode of the exter- nal crystal. this allows the user to specify the expected frequency of oscillation, and to enable detection of non-oscilla- tion and improper-osci llation faults. these ev ents can be routed to the sys_fault output pin and/or to cause a reset of the part. clock generation the clock generation unit (cgu ) generates all on-chip clocks and synchronization signals. mu ltiplication factors are pro- grammed to the plls to define the pllclk frequency. programmable values divide the pllclk frequency to generate the core clock (cclk), the syst em clocks (sysclk) and the output clock (oclk). this is illustrated in figure 8 on page 34 . writing to the cgu control registers does not affect the behav- ior of the pll immediately. regi sters are first pr ogrammed with a new value, and the pll logic executes the changes so that it transitions smoo thly from the current conditions to the new ones. sys_clkin oscillations start when power is applied to the v dd_ext pins. the rising edge of sys_hwrst can be applied as soon as all voltage supplies are within specifications (see oper- ating conditions on page 34 ), and sys_clkin oscillations are stable. a sys_clkout output pin has programmable options to out- put divided-down versions of the on-chip clocks, including usb clocks. by default, the sys_clkout pin drives a buffered ver- sion of the sys_clkin input. clock generation faults (for example pll unlock) may tri gger a reset by hardware. clock out/external clock sys_clkout can be used to output one of several different clocks used on the processor. the clocks shown in table 4 can be outputs from sys_clkout. power management as shown in table 5 and figure 4 on page 6 , the processor sup- ports three different power domains, v dd_int , v dd_ext and v dd_ana . by isolating the internal logic of the processor into its own power domain, separate from other i/o, the processor can take advantage of dynamic power management without affect- ing the other i/o devices. there are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate specifications table for processor operating conditions; even if the fea- ture/peripheral is not used. the dynamic power management feature of the processor allows the processors core clock frequency (f cclk ) to be dynam- ically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation. for more information on power pins, see operating conditions on page 34 . full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the execution state in which maximum performance can be achieved. the processor core and all enabled peripherals run at full speed. table 3. power settings mode pll pll bypassed f cclk f sysclk core power full on enabled no enabled enabled on active enabled yes enabled enabled on disabled yes enabled enabled on deep sleep disabled disabled disabled on table 4. sys_clkout source and divider options clock source divider cclk (core clock) by 4 sysclk (system clock) none oclk (output clock) programmable usbclk programmable clkbuf none, direct from sys_clkin table 5. power domains power domain pin all internal logic v dd_int digital i/o v dd_ext analog v dd_ana preliminary technical data rev. pre | page 15 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f for more information about pl l controls, see the dynamic power management chapter in the adsp-cm40x mixed-signal control processor with arm co rtex-m4 hardware reference . deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proce ssor core and to all synchronous peripherals. asynchronous periph erals may still be running but cannot access internal reso urces or external memory. voltage regulation for vdd_int tbd reset control unit reset is the initial state of the whole processor or of the core and is the result of a hardware or so ftware triggered event. in this state, all control registers are set to their default values and func- tional units are idle. exiting a core only reset starts with the core being ready to boot. the reset control unit (rcu) co ntrols how all the functional units enter and exit reset. diff erences in functional require- ments and clocking constraints define how reset signals are generated. programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. from a system perspective reset is defined by both the reset tar- get and the reset source as described below. target defined: ? hardware reset C all functional units are set to their default states without exception. history is lost. ? system reset C all functional units except the rcu are set to their default states. ? the processor core-only reset C affects the core only. the system software should guarantee that the core in reset state is not accessed by any bus master. source defined: ? hardware reset C the sys_hwrst input signal is asserted active (pulled down). ? system reset C may be triggered by software (writing to the rcu_ctl register) or by another functional unit such as the dynamic power management (dpm) unit or any of the system event controller (sec), trigger routing unit (tru), or emulator inputs. ? trigger request (peripheral). system debug the processor includes various fe atures that allow for easy sys- tem debug. these are described in the following sections. jtag debug and serial wire debug port (swj-dp) swj-dp is a combined jtag-dp and sw-dp that enables either a serial wire debug (s wd) or jtag probe to be con- nected to a target. swd signals share the same pins as jtag. there is an auto detect mechanism that switches between jtag-dp and sw-dp depending on which special data sequence is used the emulator pod transmits to the jtag pins.the swj-dp behaves as a jtag target if normal jtag sequences are sent to it and as a single wire target if the sw_dp sequence is transmitted. embedded trace macrocell (etm) and instrumentation trace macrocell (itm) the adsp-cm40x processors su pport both embedded trace macrocell (etm) and instrument ation trace macrocell (itm). these both offer an optional de bug component that enables log- ging of real-time instruction and data flow within the cpu core. this data is stored and read through special debugger pods that have the trace feature capability . the itm is a single-data pin feature and the etm is a 4-data pin feature. system watchpoint unit the system watchpoint unit (swu) is a single module which connects to a single system bu s and provides for transaction monitoring. one swu is attached to the bus going to each system slave. the swu provides ports for all system bus address channel signals. each swu contains four match groups of regis- ters with associated hardware . these four swu match groups operate independently, but shar e common event (interrupt and trigger) outputs. development tools the adsp-cm40x processor is su pported with a set of highly sophisticated and easy-to-use development tools for embedded applications. for more information, see the analog devices website. related documents tbd instruction set description see arm documents. rev. pre | page 16 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains pa ge in the circuits from the lab tm site ( http:\\www.analog.com\circuits ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying best practice design techniques preliminary technical data rev. pre | page 17 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f ADSP-CM402F/adsp-cm40 3f signal descriptions table 6 identifies each signal on the chip, describes the signal, and lists the driver type, port, and lead name. table 6. ADSP-CM402F/adsp-c m403f signal descriptions signal description driver type port lead name adc0_vin00 channel 0 single-ended analog input for adc0 tbd not muxed adc0_vin00 adc0_vin01 channel 1 single-ended analog input for adc0 tbd not muxed adc0_vin01 adc0_vin02 channel 2 single-ended analog input for adc0 tbd not muxed adc0_vin02 adc0_vin03 channel 3 single-ended analog input for adc0 tbd not muxed adc0_vin03 adc0_vin04 channel 4 single-ended analog input for adc0 tbd not muxed adc0_vin04 adc0_vin05 channel 5 single-ended analog input for adc0 tbd not muxed adc0_vin05 adc0_vin06 channel 6 single-ended analog input for adc0 tbd not muxed adc0_vin06 adc0_vin07 channel 7 single-ended analog input for adc0 tbd not muxed adc0_vin07 adc0_vin08 channel 8 single-ended analog input for adc0 tbd not muxed adc0_vin08 adc0_vin09 channel 9 single-ended analog input for adc0 tbd not muxed adc0_vin09 adc0_vin10 channel 10 single-ended analog input for adc0 tbd not muxed adc0_vin10 adc0_vin11 channel 11 single-ended analog input for adc0 tbd not muxed adc0_vin11 adc1_vin00 channel 0 single-ended analog input for adc1 tbd not muxed adc1_vin00 adc1_vin01 channel 1 single-ended analog input for adc1 tbd not muxed adc1_vin01 adc1_vin02 channel 2 single-ended analog input for adc1 tbd not muxed adc1_vin02 adc1_vin03 channel 3 single-ended analog input for adc1 tbd not muxed adc1_vin03 adc1_vin04 channel 4 single-ended analog input for adc1 tbd not muxed adc1_vin04 adc1_vin05 channel 5 single-ended analog input for adc1 tbd not muxed adc1_vin05 adc1_vin06 channel 6 single-ended analog input for adc1 tbd not muxed adc1_vin06 adc1_vin07 channel 7 single-ended analog input for adc1 tbd not muxed adc1_vin07 adc1_vin08 channel 8 single-ended analog input for adc1 tbd not muxed adc1_vin08 adc1_vin09 channel 9 single-ended analog input for adc1 tbd not muxed adc1_vin09 adc1_vin10 channel 10 single-ended analog input for adc1 tbd not muxed adc1_vin10 adc1_vin11 channel 11 single-ended analog input for adc1 tbd not muxed adc1_vin11 byp_a0 on-chip analog power regulation by pass filter node for adc0 (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed byp_a0 byp_a1 on-chip analog power regulation by pass filter node for adc1 (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed byp_a1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem (see recommended bypass - figure 4 on page 6 ) tbd not muxed byp_d0 can0_rx can0 receive tbd b pb_15 can0_tx can0 transmit tbd c pc_00 can1_rx can1 receive tbd b pb_10 can1_tx can1 transmit tbd b pb_11 cnt0_dg cnt0 count down and gate tbd b pb_02 cnt0_outa cnt0 output divider a tbd b pb_13 cnt0_outb cnt0 output divider b tbd b pb_14 cnt0_ud cnt0 count up and direction tbd b pb_01 cnt0_zm cnt0 count zero marker tbd b pb_00 cnt1_dg cnt1 count down and gate tbd b pb_05 cnt1_ud cnt1 count up and direction tbd b pb_04 cnt1_zm cnt1 count zero marker tbd b pb_03 rev. pre | page 18 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data dac0_vout analog voltage output 0 tbd not muxed dac0_vout dac1_vout analog voltage output 1 tbd not muxed dac1_vout gnd digital ground tbd not muxed gnd gnd_ana0 analog ground return for vdd_ana0 (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana0 gnd_ana1 analog ground return for vdd_ana1 (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana1 gnd_ana2 analog ground (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana2 gnd_ana3 analog ground (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana3 gnd_vref0 ground return for vref0 (see recommended bypass filter- figure 4 on page 6 ) tbd not muxed gnd_vref0 gnd_vref1 ground return for vref1 (see recommended bypass filter- figure 4 on page 6 ) tbd not muxed gnd_vref1 jtg_tck/swclk jtg clock/serial wi re clock tbd not muxed jtg_tck/swclk jtg_tdi jtg serial data in tbd not muxed jtg_tdi jtg_tdo/swo jtg serial data out/serial wire trace output tbd not muxed jtg_tdo/swo jtg_tms/swdio jtg mode select/serial wire debug data i/o tbd not muxed jtg_tms/swdio jtg_trst jtg reset tbd not muxed jtg_trst pa_00 C pa_15 port a positions 0 C 15 tbd a pa_00 C pa_15 pb_00 C pb_15 port b positions 0 C 15 tbd b pb_00 C pb_15 pc_00 C pc_07 port c positions 0 C 7 tbd c pc_00 C pc_07 pwm0_ah pwm0 channel a high side tbd a pa_02 pwm0_al pwm0 channel a low side tbd a pa_03 pwm0_bh pwm0 channel b high side tbd a pa_04 pwm0_bl pwm0 channel b low side tbd a pa_05 pwm0_ch pwm0 channel c high side tbd a pa_06 pwm0_cl pwm0 channel c low side tbd a pa_07 pwm0_dh pwm0 channel d high side tbd b pb_00 pwm0_dl pwm0 channel d low side tbd b pb_01 pwm0_sync pwm0 sync tbd a pa_00 pwm0_trip0 pwm0 shutdown input 0 tbd a pa_01 pwm1_ah pwm1 channel a high side tbd a pa_12 pwm1_al pwm1 channel a low side tbd a pa_13 pwm1_bh pwm1 channel b high side tbd a pa_14 pwm1_bl pwm1 channel b low side tbd a pa_15 pwm1_ch pwm1 channel c high side tbd a pa_08 pwm1_cl pwm1 channel c low side tbd a pa_09 pwm1_dh pwm1 channel d high side tbd b pb_02 pwm1_dl pwm1 channel d low side tbd b pb_03 pwm1_sync pwm1 sync tbd a pa_10 pwm1_trip0 pwm1 shutdown input 0 tbd a pa_11 pwm2_ah pwm2 channel a high side tbd b pb_06 pwm2_al pwm2 channel a low side tbd b pb_07 pwm2_bh pwm2 channel b high side tbd b pb_08 pwm2_bl pwm2 channel b low side tbd b pb_09 pwm2_ch pwm2 channel c high side tbd c pc_03 pwm2_cl pwm2 channel c low side tbd c pc_04 pwm2_dh pwm2 channel d high side tbd c pc_05 table 6. ADSP-CM402F/adsp-cm403f si gnal descriptions (continued) signal description driver type port lead name preliminary technical data rev. pre | page 19 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f pwm2_dl pwm2 channel d low side tbd c pc_06 pwm2_sync pwm2 sync tbd b pb_04 pwm2_trip0 pwm2 shutdown input 0 tbd b pb_05 refcap output of bandgap generator filter node (see recommended bypass filter - figure 4 on page 6 ) tbd not muxed refcap sinc0_clk0 sinc0 clock 0 tbd b pb_10 sinc0_clk1 sinc0 clock 1 tbd c pc_07 sinc0_d0 sinc0 data 0 tbd b pb_11 sinc0_d1 sinc0 data 1 tbd b pb_12 sinc0_d2 sinc0 data 2 tbd b pb_13 sinc0_d3 sinc0 data 3 tbd b pb_14 smc0_a01 smc0 address 1 tbd b pb_13 smc0_a02 smc0 address 2 tbd b pb_14 smc0_a03 smc0 address 3 tbd b pb_15 smc0_a04 smc0 address 4 tbd c pc_00 smc0_a05 smc0 address 5 tbd c pc_01 smc0_ams0 smc0 memory select 0 tbd b pb_11 smc0_ams2 smc0 memory select 2 tbd a pa_07 smc0_aoe smc0 output enable tbd b pb_12 smc0_ardy smc0 asynchronous ready tbd b pb_08 smc0_are smc0 read enable tbd b pb_09 smc0_awe smc0 write enable tbd b pb_10 smc0_d00 smc0 data 0 tbd a pa_08 smc0_d01 smc0 data 1 tbd a pa_09 smc0_d02 smc0 data 2 tbd a pa_10 smc0_d03 smc0 data 3 tbd a pa_11 smc0_d04 smc0 data 4 tbd a pa_12 smc0_d05 smc0 data 5 tbd a pa_13 smc0_d06 smc0 data 6 tbd a pa_14 smc0_d07 smc0 data 7 tbd a pa_15 smc0_d08 smc0 data 8 tbd b pb_00 smc0_d09 smc0 data 9 tbd b pb_01 smc0_d10 smc0 data 10 tbd b pb_02 smc0_d11 smc0 data 11 tbd b pb_03 smc0_d12 smc0 data 12 tbd b pb_04 smc0_d13 smc0 data 13 tbd b pb_05 smc0_d14 smc0 data 14 tbd b pb_06 smc0_d15 smc0 data 15 tbd b pb_07 spi0_clk spi0 clock tbd c pc_03 spi0_d2 spi0 data 2 tbd b pb_10 spi0_d3 spi0 data 3 tbd b pb_11 spi0_miso spi0 master in, slave out tbd c pc_04 spi0_mosi spi0 master out, slave in tbd c pc_05 spi0_rdy spi0 ready tbd c pc_02 spi0_sel1 spi0 slave select output 1 tbd c pc_06 spi0_sel2 spi0 slave select output 2 tbd b pb_13 table 6. ADSP-CM402F/adsp-cm403f si gnal descriptions (continued) signal description driver type port lead name rev. pre | page 20 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data spi0_sel3 spi0 slave select output 3 tbd b pb_14 spi0_ss spi0 slave select input tbd b pb_14 spt0_aclk sport0 channel a clock tbd b pb_00 spt0_ad0 sport0 channe l a data 0 tbd b pb_02 spt0_ad1 sport0 channe l a data 1 tbd b pb_03 spt0_afs sport0 channel a frame sync tbd b pb_01 spt0_atdv sport0 channel a transmit data valid tbd b pb_04 spt1_aclk sport1 channel a clock tbd a pa_00 spt1_ad0 sport1 channe l a data 0 tbd a pa_02 spt1_ad1 sport1 channe l a data 1 tbd a pa_03 spt1_afs sport1 channel a frame sync tbd a pa_01 spt1_atdv sport1 channel a transmit data valid tbd b pb_15 spt1_bclk sport1 channel b clock tbd a pa_04 spt1_bd0 sport1 channel b data 0 tbd a pa_06 spt1_bd1 sport1 channel b data 1 tbd a pa_07 spt1_bfs sport1 channel b frame sync tbd a pa_05 spt1_btdv sport1 channel b transmit data valid tbd c pc_00 sys_bmode0 system boot mode control 0 tbd not muxed sys_bmode0 sys_bmode1 system boot mode control 1 tbd not muxed sys_bmode1 sys_clkin system clock/crystal input tbd not muxed sys_clkin sys_clkout system processor clock output tbd not muxed sys_clkout sys_dswake0 system deep sleep wakeup 0 tbd c pc_06 sys_dswake1 system deep sleep wakeup 1 tbd c pc_07 sys_dswake2 system deep sleep wakeup 2 tbd b pb_14 sys_dswake3 system deep sleep wakeup 3 tbd b pb_13 sys_fault system complementary fault output tbd not muxed sys_fault sys_hwrst system processor hardware reset control tbd not muxed sys_hwrst sys_nmi system non-maskable interrupt tbd not muxed sys_nmi sys_resout system reset output tbd not muxed sys_resout sys_xtal system crystal output tbd not muxed sys_xtal tm0_aci1 timer0 alternate capture input 1 tbd b pb_10 tm0_aci2 timer0 alternate capture input 2 tbd b pb_08 tm0_aci3 timer0 alternate capture input 3 tbd b pb_12 tm0_aci4 timer0 alternate capture input 4 tbd b pb_15 tm0_aci5 timer0 alternate capture input 5 tbd c pc_01 tm0_aclk0 timer0 alternate clock 0 tbd b pb_13 tm0_aclk1 timer0 alternate clock 1 tbd b pb_11 tm0_aclk2 timer0 alternate clock 2 tbd a pa_11 tm0_aclk3 timer0 alternate clock 3 tbd a pa_10 tm0_aclk4 timer0 alternate clock 4 tbd a pa_09 tm0_aclk5 timer0 alternate clock 5 tbd a pa_08 tm0_clk timer0 clock tbd b pb_06 tm0_tmr0 timer0 timer 0 tbd b pb_07 tm0_tmr1 timer0 timer 1 tbd b pb_08 tm0_tmr2 timer0 timer 2 tbd b pb_09 table 6. ADSP-CM402F/adsp-cm403f si gnal descriptions (continued) signal description driver type port lead name preliminary technical data rev. pre | page 21 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f tm0_tmr3 timer0 timer 3 tbd a pa_15 tm0_tmr4 timer0 timer 4 tbd a pa_12 tm0_tmr5 timer0 timer 5 tbd a pa_13 tm0_tmr6 timer0 timer 6 tbd a pa_14 tm0_tmr7 timer0 timer 7 tbd b pb_05 trace_clk embedded trace module clock tbd b pb_00 trace_d0 embedded trace module data 0 tbd b pb_01 trace_d1 embedded trace module data 1 tbd b pb_02 trace_d2 embedded trace module data 2 tbd b pb_03 trace_d3 embedded trace module data 3 tbd c pc_02 twi0_scl twi0 serial clock tbd not muxed twi0_scl twi0_sda twi0 serial data tbd not muxed twi0_sda uart0_cts uart0 clear to send tbd b pb_05 uart0_rts uart0 request to send tbd b pb_04 uart0_rx uart0 receive tbd c pc_01 uart0_tx uart0 transmit tbd c pc_02 uart1_cts uart1 clear to send tbd a pa_11 uart1_rts uart1 request to send tbd c pc_07 uart1_rx uart1 receive tbd b pb_08 uart1_rx uart1 receive tbd b pb_15 uart1_tx uart1 transmit tbd b pb_09 uart1_tx uart1 transmit tbd c pc_00 uart2_rx uart2 receive tbd b pb_12 uart2_tx uart2 transmit tbd c pc_07 vdd_ana0 analog power supply voltage (see recommended bypass - figure 4 on page 6 ) tbd not muxed vdd_ana0 vdd_ana1 analog power supply voltage (see recommended bypass - figure 4 on page 6 ) tbd not muxed vdd_ana1 vdd_ext external voltage domain tbd not muxed vdd_ext vdd_int internal voltage do main tbd not muxed vdd_int vdd_vreg vreg supply voltage tbd not muxed vdd_vreg vref0 voltage reference for adc0. default co nfiguration is output (see recommended bypass - figure 4 on page 6 ) tbd not muxed vref0 vref1 voltage reference for adc1. default co nfiguration is output (see recommended bypass - figure 4 on page 6 ) tbd not muxed vref1 vreg_base voltage regulator bas e node tbd not muxed vreg_base table 6. ADSP-CM402F/adsp-cm403f si gnal descriptions (continued) signal description driver type port lead name rev. pre | page 22 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data ADSP-CM402F/adsp-cm403f multiplexed pins table 7 through table 9 identify the signals on each multiplexed pin on the chip, one table per port. the various functions are accessed through the indicated port_fer register and port_mux register settings for each port. table 7. signal muxing table port a port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pa_00 pwm0_sync spt1_aclk pa_01 pwm0_trip0 spt1_afs pa_02 pwm0_ah spt1_ad0 pa_03 pwm0_al spt1_ad1 pa_04 pwm0_bh spt1_bclk pa_05 pwm0_bl spt1_bfs pa_06 pwm0_ch spt1_bd0 pa_07 pwm0_cl smc0_ams2 spt1_bd1 pa_08 pwm1_ch smc0_d00 tm0_aclk5 pa_09 pwm1_cl smc0_d01 tm0_aclk4 pa_10 pwm1_sync smc0_d02 tm0_aclk3 pa_11 pwm1_trip0 uart1_cts smc0_d03 tm0_aclk2 pa_12 pwm1_ah tm0_tmr4 smc0_d04 pa_13 pwm1_al tm0_tmr5 smc0_d05 pa_14 pwm1_bh tm0_tmr6 smc0_d06 pa_15 pwm1_bl tm0_tmr3 smc0_d07 table 8. signal muxing table port b port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port_mux=b#10 port_mux=b#11 input tap pb_00 pwm0_dh trace_clk spt0_aclk smc0_d08 cnt0_zm pb_01 pwm0_dl trace_d0 spt0_afs smc0_d09 cnt0_ud pb_02 pwm1_dh trace_d1 spt0_ad0 smc0_d10 cnt0_dg pb_03 pwm1_dl trace_d2 spt0_ad1 smc0_d11 cnt1_zm pb_04 pwm2_sync uart0_rts spt0_atdv smc0_d12 cnt1_ud pb_05 pwm2_trip0 uart0_cts tm0_tmr7 smc0_d13 cnt1_dg pb_06 pwm2_ah tm0_clk smc0_d14 pb_07 pwm2_al tm0_tmr0 smc0_d15 pb_08 pwm2_bh tm0_tmr1 uart1_rx smc0_ardy tm0_aci2 pb_09 pwm2_bl tm0_tmr2 uart1_tx smc0_are pb_10 sinc0_clk0 spi0_d2 can1_rx smc0_awe tm0_aci1 pb_11 sinc0_d0 spi0_d3 can1_tx smc0_ams0 tm0_aclk1 pb_12 sinc0_d1 uart2_rx smc0_aoe tm0_aci3 pb_13 sinc0_d2 cnt0_outa spi0_sel2 smc0_a01 tm0_aclk0/sys_dswake3 pb_14 sinc0_d3 cnt0_outb spi0_sel3 smc0_a02 spi0_ss /sys_dswake2 pb_15 can0_rx spt1_atdv uart1_rx smc0_a03 tm0_aci4 preliminary technical data rev. pre | page 23 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 9. signal muxing table port c port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pc_00 can0_tx spt1_btdv uart1_tx smc0_a04 pc_01 uart0_rx smc0_a05 tm0_aci5 pc_02 uart0_tx trace_d3 spi0_rdy pc_03 spi0_clk pwm2_ch pc_04 spi0_miso pwm2_cl pc_05 spi0_mosi pwm2_dh pc_06 spi0_sel1 pwm2_dl sys_dswake0 pc_07 sinc0_clk1 uart2_tx uart1_rts sys_dswake1 rev. pre | page 24 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data adsp-cm407f/adsp-cm40 8f signal descriptions table 10 identifies each signal on the chip, describes the signal, and lists the driver type, port, and lead name. table 10. adsp-cm407f/adsp-cm408f signal descriptions signal description driver type port lead name adc0_vin00 channel 0 single-ended analog input for adc0 tbd not muxed adc0_vin00 adc0_vin01 channel 1 single-ended analog input for adc0 tbd not muxed adc0_vin01 adc0_vin02 channel 2 single-ended analog input for adc0 tbd not muxed adc0_vin02 adc0_vin03 channel 3 single-ended analog input for adc0 tbd not muxed adc0_vin03 adc0_vin04 channel 4 single-ended analog input for adc0 tbd not muxed adc0_vin04 adc0_vin05 channel 5 single-ended analog input for adc0 tbd not muxed adc0_vin05 adc0_vin06 channel 6 single-ended analog input for adc0 tbd not muxed adc0_vin06 adc0_vin07 channel 7 single-ended analog input for adc0 tbd not muxed adc0_vin07 adc1_vin00 channel 0 single-ended analog input for adc1 tbd not muxed adc1_vin00 adc1_vin01 channel 1 single-ended analog input for adc1 tbd not muxed adc1_vin01 adc1_vin02 channel 2 single-ended analog input for adc1 tbd not muxed adc1_vin02 adc1_vin03 channel 3 single-ended analog input for adc1 tbd not muxed adc1_vin03 adc1_vin04 channel 4 single-ended analog input for adc1 tbd not muxed adc1_vin04 adc1_vin05 channel 5 single-ended analog input for adc1 tbd not muxed adc1_vin05 adc1_vin06 channel 6 single-ended analog input for adc1 tbd not muxed adc1_vin06 adc1_vin07 channel 7 single-ended analog input for adc1 tbd not muxed adc1_vin07 byp_a0 on-chip analog power regulation by pass filter node for adc0 (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed byp_a0 byp_a1 on-chip analog power regulation by pass filter node for adc1 (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed byp_a1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem (see recommended bypass - figure 4 on page 6 ) tbd not muxed byp_d0 can0_rx can0 receive tbd b pb_15 can0_tx can0 transmit tbd c pc_00 can1_rx can1 receive tbd b pb_10 can1_tx can1 transmit tbd b pb_11 cnt0_dg cnt0 count down and gate tbd b pb_02 cnt0_outa cnt0 output divider a tbd b pb_13 cnt0_outa cnt0 output divider a tbd f pf_00 cnt0_outb cnt0 output divider b tbd b pb_14 cnt0_outb cnt0 output divider b tbd f pf_01 cnt0_ud cnt0 count up and direction tbd b pb_01 cnt0_zm cnt0 count zero marker tbd b pb_00 cnt1_dg cnt1 count down and gate tbd b pb_05 cnt1_outa cnt1 output divider a tbd e pe_14 cnt1_outb cnt1 output divider b tbd e pe_15 cnt1_ud cnt1 count up and direction tbd b pb_04 cnt1_zm cnt1 count zero marker tbd b pb_03 cnt2_dg cnt2 count down and gate tbd e pe_10 cnt2_ud cnt2 count up and direction tbd e pe_09 cnt2_zm cnt2 count zero marker tbd e pe_08 cnt3_dg cnt3 count down and gate tbd e pe_13 preliminary technical data rev. pre | page 25 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f cnt3_ud cnt3 count up and direction tbd e pe_12 cnt3_zm cnt3 count zero marker tbd e pe_11 eth0_crs emac0 carrier sense/rmii receive data valid tbd e pe_09 eth0_mdc emac0 management channel clock tbd e pe_11 eth0_mdio emac0 management channel serial data tbd e pe_10 eth0_ptpauxin emac0 ptp auxiliary trigger input tbd e pe_07 eth0_ptpclkin emac0 ptp clock input tbd f pf_10 eth0_ptppps emac0 ptp pulse-per-second output tbd e pe_08 eth0_refclk emac0 reference clock tbd e pe_15 eth0_rxd0 emac0 receive data 0 tbd f pf_00 eth0_rxd1 emac0 receive data 1 tbd f pf_01 eth0_txd0 emac0 transmit data 0 tbd e pe_12 eth0_txd1 emac0 transmit data 1 tbd e pe_13 eth0_txen emac0 transmit enable tbd e pe_14 gnd digital ground tbd not muxed gnd gnd_ana0 analog ground return for vdd_ana0 (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana0 gnd_ana1 analog ground return for vdd_ana1 (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana1 gnd_ana2 analog ground (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana2 gnd_ana3 analog ground (see recommended bypass - figure 4 on page 6 ) tbd not muxed gnd_ana3 gnd_vref0 ground return for vref0 (see recommended bypass filter- figure 4 on page 6 ) tbd not muxed gnd_vref0 gnd_vref1 ground return for vref1 (see recommended bypass filter- figure 4 on page 6 ) tbd not muxed gnd_vref1 jtg_tck/swclk jtg clock/serial wire clock tbd not muxed jtg_tck/swclk jtg_tdi jtg serial data in tbd not muxed jtg_tdi jtg_tdo/swo jtg serial data out/serial wire trace output tbd not muxed jtg_tdo/swo jtg_tms/swdio jtg mode select/serial wire debug data i/o tbd not muxed jtg_tms/swdio jtg_trst jtg reset tbd not muxed jtg_trst pa_00 C pa_15 port a positions 0 C 15 tbd a pa_00 C pa_15 pb_00 C pb_15 port b positions 0 C 15 tbd b pb_00 C pb_15 pc_00 C pc_15 port c positions 0 C 15 tbd c pc_00 C pc_15 pd_00 C pd_15 port d positions 0 C 15 tbd d pd_00 C pd_15 pe_00 C pe_15 port e positions 0 C 15 tbd e pe_00 C pe_15 pf_00 C pf_10 port f positions 0 C 10 tbd f pf_00 C pf_10 pwm0_ah pwm0 channel a high side tbd a pa_02 pwm0_al pwm0 channel a low side tbd a pa_03 pwm0_bh pwm0 channel b high side tbd a pa_04 pwm0_bl pwm0 channel b low side tbd a pa_05 pwm0_ch pwm0 channel c high side tbd a pa_06 pwm0_cl pwm0 channel c low side tbd a pa_07 pwm0_dh pwm0 channel d high side tbd b pb_00 pwm0_dl pwm0 channel d low side tbd b pb_01 pwm0_sync pwm0 sync tbd a pa_00 pwm0_trip0 pwm0 shutdown input 0 tbd a pa_01 table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name rev. pre | page 26 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data pwm1_ah pwm1 channel a high side tbd a pa_12 pwm1_al pwm1 channel a low side tbd a pa_13 pwm1_bh pwm1 channel b high side tbd a pa_14 pwm1_bl pwm1 channel b low side tbd a pa_15 pwm1_ch pwm1 channel c high side tbd a pa_08 pwm1_cl pwm1 channel c low side tbd a pa_09 pwm1_dh pwm1 channel d high side tbd b pb_02 pwm1_dl pwm1 channel d low side tbd b pb_03 pwm1_sync pwm1 sync tbd a pa_10 pwm1_trip0 pwm1 shutdown input 0 tbd a pa_11 pwm2_ah pwm2 channel a high side tbd b pb_06 pwm2_al pwm2 channel a low side tbd b pb_07 pwm2_bh pwm2 channel b high side tbd b pb_08 pwm2_bl pwm2 channel b low side tbd b pb_09 pwm2_ch pwm2 channel c high side tbd c pc_03 pwm2_cl pwm2 channel c low side tbd c pc_04 pwm2_dh pwm2 channel d high side tbd c pc_05 pwm2_dl pwm2 channel d low side tbd c pc_06 pwm2_sync pwm2 sync tbd b pb_04 pwm2_trip0 pwm2 shutdown input 0 tbd b pb_05 refcap output of bandgap generator filt er node (see recommended bypass filter - figure 4 on page 6 ) tbd not muxed refcap sinc0_clk0 sinc0 clock 0 tbd b pb_10 sinc0_clk1 sinc0 clock 1 tbd c pc_07 sinc0_d0 sinc0 data 0 tbd b pb_11 sinc0_d1 sinc0 data 1 tbd b pb_12 sinc0_d2 sinc0 data 2 tbd b pb_13 sinc0_d3 sinc0 data 3 tbd b pb_14 smc0_a01 smc0 address 1 tbd b pb_13 smc0_a01 smc0 address 1 tbd f pf_05 smc0_a02 smc0 address 2 tbd b pb_14 smc0_a02 smc0 address 2 tbd f pf_06 smc0_a03 smc0 address 3 tbd b pb_15 smc0_a03 smc0 address 3 tbd f pf_07 smc0_a04 smc0 address 4 tbd c pc_00 smc0_a04 smc0 address 4 tbd f pf_08 smc0_a05 smc0 address 5 tbd c pc_01 smc0_a05 smc0 address 5 tbd f pf_09 smc0_a06 smc0 address 6 tbd d pd_08 smc0_a07 smc0 address 7 tbd d pd_09 smc0_a08 smc0 address 8 tbd d pd_10 smc0_a09 smc0 address 9 tbd d pd_11 smc0_a10 smc0 address 10 tbd d pd_12 smc0_a11 smc0 address 11 tbd d pd_13 smc0_a12 smc0 address 12 tbd d pd_14 smc0_a13 smc0 address 13 tbd d pd_15 table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name preliminary technical data rev. pre | page 27 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f smc0_a14 smc0 address 14 tbd e pe_00 smc0_a15 smc0 address 15 tbd e pe_01 smc0_a16 smc0 address 16 tbd e pe_02 smc0_a17 smc0 address 17 tbd e pe_03 smc0_a18 smc0 address 18 tbd e pe_04 smc0_a19 smc0 address 19 tbd e pe_05 smc0_a20 smc0 address 20 tbd e pe_06 smc0_a21 smc0 address 21 tbd e pe_07 smc0_a22 smc0 address 22 tbd e pe_08 smc0_a23 smc0 address 23 tbd e pe_09 smc0_a24 smc0 address 24 tbd e pe_11 smc0_abe0 smc0 byte enable 0 tbd e pe_12 smc0_abe1 smc0 byte enable 1 tbd e pe_13 smc0_ams0 smc0 memory select 0 tbd b pb_11 smc0_ams0 smc0 memory select 0 tbd not muxed smc0_ams0 smc0_ams1 smc0 memory select 1 tbd e pe_10 smc0_ams2 smc0 memory select 2 tbd a pa_07 smc0_ams3 smc0 memory select 3 tbd c pc_11 smc0_aoe smc0 output enable tbd b pb_12 smc0_aoe smc0 output enable tbd f pf_03 smc0_ardy smc0 asynchronous ready tbd b pb_08 smc0_ardy smc0 asynchronous ready tbd f pf_04 smc0_are smc0 read enable tbd b pb_09 smc0_are smc0 read enable tbd not muxed smc0_are smc0_awe smc0 write enable tbd b pb_10 smc0_awe smc0 write enable tbd not muxed smc0_awe smc0_d00 smc0 data 0 tbd a pa_08 smc0_d00 smc0 data 0 tbd c pc_08 smc0_d01 smc0 data 1 tbd a pa_09 smc0_d01 smc0 data 1 tbd c pc_09 smc0_d02 smc0 data 2 tbd a pa_10 smc0_d02 smc0 data 2 tbd c pc_10 smc0_d03 smc0 data 3 tbd a pa_11 smc0_d03 smc0 data 3 tbd c pc_11 smc0_d04 smc0 data 4 tbd a pa_12 smc0_d04 smc0 data 4 tbd c pc_12 smc0_d05 smc0 data 5 tbd a pa_13 smc0_d05 smc0 data 5 tbd c pc_13 smc0_d06 smc0 data 6 tbd a pa_14 smc0_d06 smc0 data 6 tbd c pc_14 smc0_d07 smc0 data 7 tbd a pa_15 smc0_d07 smc0 data 7 tbd c pc_15 smc0_d08 smc0 data 8 tbd b pb_00 smc0_d08 smc0 data 8 tbd d pd_00 smc0_d09 smc0 data 9 tbd b pb_01 table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name rev. pre | page 28 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data smc0_d09 smc0 data 9 tbd d pd_01 smc0_d10 smc0 data 10 tbd b pb_02 smc0_d10 smc0 data 10 tbd d pd_02 smc0_d11 smc0 data 11 tbd b pb_03 smc0_d11 smc0 data 11 tbd d pd_03 smc0_d12 smc0 data 12 tbd b pb_04 smc0_d12 smc0 data 12 tbd d pd_04 smc0_d13 smc0 data 13 tbd b pb_05 smc0_d13 smc0 data 13 tbd d pd_05 smc0_d14 smc0 data 14 tbd b pb_06 smc0_d14 smc0 data 14 tbd d pd_06 smc0_d15 smc0 data 15 tbd b pb_07 smc0_d15 smc0 data 15 tbd d pd_07 spi0_clk spi0 clock tbd c pc_03 spi0_d2 spi0 data 2 tbd b pb_10 spi0_d3 spi0 data 3 tbd b pb_11 spi0_miso spi0 master in, slave out tbd c pc_04 spi0_mosi spi0 master out, slave in tbd c pc_05 spi0_rdy spi0 ready tbd c pc_02 spi0_sel1 spi0 slave select output 1 tbd c pc_06 spi0_sel2 spi0 slave select output 2 tbd b pb_13 spi0_sel3 spi0 slave select output 3 tbd b pb_14 spi0_ss spi0 slave select input tbd b pb_14 spi1_clk spi1 clock tbd c pc_12 spi1_miso spi1 master in, slave out tbd c pc_13 spi1_mosi spi1 master out, slave in tbd c pc_14 spi1_sel1 spi1 slave select output 1 tbd c pc_15 spi1_sel2 spi1 slave select output 2 tbd b pb_06 spi1_sel3 spi1 slave select output 3 tbd b pb_07 spi1_ss spi1 slave select input tbd c pc_15 spt0_aclk sport0 channel a clock tbd b pb_00 spt0_ad0 sport0 channel a data 0 tbd b pb_02 spt0_ad1 sport0 channel a data 1 tbd b pb_03 spt0_afs sport0 channel a frame sync tbd b pb_01 spt0_atdv sport0 channel a transmit data valid tbd b pb_04 spt0_bclk sport0 channel b clock tbd c pc_08 spt0_bd0 sport0 channel b data 0 tbd c pc_10 spt0_bd1 sport0 channel b data 1 tbd c pc_11 spt0_bfs sport0 channel b frame sync tbd c pc_09 spt0_btdv sport0 channel b transmit data valid tbd b pb_12 spt1_aclk sport1 channel a clock tbd a pa_00 spt1_ad0 sport1 channel a data 0 tbd a pa_02 spt1_ad1 sport1 channel a data 1 tbd a pa_03 spt1_afs sport1 channel a frame sync tbd a pa_01 spt1_atdv sport1 channel a transmit data valid tbd b pb_15 table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name preliminary technical data rev. pre | page 29 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f spt1_bclk sport1 channel b clock tbd a pa_04 spt1_bd0 sport1 channel b data 0 tbd a pa_06 spt1_bd1 sport1 channel b data 1 tbd a pa_07 spt1_bfs sport1 channel b frame sync tbd a pa_05 spt1_btdv sport1 channel b transmit data valid tbd c pc_00 sys_bmode0 system boot mode control 0 tbd not muxed sys_bmode0 sys_bmode1 system boot mode control 1 tbd not muxed sys_bmode1 sys_clkin system clock/crystal input tbd not muxed sys_clkin sys_clkout system processor clock output tbd not muxed sys_clkout sys_dswake0 system deep sleep wakeup 0 tbd c pc_06 sys_dswake1 system deep sleep wakeup 1 tbd c pc_07 sys_dswake2 system deep sleep wakeup 2 tbd b pb_14 sys_dswake3 system deep sleep wakeup 3 tbd b pb_13 sys_fault system complementary fault output tbd not muxed sys_fault sys_hwrst system processor hardware reset control tbd not muxed sys_hwrst sys_nmi system non-maskable interrupt tbd not muxed sys_nmi sys_resout system reset output tbd not muxed sys_resout sys_xtal system crystal output tbd not muxed sys_xtal tm0_aci1 timer0 alternate capture input 1 tbd b pb_10 tm0_aci2 timer0 alternate capture input 2 tbd b pb_08 tm0_aci3 timer0 alternate capture input 3 tbd b pb_12 tm0_aci4 timer0 alternate capture input 4 tbd b pb_15 tm0_aci5 timer0 alternate capture input 5 tbd c pc_01 tm0_aclk0 timer0 alternate clock 0 tbd b pb_13 tm0_aclk1 timer0 alternate clock 1 tbd b pb_11 tm0_aclk2 timer0 alternate clock 2 tbd a pa_11 tm0_aclk3 timer0 alternate clock 3 tbd a pa_10 tm0_aclk4 timer0 alternate clock 4 tbd a pa_09 tm0_aclk5 timer0 alternate clock 5 tbd a pa_08 tm0_clk timer0 clock tbd b pb_06 tm0_tmr0 timer0 timer 0 tbd b pb_07 tm0_tmr1 timer0 timer 1 tbd b pb_08 tm0_tmr2 timer0 timer 2 tbd b pb_09 tm0_tmr3 timer0 timer 3 tbd a pa_15 tm0_tmr4 timer0 timer 4 tbd a pa_12 tm0_tmr5 timer0 timer 5 tbd a pa_13 tm0_tmr6 timer0 timer 6 tbd a pa_14 tm0_tmr7 timer0 timer 7 tbd b pb_05 trace_clk clock tbd b pb_00 trace_d0 embedded trace module data 0 tbd b pb_01 trace_d1 embedded trace module data 1 tbd b pb_02 trace_d2 embedded trace module data 2 tbd b pb_03 trace_d3 embedded trace module data 3 tbd c pc_02 trace_d3 embedded trace module data 3 tbd f pf_02 twi0_scl twi0 serial clock tbd not muxed twi0_scl table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name rev. pre | page 30 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data twi0_sda twi0 serial data tbd not muxed twi0_sda uart0_cts uart0 clear to send tbd b pb_05 uart0_rts uart0 request to send tbd b pb_04 uart0_rx uart0 receive tbd c pc_01 uart0_tx uart0 transmit tbd c pc_02 uart1_cts uart1 clear to send tbd a pa_11 uart1_rts uart1 request to send tbd c pc_07 uart1_rx uart1 receive tbd b pb_08 uart1_rx uart1 receive tbd b pb_15 uart1_tx uart1 transmit tbd b pb_09 uart1_tx uart1 transmit tbd c pc_00 uart2_rx uart2 receive tbd b pb_12 uart2_tx uart2 transmit tbd c pc_07 usb0_dm usb0 data - tbd not muxed usb0_dm usb0_dp usb0 data + tbd not muxed usb0_dp usb0_id usb0 otg id tbd not muxed usb0_id usb0_vbc usb0 vbus control tbd f pf_02 usb0_vbus usb0 bus voltage tbd not muxed usb0_vbus vdd_ana0 analog power supply voltage (see recommended bypass - figure 4 on page 6 ) tbd not muxed vdd_ana0 vdd_ana1 analog power supply voltage (see recommended bypass - figure 4 on page 6 ) tbd not muxed vdd_ana1 vdd_ext external voltage domain tbd not muxed vdd_ext vdd_int internal voltage do main tbd not muxed vdd_int vdd_vreg vreg supply voltage tbd not muxed vdd_vreg vref0 voltage reference for adc0. default configuration is output (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed vref0 vref1 voltage reference for adc1. default configuration is output (see recom- mended bypass - figure 4 on page 6 ) tbd not muxed vref1 vreg_base voltage regulator base node tbd not muxed vreg_base table 10. adsp-cm407f/adsp-cm408f si gnal descriptions (continued) signal description driver type port lead name preliminary technical data rev. pre | page 31 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f adsp-cm407f/adsp-cm408f multiplexed pins table 11 through table 16 identify the signals on each multi- plexed pin on the chip, one tabl e per port. the various functions are accessed through the indicated port_fer register and port_mux register settings for each port. table 11. signal muxing table port a port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pa_00 pwm0_sync spt1_aclk pa_01 pwm0_trip0 spt1_afs pa_02 pwm0_ah spt1_ad0 pa_03 pwm0_al spt1_ad1 pa_04 pwm0_bh spt1_bclk pa_05 pwm0_bl spt1_bfs pa_06 pwm0_ch spt1_bd0 pa_07 pwm0_cl smc0_ams2 spt1_bd1 pa_08 pwm1_ch smc0_d00 tm0_aclk5 pa_09 pwm1_cl smc0_d01 tm0_aclk4 pa_10 pwm1_sync smc0_d02 tm0_aclk3 pa_11 pwm1_trip0 uart1_cts smc0_d03 tm0_aclk2 pa_12 pwm1_ah tm0_tmr4 smc0_d04 pa_13 pwm1_al tm0_tmr5 smc0_d05 pa_14 pwm1_bh tm0_tmr6 smc0_d06 pa_15 pwm1_bl tm0_tmr3 smc0_d07 table 12. signal muxing table port b port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pb_00 pwm0_dh trace_clk spt0_aclk smc0_d08 cnt0_zm pb_01 pwm0_dl trace_d0 spt0_afs smc0_d09 cnt0_ud pb_02 pwm1_dh trace_d1 spt0_ad0 smc0_d10 cnt0_dg pb_03 pwm1_dl trace_d2 spt0_ad1 smc0_d11 cnt1_zm pb_04 pwm2_sync uart0_rts spt0_atdv smc0_d12 cnt1_ud pb_05 pwm2_trip0 uart0_cts tm0_tmr7 smc0_d13 cnt1_dg pb_06 pwm2_ah tm0_clk spi1_sel2 smc0_d14 pb_07 pwm2_al tm0_tmr0 spi1_sel3 smc0_d15 pb_08 pwm2_bh tm0_tmr1 uart1_rx smc0_ardy tm0_aci2 pb_09 pwm2_bl tm0_tmr2 uart1_tx smc0_are pb_10 sinc0_clk0 spi0_d2 can1_rx smc0_awe tm0_aci1 pb_11 sinc0_d0 spi0_d3 can1_tx smc0_ams0 tm0_aclk1 pb_12 sinc0_d1 spt0_btdv uart2_rx smc0_aoe tm0_aci3 pb_13 sinc0_d2 cnt0_outa spi0_sel2 smc0_a01 tm0_aclk0/sys_dswake3 pb_14 sinc0_d3 cnt0_outb spi0_sel3 smc0_a02 spi0_ss /sys_dswake2 pb_15 can0_rx spt1_atdv uart1_rx smc0_a03 tm0_aci4 rev. pre | page 32 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data table 13. signal muxing table port c port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pc_00 can0_tx spt1_btdv uart1_tx smc0_a04 pc_01 uart0_rx smc0_a05 tm0_aci5 pc_02 uart0_tx trace_d3 spi0_rdy pc_03 spi0_clk pwm2_ch pc_04 spi0_miso pwm2_cl pc_05 spi0_mosi pwm2_dh pc_06 spi0_sel1 pwm2_dl sys_dswake0 pc_07 sinc0_clk1 uart2_tx uart1_rts sys_dswake1 pc_08 spt0_bclk smc0_d00 pc_09 spt0_bfs smc0_d01 pc_10 spt0_bd0 smc0_d02 pc_11 smc0_ams3 spt0_bd1 smc0_d03 pc_12 spi1_clk smc0_d04 pc_13 spi1_miso smc0_d05 pc_14 spi1_mosi smc0_d06 pc_15 spi1_sel1 smc0_d07 spi1_ss table 14. signal muxing table port d port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pd_00 smc0_d08 pd_01 smc0_d09 pd_02 smc0_d10 pd_03 smc0_d11 pd_04 smc0_d12 pd_05 smc0_d13 pd_06 smc0_d14 pd_07 smc0_d15 pd_08 smc0_a06 pd_09 smc0_a07 pd_10 smc0_a08 pd_11 smc0_a09 pd_12 smc0_a10 pd_13 smc0_a11 pd_14 smc0_a12 pd_15 smc0_a13 preliminary technical data rev. pre | page 33 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 15. signal muxing table port e port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pe_00 smc0_a14 pe_01 smc0_a15 pe_02 smc0_a16 pe_03 smc0_a17 pe_04 smc0_a18 pe_05 smc0_a19 pe_06 smc0_a20 pe_07 eth0_ptpauxin smc0_a21 pe_08 eth0_ptppps smc0_a22 cnt2_zm pe_09 eth0_crs smc0_a23 cnt2_ud pe_10 eth0_mdio smc0_ams1 cnt2_dg pe_11 eth0_mdc smc0_a24 cnt3_zm pe_12 eth0_txd0 smc0_abe0 cnt3_ud pe_13 eth0_txd1 smc0_abe1 cnt3_dg pe_14 eth0_txen cnt1_outa pe_15 eth0_refclk cnt1_outb table 16. signal muxing table port f port_fer = 0 port_fer = 1 gpio port_mux=b#00 port_mux=b#01 port _mux=b#10 port_mux=b#11 input tap pf_00 eth0_rxd0 cnt0_outa pf_01 eth0_rxd1 cnt0_outb pf_02 usb0_vbc trace_d3 pf_03 smc0_aoe pf_04 smc0_ardy pf_05 smc0_a01 pf_06 smc0_a02 pf_07 smc0_a03 pf_08 smc0_a04 pf_09 smc0_a05 pf_10 eth0_ptpclkin rev. pre | page 34 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data specifications for information about product specifications please contact your adi representative. operating conditions clock related operating conditions table 17 describes the core clock ti ming requirements. the data presented in the tables applies to all speed grades except where expressly noted. figure 8 provides a graphical representation of the various clocks and their available divider values. parameter conditions min nominal max unit v dd_int 1 1 the expected nominal value is 1.2 v ? 5%, and initial customer designs should design with a programmable regulator that can be adjusted from 1.0 v to 1.4 v in 50 mv ste ps. digital internal supply voltage tbd mhz tbd tbd tbd v v dd_ext 2 2 must remain powered (even if the as sociated function is not used). digital external supply voltage 3.13 3.3 3.47 v v dd_ana 2 analog supply voltage 3.13 3.3 3.47 v v ih 3 3 parameter value applies to all input and bidirectio nal signals except twi signals and usb0 signals. high level input voltage v dd_ext = 3.47 v 2.0 v v ihtwi 4 4 parameter applies to twi_sda and twi_scl. high level input voltage v dd_ext = 3.47 v 0.7 v vbustwi v vbustwi v v il 3 low level input voltage v dd_ext = 3.13 v 0.8 v v iltwi 4 low level input voltage v dd_ext = 3.13 v 0.3 v vbustwi v t j junction temperature t ambient = tbdc to +tbdc C40 105 c table 17. clock operating conditions parameter maximum unit f cclk core clock frequency (cclk sysclk, csel syssel) tbd mhz f sysclk sysclk frequency tbd mhz f oclk output clock frequency tbd mhz table 18. phase-locked loop operating conditions parameter minimum maximum unit f pllclk pll clock frequency tbd tbd mhz figure 8. clock relationships and divider values sys_clkin pll dclk (= usbclk) sysclk (= sclk) cclk csel (1 - 31) ssel (1 - 31) dsel (1 - 31) oclk osel (1 - 127) pllclk preliminary technical data rev. pre | page 35 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f electrical characteristics total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 35 shows the current dissipation for internal circuitry (v dd_int ). i dd_deepsleep specifies static power dissi pation as a function of voltage (v dd_int ) and temperature, and i dd_int specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (v dd_int ) and frequency. there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf) which represents application code runn ing on the processor core and l1 memories. the asf is combined with the cclk frequency and v dd_int dependent data in table tbd to calculate this part. the second part is due to transistor switch ing in the system clock (sysclk) domain, which is included in the i dd_int specification equation (tbd). parameter test conditions min typical max unit v oh high level output voltage v dd_ext = 3.13 v, i oh = C0.5 ma 2.4 v v ol low level output voltage v dd_ext = 3.13 v, i ol = 2.0 ma 0.4 v v oltwi 1 1 applies to bidirectional pins twi_scl and twi_sda. low level output voltage v dd_ext = 3.13 v, i ol =2.0ma tbd v i ih 2 2 applies to input pins. high level input current v dd_ext =3.47 v, v in = 3.47 v 10 a i il 2 low level input current v dd_ext =3.47 v, v in = 0 v 10 a i ihp 3 3 applies to jtag input pins (jtg_tck, jtg_tdi, jtg_tms, jtg_trst) . high level input current jtag v dd_ext = 3.47 v, v in = 3.47 v 100 a i ozh 4 4 applies to three-statable pins. three-state leakage current v dd_ext = 3.47 v, v in = 3.47 v 10 a i ozhtwi 1 three-state leakage current v dd_ext =3.47 v, v in = tbd v tbd a i ozl 4 three-state leakage current v dd_ext = 3.47 v, v in = 0 v 10 a c in 5, 6 5 guaranteed, but not tested. 6 applies to all signal pins. input capacitance f in = 1 mhz, t j = 25c, v in =3.3v tbd tbd pf i dd_deepsleep 7 7 see the adsp-cm40x mixed-signal control processo r with arm cortex-m4 hardware reference for definition of deep sleep operating mode. v dd_int current in deep sleep mode v dd_int = tbd v, f cclk = 0 mhz, f sysclk =0mhz, t j = 25c, asf = 0.00 tbd ma i dd_idle v dd_int current in idle v dd_int = tbd v, f cclk = tbd mhz, t j = 25c, asf = tbd tbd ma i dd_typ v dd_int current v dd_int = tbd v, f cclk = tbd mhz, t j = 25c, asf = 1.00 tbd ma i dd_deepsleep v dd_int current in deep sleep mode f cclk = 0 mhz, f sysclk = 0 mhz tbd ma i dd_int v dd_int current f cclk ?? 0 mhz, f sysclk ? 0 mhz tbd ma rev. pre | page 36 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data adc/dac specifications adc specifications typical values assume v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. parameter min typ max unit test conditions/comment analog input adc0_v in, 00C11 , adc1_v in, 00C11 requirement single-ended input voltage range 0 2.5 v characteristic dc leakage current tbd a input resistance tbd ohms figure 5 on page 6 input capacitance tbd pf condition 1= track, figure 5 on page 6 tbd pf condition 2 = hold, figure 5 on page 6 voltage reference (output mode) v ref0 , v ref1 characteristic output voltage 2.5 1.25mv v long-term stability tbd ppm output voltage thermal hysteresis tbd ppm output impedance tbd ohms temperature coefficient tbd ppm/c C40c to +105c voltage reference (input mode) v ref0 , v ref1 requirement input voltage range 0 2.5 v dc leakage current tbd a input capacitance tbd pf static performance dc accuracy adc0_v in, 00C11 , adc1_v in, 00C11 characteristic resolution 16 bits no missing codes, natural binary coding adsp-cm403f/adsp-cm408f differential non-linearity (dnl) C0.90/+1.5 lsb figure 9 on page 39 integral non-linearity (inl) tbd 3.5 tbd lsb figure 12 on page 39 offset error tbd tbd lsb offset error match tbd lsb offset drift tbd lsb gain error tbd lsb gain error match tbd lsb ADSP-CM402F/adsp-cm407f differential non-linearity (dnl) C1.0/+2.0 lsb figure 9 on page 39 integral non-linearity (inl) tbd 12.0 tbd lsb figure 12 on page 39 offset error tbd tbd lsb offset error match tbd lsb offset drift tbd lsb gain error tbd lsb gain error match tbd lsb preliminary technical data rev. pre | page 37 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f dynamic performance throughput adc0_v in, 00C11 , adc1_v in, 00C11 conversion rate 2.63 msps acquisition time 150 ns figure tbd ac accuracy adc0_v in, 00C11 , adc1_v in, 00C11 characteristic adsp-cm403f/adsp-cm408f signal-to-noise ratio (snr) 81.25 db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps signal-to-(noise + distortion) ratio (sinad) 81 db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps total harmonic distortion (thd) C90 db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps spurious-free dynamic range| (sfdr) 90 dbc f in = 1 khz, 0 v to 2.5 v input, 2.63 msps dynamic range 82 tbd db f in = dc effective number of bits (enob) 13.2 bits ADSP-CM402F/adsp-cm407f signal-to-noise ratio (snr) 74 db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps signal-to-(noise + distortion) ratio (sinad) 73 db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps total harmonic distortion (thd) C88 tbd db f in = 1 khz, 0 v to 2.5 v input, 2.63 msps spurious-free dynamic range (sfdr) 88 tbd dbc f in = 1 khz, 0 v to 2.5 v input, 2.63 msps dynamic range 75.5 tbd db f in = dc effective number of bits (enob) tbd 11.8 bits channel-to-channel isolation tbd db any channel pair referenced on same adc adc-to-adc isolation tbd db any channel pair referenced on opposite adc psrr tbd db 100 mv p-p @1 khz applied to v dd_ana parameter min typ max unit test conditions/comment rev. pre | page 38 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data dac specifications typical values assume v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. parameter min typ max unit test condition analog output dac0_vout,dac1_vout characteristic output voltage range tbd 0.1 to 2.5 tbd v output impedance tbd ohms ohms ohms normal operation dac @ full scale dac @ zero scale update rate 50 khz short circuit current to gnd 30 ma short circuit current to v dd 30 ma static performance dc accuracy rl = 500 ohms, cl = 100 pf characteristic resolution 12 bits differential non-linearity (dnl) 0.5 tbd lsb guaranteed monotonic integral non-linearity (inl) 2 tbd lsb offset error tbd tbd mv measured at code tbd, figure 23 on page 41 , figure 27 on page 42 full-scale error tbd tbd % fsr % of full scale, measured at code 0xfff, figure 28 on page 42 , figure 30 on page 42 gain error tbd tbd % fsr % of full scale, figure 28 on page 42 , figure 30 on page 42 dc isolation tbd uv static output of dac0_vout while dac1_vout toggles 0 to full scale dynamic performance ac accuracy rl = 500 ohms, cl = 100 pf characteristic signal-to-noise ratio (snr) 70 db signal-to-(noise + distortion) ratio (sinad) 69 db total harmonic distortion tbd db dynamic range tbd db settling time 10 tbd sec from ? to ? full scale, figure 31 on page 42 slew rate 1.5 v/sec d/a glitch energy tbd nv/sec measured when code changes from 0x7ff to 0x800 dac to dac isolation tbd nv/sec psrr tbd db 100mv p-p @1khz applied to v dd_anax preliminary technical data rev. pre | page 39 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f adc typical performance characteristics v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. figure 9. dnl vs. code figure 10. histogram of dc input at code center (external reference) figure 11. histogram of dc input at code center (internal reference) 4095 code 8192 12288 16384 positive inl = tbd negative inl = tbd 0 dnl (lsb) code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts fi 12. inl s. cd fi 13. histm f dc int t cd tnsitin (extn rfn) fi 14. histm f dc int t cd tnsitin (intn rfn) 4095 code 8192 12288 16384 positive inl = tbd negative inl = tbd 0 inl (lsb) code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts rev. pre | page 40 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data figure 15. fft plot (external reference) figure 16. snr, sinad, and enob vs. external reference voltage figure 17. sinad vs. frequency 0 frequency (khz) 500 750 1000 0 amplitude (db) 250 1250 f s = 2.63 msps f in = 1 khz snr = tbd thd = tbd sinad = tbd 0.0 reference volatge (v) 0.75 1.00 1.50 snr, sinad (db) 0.25 2.50 0.50 1.25 1.75 2.25 2.00 snr sinad enob 12 13 14 15 16 enob (bits) frequency (khz) 80 85 90 95 1 10 100 1000 sinad (db) vdd_ana = tbd v vdd_ana = 3.3 v vdd_ana = tbd v 65 70 75 fi 18. fft pt (intn rfn) fi 19. thd nd sfdr s. extn rfn vt fi 20. thd s. fn 0 frequency (khz) 500 750 1000 0 amplitude (db) 250 1250 f s = 2.63 msps f in = 1 khz snr = tbd thd = tbd sinad = tbd 0.0 reference voltage (v) 0.75 1.00 1.50 thd (db) 0.25 2.50 0.50 1.25 1.75 2.25 2.00 thd sfdr 80 85 90 95 100 sfdr (db) frequency (khz) - 90 thd (db) - 95 - 100 - 105 - 110 - 85 1 10 100 1000 vdd_ana = tbd v vdd_ana = 3.3 v vdd_ana = tbd v preliminary technical data rev. pre | page 41 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f dac typical performance characteristics v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. figure 21. dnl vs. code figure 22. inl error and dnl error vs. temperature figure 23. zero-code error and offset error vs. temperature 0 code 500 1000 1500 0 dnl error (lsb) 2000 2500 3000 3500 4000 temperature (c) 8 6 4 2 0 - 8 - 6 - 4 - 2 error (lsb) vdd = vref = tbd v max inl max dnl min dnl min inl - 50 - 25 0 25 50 75 100 125 - 50 temperature (c) - 25 0 25 1.5 1.0 0.5 0 - 2.0 - 1.5 - 1.0 - 0.5 error (mv) 50 75 100 zero-code error 125 - 2.5 offset error fi 24. inl s. cd fi 25. inl e nd dnl e s. s fi 26. inl e nd dnl e s. s 0 code 500 1000 1500 0 inl error (lsb) 2000 2500 3000 3500 4000 vdd_ana (v) 3.0 3.2 8 6 4 0 - 8 - 6 - 4 error (mv) 3.1 3.3 3.4 3.6 2.9 3.5 2 - 2 max inl max dnl min dnl min inl t j = 25c 2.9 temperature (c) 3.1 3.2 1.5 1.0 0.5 0 - 2.0 - 1.5 - 1.0 - 0.5 error (mv) 3.3 3.4 3.5 zero-code error 3.6 - 2.5 offset error 3.0 rev. pre | page 42 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data figure 27. zero-code error and offset error vs. supply figure 28. gain error and full-scale error vs. temperature figure 29. noise spectral density vdd_ana (v) 3.0 3.2 1.0 0.5 0 - 0.5 - 1.0 - 2.5 - 2.0 - 1.5 error (mv) 3.1 3.3 3.4 3.6 2.9 3.5 zero-code error offset error temperature (c) 0 - 0.02 - 0.04 - 0.06 - 0.14 - 0.12 - 0.10 - 0.08 error (% fsr) gain error - 0.16 full-scale error - 0.18 - 0.20 - 50 - 25 0 25 50 75 100 125 frequency (hz) 500 600 700 800 10 100 1k 10k 2 8 7 3 8 7 1 2 , 6 ( q 9 + ] 200 300 400 100k 1m 100 0 fi 30. gin e nd f-s e s. s fi 31. sttin tim s. citi ld vdd (v) 3.0 3.2 1.0 0.5 0 - 1.0 - 2.0 error (% fsr) 3.1 3.3 3.4 3.6 2.9 3.5 - 0.5 - 1.5 gain error full-scale error capacitance (nf) 13 16 14 time (s) 245 10 06 vdd_ana = tbd v 12 10 8 6 4 789 vdd_ana = tbd v preliminary technical data rev. pre | page 43 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f flash specifications the flash features include: ? 100,000 erase cycles per sector ? 20 years data retention flash program/erase suspend command table 19 lists parameters for th e flash suspend command. flash ac characteristics and operating conditions table 20 identifies flash specific operating conditions. table 19. suspend parameters 1,2,3 parameter condition typ max units notes erase to suspend sector erase or erase resume to erase suspend 700 C s 1 program to suspend program re sume to program suspend 5 C s 1 subsector erase to suspend subsector erase or subsector erase resume to erase suspend 50 C s 1 suspend latency program 7 C s 2 suspend latency subsector erase 15 C s 2 suspend latency erase 15 C s 3 1 timing is not internally controlled. 2 any read command accepted. 3 any command except the following are accepted: sector, subsector, or bulk erase; write status register. table 20. ac characteristics and operating conditions parameter symbol min typ 1 max unit clock frequency for all commands other than read (spi-er, qio-spi protocol) f c dc C 100 mhz clock frequency for read commands f r dc C 54 mhz page program cycle time (256 bytes) 2 t pp C0.5 5 ms page program cycle time (n bytes) 2,3 t pp Cint(n/8) 0.0155 ms subsector erase cycle time t sse C0.3 1.5s sector erase cycle time t se C0.7 3 s bulk erase cycle time t be C170 250s 1 typical values given for t j = 25c. 2 when using the page program command to program consecutive bytes, optimized timing s are obtained with one sequence including al l the bytes versus several sequences of only a few bytes (1 < n < 256). 3 int(a) corresponds to the upper integer part of a. for example int(12/8) = 2, int(32/8) = 4 int(15.3) =16. rev. pre | page 44 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data absolute maximum ratings stresses greater than those listed in the table may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 32 and table 22 provides details about package branding. for a complete listing of prod- uct availability, see pre-release products on page 82 . parameter rating internal supply voltage (v dd_int ) C0.33 v to +1.32 v external (i/o) supply voltage (v dd_ext ) C0.33 v to +3.63 v analog supply voltage (v dd_ana ) C0.33 v to +3.63 v digital input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 21 . 2 applies only when v dd_ext is within specifications. when v dd_ext is outside speci- fications, the range is v dd_ext 0.2 volts. C0.33 v to +3.63 v twi digital input voltage 1, 2, 3 3 applies to pins twi_scl and twi_sda. C0.33 v to +5.50 v digital output voltage swing C0.33 v to v dd_ext + 0.5 v analog input voltage C0.3 v to v ref0 /v ref1 + 0.3 v usb0_dx input C0.33 v to +5.25 v usb0_vbus input voltage C0.33 v to +6.00 v storage temperature range C65c to +150c junction temperature under bias +125 c table 21. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with th e exception of sys_clkin, sys_xtal. v in min (v) v in max (v) maximum duty cycle tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd figure 32. product information on package table 22. package brand information brand key field description adsp-cm40x product name 1 1 see available products in pre-release products on page 82 . t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. d a t a t b d preliminary technical data rev. pre | page 45 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f timing specifications specifications are subject to change without notice. clock and reset timing table 23 and figure 33 describe clock and reset operations. per the cclk, sysclk, sclk, dclk, and oclk timing specifica- tions in table 17 on page 34 , combinations of sys_clkin and clock multipliers mu st not select clock rates in excess of the processors maximum instruction rate. table 23. clock and reset timing parameter min max unit timing requirements f ckin sys_clkin frequency (using a crystal) 1, 2, 3 20 50 mhz f ckin sys_clkin frequency (using a crystal oscillator) 1, 2, 3 20 60 mhz t ckinl sys_clkin low pulse 1 tbd ns t ckinh sys_clkin high pulse 1 tbd ns t wrst sys_hwrst asserted pulse width low 4 11 t ckin ns 1 applies to pll bypass mode and pll non bypass mode. 2 the t ckin period (see figure 33 ) equals 1/f ckin . 3 if the cgu_ctl.df bit is set, the minimum f ckin specification is 40 mhz. 4 applies after power-up se quence is complete. see table 24 and figure 34 for power-up reset timing. figure 33. clock and reset timing sys_clkin t wrst t ckin t ckinl t ckinh sys_hwrst rev. pre | page 46 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data power-up reset timing in figure 34 , v dd_supplies are v dd_int , v dd_ext , v dd_vreg ,v dd_ana0 , and v dd_ana1 . table 24. power-up reset timing parameter min max unit timing requirement t rst_in_pwr sys_hwrst deasserted after v dd_int , v dd_ext , v dd_vreg , v dd_ana0 , v dd_ana1 , and sys_clkin are stable and within specification 11 t ckin ns figure 34. power -up reset timing reset t rst_in_pwr clkin v dd_supplies preliminary technical data rev. pre | page 47 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f asynchronous read table 25. asynchronous memory read (bxmode = b#00) parameter min max unit timing requirements t sdatare data in setup before smc0_are high tbd ns t hdatare data in hold after smc0_are high tbd ns t dardyare smc0_ardy valid after smc0_are low 1, 2 (rat C 2.5) t sclk C tbd ns switching characteristics t addrare smc0_ax/smc0_amsx assertion before smc0_are low 3 (prest + rst + preat) t sclk C tbd ns t aoeare smc0_aoe assertion before smc0_are low (rst + preat) t sclk C tbd ns t hare output 4 hold after smc0_are high 5 rht t sclk Ctbd ns t ware smc0_are active low width 6 rat t sclk C tbd ns t dareardy smc0_are high delay after smc0_ardy assertion 1 2.5 t sclk 3.5 t sclk + tbd ns 1 smc0_bxctl.ardyen bit = 1. 2 rat value set using the smc_bxtim.rat bits. 3 prest, rst, and preat values set using the smc_bxetim.pre st bits, smc_bxtim.rst bits, and the smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams , smc0_aoe , smc0_abex . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. figure 35. asynchronous read smc0_are smc0_amsx smc0_ax t ware smc0_aoe smc0_dx (data) smc0_ardy t aoeare t addrare t dardyare t hare t hdatare t dareardy t sdatare rev. pre | page 48 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data asynchronous flash read table 26. asynchronous flash read parameter min max unit switching characteristics t amsadv smc0_ax (address)/smc0_amsx assertion before smc0_aoe low 1 prest t sclk C tbd ns t wadv smc0_aoe active low width 2 rst t sclk C tbd ns t dadvare smc0_are low delay from smc0_aoe high 3 preat t sclk C tbd ns t hare output 4 hold after smc0_are high 5 rht t sclk C tbd ns t ware 6 smc0_are active low width 7 rat t sclk C tbd ns 1 prest value set using the smc_bxetim.prest bits. 2 rst value set using the smc_bxtim.rst bits. 3 preat value set using th e smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams , smc0_aoe . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. 7 rat value set using the smc_bxtim.rat bits. figure 36. asynchronous flash read smc0_ax (address) t amsadv t dadvare t wadv t ware t hare read latched data smc0_amsx (nor_ce) smc0_aoe (nor_adv) smc0_are (nor_oe) smc0_dx (data) preliminary technical data rev. pre | page 49 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f asynchronous page mode read table 27. asynchronous page mode read parameter min max unit switching characteristics t av smc0_ax (address) valid for first address min width 1 (prest + rst + preat + rat) t sclk C tbd ns t av1 smc0_ax (address) valid for subsequent smc0_ax (address) min width pgws t sclk C tbd ns t wadv smc0_aoe active low width 2 rst t sclk C tbd ns t hare output 3 hold after smc0_are high 4 rht t sclk C tbd ns t ware 5 smc0_are active low width 6 rat t sclk C tbd ns 1 prest, rst, preat and rat values set using the smc_bxetim.prest bits, smc_bxtim.rst bits, smc_bx etim.preat bits, and the smc_bx tim.rat bits. 2 rst value set using th e smc_bxtim.rst bits. 3 output signals are smc0_ax, smc0_amsx , smc0_aoe . 4 rht value set using the smc_bxtim.rht bits. 5 smc_bxctl.ardyen bit = 0. 6 rat value set using the smc_bxtim.rat bits. figure 37. asynchronous page mode read smc0_amsx (nor_ce) smc0_are (nor_oe) smc0_aoe (nor_adv) smc0_dx (data) a0 t wadv t ware t hare d0 d1 d2 d3 a0 + 1 a0 + 2 a0 + 3 t av t av1 t av1 t av1 read latched data read latched data read latched data read latched data smc0_ax (address) rev. pre | page 50 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data asynchronous write table 28. asynchronous memory write (bxmode = b#00) parameter min max unit timing requirement t dardyawe 1 smc0_ardy valid after smc0_awe low 2 (wat C 2.5) t sclk C tbd ns switching characteristics t endat data enable after smc0_amsx assertion tbd ns t ddat data disable after smc0_amsx deassertion tbd ns t amsawe smc0_ax/smc0_amsx assertion before smc0_awe low 3 (prest + wst + preat) t sclk C tbd ns t hawe output 4 hold after smc0_awe high 5 wht t sclk C tbd ns t wawe 6 smc0_awe active low width 2 wat t sclk C tbd ns t daweardy 1 smc0_awe high delay after smc0_ardy assertion 2.5 t sclk 3.5 t sclk + tbd ns 1 smc_bxctl.ardyen bit = 1. 2 wat value set using the smc_bxtim.wat bits. 3 prest, wst, preat values set using the smc_bxetim.prest bits, smc_bxtim.wst bits, smc_bxetim.pre at bits, and the smc_bxtim.rat bits. 4 output signals are data, smc0_ax, smc0_amsx , smc0_abex . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. figure 38. asynchronous write smc0_awe smc0_abex smc0_ax t dardyawe t amsawe t daweardy t endat t ddat t hawe t wawe smc0_amsx smc0_dx (data) smc0_ardy preliminary technical data rev. pre | page 51 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f asynchronous flash write all accesses table 29. asynchronous flash write parameter min max unit switching characteristics t amsadv smc0_ax/smc0_amsx assertion before smc0_aoe low 1 prest t sclk C tbd ns t dadvawe smc0_awe low delay from smc0_aoe high 2 preat t sclk C tbd ns t wadv smc0_aoe active low width 3 wst t sclk C tbd ns t hawe output 4 hold after smc0_awe high 5 wht t sclk C tbd ns t wawe 6 smc0_awe active low width 7 wat t sclk C tbd ns 1 prest value set using the smc_bxetim.prest bits. 2 preat value set using th e smc_bxetim.preat bits. 3 wst value set using the smc_bxtim.wst bits. 4 output signals are data, smc0_ax, smc0_amsx , smc0_abex . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. 7 wat value set using the smc_bxtim.wat bits. figure 39. asynchronous flash write smc0_amsx (nor_ce ) smc0_awe (nor_we) smc0_ax (address) smc0_aoe (nor_adv) t amsadv t dadvawe smc0_dx (data) t wadv t wawe t hawe table 30. all accesses parameter min max unit switching characteristic t turn smc0_amsx inactive width (it + tt) t sclk C tbd ns rev. pre | page 52 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (spt_clk) width. in figure 40 either the rising edge or the fall- ing edge of spt_clk (external or internal) can be used as the active sampling edge. table 31. serial portsexternal clock parameter min max unit timing requirements t sfse frame sync setup before spt_clk (externally generated frame sync in either transmit or receive mode) 1 tbd ns t hfse frame sync hold after spt_clk (externally generated frame sync in either transmit or receive mode) 1 tbd ns t sdre receive data setup before receive spt_clk 1 tbd ns t hdre receive data hold after spt_clk 1 tbd ns t sclkw spt_clk width for external spt_clk data/fs receive 2 [0.5 t sclk C tbd] or [tbd] ns spt_clk width for external spt_clk data/fs transmit 2 [0.5 t sclk C tbd] or [8tbd] ns t sptclk spt_clk period for external spt_clk data/fs receive 2 [t sclk C tbd] or [tbd] ns spt_clk period for external spt_clk data/fs transmit 2 [t sclk C tbd] or [tbd] ns switching characteristics t dfse frame sync delay after spt_clk (internally generated frame sync in either transmit or receive mode) 3 tbd ns t hofse frame sync hold after spt_clk (internally generated frame sync in either transmit or receive mode) 3 tbd ns t ddte transmit data delay after transmit spt_clk 3 tbd ns t hdte transmit data hold after transmit spt_clk 3 tbd ns 1 referenced to sample edge. 2 whichever is greater. 3 referenced to drive edge. preliminary technical data rev. pre | page 53 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 32. serial portsinternal clock parameter min max unit timing requirements t sfsi frame sync setup before spt_clk (externally generated frame sync in either transmit or receive mode) 1 tbd ns t hfsi frame sync hold after spt_clk (externally generated frame sync in either transmit or receive mode) 1 tbd ns t sdri receive data setup before spt_clk 1 tbd ns t hdri receive data hold after spt_clk 1 tbd ns switching characteristics t dfsi frame sync delay after spt_clk (internally generated frame sync in transmit or receive mode) 2 tbd ns t hofsi frame sync hold after spt_clk (internally generated frame sync in transmit or receive mode) 2 tbd ns t ddti transmit data delay after spt_clk 2 tbd ns t hdti transmit data hold after spt_clk 2 tbd ns t sclkiw spt_clk width for internal spt_clk data/fs transmit 3 [0.5 t sclk C tbd] or [tbd] ns spt_clk width for internal sp t_clk data/fs receive [0.5 t sclk C tbd] or [tbd] ns t sptclk spt_clk period for internal spt_clk data/fs transmit 3 [t sclk C tbd] or [tbd] ns t sptclk spt_clk period for internal spt_clk data/fs receive 3 [t sclk C tbd] or [tbd] ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 whichever is greater. rev. pre | page 54 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data figure 40. serial ports drive edge sample edge spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) t hofsi t hfsi t hdri data receiveinternal clock drive edge sample edge t hfsi t ddti data transmitinternal clock drive edge sample edge t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsi t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) preliminary technical data rev. pre | page 55 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 33. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit spt_clk 1 tbd ns t ddtte data disable from external transmit spt_clk 1 tbd ns t ddtin data enable from internal transmit spt_clk 1 tbd ns t ddtti data disable from internal transmit spt_clk 1 tbd ns 1 referenced to drive edge. figure 41. serial portsenable and three-state drive edge drive edge t ddtin t ddten t ddtte spt_clk (sport clock internal) spt_a/bdx (data channel a/b) spt_clk (sport clock external) spt_a/bdx (data channel a/b) drive edge drive edge t ddtti rev. pre | page 56 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data the spt_tdv output signal becomes active in sport multi- channel mode. during transmit slots (enabled with active channel selection registers) th e spt_tdv is asserted for com- munication with external devices. table 34. serial portstd v (transmit data valid) parameter min max unit switching characteristics t drdven data-valid enable delay from drive edge of external clock 1 tbd ns t dfdven data-valid disable delay from drive edge of external clock 1 tbd ns t drdvin data-valid enable delay from drive edge of internal clock 1 tbd ns t dfdvin data-valid disable delay from drive edge of internal clock 1 tbd ns 1 referenced to drive edge. figure 42. serial portstransmit data valid internal and external clock drive edge drive edge spt_clk (sport clock external) t drdven t dfdven drive edge drive edge spt_clk (sport clock internal) t drdvin t dfdvin spt_a/btdv spt_a/btdv preliminary technical data rev. pre | page 57 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 35. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transmit frame sync or external receive frame sync with mce = 1, mfd = 0 1 tbd ns t ddtenfs data enable for mce = 1, mfd = 0 1 tbd ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justi fied as well as standard seri al mode, and mce = 1, mfd = 0. figure 43. external late frame sync drive sample 2nd bit 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) rev. pre | page 58 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data serial peripheral interface (spi) portmaster timing table 36 and figure 44 describe spi port master operations. note that: ? in dual mode data transmit the spi_miso signal is also an output. ? in quad mode data transmit the spi_miso, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_mosi signal is also an input. ? in quad mode data receive the spi_mosi, spi_d2, and spi_d3 signals are also inputs. table 36. serial peripheral interface (spi) portmaster timing parameter min max unit timing requirements t sspidm data input valid to spi_clk edge (data input setup) tbd ns t hspidm spi_clk sampling edge to data input invalid tbd ns switching characteristics t sdscim spi_sel low to first spi_clk edge 1 [0.5 t sclk C tbd] or [tbd] ns t spichm spi_clk high period for data transmit 1 [0.5 t sclk C tbd] or [tbd] ns spi_clk high period for data receive 1 [0.5 t sclk C tbd] or [tbd] ns t spiclm spi_clk low period for data transmit 1 [0.5 t sclk C tbd] or [tbd] ns spi_clk low period for data receive 1 [0.5 t sclk C tbd] or [tbd] ns t spiclk spi_clk period for data transmit 1 [t sclk C tbd] or [tbd] ns spi_clk period for data receive 1 [t sclk C tbd] or [tbd] ns t hdsm last spi_clk edge to spi_sel high 2 t sclk Ctbd ns t spitdm sequential transfer delay 1, 2 [t sclk C tbd] or [tbd] ns t ddspidm spi_clk edge to data out valid (data out delay) tbd ns t hdspidm spi_clk edge to data out invalid (data out hold) tbd ns 1 whichever is greater. 2 applies to sequential mode with stop 1. preliminary technical data rev. pre | page 59 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f figure 44. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spi_sel (output) spi_clk (output) data outputs (spi_mosi) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm data inputs (spi_miso) data outputs (spi_mosi) data inputs (spi_miso) rev. pre | page 60 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data serial peripheral interface (spi) portslave timing table 37 and figure 45 describe spi port slave operations. note that: ? in dual mode data transmit the spi_mosi signal is also an output. ? in quad mode data transmit the spi_mosi, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_miso signal is also an input. ? in quad mode data receive the spi_miso, spi_d2, and spi_d3 signals are also inputs. table 37. serial peripheral interface (spi) portslave timing parameter min max unit timing requirements t spichs spi_clk high period for data transmit 1 [0.5 t sclk C tbd] or [tbd] ns spi_clk high period for data receive 1 [0.5 t sclk C tbd] or [tbd] ns t spicls spi_clk low period for data transmit 1 [0.5 t sclk C tbd] or [tbd] ns spi_clk low period for data receive 1 [0.5 t sclk C tbd] or [tbd] ns t spiclk spi_clk period for data transmit 1 [t sclk C tbd] or [tbd] ns spi_clk period for data receive 1 [t sclk C tbd] or [tbd] ns t hds last spi_clk edge to spi_ss not asserted tbd ns t spitds sequential transfer delay 0.5 t spiclk C tbd ns t sdsci spi_ss assertion to first spi_clk edge tbd ns t sspid data input valid to spi_clk edge (data input setup) tbd ns t hspid spi_clk sampling edge to data input invalid tbd ns switching characteristics t dsoe spi_ss assertion to data out active tbd tbd ns t dsdhi spi_ss deassertion to data high impedance tbd tbd ns t ddspid spi_clk edge to data out valid (data out delay) tbd ns t hdspid spi_clk edge to data out invalid (data out hold) tbd ns 1 whichever is greater. preliminary technical data rev. pre | page 61 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f figure 45. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spi_ss (input) spi_clk (input) t hspid data outputs (spi_miso) cpha = 1 cpha = 0 data inputs (spi_mosi) data outputs (spi_miso) data inputs (spi_mosi) rev. pre | page 62 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data serial peripheral interface (spi) portspi_rdy slave timing table 38. spi portspi_rdy slave timing parameter min max unit switching characteristics t dspisckrdysr spi_rdy de-assertion from valid input spi_ clk edge in slave mode receive 2.5 t sclk 3.5 t sclk + tbd ns t dspisckrdyst spi_rdy de-assertion from valid input spi_clk edge in slave mode transmit 3.5 t sclk 4.5 t sclk + tbd ns figure 46. spi_rdy de-assertion from valid input spi_clk edge in slave mode receive (fcch = 0) figure 47. spi_rdy de-assertion fr om valid input spi_clk edge in slave mode tran smit (fcch = 1) spi_clk (cpol = 0) spi_clk (cpol = 1) t dspisckrdysr spi_rdy (o) spi_clk (cpol = 0) spi_clk (cpol = 1) cpha = 1 cpha = 0 spi_clk (cpol = 1) spi_clk (cpol = 0) t dspisckrdyst spi_rdy (o) spi_clk (cpol = 1) spi_clk (cpol = 0) cpha = 1 cpha = 0 preliminary technical data rev. pre | page 63 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f serial peripheral interface (spi) portopen drain mode timing in figure 48 and figure 49 , the outputs can be spi_mosi spi_miso, spi_d2, and/or spi_d3 depending on the mode of operation. table 39. spi port odm master mode timing parameter min max unit switching characteristics t hdspiodmm spi_clk edge to high impeda nce from data out valid tbd ns t ddspiodmm spi_clk edge to data out vali d from high impedance tbd tbd ns figure 48. odm master table 40. spi portodm slave mode parameter min max unit timing requirements t hdspiodms spi_clk edge to high impeda nce from data out valid tbd ns t ddspiodms spi_clk edge to data out va lid from high impedance tbd ns figure 49. odm slave spi_clk (cpol = 0) t hdspiodmm spi_clk (cpol = 1) t ddspiodmm t ddspiodmm t hdspiodmm output (cpha = 1) output (cpha = 0) t hdspiodms t ddspiodms t ddspiodms t hdspiodms spi_clk (cpol = 0) spi_clk (cpol = 1) output (cpha = 1) output (cpha = 0) rev. pre | page 64 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data serial peripheral interface (spi) portspi_rdy timing table 41. spi portspi_rdy timing parameter min max unit timing requirements t srdysckm0 minimum setup time for spi_rdy de-assertion in master mode before last spi_clk edge of valid data transfer to block subsequent transfer with cpha = 0 (2.5 + 1.5 baud 1 ) t sclk + tbd ns t srdysckm1 minimum setup time for spi_rdy de-assertion in master mode before last spi_clk edge of valid data transfer to block subsequent transfer with cpha = 1 (1.5 baud 1 ) t sclk + tbd ns switching characteristic t srdysckm time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transfer with cpha = 0 and baud = 0 (stop, lead, lag = 0) 3 t sclk 4 t sclk + tbd ns time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transfer with cpha = 0 and baud 1 (stop, lead, lag = 0) (4 + 1.5 baud 1 ) t sclk (5 + 1.5 baud 1 ) t sclk + tbd ns time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transfer with cpha = 1 (stop, lead, lag = 0) (3 + 0.5 baud 1 ) t sclk (4 + 0.5 baud 1 ) t sclk + tbd ns 1 baud value set using the spi_clk.baud bits. figure 50. spi_rdy setup befo re spi_clk with cpha = 0 figure 51. spi_rdy setup befo re spi_clk with cpha = 1 spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm0 spi_rdy spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm1 spi_rdy preliminary technical data rev. pre | page 65 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f figure 52. spi_clk switching diagram after spi_rdy assertion, cpha = x spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm spi_rdy rev. pre | page 66 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data general-purpose port timing table 42 and figure 53 describe general-purpose port operations. timer cycle timing table 43 and figure 54 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /4) mhz. the width value value is the timer period assigned in the tmx_ tmrn_width register and can range from 1 to 2 32 C 1. table 42. general-purpose port timing parameter min max unit timing requirement t wfi general-purpose port pin input pulse width 2 t sclk ns figure 53. general-purpose port timing gpio input t wfi table 43. timer cycle timing parameter min max unit timing requirements t wl timer pulse width input low (measured in sclk cycles) 1 2 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 2 t sclk ns switching characteristics t hto timer pulse width output (measured in sclk cycles) t sclk width value C tbd t sclk width value + tbd ns 1 the minimum pulse widths apply for tmx signal s in width capture and external clock modes. figure 54. timer cycle timing tmr output tmr input t wh , t wl t hto preliminary technical data rev. pre | page 67 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f up/down counter/rotary encoder timing pulse width modulator (pwm) timing table 45 and figure 56 describe pwm operations. table 44. up/down counter/rotary encoder timing parameter min max unit timing requirement t wcount up/down counter/rotary encoder input pulse width 2 t sclk ns figure 55. up/down counter/rotary encoder timing cnt_ud cnt_dg cnt_zm t wcount table 45. pwm timing parameter min max unit timing requirement t es external sync pulse width 2 t sclk ns switching characteristics t dodis output inactive (off) after trip input 1 tbd ns t doe output delay after external sync 1, 2 2 t sclk + tbd 5 t sclk + tbd ns 1 pwm outputs are: pwmx_ah, pwmx_al, pwmx_bh, pwmx_bl, pwmx_ch, and pwmx_cl. 2 when the external sync signal is synchronou s to the peripheral clock, it takes fewer clock cycles for the output to appear comp ared to when the external sync signal is asynchronous to the peripheral cloc k. for more information, see the adsp-cm40x microcontrolle r hardware reference . figure 56. pwm timing pwm_trip pwm_sync (as input) t es t doe output t dodis rev. pre | page 68 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-cm40x mixed-signal control processor with arm cortex-m4 hardware reference . can interface the can interface timing is described in the adsp-cm40x mixed-signal control processor with arm cortex-m4 hardware reference . universal serial bus (usb) on-the-goreceive and transmit timing the usb interface timing is described in the adsp-cm40x mixed-signal control processor with arm cortex-m4 hardware reference . preliminary technical data rev. pre | page 69 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f 10/100 ethernet mac controller timing table 46 through table 48 and figure 57 through figure 59 describe the 10/100 ethernet mac cont roller operations. table 46. 10/100 ethernet mac controll er timing: rmii receive signal parameter 1 min max unit timing requirements t refclkf ethx_refclk frequency (f sclk = sclk frequency) none 50 + 1% mhz t refclkw ethx_refclk width (t refclk = ethx_refclk period) t refclk 35% t refclk 65% ns t refclkis rx input valid to rmii ethx_refcl k rising edge (data in setup) tbd ns t refclkih rmii ethx_refclk rising edge to rx input invalid (data in hold) tbd ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. figure 57. 10/100 ethernet mac controller timing: rmii receive signal table 47. 10/100 ethernet mac controller timing: rmii transmit signal parameter 1 min max unit switching characteristics t refclkov rmii ethx_refclk rising edge to transm it output valid (data out valid) tbd ns t refclkoh rmii ethx_refclk rising edge to transmit output invalid (data out hold) tbd ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. figure 58. 10/100 ethernet mac controller timing: rmii transmit signal t refclkis t refclkih ethx_rxd1C0 ethx_crs ethx_rxerr rmii_ref_clk t refclkw t refclk t refclkov t refclkoh rmii_ref_clk ethx_txd1C0 ethx_txen t refclk rev. pre | page 70 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data table 48. 10/100 ethernet mac controller timing: rmii station management parameter 1 min max unit timing requirements t mdios ethx_mdio input valid to ethx_mdc rising edge (setup) tbd ns t mdcih ethx_mdc rising edge to ethx _mdio input invalid (hold) tbd ns switching characteristics t mdcov ethx_mdc falling edge to ethx_mdio output valid t sclk + tbd ns t mdcoh ethx_mdc falling edge to ethx _mdio output invalid (hold) t sclk Ctbd ns 1 ethx_mdc/ethx_mdio is a 2-wire se rial bidirectional port for cont rolling one or more external phys . ethx_mdc is an output clock whose minimum period is programmable as a multiple of the system cloc k sclk. ethx_mdio is a bi directional data line. figure 59. 10/100 ethernet mac contro ller timing: rmii station management ethx_mdio (input) ethx_mdio (output) ethx_mdc (output) t mdios t mdcoh t mdcih t mdcov preliminary technical data rev. pre | page 71 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f jtag test and emulation port timing table 49 and figure 60 describe jtag port operations. table 49. jtag port timing parameter min max unit timing requirements t tck jtg_tck period 20 ns t stap jtg_tdi, jtg_tms setup before jtg_tck high tbd ns t htap jtg_tdi, jtg_tms hold after jtg_tck high tbd ns t ssys system inputs setup before jtg_tck high 1 tbd ns t hsys system inputs hold after jtg_tck high 1 tbd ns t trstw jtg_trst pulse width (measured in jtg_tck cycles) 2 tbd tck switching characteristics t dtdo jtg_tdo delay from jtg_tck low tbd ns t dsys system outputs delay after jtg_tck low 3 tbd ns 1 system inputs = pa_15C0, pb_15C0, pc_15C0, pd_15C0, pe_15C0, pf_10C0, sys_bmode0C1, sys_hwrst , sys_fault , sys_nmi , twi0_scl, twi0_sda. 2 50 mhz maximum. 3 system outputs = pa_15C0, pb_15C0, pc_15C0, pd_15C0, pe_15C0, pf_10C0, smc0_ams0 , smc0_are , smc0_awe , sys_clkout, sys_fault , sys_resout . figure 60. jtag port timing jtg_tck jtg_tms jtg_tdi jtg_tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys rev. pre | page 72 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data output drive currents figure 61 and figure 62 show typical current-voltage character- istics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all pins (see figure 63 ). v load is equal to (v dd_ext )/2. the graph of figure 64 shows how output rise and fall times vary with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 61. driver type a current figure 62. driver type b current 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 200 120 80 C 200 C 120 C 40 4.0 v ddext = tbdv @ C 40 c v ddext = 3.3v @ 25 c C 80 C 160 40 160 v ddext = tbdv @ 105 c tbd 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 160 120 80 C 160 C 40 4.0 v ddext = tbdv @ C 40 c v ddext = 3.3v @ 25 c C 80 C 120 40 v ddext = tbdv @ 105 c tbd figre 63. eiaent deice loading or ac measrements (incdes a fixtres) figre 64. drier tpe a tpica rise and fa times (10-90) s. load capacitance t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output load capacitance (pf) 12 0 14 8 4 2 6 rise and fall times (ns) 10 0 250 200 50 100 150 16 t fall = 3.3v @ 25 c t rise = 3.3v @ 25 c tbd preliminary technical data rev. pre | page 73 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) measured by customer at top center of package. ? jt = from table 50 and table 51 p d = power dissipation (see total power dissipation on page 35 for the method to calculate p d ) values of ? ja are provided for packag e comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of ? jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. in table 50 and table 51 , airflow measurements comply with jedec standards jesd51-2 and jesd51-6. the junction-to- case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. table 50. thermal characteristics (120-lead lqfp) parameter condition typical unit ? ja 0 linear m/s air flow 21.5 c/w ? ja 1 linear m/s air flow 19.2 c/w ? ja 2 linear m/s air flow 18.4 c/w ? jc 9.29 c/w ? jt 0 linear m/s air flow 0.25 c/w ? jt 1 linear m/s air flow 0.40 c/w ? jt 2 linear m/s air flow 0.56 c/w table 51. thermal characteristics (176-lead lqfp) parameter condition typical unit ? ja 0 linear m/s air flow 21.5 c/w ? ja 1 linear m/s air flow 19.3 c/w ? ja 2 linear m/s air flow 18.5 c/w ? jc 9.24 c/w ? jt 0 linear m/s air flow 0.25 c/w ? jt 1 linear m/s air flow 0.37 c/w ? jt 2 linear m/s air flow 0.48 c/w t j t case ? jt p d ? ?? + = t j t a ? ja p d ? ?? + = rev. pre | page 74 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data 120-lead lqfp lead assignments table 52 lists the 120-lead lqfp package by lead number and table 53 lists the 120-lead lqfp package by signal. table 52. 120-lead lqfp lead assignment (numerical by lead number) lead no. signal name lead no. signal name lead no. signal name lead no. signal name 1 pa_13 32 jtg_trst 63 adc1_vin05 94 dac0_vout 2 vdd_ext 33 jtg_tdo/swo 64 adc1_vin06 95 vdd_ext 3 pa_12 34 jtg_tms/swdio 65 adc1_vin07 96 vdd_int 4 pa_11 35 pc_07 66 adc1_vin08 97 vdd_ext 5 pa_10 36 vdd_ext 67 adc1_vin09 98 gnd 6 pa_09 37 pc_06 68 adc1_vin10 99 sys_nmi 7 pa_08 38 pc_05 69 adc1_vin11 100 vdd_ext 8 pa_07 39 pc_04 70 vdd_ana1 101 vdd_ext 9 vdd_ext 40 pc_03 71 gnd_ana1 102 pb_10 10 pa_06 41 pc_02 72 byp_a1 103 pb_08 11 pa_05 42 pc_01 73 vref1 104 pb_09 12 pa_04 43 vdd_ext 74 gnd_vref1 105 pb_06 13 pa_03 44 vdd_int 75 refcap 106 pb_07 14 pa_02 45 pc_00 76 gnd_vref0 107 pb_05 15 pa_01 46 pb_14 77 vref0 108 vdd_int 16 vdd_int 47 pb_15 78 byp_a0 109 vdd_ext 17 vdd_ext 48 pb_13 79 gnd_ana0 110 pb_04 18 sys_resout 49 vdd_ext 80 vdd_ana0 111 pb_03 19 pa_00 50 pb_11 81 adc0_vin11 112 pb_02 20 sys_fault 51 pb_12 82 adc0_vin10 113 pb_01 21 sys_hwrst 52 gnd 83 adc0_vin09 114 pb_00 22 vdd_ext 53 vdd_ext 84 adc0_vin08 115 pa_15 23 sys_xtal 54 vdd_int 85 adc0_vin07 116 vdd_ext 24 sys_clkin 55 byp_d0 86 adc0_vin06 117 pa_14 25 vreg_base 56 dac1_vout 87 adc0_vin05 118 sys_clkout 26 vdd_vreg 57 adc1_vin00 88 adc0_vin04 119 sys_bmode1 27 vdd_ext 58 adc1_vin01 89 adc0_vin03 120 sys_bmode0 28 twi0_scl 59 adc1_vin02 90 gnd_ana2 121* gnd 29 twi0_sda 60 adc1_vin03 91 adc0_vin02 30 jtg_tdi 61 gnd_ana3 92 adc0_vin01 31 jtg_tck/swclk 62 adc1_vin04 93 adc0_vin00 * pin no. 121 is the gnd supply (see figure 66 ) for the processor; this pad must connect to gnd. preliminary technical data rev. pre | page 75 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 53. 120-lead lqfp lead assignme nt (alphabetical by signal name) signal name lead no. signal name lead no. signal name lead no. signal name lead no. adc0_vin00 93 gnd 121* pb_03 111 twi0_scl 28 adc0_vin01 92 gnd_ana0 79 pb_04 110 twi0_sda 29 adc0_vin02 91 gnd_ana1 71 pb_05 107 vdd_ana0 80 adc0_vin03 89 gnd_ana2 90 pb_06 105 vdd_ana1 70 adc0_vin04 88 gnd_ana3 61 pb_07 106 vdd_ext 2 adc0_vin05 87 gnd_vref0 76 pb_08 103 vdd_ext 9 adc0_vin06 86 gnd_vref1 74 pb_09 104 vdd_ext 17 adc0_vin07 85 jtg_tck/swclk 31 pb_10 102 vdd_ext 22 adc0_vin08 84 jtg_tdi 30 pb_11 50 vdd_ext 27 adc0_vin09 83 jtg_tdo/swo 33 pb_12 51 vdd_ext 36 adc0_vin10 82 jtg_tms/swdio 34 pb_13 48 vdd_ext 43 adc0_vin11 81 jtg_trst 32 pb_14 46 vdd_ext 49 adc1_vin00 57 pa_00 19 pb_15 47 vdd_ext 53 adc1_vin01 58 pa_01 15 pc_00 45 vdd_ext 95 adc1_vin02 59 pa_02 14 pc_01 42 vdd_ext 97 adc1_vin03 60 pa_03 13 pc_02 41 vdd_ext 100 adc1_vin04 62 pa_04 12 pc_03 40 vdd_ext 101 adc1_vin05 63 pa_05 11 pc_04 39 vdd_ext 109 adc1_vin06 64 pa_06 10 pc_05 38 vdd_ext 116 adc1_vin07 65 pa_07 8 pc_06 37 vdd_int 16 adc1_vin08 66 pa_08 7 pc_07 35 vdd_int 44 adc1_vin09 67 pa_09 6 refcap 75 vdd_int 54 adc1_vin10 68 pa_10 5 sys_bmode0 120 vdd_int 96 adc1_vin11 69 pa_11 4 sys_bmode1 119 vdd_int 108 byp_a0 78 pa_12 3 sys_clkin 24 vdd_vreg 26 byp_a1 72 pa_13 1 sys_clkout 118 vref0 77 byp_d0 55 pa_14 117 sys_fault 20 vref1 73 dac0_vout 94 pa_15 115 sys_hwrst 21 vreg_base 25 dac1_vout 56 pb_00 114 sys_nmi 99 gnd 98 pb_01 113 sys_resout 18 gnd 52 pb_02 112 sys_xtal 23 * pin no. 121 is the gnd supply (see figure 66 ) for the processor; this pad must connect to gnd. rev. pre | page 76 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data figure 65 shows the top view of the 120-lead lqfp package lead configuration and figure 66 shows the bottom view of the 120- lead lqfp package lead configuration. figure 65. 120-lead lqfp package lead configuration (top view) figure 66. 120-lead lqfp package lead configuration (bottom view) lead 1 lead 3 0 lead 90 lead 61 lead 120 lead 91 lead 3 1lead 60 lead 1 120-lead lqfp_ep top view indicator lead 3 0 lead 1 lead 61 lead 90 lead 3 1 lead 60 lead 120 120-lead lqfp_ep bottom view lead 91 gnd pad (lead 121) preliminary technical data rev. pre | page 77 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f 176-lead lqfp lead assignments table 54 lists the 176-lead lqfp package by lead number and table 55 lists the 176-lead lqfp package by signal. table 54. 176-lead lqfp lead assignment (numerical by lead number) lead no. signal name lead no. signal name lead no. signal name lead no. signal name 1 pa_13 46 jtg_trst 91 pe_05 136 vdd_ext 2 vdd_ext 47 jtg_tdo/swo 92 pe_04 137 vdd_ext 3 pa_12 48 jtg_tms/swdio 93 vdd_ext 138 pd_12 4 pa_11 49 pc_07 94 vdd_int 139 pd_13 5 pc_15 50 vdd_ext 95 byp_d0 140 pd_10 6 pa_10 51 pc_05 96 gnd_ana3 141 pd_11 7 pc_14 52 pc_06 97 adc1_vin00 142 pd_08 8 vdd_ext 53 pf_10 98 adc1_vin01 143 pd_09 9 pc_13 54 pc_04 99 adc1_vin02 144 vdd_ext 10 pc_11 55 pf_08 100 adc1_vin03 145 pd_07 11 pc_12 56 pf_09 101 adc1_vin04 146 pd_06 12 pa_09 57 vdd_ext 102 adc1_vin05 147 smc0_ams0 13 pa_08 58 pf_06 103 adc1_vin06 148 smc0_awe 14 pa_07 59 pf_07 104 adc1_vin07 149 smc0_are 15 vdd_ext 60 pc_03 105 vdd_ana1 150 vdd_ext 16 pa_06 61 pf_05 106 gnd_ana1 151 pb_10 17 pa_05 62 pc_01 107 byp_a1 152 pb_09 18 pa_04 63 pc_02 108 vref1 153 pb_08 19 pa_03 64 vdd_ext 109 gnd_vref1 154 pb_07 20 pa_02 65 vdd_int 110 refcap 155 pb_06 21 pa_01 66 pc_00 111 gnd_vref0 156 pb_05 22 vdd_int 67 pf_04 112 vref0 157 vdd_int 23 vdd_ext 68 pf_03 113 byp_a0 158 vdd_ext 24 sys_resout 69 pf_02 114 gnd_ana0 159 pb_03 25 pa_00 70 pf_01 115 vdd_ana0 160 pb_04 26 sys_fault 71 pf_00 116 adc0_vin07 161 pd_05 27 sys_hwrst 72 vdd_ext 117 adc0_vin06 162 pb_02 28 vdd_ext 73 pe_15 118 adc0_vin05 163 pd_03 29 sys_xtal 74 pe_14 119 adc0_vin04 164 pd_04 30 sys_clkin 75 pe_13 120 adc0_vin03 165 vdd_ext 31 vreg_base 76 pb_14 121 adc0_vin02 166 pd_01 32 vdd_vreg 77 pb_15 122 adc0_vin01 167 pd_02 33 vdd_ext 78 pb_13 123 adc0_vin00 168 pb_01 34 usb0_dm 79 vdd_ext 124 gnd_ana2 169 pd_00 35 usb0_dp 80 pb_11 125 vdd_ext 170 pa_15 36 usb0_vbus 81 pb_12 126 pe_03 171 pb_00 37 usb0_id 82 pe_12 127 pe_02 172 vdd_ext 38 pc_10 83 gnd 128 vdd_int 173 pa_14 39 pc_08 84 pe_11 129 vdd_ext 174 sys_clkout 40 pc_09 85 pe_10 130 pe_01 175 sys_bmode1 41 vdd_ext 86 vdd_ext 131 gnd 176 sys_bmode0 * pin no. 177 is the gnd supply (see figure 68 ) for the processor; this pad must connect to gnd. rev. pre | page 78 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data 42 twi0_scl 87 pe_09 132 sys_nmi 177* gnd 43 twi0_sda 88 pe_08 133 pe_00 44 jtg_tdi 89 pe_07 134 pd_15 45 jtg_tck/swclk 90 pe_06 135 pd_14 table 54. 176-lead lqfp lead assignment (numerical by lead number) lead no. signal name lead no. signal name lead no. signal name lead no. signal name * pin no. 177 is the gnd supply (see figure 68 ) for the processor; this pad must connect to gnd. preliminary technical data rev. pre | page 79 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f table 55. 176-lead lqfp lead assignme nt (alphabetical by signal name) signal name lead no. signal name lead no. signal name lead no. signal name lead no. adc0_vin00 123 pa_12 3 pd_09 143 sys_resout 24 adc0_vin01 122 pa_13 1 pd_10 140 sys_xtal 29 adc0_vin02 121 pa_14 173 pd_11 141 twi0_scl 42 adc0_vin03 120 pa_15 170 pd_12 138 twi0_sda 43 adc0_vin04 119 pb_00 171 pd_13 139 usb0_dm 34 adc0_vin05 118 pb_01 168 pd_14 135 usb0_dp 35 adc0_vin06 117 pb_02 162 pd_15 134 usb0_id 37 adc0_vin07 116 pb_03 159 pe_00 133 usb0_vbus 36 adc1_vin00 97 pb_04 160 pe_01 130 vdd_ana0 115 adc1_vin01 98 pb_05 156 pe_02 127 vdd_ana1 105 adc1_vin02 99 pb_06 155 pe_03 126 vdd_ext 2 adc1_vin03 100 pb_07 154 pe_04 92 vdd_ext 8 adc1_vin04 101 pb_08 153 pe_05 91 vdd_ext 15 adc1_vin05 102 pb_09 152 pe_06 90 vdd_ext 23 adc1_vin06 103 pb_10 151 pe_07 89 vdd_ext 28 adc1_vin07 104 pb_11 80 pe_08 88 vdd_ext 33 byp_a0 113 pb_12 81 pe_09 87 vdd_ext 41 byp_a1 107 pb_13 78 pe_10 85 vdd_ext 50 byp_d0 95 pb_14 76 pe_11 84 vdd_ext 57 gnd 131 pb_15 77 pe_12 82 vdd_ext 64 gnd 83 pc_00 66 pe_13 75 vdd_ext 72 gnd 177* pc_01 62 pe_14 74 vdd_ext 79 gnd_ana0 114 pc_02 63 pe_15 73 vdd_ext 86 gnd_ana1 106 pc_03 60 pf_00 71 vdd_ext 93 gnd_ana2 124 pc_04 54 pf_01 70 vdd_ext 125 gnd_ana3 96 pc_05 51 pf_02 69 vdd_ext 129 gnd_vref0 111 pc_06 52 pf_03 68 vdd_ext 136 gnd_vref1 109 pc_07 49 pf_04 67 vdd_ext 137 jtg_tck/swclk 45 pc_08 39 pf_05 61 vdd_ext 144 jtg_tdi 44 pc_09 40 pf_06 58 vdd_ext 150 jtg_tdo/swo 47 pc_10 38 pf_07 59 vdd_ext 158 jtg_tms/swdio 48 pc_11 10 pf_08 55 vdd_ext 165 jtg_trst 46 pc_12 11 pf_09 56 vdd_ext 172 pa_00 25 pc_13 9 pf_10 53 vdd_int 22 pa_01 21 pc_14 7 refcap 110 vdd_int 65 pa_02 20 pc_15 5 smc0_ams0 147 vdd_int 94 pa_03 19 pd_00 169 smc0_are 149 vdd_int 128 pa_04 18 pd_01 166 smc0_awe 148 vdd_int 157 pa_05 17 pd_02 167 sys_bmode0 176 vdd_vreg 32 pa_06 16 pd_03 163 sys_bmode1 175 vref0 112 pa_07 14 pd_04 164 sys_clkin 30 vref1 108 pa_08 13 pd_05 161 sys_clkout 174 vreg_base 31 pa_09 12 pd_06 146 sys_fault 26 pa_10 6 pd_07 145 sys_hwrst 27 pa_11 4 pd_08 142 sys_nmi 132 * pin no. 177 is the gnd supply (see figure 68 ) for the processor; this pad must connect to gnd. rev. pre | page 80 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data figure 67 shows the top view of the 176-lead lqfp lead config- uration and figure 68 shows the bottom vi ew of the 176-lead lqfp lead configuration. figure 67. 176-lead lqfp_ep lead configuration (top view) lead 1 lead 44 lead 1 3 2 lead 8 9 lead 176 lead 1 33 lead 45 lead 88 lead 1 indicator 176-lead lqfp_ep top view figre 68. 176-lead lqfp_ep lead conigration (bottom vie) lead 1 3 2 lead 8 9 lead 1 lead 44 lead 1 33 lead 176 lead 88 lead 45 176-lead lqfp_ep bottom view gnd pad (lead 177) preliminary technical data rev. pre | page 81 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f outline dimensions dimensions in figure 69 (for the 120-lead lqfp) and in figure 70 (for the 176-lead lqfp) are shown in millimeters. figure 69. 120-lead low profile quad flat package, exposed pad [lqfp_ep] 1 (sw-120-3) dimensions shown in millimeters 1 for information relating to th e sw-120-3 packages exposed pad, see the table endnote in 120-lead lqfp lead assignments on page 74 . 120 60 90 61 31 1 30 91 bottom view (pins up) compliant to jedec standards ms-026-bee-hd * note: exposed pad dimensions are preliminary and for eng grade material only. the pad size may change for volume production material. to maintain compatibility pcb designers must observe the specified keep-out area. 1.45 1.40 1.35 0.15 0.10 0.05 top view (pins down) 91 1 90 31 30 60 61 120 0.23 0.18 0.13 0.40 bsc lead pitch 11.60 ref sq 1.60 max 16.20 16.00 sq 15.80 14.10 14.00 sq 13.90 view a 0.08 coplanarity view a rotated 90 ccw 12 7 0 0.20 0.15 0.09 0.75 0.60 0.45 1.00 ref * exposed pad 5.40 ref 7.675 ref 3.50 ref 0.10 ref u-groove * see note (10 8 mm area) 2.25 ref 3.15 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 seating plane rev. pre | page 82 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f preliminary technical data pre-release products figure 70. 176-lead low profile quad flat package, exposed pad [lqfp_ep] 1 (sw-176-3) dimensions shown in millimeters 1 for information relating to th e sw-176-3 packages exposed pad, see the table endnote in 176-lead lqfp lead assignments on page 77 . model temperature range 1, 2 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 34 for the junction temperature (tj) specification wh ich is the only tempe rature specification. 2 actual temperature range for eng grade produc t is subject to change, and will be provid ed to the customer at the time of shipme nt. the production target for ambient temperature is C40c to +85c. package description package option processor instruction rate (max) adsp-cm403fbswzeng tbd 120-lead low-profile quad flat package exposed pad sw-120-3 tbd mhz adsp-cm408fbswzeng tbd 176-lead low-profile quad flat package exposed pad sw-176-3 tbd mhz compliant to jedec standards ms-026-bga-hd 0.15 0.10 0.05 0.08 coplanarity 0.20 0.15 0.09 1.45 1.40 1.35 7 0 view a rotated 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc lead pitch 24.10 24.00 sq 23.90 26.20 26.00 sq 25.80 top view (pins down) bottom view (pins up) 1 44 1 44 45 89 88 45 88 132 89 132 176 133 176 133 1.60 max 1.00 ref seating plane view a 5.80 ref 7.56 ref 3.50 ref 3.027 ref 2.225 ref 21.50 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 * exposed pad 0.10 ref * note: exposed pad dimensions are preliminary and for eng grade material only. the pad size may change for volume production material. to maintain compatibility pcb designers must observe the specified keep-out area. u-groove * see note (12 8 mm area) preliminary technical data rev. pre | page 83 of 84 | september 2013 ADSP-CM402F / cm403f/cm407f / cm408f rev. pre | page 84 of 84 | september 2013 preliminary technical data ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr11805-0-9/13(pre) ADSP-CM402F / cm403f/cm407f / cm408f |
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