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description the hfbr-57e0 small form factor pluggable lc trans- ceivers provide the system designer with a product to implement a range of solutions for multimode fiber fast ethernet and sonet oc-3 (sdh stm-1) physical layers for atm and other services. this transceiver operates at a nominal wavelength of 1300 nm with an lc fiber connector interface with an external connector shield (hfbr-57e0). transmitter section the transmitter section of the hfbr-57e0 utilizes a 1300 nm ingaasp led. this led is packaged in the optical subassembly portion of the transmitter section. it is driven by a custom silicon ic which converts differential pecl logic signals, ecl referenced (shifted) to a +3.3 v supply, into an analog led drive current. receiver section the receiver section of the hfbr-57e0 utilizes an ingaas pin photodiode coupled to a custom silicon transimped- ance preamplifier ic. it is packaged in the optical subas- sembly portion of the receiver. this pin/preamplifier combination is coupled to a custom quantizer ic which provides the final pulse shaping for the logic output and the loss of signal (los) function. the data output is differential. the data output is pecl compatible, ecl referenced (shifted) to a +3.3 v power supply. this circuit also includes a loss of signal (los) detection circuit which provides an open collector logic high output in the absence of a usable input optical sig- nal. the los output is +3.3 v ttl. features rohs compliant full compliance with atm forum uni sonet oc-3 multimode fiber physical layer specification full compliance with the optical performance require- ments of the fddi pmd standard full compliance with the optical performance require- ments of 100base-fx version of ieee802.3u industry standard small form pluggable (sfp) pack- age lc duplex connector optical interface operates with 62.5/125 m and 50/125 m multimode fiber single +3.3 v power supply +3.3 v ttl los output receiver outputs are squelch enabled manufactured in an iso 9001 certified facility temperature range: 0 c to +70 c hfbr-57e0lz/pz: -40 c to +85 c hfbr-57e0alz/apz: bail de-latch option applications oc-3 sfp transceivers are designed for atm lan and wan applications such as: atm switches and routers sonet/sdh switch infrastructure multimode fiber atm backbone links fast ethernet hfbr-57e0lz/alz/pz/apz multimode small form factor pluggable transceivers with lc connector for atm, fddi, fast ethernet and sonet oc-3/sdh stm-1 data sheet
2 light from fiber optical interface light to fiber receiver photodetector amplification & quantizattion transmitter led led driver electrical interface rd+ (receive data) rd- (receive data) loss of signal td+ (transmit data) td- (transmit data) eeprom mod-def2 mod-def1 mod-def0 tx disable 20 19 18 17 16 15 14 13 12 11 v ee t td- td+ v ee t v cc t v cc r v ee r rd+ rd- v ee r 1 2 3 4 5 6 7 8 9 10 v ee t nc** tx disable mod-def(2) mod-def(1) mod-def(0) nc los v ee r v ee r top of board bottom of board ( as viewed through top of board ) loss of signal the loss of signal (los) output indicates that the optical input signal to the receiver does not meet the minimum detectablelevel for fddi and oc-3 compliant signals. when los is high it indicates loss of signal. when los is low it indicates normal operation. the los thresholds are set to indicate a definite optical fault has occurred (e.g., disconnected or broken fiber connection to receiver, failed transmitter). module package the transceiver meets the small form pluggable (sfp) industry standard package utilizing an integral lc duplex optical interface connector. the hot-pluggable capabil- ity of the sfp package allows the module to be installed at any time C even with the host system operating and on-line. this allows for system configuration changes or maintenance without system down time. the hfbr-57e0 uses a reliable 1300 nm led source and requires a 3.3 v dc power supply for optimal design. module diagrams figure 1 illustrates the major functional components of the hfbr-57e0. the connection diagram of the module is shown in figure 2. figures 5 and 7 depict the external configuration and dimensions of the module. installation the hfbr-57e0 can be installed in or removed from any multisource agreement (msa) C compliant small form pluggable port regardless of whether the host equip- figure 2. connection diagram of module printed circuit board. ** connect to internal ground. ment is operating or not. the module is simply inserted, electrical interface first, under finger pressure. controlled hot-plugging is ensured by design and by 3-stage pin se- quencing at the electrical interface. the module housing makes initial contact with the host board emi shield miti- gating potential damage due to electro-static discharge (esd). the 3-stage pin contact sequencing involves (1) ground, (2) power, and then (3) signal pins, making con- tact with the host board surface mount connector in that order. this printed circuit board card-edge connector is depicted in figure 2. figure 1. transceiver functional diagram
3 serial identification (eeprom) the hfbr-57e0 complies with the industry standard msa that defines the serial identification protocol. this protocol uses the 2-wire serial cmos e2prom protocol of the atmel at24c01a or equivalent. the contents of the hfbr-57e0 serial id memory are defined in table 3 as specified in the sfp msa. functional data i/o the hfbr-57e0 fiberoptic transceiver is designed to ac- cept industry standard differential signals. in order to re- duce the number of passive components required on the customers board, avago has included the functionality of the transmitter bias resistors and coupling capacitors within the fiberoptic module. the transceiver is compat- ible with an ac-coupled configuration and is internally terminated. figure 5 depicts the functional diagram of the hfbr-57e0. regulatory compliance see table 1 for transceiver regulatory compliance perfor- mance. the overall equipment design will determine the certification level. the transceiver performance is offered as a figure of merit to assist the designer. table 1. regulatory compliance feature test method performance electrostatic discharge (esd) to the electrical pins mil-std-883c meets class 2 (2000 to 3999 volts).withstand up to 2200 v applied between electrical pins. electrostatic discharge (esd) to the duplex lc receptacle variation of iec 61000-4-2 typically withstand at least 25 kv without damage when the lc connector receptacle is contacted by a human body model probe. electromagnetic interference (emi) fcc class b cenelec cen55022 class b (cispr 21) vcci class 1 system margins are dependent on customer board and chassis design. immunity variation of iec 61000-4-3 typically shows a negligible effect from a 10 v/m field swept from 80 to 450 mhz applied to the transceiver without a chassis enclosure. eye safety ael class 1 en60825-1 (+a11) compliant per avago testing under single fault conditions. tuv certification: r 72042022 component recognition underwriters laboratories and ca- nadian standard associations joint component recognition for informa- tion technology equipment including electrical business equipment ul file#: e173874 rohs compliance reference to eu rohs directive 2002/95/ec electrostatic discharge (esd) there are two conditions in which immunity to esd damage is important. table 1 documents our immunity to both of these conditions. the first condition is during handling of the transceiver prior to insertion into the transceiver port. to protect the transceiver, it is important to use normal esd handling precautions. these precautions include using grounded wrist straps, workbenches, and floor mats in esd controlled areas. the esd sensitivity of the hfbr-57e0 is compatible with typical industry production environments. the second condition is static discharges to the exterior of the host equipment chassis after installation. to the extent that the duplex lc optical interface is exposed to the outside of the host equipment chassis, it may be subject to system- level esd requirements. the esd performance of the hfbr-57e0 exceeds typical industry standards. immunity equipment hosting the hfbr-57e0 modules will be sub- jected to radio-frequency electro magnetic fields in some environments. these transceivers have good immunity to such fields due to their shielded design.
4 200 100 l c C transmitter output optical rise/fall times C ns 1280 1300 1320 180 160 140 120 1360 1340 dl - transmitter output optical spectral width (fwhm) - nm 1.0 1.5 2.5 3.0 2.0 hfbr-57e0 transmitter test results of l c , dl and t r/f are correlated and comply with the allowed spectral width as a function of center wavelength for various rise and fall times. 1260 t r/f C transmitter output optical rise/ fall times C ns 3.0 0 1 2 3 4 5 6 -3 -2 -1 0 1 2 3 eye sampling time position (ns) relative input optical power (db) conditions: 1. t a = +25 c 2. v cc = 3.3 v dc 3. input optical rise/fall times = 1.0/2.1 ns. 4. input optical power is normalized to center of data symbol. 5. note 13 and 14 apply. electromagnetic interference (emi) most equipment designs utilizing these high-speed trans- ceivers from avago will be required to meet the require- ments of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. the metal housing and shielded design of the hfbr-57e0 minimize the emi challenge facing the host equipment designer. these transceivers provide superior emi perfor- mance. this greatly assists the designer in the manage- ment of the overall system emi performance. eye safety these transceivers provide class 1 eye safety by design. avago has tested the transceiver design for compliance with the requirements listed in table 1 under normal operating conditions and under a single fault condition. flammability the hfbr-57e0 transceiver housing is made of metal and high strength, heat resistant, chemically resistant, and ul 94v-0 flame retardant plastic. shipping container the transceiver is packaged in a shipping container de- signed to protect it from mechanical and esd damage during shipment or storage. transceiver optical power budget versus link length optical power budget (opb) is the available optical power for a fiberoptic link to accommodate fiber cable loses plus losses due to in-line connectors, splices, optical switches, and to provide margin for link aging and unplanned losses due to cable plant reconfiguration or repair. avago led technology has produced 1300 nm led devices with lower aging characteristics than normally associated with these technologies in the industry. the industry convention is 1.5 db aging for 1300 nm leds. the 1300 nm avago leds are specified to experience less than 1 db of aging over normal commercial equipment mission life periods. contact your avago sales representative for additional details. ordering information the hfbr-57e0 1300 nm product is available for produc- tion orders through the avago component field sales offices and authorized distributors worldwide. for technical information regarding this product, please visit the avago website at www.avagotech.com. use the quick search feature to search for this part num- ber. you may also contact the avago products customer response centre. applications support materials contact your local avago component field sales office for information on how to obtain pcb layouts and evalu- ation boards for the transceivers. figure 4. relative input optical power vs. eye sampling time position figure 3. transmitter output optical spectral width (fwhm) vs. transmit- ter output optical center wavelength and rise/fall times
5 figure 5. recommended application configuration led driver & safety circuitry 50 50 so+ soC amplification & quantization 50 50 si+ siC rx_los gpio(x) gpio(x) gp14 td+ tdC tx gnd mod_def2 eeprom mod_def1 mod_def0 rx gnd 3.3 v 4.7 k to 10 k 3.3 v 4.7 k to 10 k 4.7 k to 10 k protocol ic hfbr-57e0 1 h 1 h 10 f vc c t 0.1 f 0.1 f 3.3 v 4.7 k to 10 k 10 f 0.1 f serdes rd+ rdC rx_los 0.1 f 0.1 f 0.1 f 0.1 f 82 82 3.3 v 130 130 vccr 130 130 3.3 v 82 82 tx dis 4.7 k to 10 k v cc t 0.1 f 0.1 f 10 f 1 h 1 h 0.1 f 10 f 3.3 v sfp module v cc r host board note: inductors must have less than 1 ohm series resistance per msa. figure 6. msa required power supply filter
6 table 2. pin description pin name function/description msa notes 1v ee t transmitter ground 2nc nc 1 3 tx disable transmitter disable- module disables on high or open 4 mod-def2 module definition 2 - two wire serial id interface 2 5 mod-def1 module definition 1 - two wire serial id interface 2 6 mod-def0 module definition 0 - grounded in module 2 7nc nc 8 los loss of signal - high indicates loss of signal 3 9v ee r receiver ground 10 v ee r receiver ground 11 v ee r receiver ground 12 rd- inverse received data out 4 13 rd+ received data out 4 14 v ee r receiver ground 15 v cc r receiver power -3.3 v 10% 5 16 v cc t transmitter power -3.3 v 10% 5 17 v ee t transmitter ground 18 td+ transmitter data in 6 19 td- inverse transmitter data in 6 20 v ee t transmitter ground notes: 1. pin 2 connected to internal ground. 2. mod-def 0, 1, 2. are the module definition pins. they should be pulled up with a 4.7 k - 10 k resistor on the host board to a supply less than v cc t +0.3 v or v cc r +0.3 v. mod-def 0 is grounded by the module to indicate that the module is present. mod-def 1 is clock line of two wire serial interface for optional serial id. mod-def 2 is data line of two wire serial interface for optional serial id. 3. los (loss of signal) is an open collector/drain output which should be pulled up externally with a 4.7 - 10 k resistor on the host board to a supply < v cc t, r +0.3 v. when high, this output indicates the received optical power is below the worst case receiver sensitivity (as defin ed by the standard in use). low indicates normal operation. in the low state, the output will be pulled to <0.8 v. 4. rd-/+: these are the differential receiver outputs. they are ac coupled 100 differential lines which should be terminated with 100 dif- ferential at the serdes. the ac coupling is done inside the module and is thus not required on the host board. the voltage sw ing on these lines will be between 400 and 2000 mv differential (200 - 1000 mv single ended) when properly terminated. 5. v cc r and v cc t are the receiver and transmitter power supplies. they are defined as 2.97 - 3.63 v at the sfp connector pin. the maximum supply current is 230 ma and the associated in-rush current will typically be no more than 30 ma above steady state after 500 n anoseconds. 6. td-/+: these are the differential transmitter inputs. they are ac coupled differential lines with 100 differential termination inside the module. the ac coupling is done inside the module and is thus not required on the host board. the inputs will accept differential swing s of 400 - 2000 mv (200 - 1000 mv single ended), though it is recommended that values between 400 and 1200 mv differential (200 - 600 mv single ended) be used for best emi performance. these levels are compatible with cml and lvpecl voltage swings.
7 table 3. eeprom serial id memory contents add hex ascii add hex ascii add hex ascii add hex ascii 0 03 33 20 63 note 3 95 note 3 1 04 34 20 64 00 96 note 5 2 07 35 20 65 12 97 note 5 3 00 36 00 66 00 98 note 5 4 00 37 00 67 00 99 note 5 5 01, note 6 38 17 68 note 1 100 note 5 6 20, note 6 39 6a 69 note 1 101 note 5 7 00 40 48 h 70 note 1 102 note 5 8 00 41 46 f 71 note 1 103 note 5 9 00 42 42 b 72 note 1 104 note 5 10 00 43 52 r 73 note 1 105 note 5 11 03, note 7 44 2d - 74 note 1 106 note 5 12 02, note 8 45 35 5 75 note 1 107 note 5 13 00 46 37 7 76 note 1 108 note 5 14 00 47 45 e 77 note 1 109 note 5 15 00 48 30 0 78 note 1 110 note 5 16 c8 49 41, note 4 a 79 note 1 111 note 5 17 c8 50 50, note 4 p 80 note 1 112 note 5 18 00 51 5a, note 4 z 81 note 1 113 note 5 19 00 52 20, note 4 82 note 1 114 note 5 20 41 a 53 20, note 4 83 note 1 115 note 5 21 56 v 54 20 84 note 2 116 note 5 22 41 a 55 20 85 note 2 117 note 5 23 47 g 56 30 0 86 note 2 118 note 5 24 4f o 57 30 0 87 note 2 119 note 5 25 20 58 30 0 88 note 2 120 note 5 26 20 59 30 0 89 note 2 121 note 5 27 20 60 05 90 note 2 122 note 5 28 20 61 1e 91 note 2 123 note 5 29 20 62 00 92 00 124 note 5 30 20 93 00 125 note 5 31 20 94 00 126 note 5 32 20 127 note 5 1. addresses 68 - 83 specify a unique identifier. 2. addresses 84 - 91 specify the date code. 3. addresses 63 and 95 are check sums. address 63 is the check sum for bytes 0 - 62 and address 95 is the check sum for bytes 64 - 94. 4. part number options lz, pz, alz, apz, etc. example: for ap option, hexes in addresses 49, 50, 51, 52 and 52 will be 41, 50 , 5a, 20 and 20 respectively. 5. addresses 96-127 are vendor specific data. 6. addresses 5 and 6 specify compliance code. address 5 with hex 01 for oc-3 and address 6 with hex 20 for fast ethernet. 7. address 11 specifies encoding code. hex 03 for oc-3 and hex 02 for fast ethernet. 8. address 12 specifies bit rate. hex 02 for oc-3 and hex 01 for fast ethernet.
8 figure 7. module drawing 13.80.1 [0.5410.004] 2.60 [0.10] 55.20.2 [2.170.01] 13.40.1 [0.5280.004] avago hfbr-57e0xxz yyww country of origin device shown with dust cap and bail wire delatch 6.250.05 [0.2460.002] tx rx dimensions are in millimeters (inches) 8.50.1 [0.3350.004] front edge of sfp transceiver cage 0.7max. uncompressed [0.028] 13.00.2 [0.5120.008] 6.6 [0.261] 13.50 [0.53] area for process plug 14.8max. uncompressed [0.583] tcase reference point
9 figure 8. sfp host board mechanical layout 2x 1.7 20x 0.5 0.03 0.9 2 0.005 typ. 0.06 l a s b s 10.53 11.93 20 10 11 pin 1 20 10 11 pin 1 0.8 typ. 10.93 9.6 2x 1.55 0.05 3.2 5 legend 1. pads and vias are chassis ground 2. through holes, plating optional 3. hatched area denotes component and trace keepout (except chassis ground) 4. area denotes component keepout (traces allowed) dimensions are in millimeters 4 3 2 1 1 26.8 5 11x 2.0 10 3x 41.3 42.3 b 10x ? 1.05 0.01 16.25 ref . 14.25 11.08 8.58 5.68 2.0 11x 11.93 9.6 4.8 8.48 a 3.68 see detail 1 9x 0.95 0.05 2.5 7.1 7.2 2.5 10 3x 34.5 16.25 min. pitch y x detail 1 ? 0.85 0.05 pcb edge 0.06 l a s b s ? 0.1 l a s b s ? 0.1 l x a s ? 0.1 l x a s ? 0.1 s x y
10 figure 9. sfp assembly drawing [.600.004] dimensions are in millimeters [ inches ] . 15.250.1 [.640.004] 16.250.1min pitch [.410.004] 10.40.1 .39 to pcb 10ref [.020.004] below pcb 0.40.1 .39 9.8max .49 12.4ref .05 below pcb 1.15ref [1.64.02] 41.730.5 [.14.01] 3.50.3 [.07.04] 1.70.9 .59 15max area for process plug tcase reference point pcb msa-specified bezel bezel cage assembly
11 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. it should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. exposure to the absolute maximum ratings for extended periods can adversely affect device reliability. parameter symbol minimum typical maximum units notes storage temperature t s -40 +100 c supply voltage v cc -0.5 3.63 v data input voltage v i -0.5 v cc v differential input voltage (p-p) v d 2.4 v 1 output current i o 50 ma recommended operating conditions parameter symbol minimum typical maximum units notes case operating temperature hfbr-57e0lz/pz hfbr-57e0alz/apz t c t c 0 -40 +70 +85 c c supply voltage v cc 2.97 3.3 3.63 v data input: transmitter differential input voltage (td+/-) v i 0.5 0.8 2.4 v data and loss of signal output load r l 50 2 transmitter electrical characteristics hfbr-57e0lz/pz (t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) hfbr-57e0alz/apz (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) parameter symbol minimum typical maximum units notes supply current i cc 165 210 ma 3 power dissipation p diss 0.55 0.80 w 5a transmitter disable (tx disable) high v ih 2.0 3.5 v transmitter disable (tx disable) low v il 0 0.8 v receiver electrical characteristics hfbr-57e0lz/pz (t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) hfbr-57e0alz/apz (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) parameter symbol minimum typical maximum units notes supply current i cc 95 150 ma 4 power dissipation p diss 0.35 0.55 w 5b data output: receiver differential output voltage (rd+/-) v o 0.4 2.0 v 6a6b data output rise time t r 0.35 2.2 ns 7 data output fall time t f 0.35 2.2 ns 7 loss of signal output voltage - low losv ol 0.8 v 6a loss of signal output voltage - high losv oh 2.0 v 6a power supply noise rejection psnr 50 mv
12 notes: 1. this is the maximum voltage that can be applied across the differential transmitter data inputs to prevent damage to the inpu t esd protec- tion circuit. 2. the data outputs are terminated with 50 . the loss of signal output is terminated with 50 connected to a pull-up resistor of 4.7 k tied to v cc . 3. the power supply current needed to operate the transmitter is provided to differential ecl circuitry. this circuitry maintain s a nearly constant current flow from the power supply. constant current opera tion helps to prevent unwanted electrical noise from being generated a nd con- ducted or emitted to neighboring circuitry. 4. this is the receiver supply current measured in ma. 5a. the power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current. 5b. the power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus t he sum of the products of the output voltages and currents. 6a. differential output voltage is internally ac coupled. the loss of signal low and high voltages are measured with load condi tion as mentioned in note 2. 6b. data and data-bar outputs are squelched at los assert level. when the received light drops below los assert point, it will force receiver data and data-bar to go to steady pecl levels high and low respectively. 7. the data output rise and fall times are measured between 20% and 80% levels. transmitter optical characteristics hfbr-57e0lz/pz(t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) hfbr-57e0alz/apz (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) parameter symbol minimum typical maximum units notes output optical power bol 62.5/125 m, na = 0.275 fiber eol p o -19 -20 -15.7 -14 dbm avg 8 output optical power bol 50/125 m, na = 0.20 fiber eol p o -22.5 -23.5 -14 dbm avg 8 transmitter disable (high) p o(off ) -45 dbm center wavelength c 1270 1308 1380 nm 21, figure 3 spectral width - fwhm spectral width - rms 147 63 nm 9, 21, figure 3 optical rise time t r 0.6 1.2 3.0 ns 10, 21, figure 3 optical fall time t f 0.6 2.0 3.0 ns 10, 21, figure 3 systematic jitter contributed by the transmit- ter - oc-3 sj 0.25 1.2 ns p-p 11a duty cycle distortion contributed by the transmitter - fe dcd 0.20 0.6 ns p-p 11b data dependent jitter contributed by the transmitter - fe ddj 0.07 0.6 ns p-p 11c random jitter contributed by the transmitter oc-3 fe rj 0.10 0.10 0.52 0.69 ns p-p 12a 12b notes: 8. these optical power values are measured with the following conditions: the beginning of life (bol) to the end of life (eol) optical power degradation is typically 1.5 db per the industry convention for long wave- length leds. the actual degradation observed in avagos 1300 nm led products is < 1 db, as specified in this data sheet. over t he specified operating voltage and temperature ranges. w ith 25 mbd (12.5 mhz square-wave), input signal. at the end of one meter of noted optical fiber with cladding modes removed. the average power value can be converted to a peak power value by adding 3 db. higher output optical power transmitters are available on special request. please consult with your local avago sales representative for further details. 9. the relationship between full width half maximum and rms values for spectral width is derived from the assumption of a gauss ian shaped spectrum which results in a 2.35 x rms = fwhm relationship. 10. the optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 mbd (12.5 mhz square -wave) input signal. the ansi t1e1.2 committee has designated the possibility of defining an eye pattern mask for the transmitter optical out put as an item for further study. avago will incorporate this requirement into the specifications for these products if it is defined. the hfbr -57e0 products typically comply with the template requirements of ccitt (now itu-t) g.957 section 3.2.5, figure 2 for the stm- 1 rate, exclud ing the optical receiver filter normally associated with single mode fiber measurements which is the likely source for the ansi t1e1.2 committee to follow in this matter.
13 notes: 11a. systematic jitter contributed by the transmitter is defined as the combination of duty cycle distortion and data dependent jitter. systematic jitter is measured at 50% threshold using a 155.52 mbd (77.5 mhz square-wave), 2 23 - 1 psuedorandom data pattern input signal. 11b. duty cycle distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal using a n idle line state, 125 mbd (62.5 mhz square-wave), input signal. 11c. data dependent jitter contributed by the transmitter is specified with the fddi test pattern described in fddi pmd annex a. 5. 12a. random jitter contributed by the transmitter is specified with a 155.52 mbd (77.5 mhz square-wave) input signal. 12b. random jitter contributed by the transmitter is specified with an idle line state, 125 mbd (62.5 mhz square-wave) input sig nal. see applica- tion information - transceiver jitter performance section of this data sheet for further details. receiver optical and electrical characteristics hfbr-57e0lz /pz(t c = 0 oc to +70 oc, v cc = 2.97 v to 3.63 v) hfbr-57e0alz/apz (t c = -40 oc to +85 oc, v cc = 2.97 v to 3.63 v) parameter symbol minimum typical maximum units notes input optical power minimum at window edge oc-3 fe p in min (w) -30 -31 dbm avg 13a, figure 4 13b input optical power at eye center oc-3 fe p in min (c) -31 -31.8 dbm avg 14a, figure 4 14b input optical power maximum oc-3 fe p in max -14 -14 dbm avg 13a 13b operating wavelength 1270 1380 nm systematic jitter contributed by the receiver oc-3 sj 0.11 1.2 ns p-p 15a duty cycle distortion contributed by the receiver fe dcd 0.08 0.4 ns p-p 15b data dependent jitter contributed by the receiver fe ddj 0.02 1.0 ns p-p 15c random jitter contributed by the receiver oc-3 fe rj 0.14 0.14 1.91 2.14 ns p-p 16a 16b loss of signal - deasserted oc-3 fe p a p d + 1.5 db -31 -33 dbm avg 17 loss of signal - asserted p d -45 dbm avg 18 loss of signal - hysteresis p a - p d 1.5 db loss of signal deassert time (on to off ) 0 2 100 s 19 loss of signal assert time (off to on) 0 5 350 s 20 notes: 13a. this specification is intended to indicate the performance of the receiver section of the transceiver when input optical po wer signal character- istics are present per the following definitions. the input optical power dynamic range from the minimum level (with a window ti me-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a bit error rate (ber) better than or equal to 1 x 10 -10. - at the beginning of life (bol) - over the specified operating temperature and voltage ranges - input is a 155.52 mbd, 2 23 -1 prbs data pattern with 72 1 s and 72 0s inserted per the ccitt (now itu-t) recommendation g.958 appendix i. - receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. the actual test data wind ow time-width is set to simulate the effect of worst case optical input jitter based on the transmitter jitter values from the specification ta bles. the test window time-width is 3.32 ns. - transmitter operating with a 155.52 mbd, 77.5 mhz square-wave, input signal to simulate any cross-talk present between the tr ansmitter and receiver sections of the transceiver.
14 13b. this specification is intended to indicate the performance of the receiver section of the transceiver when input optical po wer signal characteristics are present per the following definitions. the input optical power dynamic range from the minimum level (with a window time-width) t o the maximum level is the range over which the receiver is guaranteed to provide output data with a bit error rate (ber) better than or equa l to 2.5 x 10 -10 . ? at the beginning of life (bol) ? over the specified operating temperature and voltage ranges ? input symbol pattern is the fddi test pattern defined in fddi pmd annex a.5 with 4b/5b nrzi encoded data that contains a duty cycle base-line wander effect of 50 khz. this sequence causes a near worst case condition for inter-symbol interference. ? receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. this worst case window time-width is the mi nimum allowed eye-opening presented to the fddi phy pm_data indication input (phy input) per the example in fddi pmd annex e. this minimum wi ndow time-width of 2.13 ns is based upon the worst case fddi pmd active input interface optical conditions for peak-to-peak dcd (1.0 ns), ddj (1.2 ns) and rj (0.76 ns) presented to the receiver. to test a receiver with the worst case fddi pmd active input jitter condition requires exacting control over dcd, ddj and rj j itter compo nents that is difficult to implement with production test equipment. the receiver can be equivalently tested to the worst case fddi pmd inpu t jitter condi- tions and meet the minimum output data window time-width of 2.13 ns. this is accom plished by using a nearly ideal input optica l signal (no dcd, insignificant ddj and rj) and measuring for a wider window time-width of 4.6 ns. this is possible due to the cumula tive effect o f jitter components through their superposition (dcd and ddj are directly additive and rj components are rms additive). specifically, when a nearly ideal input optical test signal is used and the maximum receiver peak-to-peak jitter contributions of dcd (0.4 ns), ddj (1.0 ns), and rj (2.14 ns) exist, the minimum window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. this wider window time-width o f 4.6 ns guarantees the fddi pmd annex e minimum window time-width of 2.13 ns under worst case input jitter conditions to the avago receiver. ? transmitter operating with an idle line state pattern, 125 mbd (62.5 mhz square-wave), input signal to simulate any cross-tal k present between the trans mit ter and receiver sections of the transceiver. 14a. all conditions of note 13a apply except that the measurement is made at the center of the symbol with no window time- widt h. 14b. all conditions of note 13b apply except that the measurement is made at the center of the symbol with no window time-width . 15a. systematic jitter contributed by the receiver is defined as the combination of duty cycle distortion and data dependent ji tter. systematic jitter is measured at 50% threshold using a 155.52 mbd (77.5 mhz square- wave), 2 23 -1 psuedorandom data pattern input signal. 15b duty cycle distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an idle line state, 125 mbd (62.5 mhz square-wave), input signal. the input optical power level is -20 dbm average. 15c. data dependent jitter contributed by the receiver is specified with the fddi ddj test pattern described in the fddi pmd ann ex a.5. the input optical power level is -20 dbm average. 16a. random jitter contributed by the receiver is specified with a 155.52 mbd (77.5 mhz square- wave) input signal. 16b. random jitter contributed by the receiver is specified with an idle line state, 125 mbd (62.5 mhz square-wave), input signa l. the input optical power level is at maximum p in min (w). see application information - transceiver jitter section for further information. 17. this value is measured during the transition from low to high levels of input optical power. 18. this value is measured during the transition from high to low levels of input optical power. at loss of signal assert, the receiver outputs data out and data out bar go to steady pecl levels high and low respectively. 19. the loss of signal output shall be de-asserted within 100 s after a step increase of the input optical power. 20. loss of signal output shall be asserted within 350 s after a step decrease in the input optical power. at loss of signal assert, the receiver outputs data out and data out bar go to steady pecl levels high and low respectively. 21. the hfbr-57e0 transceiver complies with the requirements for the trade-offs between center wavelength, spectral width, and r ise/fall times shown in figure 3. this figure is derived from the fddi pmd standard (iso/iec 9314-3 : 1990 and ansi x3.166 - 1990) per the desc ription in ansi t1e1.2 revision 3. the interpretation of this figure is that values of center wavelength and spectral width must lie along the appropriate optical rise/fall time curve.
ordering information 1300 nm led (operating case temperature 0 to +70 c) hfbr-57e0lz standard de-latch hfbr-57e0pz bail de-latch 1300 nm led (operating case temperature -40 c to +85 c) hfbr-57e0alz standard de-latch hfbr-57e0apz bail de-latch eeprom contents and/or label options hfbr-57e0lz-yyy standard de-latch, 0 to +70c hfbr-57e0pz-yyy bail de-latch, 0 to +70c hfbr-57e0alz-yyy standard de-latch, -40c to +85c hfbr-57e0apz-yyy bail de-latch, -40c to +85c where yyy is customer specific. handling precaution the hfbr-57e0xxz is a pluggable module and is not designed for aqueous wash, ir reflow or wave soldering pro- cesses. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. obsoletes av01-0456en av02-2810en - januaray 20, 2011

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