1 idt29fct2052at/bt/ct fast cmos octal registered transceiver commercial temperature range september 1999 1999 integrated device technology, inc. dsc-5482/- c idt29fct2052at/bt/ct commercial temperature range fast cmos octal registered transceiver description: the idt29fct2052at/bt/ct/dt is an 8-bit registered transceiver built using an advanced dual metal cmos technology. two 8-bit back-to- back registers store data flowing in both directions between two bidirectional buses. separate clock, clock enable and 3-state output enable signals are provided for each register. both a outputs and b outputs are guaranteed to sink 64ma. the idt29fct2052at/bt/ct has balanced drive outputs with current limiting resistors. this offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. the idt29fct2052t part is a plug-in replacement for the idt29fct52t part. functional block diagram a 1 a 2 a 4 a 5 a 6 a 7 a 3 a 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 0 d 1 d 2 d 4 d 5 d 6 d 7 d 3 d 0 ce cp a reg. q 1 q 2 q 4 q 5 q 6 q 7 q 3 q 0 d 1 d 2 d 4 d 5 d 6 d 7 d 3 d 0 ce cp b reg. q 1 q 2 q 4 q 5 q 6 q 7 q 3 q 0 oea cpb ceb oeb cpa cea features: - low input and output leakage 1 a (max.) - extended commercial range of C40c to +85c - cmos power levels - true ttl input and output compatibility v oh = 3.3v (typ.) v ol = 0.3v (typ.) - meets or exceeds jedec standard 18 specifications - product available in radiation tolerant and radiation enhanced versions - available in pdip, soic, ssop, qsop, and tssop packages - a, b and c speed grades - resistor outputs (-15ma i oh , 12ma i ol ) - reduced system switching noise
2 commercial temperature range idt29fct2052at/bt/ct fast cmos octal registered transceiver pin configuration pdip/ soic/ ssop/ qsop/ cerpack top view 2 3 1 20 19 18 15 16 9 10 a 6 a 7 a 1 a 0 a 2 a 5 a 3 a 4 b 6 b 7 23 22 24 21 17 5 6 7 4 p24-1 d24-1 so24-2 so24-7 so24-8 8 v cc b 2 b 0 b 1 b 3 b 4 b 5 13 14 11 12 cea gnd oeb cpa oea cpb ceb note: 1. h = high voltage level l = low voltage level x = dont care nc = no change - = low-to-high transition register function table (1) (applies to a or b register) inputs internal d cp ce q function x x h n c hold data l - l l load data h - lh output control (1) internal oe q y-outputs function h x z disable outputs l l l enable outputs lh h note: 1. h = high voltage level l = low voltage level x = dont care z = high-impedance absolute maximum ratings (1) symbol rating max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C65 to +120 ma 8t-link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. inputs and vcc terminals only. 3. outputs and i/o terminals only. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf 8t-link note: 1. this parameter is measured at characterization but not tested.
3 idt29fct2052at/bt/ct fast cmos octal registered transceiver commercial temperature range pin description name i/o description a 0-7 i/o eight bidirectional lines carrying the a register inputs or b register outputs. b 0-7 i/o eight bidirectional lines carrying the b register inputs or a register outputs. cpa i clock for the a register. when cea is low, data is entered into the a register on the low-to-high transition of the cpa signal. cea i clock enable for the a register. when cea is low, data is entered into the a register on the low-to-high transition of the cpa signal. when cea is high, the a register holds its contents, regardless of cpa signal transitions. oeb i output enable for the a register. when oeb is low, the a register outputs are enabled onto the b 0-7 lines. when oeb is high, the b 0-7 outputs are in the high-impedance state. cpb i clock for the b register. when ceb is low, data is entered into the b register on the low-to-high transition of the cpb signal. ceb i clock enable for the b register. when ceb is low, data is entered into the b register on the low-to-high transition of the cpb signal. when ceb is high, the b register holds its contents, regardless of cpb signal transitions. oea i output enable for the b register. when oea is low, the b register outputs are enabled onto the a 0-7 lines. when oea is high, the a 0-7 outputs are in the high-impedance state. dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = -40c to +85c, v cc = 5.0v 5% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 v v il input low level guaranteed logic low level 0.8 v i ih input high current (4) v cc = max. v i = 2.7v 1 a i il input low current (4) v i = 0.5v 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 i ozl (3-state output pins) (4) v o = 0.5v 1 i i input high current (4) v cc = max., v i = v cc (max.) 1 a v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v v h input hysteresis 200 mv i cc quiescent power supply current v cc = 3v, v in = gnd or v cc 0.01 1 ma output drive characteristics symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) 16 48 ma i odh output high current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) C16 C48 ma v oh output high voltage v cc = min. i oh = -15ma 2.4 3.3 v v in = v ih or v il v ol output low voltage v cc = min. i ol = 12ma 0.3 0.5 v v in = v ih or v il notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5 m a at t a = -55c.
4 commercial temperature range idt29fct2052at/bt/ct fast cmos octal registered transceiver notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp/ 2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2 ma i ccd dynamic power supply current (4) v cc = max. outputs open oe a or oe b = gnd v in = v cc v in = gnd 0.06 0.12 ma/ mhz one input toggling 50% duty cycle i c total power supply current (6) v cc = max. outputs open v in = v cc v in = gnd 0.62.2ma f cp = 10mhz 50% duty cycle oe a or oe b = gnd one bit toggling v in = 3.4v v in = gnd 1.14.2 at fi = 5mhz 50% duty cycle v cc = max. outputs open v in = v cc v in = gnd 1.54 (5) f cp = 10mhz 50% duty cycle oe a or oe b = gnd eight bits toggling v in = 3.4v v in = gnd 3.813 ( 5) at fi = 2.5mhz 50% duty cycle
5 idt29fct2052at/bt/ct fast cmos octal registered transceiver commercial temperature range notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. switching characteristics over operating range (1) 29fct2052at 29fct2052bt 29fct2052ct symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. unit t plh t phl propagation delay cpa, cpb to an, bn c l = 50pf r l = 500 w 2 10 2 7.5 2 6.3 ns t pzh t pzl output enable time oea or oeb to an, bn 1.5 10.5 1.5 8 1.5 7 ns t phz t plz output disable time oea or oeb to an, bn 1.5 10 1.5 7.5 1.5 6.5 ns t su set-up time, high or low an, bn to cpa, cpb 2.5 2.5 2.5 ns t h hold time, high or low an, bn to cpa, cpb 2 1.5 1.5 ns t su set-up time, high or low cea , ceb to cpa, cpb 333 ns t h hold time, high or low cea , ceb to cpa, cpb 222 ns t w clock pulse width high or low (3) 333 ns
6 commercial temperature range idt29fct2052at/bt/ct fast cmos octal registered transceiver pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test cir cuits and w a veforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns switch position test switch open drain disable low closed enable low all other tests open 8-link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
7 idt29fct2052at/bt/ct fast cmos octal registered transceiver commercial temperature range corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information xx temp. range fct xxxx device type x package x process blank p d so py q 52at 52bt 52ct commercial octal registered transceiver 29 - 40c to +85c x family 20 balanced drive plastic dip (p24-1) cerdip (d24-1) small outline ic (so24-2) shrink small outline package (so24-7) quarter-size small outline package (so24-8)
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