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r2a20056bm rev. 1.23 lithium-ion battery charger ic with auto load current distribution apr 15,2013 datasheet r03ds0075ej0100 apr 15,2013 r03ds0075ej0100 rev. 1.23 page 1 of 37 - allows to usb charging - automatic usb detection and automatic input current limitation setup (usb battery charging 1.2 and vbus divided port) - input current limitation is programmable by i2c i 2 c 100ma/500ma/1000ma/15 00ma/1800ma/limitless/suspend - weak battery charge function - high precision charge control voltage : 4.2v+/-21mv (+/-0.5%) - auto load current distribution control - auto power management between system load and ba ttery charge within input current limitation - built-in low ron path switch (30mohm) - system output voltage regulation default position : v in pass-through switching between v in pass-through and v sys45 - compliance with jeita guideline - thermistor i/f detects battery temp. to cont rol cc/cv parameters by built-in charge profile - i2c interface - adjustable charging parameters - protection function - input uvlo/ovlo - batte ry over voltage detection - timer - chip temperature detection - thermal shutdown - recharge function - gate control for system load sw (/sg) - input power ok output (/pok) - charge state output (/stat) description r2a20056bm is a semiconductor integrated circuit designed for lithium-ion battery charger control ic. built-in input current limitation circuit compliant with usb requirements and dual output (system and battery) control circuit allows to supply the system power and the battery charging power simultaneously from input power. features - digital still camera - digital video camera - mobile phone - pda/pnd - tablet/note pc - portable audio player - portable game machine application
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 2 of 37 block diagram hat1069c is recommended load sw (optional) 30m ? /stat /pok richg adaptor usb charger logic timer ctl usup /cen system bat sys usb100/500/1000/ 1500/1800ma/limitless current limit - + uvlo ovlo current monitor th monitor th i2c osc vref thvdd logicvdd gnd sys sys in scl sda host sys sw gate control /sg vref logicvdd logicvdd dp dm usb detection thvdd sgref cccvsys gate control bat voltage detector logicvdd logicvdd usb sw d- d- d- d- d+ d+ d+ d+ d- d+ tsd/chip temperature detector thvdd 700kohm 700kohm 100kohm 100kohm 100kohm
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 3 of 37 index 1234 a b c d e 5 bat bat sys sys in in scl sda dm th th vdd richg /pok /stat dp sg ref gnd /cen ctl usup /sg n.c. n.c. in in pin function pin configuration /cen charge function lo enable hi disable usup suspend lo disable hi enable ctl sdp input current limit lo 100ma hi 500ma no. terminal name i/o function a1,a2,b1,b2 in i power input(each in terminal must be short-circuited on the board) a3,b3 n.c. - non connect (keep these terminals open) a4,b4 sys o system power output (each sys terminal must be short-circuited on the board) a5,b5 bat i/o battery connection terminal (each bat terminal must be short-circuited on the board) c1 gnd gnd ground c2 /cen i charge enable c3 ctl i input current limitation terminal c4 usup i suspend terminal c5 richg o resistor connection terminal for setting charge current d1 /stat o charge state output (during charge:on, error : blinking) d2 dp i usb dp port input d3 sgref i reference voltage input terminal for /sg control voltage d4 /sg o gate control terminal for system load sw d5 thvdd o regulated voltage output for the thermistor (2.0v) e1 /pok o input power ok output(open drain) e2 dm i usb dm port input e3 sda i/o serial data input/output e4 scl i serial clock input e5 th i thermistor input
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 4 of 37 *1 within 200s *2 this value is at 75mm x 75mm x 1mm of fr4 board with 4 layers at ta=25 degc. it depends on the board condition. (ta=25degc, unless otherwise specified.) (ta=25degc, unless otherwise specified.) absolute maximum ratings recommended operating condition symbol items ratings unit v max input voltage in -0.3 to 25 v other pin -0.3 to 6.5 v i inmax input current in 2.5 a in (peak) *1 4.0 a i omax output current sys 2.5 a sys (peak) *1 4.0 a bat 2.5 a bat (peak) *1 4.0 a thvdd 1 ma i osmax output sink current /stat,/pok 15 ma t opr operating temperatur e range -30 to 85 degc t stg storage temperature range -40 to 125 degc t j junction temperature -30 to 125 degc p d power dissipation *2 2.12 w symbol items min max unit v in in input voltage 4.5 5.5 v i in in input current - 1.5 a i sys sys output current - 2 a i bat bat output current - 2 a i chg charge current - 1 a t j junction temperature -30 125 degc r ichg resistor value for setting charge current 1.6 24 kohm
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 5 of 37 (ta=25degc and vin=5v, unless otherwise specified.) *1:design guarantee item symbol condition rated value unit min. typ. max. input voltage detection v in detection voltage v uvlo when v in voltage rising 250mv hysteresis 3.1 3.3 3.5 v v in detection voltage v inbat(vin-vbat v bat =3.6v, when v in voltage rising, 45mv hysteresis 0 90 180 mv /pok detection time *1 t dglh(/pok) v in :0v to 5v, /pok = lo 64 ms input over voltage protection(ovp) v ovp when v in voltage rising, 110mv hysteresis 6.1 6.3 6.5 v ovp detection time *1 t dglh(ovp) when v in voltage rising 32 s ovp release detection time *1 t dgll(ovp) when v in voltage falling 64 ms over load detection v hl when v in voltage falling 4.3 4.4 4.5 v circuit current bat discharge current 1 i sb1(bat) v bat =4.2v, no load on sys pin 7.5 a bat discharge current 2 i sb2(bat) v in =5v, v bat =4.2v, no loads on sys pin, at charge completion 7.5 a bat discharge current 3 i sb3(bat) v bat =3.2v, no load on sys pin, at ?error 1? 20 a standby current i sb(in) v in =5v,suspend 1.5 ma circuit current i cc(in) v in =5v, /cen=hi, i sys =0 6 ma auto load current distribution and input current limitation on resistance between in and sys r in - sys v in =5.0v,i sys =0.2a usb1500ma setting 250 450 m ? on resistance between bat and sys (supplied from bat) r bat - sys v in =0v,v bat =4.2v, i sys =0.2a 30 60 m ? vsys regulation voltage v sys45 v in =5v,v bat =3.5v 4.4 4.5 4.6 v input current limitation i lim0 usb100ma mode 80 90 100 ma i lim1 usb500ma mode 450 475 500 ma i lim2 usb1000ma mode 800 900 1000 ma i lim3 usb1500ma mode 1200 1350 1500 ma i lim4 adp1800ma mode 1500 1710 1800 ma vsys regulation voltage (when current distribution works) v sys43 usb500mamode when current distribution works v in =5v,v bat =3.7v 4.2 4.3 4.4 v regulation voltage between bat and sys v sysr usb100mamode i sys =200ma v in =5v,v bat =3.7v 0.05 0.1 0.15 v electrical characteristics
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 6 of 37 (ta=25degc and vin=5v, unless otherwise specified.) *1: design guarantee *2: ncp15wf104f03rc(murata) item symbol condition rated value unit min. typ. max. battery voltage detection charge control voltage(4.20v) v chg4.20v v chg =4.20v,i bat =0a 4.179 4.200 4.221 v charge control voltage(4.15v) v chg4.15v v chg =4.15v,i bat =0a 4.10 4.15 4.20 v charge control voltage(4.10v) v chg4.10v v chg =4.10v,i bat =0a 4.05 4.10 4.15 v charge control voltage(4.05v) v chg4.05v v chg =4.05v,i bat =0a 4.00 4.05 4.10 v charge control voltage(4.00v) v chg4.00v v chg =4.00v,i bat =0a 3.95 4.00 4.05 v charge start voltage v start when v bat voltage rising, 100mv hysteresis 1.40 1.50 1.60 v quick charge start voltage v qchgon when v bat voltage rising, 100mv hysteresis 2.90 3.00 3.10 v recharge start voltage v rechg when v bat voltage falling, 3.70 3.80 3.90 v overvoltage detection voltage v ov when v bat voltage rising 4.27 4.35 4.43 v charge current detection quick charge current(1.0c) i chg1.0c richg=(3kohm),v bat =3.5v 450 500 550 ma quick charge current(0.5c) i chg0.5c richg=(3kohm),v bat =3.5v 200 250 300 ma trickle charge current(0.2c) i prechg0.2c richg=(3kohm),v bat =2.5v 70 100 130 ma trickle charge current(0.1c) i prechg0.1c richg=(3kohm),v bat =2.5v 355065ma charge completion current(0.2c) i fc0.2c richg=(3kohm),when cv control 70 100 130 ma charge completion current(0.1c) i fc0.1c richg=(3kohm),when cv control 35 50 65 ma charge completion current(0.05c) i fc0.05c richg=(3kohm),when cv control 10 25 40 ma timer circuit oscillation frequency f osc 57.6 64.0 70.4 khz trickle charge timer *1 t dchg 54 60 66 min quick charge timer *1 t chg 270 300 330 min weak battery timer *1 t wchg 36 40 44 min chip temperature detection chip temperature detection *1 t treg chip temperature, 10degc hysteresis 110 degc chip temperature reset detection *1 t trgrst chip temperature 125 degc thermal shutdown temperature *1 t sd chip temperature 150 degc thermistor detection *2 thvdd output voltage v thvdd io=0ma 1.90 2.00 2.10 v temperature protec tion detect voltage 1 t thmvl r pu =100k,r th =311.6k, 2.5degc( 2.5degc) 73.15 75.70 78.12 % temperature protection detect voltage hysteresis 1 v thmvl 2.5degc+2.5degc 2degc 17 51 85 mv temperature protec tion detect voltage 2 t thml r pu =100k,r th =184.5k, 12.5degc( 2.5degc) 61.93 64.85 67.71 % temperature protection detect voltage hysteresis 2 v thml 12.5degc+2.5 2degc 20 59 98 mv temperature protec tion detect voltage 3 t thmh r pu =100k,r th =45.5k, 42.5degc( 2.5degc) 29.03 31.27 33.63 % temperature protection detect voltage hysteresis 3 v thmh 42.5degc-2.5 2degc) 16 47 78 mv temperature protec tion detect voltage 4 t thmvh r pu =100k,r th =24.5k, 57.5degc( 2.5degc) 18.18 19.69 21.32 % temperature protection detect voltage hysteresis 4 v thmvh 57.5degc-2.5degc 2degc 11 32 53 mv thermistor connection detect voltage t thcon r pu =100k 90 93 96 % electrical characteristics
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 7 of 37 (ta=25degc and vin=5v, unless otherwise specified.) electrical characteristics item symbol condition rated value unit min. typ. max. /cen,ctl,usup terminal input high voltage v inh 1.2 v input low voltage v inl 0.5 v input source current i ih v inh =2.8v 50 a input sink current i il v inl =0.03v 1 a scl,sda terminal input high voltage v inh(i2c) 1.4 v input low voltage v inl(i2c) 0.3 v output low voltage (sda) v ol(sda) i sink =3ma 0.4 v input source current i ih(i2c) v inh(i2c) =1.8v 5 a input sink current i il(i2c) v inl(i2c) =0.03v 1 a /pok,/stat terminal output low voltage v ol i sink =5ma 0.4 v gate control for system load sw low battery detection voltage (internal) v sysswoff v sgref >v sysref_sw 3.3 3.4 3.5 v low battery detection voltage hysteresis (internal setting) v sysswoff_in_hys v sgref >v sysref_sw 33 100 166 mv low battery detection voltage hysteresis (external setting) v sysswoff_out_hys v sysswoff_out =3.4v 100 200 300 mv sgref detection voltage v sysref_sw 1.7 1.8 1.9 v usb detection dp to dm short resistance r dpm_short usb battery charging 1.2 125 200 ? dp terminal voltage v dp_src usb battery charging 1.2 0.5 0.6 0.7 v dm terminal voltage v dm_src usb battery charging 1.2 0.5 0.6 0.7 v dp terminal sink current i dp_sink usb battery charging 1.2 50 150 a dm terminal sink current i dm_sink usb battery charging 1.2 50 150 a data detection voltage (when rising) v dat_ref usb battery charging 1.2 0.25 0.40 v divided port divided port middle voltage v div_mid 1.90 2.00 2.10 v divided port high voltage v div_high 2.55 2.68 2.81 v
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 8 of 37 *1 state transition judgment includes battery temperature detection. state is kept in default(00h) when th temperature protection ( hign or low) and thermistor open. *2 it's ?or? condition with t thm < t thcon when thbatcon='1' (set by i2c). *3 it's 'or' condition with t thm > t thcon when thbatcon='1' (set by i2c). *4 these judgment times are 384ms for these transitions. *5 refer to input voltage detection about the condition of /pok=?l? or ?h?. timer start 0.2c: 7.68s 0.2c ? 1.0c: 512ms x 48step=24.58s quick charge (03h) 0.2c to1.0cstop increasing high temp. charge-1 (04h) 0.2c high temp. charge-2 (05h) charge completion (07h) v bat < v qchgon and v bat < v sys v bat < v qchgon and v bat < v sys t treg t sd or v bat >v ov timer is not reset in the state inside of broken line charge control compliant with jeita guideline (/stat=l) (/stat=l) (/stat=l) (/stat=h) (/stat=h) error-2 (0ah) 01h, 03h,04h and 05h state t thm >t thmvh or t thm < t thmvl t thm < t thmvh and t thm >t thmvl hold timer v qchgon t thmvh or t thm < t thmvl v start v sys (mosfet between bat and sys : on), the state is not changed except for battery voltage error or chip temperature error. there are 3 operations of timer in each transition for trickle charge timer and quick charge timer. - ?reset timer? - ?hold timer? - ?restart timer? the release conditions against ?error 1? are as follows: -v in not detected [/pok=?h?] - suspend - charge stop [/cen=?h?] - battery non-connection v qchgon r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 9 of 37 quick charge timer trickle charge timer (t dchg ) progress flog timer stop (3.0v) (4.2v) (3.8v) bat terminal voltage: actual battery voltage + internal resistance x charge current actual battery voltage battery voltage timer stop charge completion current trickle charge charge completion recharge completion cv control recharge start quick charge current setting value(1.0c) 0.1c charge current quick charge ta=85degc ta=27degc ta=0degc forced charge 0.2c cc control (7.68sec) (24.58sec) on /stat(led) on off adjustable (0.1c or 0.2c) (t chg ) progress flog timer stop note: * during quick charge, junction temperature is monitored to limit charge current value between 0.2c-1.0c so that the juncti on temperature may not exceed ttreg. * the high temp. charge-1 (04h) is oper ating at ta=85 degc in above waveform. v chg v rechg v qcchgon timer working timer working timer working charge state diagram (7.68sec)
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 10 of 37 * : ncp15wf104f03rc (murata) battery temperature detection charge stop charge stop 2.5/5degc normal temp. normal charge high temp. low temp cv voltage cc current v chg4.20v i chg1.0c 40/42.5degc v chg4.05v ovp detection v ov 12.5/15degc low temp. low rate charge 55/57.5degc temp. protection temp. protection charge operation range charge state battery temp. high temp. low rate charge this ic detects battery temperature with thermistor i/f and controls cv voltage according to built-in charge profile. there is the delay time(64ms x 4times =256ms) for preventing erroneous detecti on before judging the battery temperature. when pse control (adr=02h) is ?enable? setting, the charge control voltage changes as the above chart according to jeita guide line. but when vchg setting (adr=00h) is 4.00v, the charge control voltage at low rate charge is also 4.00v not 4.05v. when pse control (adr=02h) is ?disable? setting, the charge control voltage depends on the vchg setting (adr=00h). when thbatcon (adr=02h) is ?enable? setting, the battery connection is detected with battery voltage or th voltage. for details, please refer to ?battery connection detection?. when thermistor is not used, please connect th term inal with thvdd terminal and set ?pse control (adr=02h)? to ?disable?. resister value for thermistor function description temp. (deg.c) r(k ? ) 2.5 311.6 5.0 272.5 12.5 184.5 15.0 162.7 temp. (deg.c) r(k ? ) 40.0 50.7 42.5 45.5 55.0 27.1 57.5 24.5 0degc detection 10degc detection 45degc detection 60degc detection control diagram corresponding jeita guideline
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 11 of 37 usb port detection [ usb port detection flow chart ] no no yes v in >3.3v v bat > v sysswoff dp < v lgc_low dead battery provision mode yes dm > v dat_ref yes no dcp dp > v dat_ref yes no data contact detection primary detection secondary detection cdp sdp yes dm >1.0v yes 700ms timer start usb battery charging 1.2 timer 700ms? dp>3.3v no v bat > v sysswoff suspend sdp & timer > t wchg dm >1.0v yes dp error dm>3.3v dm error dp>2.3v vbus divided port 3 dm>2.3v vbus divided port 2 vbus divided port 1 no yes yes yes yes no no no no (v lgc_low : 0~0.8v) (v dat_ref : 0.25~0.4v divided port detection (dm : 200kohm pulled-down) divided port detection (dm : 200kohm pulled-down) function description tout_dcd: ?1? tout_wkb: ?1? this ic detects the type of usb port as the following chart after usb connection.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 12 of 37 6 types of usb port detection are enabled by detecting dp and dm terminals and the current limit is automatically set for each port. this detection starts after applying the voltage above v ulvo (typ. 3.3v) to in terminal or sendi ng reset signal by rst_usbdet (adr:02h). 04h usb detection result (read only) the detection result is stored in the registers. when dp and dm terminals are open, this ic regards the port as sdp and indicates ?1? in ?tout_dcd? register. when dp>3.3v or dm>3.3v, this ic indicates 'error' register and enter the suspend mode. suspend is can be dissolved by ?rst_usbdet? or ?usbmd?. *1 it depends on ctl terminal setting for vbus divided port, this ic detects the combination of the divided voltage with ?dp? and ?dm? terminals as the following chart. usb detection timing chart v in usb detection sys voltage /pok <- attach detecting max 1s 4ms 64ms battery voltage dp and dm terminal become hi-z (open) after usb detection. function description no. port usb battery charging 1.2 current limit (ma) 1 sdp (standard downstream port) o 100 or 500 *1 2 cdp (charging downstream port) o 1500 3 dcp (dedicated charging port) o 1500 4 vbus divided port 1 - 500 5 vbus divided port 2 - 1000 6 vbus divided port 3 - 1800 ctl sdp current limit lo 100ma hi 500ma bit5 bit4 bit3 usb 0 0 0 sdp (standard downstream port) 0 0 1 cdp (charging downstream port) 0 1 0 dcp (dedicated charging port) 1 0 0 vbus divided port 1 1 0 1 vbus divided port 2 1 1 0 vbus divided port 3 0 1 1 dp error 1 1 1 dm error port dp dm current limit(ma) vbus divided port 1 2.00v 2.00v 500 vbus divided port 2 2.00v 2.68v 1000 vbus divided port 3 2.68v 2.00v 1800 sys control voltage * these voltages are the divided voltage at v in =5.0v. these voltages also change with v in voltage at this dividing ratio. * please set the downside resistance of the divided resistances to be above 100kohm.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 13 of 37 dead battery provision when vbat < v sysswoff_set (low battery detection voltage) at the usb detection, the behaviors for each usb port are as follows: < sdp ( standard downstream port) > - sg terminal is ?h?. - trickle charge or quick charge can start. - dead battery provision starts and dp terminal outputs v dp_src (typ. 0.6v). - if vbat doesn?t exceed v sysswoff in t wchg (typ. 40min.), it shifts into the suspend mode. please reconnect with v in to resolve this suspend mode. - it can stop weak battery timer to set time r control (adr=01h) to ?reset? or ?count stop?. setting input current with ?usbmd?=?1? can avoid shifting into the suspend mode. - when vbat > v sysswon ( v sysswoff + v sysswoff_hys ) , the usb detection is carried out again. during the usb detection, it shifts into the su spend mode and sys terminal outputs bat voltage. the charge function starts from ?default (00h)? and sg terminal is ?l?. dp and dm terminals becomes hi-z (open) after the usb detection. if the battery voltage drops below v sysswoff after this, dead battery prov ision doesn?t start again. /sg is set to ?h? but weak battery timer and v dp_src output from dp terminal don?t operate. < dcp ( dedicated charging port) > - sg terminal is ?h?. - trickle charge or quick charge can start. - dead battery provision starts and dp terminal outputs v dp_src (typ. 0.6v). - weak battery timer (typ. 40 min) doesn?t count up. but the each charging timer (trickle or quick charge timer) counts up. - when vbat > v sysswon ( v sysswoff + v sysswoff_hys ) , the usb detection is carried out again. during usb detection, it shifts into the susp end mode and sys terminal outputs bat voltage. the charge function starts from ?default (00h)? and sg terminal is ?l?. dp and dm terminals becomes hi-z (open) after the usb detection. if the battery voltage drops below v sysswoff after this, dead battery provision doesn?t start again. /sg is set to ?h? but v dp_src output from dp terminal doesn?t operate. < cdp ( charging downstream port) > - the operation is the same as dcp. but during de ad battery provision mode, this port is detected as ?dcp? and usb detection register (adr=04h) also indicates ?dcp?. < divided port 1,2,3> - there isn?t dead battery provision for divided port. usb detection after good battery detection doesn?t start. - sg terminal is ?h?. connecting in terminal when bat is open is r egarded as ?weak battery? and dead battery provision starts. if dead battery provision continues in t wchg , it shifts into the suspend mode. for avoiding shifting into the suspend m ode, set timer control (adr=01h) to ?reser? or ?count stop?. function description
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 14 of 37 this function controls ?/sg? terminal. ?/sg? terminal is connected with the loadsw (recommended renesas hat1069c) between the sys terminal and system, and controls power supply to system on/off. and ?/sg? terminal can be used for the control of an usb sw because this terminal becomes ?h? (off) during the usb detection. 1. ?/sg? = ?h? (?off?) during the usb detection or dead battery provision. ?h? voltage during the usb detection can become the bat voltage. refer to ?starting function after in connected?. 2. this function can be selected fo r ?enable? or ?disable? by sgctl (adr=02h). 3. when the battery voltage is low, all current can be used for charging by stopping the current supply for system with the loadsw off. (after usb detection & sgctl: enable) [/sg control in each condition about the in and the bat ( except for the usb detection, dead battery provision and sgctl: disable)] (1) in : connect , bat : connect v bat < v start on(?l?) v start < v bat r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 15 of 37 input current limitation / control between sys and bat - usb detection (usb battery charging 1.2) - input current limitation(100ma/ 500ma/1000ma/1500ma/1800ma/limitless/ suspend) can be set by i2c. -the current limit is dropped as the lis t for protection when sys is shorted. -when the total sum of the charge current and the system current is below the input limit current, sys terminal outputs in voltage directly. when in voltage is over 5.4v, sys volt age is controlled to be below 5.4v. capable for switching between v sys45 and v in pass-through by i2c. -ic switches the system power s upply and the battery charge seamlessly within input current limitation. system usb in sys bat i sys i chg i bat v bat v sys i in cc/cv /sys control sys_reg current limit /sg sys sw gate control example of power control between the system supply and the battery charge conditions : in=5.0v is connected, i in_max =500ma, i chg =350ma, chargeable battery is connected. (1) (2) (3) the ic charges the battery at i chg =350ma and supplies the system current(isys) within i in_max =500ma. when the system current(i sys ) increases and the total sum of i sys and i chg reaches i in_max , the ic reduces the charge current. when the system current (i sys ) increases more and i sys exceeds i in_max , v sys falls to v bat -v sysr and the battery supplies the load current to system through the path sw. (ic attempts to sustain the system vo ltage no matter what causes it to drop.) time current 0ma 350ma input voltage v bat -v sysr input current (i in ) i in_max time v sys v sys43 (2) (1) (3) battery to system current (i bat ) vbat system current (i sys ) charge current (i chg ) v in pass-through or v sys45 current limit setting at sys short 100ma 500ma 20% 1000ma 40% 1500ma 1800ma 50% ( design guarantee) function description input current limit when sys is shorted. auto load current distribution control
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 16 of 37 v in v uvlo v inbat v ovp t dglh(/pok) /pok v ovphys v inbathys v uvlohys t dglh(ovp) t dgll(ovp) t dgll(/pok) 32s 64ms 64ms usb detection 64ms detection max 1s over load detection input voltage detection /pok timing chart v in voltage range during normal operation operation of over load detection v in sys isys overload (adr:03h bit0) v hl control (v in ) bat bat-v sysr control '0' '0' '1' overload (current capability < current limit) function description when in voltage drops below v hl , the input current is controlled as the current at the time regardless of the current limit setting. the overload register (adr:03h bit0) indicate '1'. this ic detects lack of current capability of power supply and prevents exceeded current from flowing from in terminal. v uvlo v bat +v inbat : power supply from in to sys and charging are available. /pok =l. v ovp r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 17 of 37 connection sequence battery condition thermistor included in battery *1 on board *2 no use *3 bat -> in normal starting from default(00h) starting from default(00h) starting from default(00h) open battery starting from default(00h) starting from default(00h) starting from default(00h) in -> bat *4 normal starting from default(00h) forbidden open battery default(00h) connection sequence battery condition thermistor included in battery *1 on board no use bat -> in normal starting from default(00h) forbidden open battery starting from default(00h) in -> bat *4 normal starting from default(00h) open battery starting from default(00h) thbatcon : ?disable? thbatcon : ?enable? *1 : th voltage is in the charging range. charging doesn?t starts with no battery because th voltage is not in the charging range. *2 : th voltage is in the charging range. *3 : pse control : ?disable? *4 : don?t start charging with no battery. function description battery connection detection
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 18 of 37 battery connection is detected by battery voltage as follows: - battery voltage (v bat ) > charge start voltage (v start ) when register [ thbatcon (adr:02h) ] is set to ?enable?, battery connection is detected by battery voltage or th terminal voltage as follows: - battery voltage (v bat ) > charge start voltage (v start ) - th terminal voltage < thermistor connection detect voltage (v thcon ) when thermistor is included in battery pack and this register is set to ?enable?, charging can also starts for an open battery. when thermistor isn?t included in battery pack, please don?t set this register ?enable?. the list in the previous page shows the behav ior with 3 kinds of thermistor setting and 2 kinds of battery. ?included in battery? , ?on board? , ?no use? ?normal? , ?open battery? when thbatcon(adr:02h) is ?disable? setting (default setting) , the battery connection is detected by only battery voltage. when in is connected after ?battery connection ?, charging starts from ?default (00h)? state for both ?normal? and ?open battery ?. when in is connected before ?battery connection?, charging starts for ?normal? battery as same as when in is connected after ?battery connection?. for ?open battery ?, the state stays at ?default(00h)? because it can?t detect battery connection. and charging is forbidden with no battery when thermistor is ?on board? or ?no use?. if thbatcon (adr:02h) is set to ?enable?, battery connection is detected by either battery voltage or th terminal voltage. charging also starts for ?open battery? as same as ?normal?. so it is possible to charge for all batteries when thermistor is ?included in battery?. when thermistor is ?on board? or ?no use?, th batcon (adr:02h) ?enable? setting is forbidden. and please don?t charge with no battery. function description
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 19 of 37 /sg bat vsys (1) usb detection with good battery (v bat >v sysswoff ) after in connected vuvlo v in sys bat voltage usb detection normal charge loadsw on loadsw off loadsw on /pok i2c 4ms 64ms sys control voltage (v in pass-through or v sys45 ) (1) usb detection with good battery (v bat >v sysswoff ) after in connected (2) usb detection with weak battery (v bat r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 20 of 37 (2) usb detection with weak battery (v bat r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 21 of 37 bat voltage /sg bat 100ms vsys v sysswon bat sys loadsw on loadsw off loadsw off vuvlo v in loadsw on normal charging * dead battery provision does n?t start for divided port. /pok i2c enable disable 4ms 64ms 64ms sys control voltage sys control voltage usb detection function description (3) usb detection with weak battery (v bat r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 22 of 37 /sg 100ms vsys v sysswon bat sys dead battery provision loadsw on loadsw off vuvlo v in loadsw on normal charge /pok i2c enable disable 4ms 64ms 64ms open after usb detection v dp_src dp open sys control voltage sys control voltage usb re-detection the condition of dp changes during usb re-detection. 64ms 64ms usb detection bat battery connection bat voltage bat voltage 0v function description (4) usb detection with no battery after in connected [battery charging 1.2 port] * weak battery timer operates during dead battery provision at sdp. if the battery voltage doesn?t exceed v sysswoff in t wchg (typ. 40min.), it shifts into the suspend mode. (refer to ?dead battery provision?.) * dead battery provision lasts when a weak battery is connected. usb re-detection starts when the battery becomes a good battery. * please start charging after connecting a battery. don?t start charging with no battery.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 23 of 37 /sg 100ms vsys v sysswon bat sys loadsw on loadsw off vuvlo v in loadsw on normal charging * dead battery provision does n?t start for divided port. /pok i2c enable disable 4ms 64ms 64ms sys control voltage sys control voltage usb detection battery connection bat voltage 0v function description (5) usb detection with no battery after in connected [divided port] * /sg doesn?t change when a weak battery is connected. /sg becomes ?l? after the battery becomes a good battery. * please start charging after connecting a battery. don?t start charging with no battery.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 24 of 37 forced charge trickle charge current or quick charge current charge current /stat (led) input connection 1256ms max input connection detection forced charge on forced charge current 640ms battery voltage detection off on forced charge mode timing from input detection to charge start trickle charge or quick charge mode (0.1c) (0.2c) 0.1c or 0.2c selectable by register 256ms after input power detection, forced char ge starts for canceling the cutoff st ate of battery due to over-discharge. the forced charged current is the same as trickle charge current setting. register ( adr=00h bit6) is available for changing setting. charging starts even with an open battery by this function. please refer to battery connection detection. trickle charge (0.1c constant current charge) after input detection and battery detec tion, trickle charge starts when v bat < v qcchgon (typ. 3.0v). - when detecting v bat >v qcchgon , the state shifts to quick charge mode. - trickle charge timer starts when trickle charge starts. - after trickle charge timer expires, the state shifts to ?error mode 1? if v bat < v qcchgon . however trickle timer stops when the battery voltage becomes below v start . when bat is shorted, this timer also stops. nobat(adr= 03h, bit5) indicates detecting the battery voltage below v start . after nobat=?1? by detecting v bat v ov (typ. 4.35v), the state shifts to ?error mode 1?. trickle charge setting is selectable between 0. 1c and 0.2c by register (adr=00h bit4,5). quick charge (1.0c constant current charge) quick charge starts after detecting v bat >v qcchgon . - when detecting v bat =v chg , the state shifts to cv (constant voltage) charge mode. - quick charge timer starts when quick charge starts. - when detecting v bat < (v chgon ? hysteresis voltage) (typ. 2.9v) , the state shifts to trickle charge mode. - when detecting v bat >v ov (typ. 4.35v), the state shifts to ?error mode 1?. during quick charge, this ic monitors junction tem perature and controls the cu rrent between 0.2c and 1.0c not to exceed t treg . the quick charge current is selectable between 0. 5c and 1.0c by register (adr=00h bit 0). function description battery temp. detection
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 25 of 37 quick charge mode timing to quick charge(1.0c) charge current battery voltage quick charge current (0.2c) quick charge current (1.0c) (7.68sec) (24.58sec) 256ms trickle charge current (0.1c) trickle charge mode quick charge start voltage detection v qcchgon 256ms charge completion current detection 384ms 256ms battery voltage detection v bat terminal discharge (about 200 a) charge completion detection timing of charge completion detection charge current battery voltage charge completion (07h) constant voltage charge when detecting v bat =charge control voltage during quick charge mode, constant vo ltage charge starts. - when the charge current falls below charge completion current during constant voltage charge, the state shifts to charge completion detection mode. if v bat >v rechg (typ. 3.8v), the state shifts to charge completion state. - when v start r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 26 of 37 256ms battery voltage detection recharge detection timing of recharge judgment quick charge mode recharge function after charge completion, battery voltage continues to be monitored. when v bat < v rechg , recharge starts. quick charge timer also starts to operate when recharge starts. charge current battery voltage quick charge current (beginning) (0.2c) quick charge current (1.0c) led control (/stat) *1:refer to the charge state diagram on duty 50% on duty 50% on duty 50% function description mode led blink cycle default off - forced charge on - trickle charge on - quick charge on - high temp. charge-1 on - high temp. charge-2 on - charge completion detection off - charge completion off - error-1 *1 blink 1 128ms error-2 *1 blink 2 1024ms error-3 *1 blink 2 1024ms battery non-connection off -
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 27 of 37 charge current setting [ design guarantee except for ichg=500ma ] accuracy of each setting about charge current and charge completion current charge current is set by the external resistance with richg terminal. here is the formula between r ichg and i chg1.0c . r ichg = 812 x i chg1.0c -0.9 r ichg (kohm) : external resistance with richg i chg1.0c (ma) : quick charge setting 0.2c, 0.1c and 0.05c are 20%, 10% and 5% current of 1.0c. they can be set by register ( adr=00h). the accuracy of each current is as the following list. please use the current over 5ma. i chg1.0c i prechg0.2c , i prechg0.1c i fc0.2c , i fc0.1c i fc0.05c charge current (ma) charge completion current (ma) accuracy(%) item quick charge current(i chg1.0c ) setting 500ma r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 28 of 37 chip temperature detection and thermal shutdown i chg (a) battery voltage (v) 1.0c/0.5c junction temperature (degc) (110degc) (100degc) ichg(ma) 0.2c (125degc) increase of i chg is stopped and t j falls. when t j t trgrst , i chg is set at 0.2c by the chip temperature reset detection. t j rises at t sd by abnormal situation. charging operation stops by thermal shutdown. quick charge starts. chip temperature detection thermal shutdown during quick charge, junction temperature is monitored to limit charge current bet ween 0.2c to 1.0c so that junction temperature may not exceed t treg . when junction temperature reaches tsd( default: 150degc) under charge, ic stops to supply from in to sys and the state moves to error mode. when t j >t treg , ic stops increasing i chg . when i chg reaches 1.0c (regulated value), ic stops to increase i chg . t sd t trgrst t treg t treg_down (t treg -hysteresis voltage) function description
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 29 of 37 03h state register (read only) 05h state register (read only) 05h<4> ~ <7> keep 0 when charge full, full=0 and tout=0. when suspend, tsd=0,tout=0,full=0,vbath=0,nobat=1. 04h temp register (read only) 04h usb detection result (read only) register map adr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r/w - trickle fc vchg ichg 01h r/w usbmd timer ctl3 /cen2 02h r/w sysmode rst_usbdet thbatcon sgctl fulmd rechg pse 03h r gdbat vbath nobat full tout tsd pok overload 04h r tout_wkb tout_dcd usb temp 05h r 0 0 0 0 stat3 stat2 stat1 stat0 0 1 condition of ?1? overload not overload overload v in < v hl pok not detect v in detect v in /pok=?l? tsd ic chip temperature is normal thermal protection work (ic stop) t j > t sd tout timer normal time out (charging stop) timeout of trickle or quick charge timer full charging not complete charging complete i chg < i fc (during cv) nobat battery detected no battery v bat < v start vbath battery voltage normal b attery over voltage v bat > v ov gdbat weak battery good battery v sysswoff < v bat bit2 bit1 bit0 temp 0 0 0 temperature protection (low temp.) 0 0 1 low rate charge (low temp.) 0 1 0 normal charge 0 1 1 low rate charge (high temp.) 1 0 0 temperature protection (high temp.) 1 0 1 no thermistor bit5 bit4 bit3 usb 0 0 0 sdp (standard downstream port) 0 0 1 cdp (charging downstream port) 0 1 0 dcp (dedicated charging port) 1 0 0 divided port 1 1 0 1 divided port 2 1 1 0 divided port 3 0 1 1 dp error 1 1 1 dm error bit7 weak battery timer 0normal 1 time out stat3 stat2 stat1 stat0 state 0000 default 0 0 0 1 forced charge 0 0 1 0 trickle charge 0 0 1 1 quick charge 0 1 0 0 high temp. charge-1 0 1 0 1 high temp. charge-2 0 1 1 0 charge completion detection 0 1 1 1 charge completion 1 0 0 0 battery non-connection 1 0 0 1 error-1 1 0 1 0 error-2 1 0 1 1 error-3 bit6 connect detection 0normal 1 time out 04h tout_wkb register (read only) 04h tout_dcd register (read only)
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 30 of 37 *default setting register setting adr=00h r/w ichg * quick charge current bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0.5c -------0 1.0c -------1 vchg * charge control voltage bit7 bi t6 bit5 bit4 bit3 bit2 bit1 bit0 4.00v - - - - 0 0 0 - 4.05v - - - - 0 0 1 - 4.10v - - - - 0 1 0 - 4.15v - - - - 0 1 1 - 4.20v - - - - 1 0 0 - no use ----101- ----110- ----111- fc * charge completion current bit7 bi t6 bit5 bit4 bit3 bit2 bit1 bit0 0.05c - - 0 0 - - - - 0.1c - - 0 1 - - - - 0.2c - - 1 0 - - - - no use - - 1 1 - - - - trickle * trickle charge current bit7 bi t6 bit5 bit4 bit3 bit2 bit1 bit0 0.1c -0------ 0.2c -1------ adr=01h r/w /cen2 * charger control *1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 enable - ------0 disable -------1 ctl3 * input current limitation *2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 100ma - - - - 0 0 0 - 500ma - - - - 0 0 1 - 1000ma - - - - 0 1 0 - 1500ma - - - - 0 1 1 - 1800ma - - - - 1 0 0 - limitless - - - - 1 0 1 - no use - - - - 1 1 0 - suspend - - - - 1 1 1 - timer * timer control bit7 bit6 bit 5 bit4 bit3 bit2 bit1 bit0 disable(reset) - 0 0 0 - - - - enable(normal) - 0 0 1 - - - - enable(slow x 2) *3 - 010 - - - - enable(slow x 4) *4 - 011 - - - - enable(count stop) *5 - 100 - - - - no use - 101 - - - - - 110 - - - - - 111 - - - - usbmd * usb control select *2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 depend on terminals 0 ------- depend on register 1 -------
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 31 of 37 *2) when usbmd=0, terminal setting(usup) is availa ble. when usbmd=1, register(ctl3) is available and the suspend function by weak battery timer is unavailable. re-connect with in when going into the suspend mode by weak battery timer. *3) slow: 2 times of normal mode(trickle charge timer=120min., quick charge timer=600min , weak battery timer = 80min.) *4) slow: 4 times of normal mode(trickle charge timer=240min., quick charge timer=1200min , weak battery timer = 160min.) *5) count stop : timer is suspended.(not reset) *6) when rst_usb=1, the usb detecting is in reset and /sg output is 'l'. when rst_usb=0, the usb detecting will restart. during the usb detection, /sg is 'h'. after usb detection, /sg output is determined by the sg function. usb re-detection by rst_usbdet can reset the suspend by usb detecting error. *7) the sys voltage setting can be set by the sysmode register. * when v in <2.0v, the register is reset. (this value is design guarantee). *1) when /cen=l and /cen2(register)='0', charge operation is enable. [truth table] register setting adr=02h r/w pse * pse control bit7 bit6 bit5 b it4 bit3 bit2 bit1 bit0 enable - - - - - - - 0 disable -------1 rechg * recharge control bit7 bit6 b it5 bit4 bit3 bit2 bit1 bit0 enable - - - - - - 0 - disable ------1- fulmd * operation after charge completion bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stop charge - - - - - 0 - - continue to charge(inform full) - - - - - 1 - - sgctl * /sg control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 enable - - - - 0 - - - disable - - - - 1 - - - thbatcon * battery detection by th terminal bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 disable - - - 0 - - - - enable - - - 1 - - - - rst_usbdet * usb detection reset bit7 bit6 b it5 bit4 bit3 bit2 bit1 bit0 disable --0----- enable (reset) - - 1 - - - - - sysmode * sys output mode *1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 v in pass-through 00------ 01------ v sys45 (typ. 4.5v) 10------ v in pass-through 1 1 - - - - - - /cen /cen2 charge operation lo 0 charge start lo 1 charge stop hi 0 charge stop hi 1 charge stop
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 32 of 37 i 2 c timing chart sda v ih v il scl v ih v il start start start stop t r , t f t buf t hd:sta t su:dat t hd:dat t su:sto t low t su:sta t high symbol item min. max. unit f scl scl clock frequency 0 400 khz t buf bus free time between stop condition and start condition 1.3 - s t hd:sta start condition hold time (after this period, the first clock pulse is generated) 0.6 - s t low scl low period 1.3 - s t high scl high period 0.6 - s t su:sta start condition setup time 0.6 - s t hd:dat data hold time 0 0.9 s t su:dat data setup time 100 - ns t r rise time (sda and scl) - 300 ns t f fall time (sda and scl) - 300 ns t su:sto stop condition setup time 0.6 - s c b bus line capacitive load - 400 pf note : above values are specified by v ih min and v il max. i 2 c bus line characteristics
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 33 of 37 (solid line: from master to r2a20056, dotted line: from r2a20056 to master) sda scl *** *** * ack xx xx xa2a1 a0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack w register address (sub-address) write data slave address start condition stop condition 1. start condition last first lsb msb 2. slave address 0 0 1 1 0 1 1 3. stop condition sda scl start condition *** *** * ack xx a1 a0 ack w register address (sub-address) slave address read data slave address start condition stop condition d7 d6 d5 d4 d3 d2 d1 d0 nack *** *** * r ack xxxa2 5. write mode :data input from master to r2a20056 set sda from high to low when scl=high. set sda from low to high when scl=high. write code : sda=low read code : sda=high (solid line: from master to r2a20056, dotted line: from r2a20056 to master) 6. read mode :data output from r2a20056 to master when master inputs slave address(8bit) and write code after st art condition, r2a20056 res ponds with an acknowledge'0'. and then, when master inputs register address(8bit) , r2a20056bm responds wi th an acknowledge'0'. and then, when master inputs start condition, slave address, and read code, r2a20056 res ponds with an acknowledge'0' and outputs read data. lastly, master inputs acknowledge' 1'(or opens bus line) and stop condition. 4. read/write code serial communication format r2a20056 will respond with an acknowledge ?0? when; - master inputs slave address (8bit) and write code after start condition - master inputs register address (8bit) - master inputs write data (8bit) lastly, master will input stop condition.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 34 of 37 [ the circuit around sda, scl terminals ] < ?h? voltage > dwn up dwn pup h r r r v v ? ? ? ? ? ?? dwn mos up dwn mos pup l r r r r r v v // // ? ? ? dwn mos r r ?? < ?l? voltage> please set the pull-up resistances to satisfy the calculating formula. v pup [v] : pull-up voltage r up [k ? ] : pull-up resistance r mos [k ? ] : on resistance of nmos in host dwn up r r ?? item rated value unit min. typ. max. pull-down resistance of scl,sda 500 700 900 k ? [ pull-down resistance with ?scl? and ?sda? terminals ] [ i2c communication notice ] scl sda the example of ng scl,sda : ?l? => miss-detecting as ?start condition? no ?ack? serial communication format r dwn is affected lightly because of . . r dwn is affected lightly because of there are pull-down resistances with ?s cl? and ?sda? terminals in this ic. resending the command in the error please resend the command when ack is not returned normally. timing adjust when turning off the pull-up power supply please make ?scl? fall faster than ?sda ? when pull-up power is turned off while voltage is suppli ed to the in terminal. if ?l? signal is input to ?scl? and ?sda? terminals before normal i2c signal, this ic may not accept this i2c signal because of detecting ?start condition?. when the pull-up voltage is turned off during continuing to supply voltage to the in terminal, the ?l? signal may be miss-detected as the start condition. please take measures as follows:
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 35 of 37 4.7k~10kohm typical application circuit richg adaptor usb ctl usup /cen system bat sys th /stat /pok gnd sys sys in scl sda host /sg dp dm thvdd sgref hat1069c usb sw d- d- d- d- d+ d+ d+ d+ d- d+ thvdd 100kohm thermistor (100kohm) ncp15wf104f03rc (murata) 4.7f 4.7f 10f terminal name recommended capacitance in 4.7~10f sys 10f bat 4.7~10f 4.7k~10kohm r2a20056bm set the limit resistances not to beyond the absolute maximum ratings. let ?/pok? and ?/stat? open if not used. let ?sda? and ?scl? connect to gnd if not used. let ?/cen? ,?ctl? and ?usup? fix to ?h? or ?l? if not used. let ?thvdd? open if not used. let ?/sg? open if not used. let ?th? connect to ?thvdd? if not used. set the resistance value with ?charge current setting?. let ?sgref? set to be 0.3v if not used. port is detected by ?dp? and ?dm? terminals. set the port setting as the desired current limit value if not used. usage example) sdp : 20kohm pull-down resistance with ?dp? and ?dm? dcp : connect ?dp? and ?dm? to each other set the resistance value with ?sgref terminal setup?. thvdd sgref 51k ? 9.1k ? nc let ?nc? open.
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 36 of 37 seating plane area 4 0.05 0.05 m s ab area 52 3 4 1 s 25-0.260.03 e s 0.06 b d b a c a unit:mm package dimensions
r2a20056bm apr 15,2013 r03ds0075ej0100 rev. 1.23 page 37 of 37 usage note please do not connect ?sys? terminal to gnd. if ?sys? terminal is connected with gnd in battery connection mode, large currents flow from ?bat? to ?sys? through the body diode in mos-fet between bat and sys. if large current continues to flow, it causes power dissipation in the ic to increase. the ic will then heat up and may damage the ic. the heat may also cause the ic to burn. if the battery completion is detected at ?fulmd?=?1? (adr=02h bit=2), ?full? (adr=03h bit=4) becomes ?1? but charging continues. timer also continues after ?full? becomes ?1?.so charging stops after quick charge timer ends even at ?fulmd?=?1?. timer can be stopped by ?count stop? (adr=01h bit 4~6). trickle timer stops when the battery voltage is below v start . when bat is shorted, this timer also stops. nobat(adr=03h, bit5) indicates detecting the battery voltage below v start . after nobat=?1? by detecting v bat notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2013 renesas electronics corporation. all ri g hts reserved . colo p hon 2.2

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