View PD8875-15_8098780.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
mos integrated circuit pd8875 (5400+5400) pixels 3 color + ( 5400+5400 ) pixels b&w ccd linear image sensor data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. document no. s18949ej1v0ds00 (1st edition) date published september 2007 ns printed in japan 2007 description the pd8875cy-a is a color ccd (charge coupled device) linear image sensor that c hanges optical images to electrical signal. it has 3 rows of (5400 + 5400) staggered color pixels and (5400 + 5400) staggered pixels of black and white , and each row has dual-sided readout type of charge transfer register. and it has reset feed-through level clamp circuits and voltage amplifiers. therefore, it is suitable for 1200 dpi / a4 color image scanners. features ? valid photocell : (5400 + 5400) staggered pixels of rgb + (5400 + 5400) staggered pixels of b&w ? photocell?s size : 5.25 5.75 m (rgb), 5.25 3.2 m (b&w) ? line spacing : 63 m (12 lines) red line - green line, green line - blue line 63 m (12 lines) blue odd line - b&w even line ? color filter : high transmittance new color filter primary colors (red, green and blue), pigm ent filter (with light resistance 107 lx?hour) ? resolution : 48 dot/mm a4 (210 297 mm) size (shorter side) for color and b&w 1200 dpi us letter (8.5? 11?) size (shorter side) for color and b&w ? drive clock level : cmos output under 5 v operation ? data rate : 20 mhz max (rgb), 40 mhz max (b&w at 600 dpi mode) ? power supply : + 12 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package pd8875cy-a ccd linear image sensor 22 pin plastic dip (10.16 mm (400)) remark the pd8875cy-a is a lead-free product.
2 pd8875 data sheet s18949ej1v0ds block diagram 2l clb r s10800 ccd analog shift register d65 d67 tansfer gate d17 . . . d63 s2 s4 photocell (b&w_even) sel2 photocell (red) d63 s1 ccd analog shift registe r s1 tansfer gate ccd analog shift registe r s10799 photocell (b&w_odd) s3 s1 d64 d66 13 tg 1 16 12 14 15 tansfer gate tansfer gate s4 10 1 2 11 gnd 9 8 5 7 s10800 d65 21 tansfer gate ccd analog shift registe r d67 s3 s10799 d64 d66 s4 v out 3 (red, b&w_odd) 1 d17 d18 s3 d18 tansfer gate ccd analog shift registe r v out 2 (green, b&w_odd) 22 d17 s10800 d65 d67 d63 s2 s4 d17 s1 d63 s10800 d65 s10799 d64 d66 ccd analog shift registe r d18 ccd analog shift registe r tansfer gate sel1 tansfer gate photocell (green) s2 s3 d67 d64 d66 s10799 2 1 s2 ccd analog shift registe r photocell (blue) 17 2 ccd analog shift register tansfer gate d18 1l 2 v od2 19 gnd 20 v out 1 (blue, b&w_even) v od1 4 3 photocell (blue) photocell (green) photocell (red) . . . . . . . . . . . . . . . . . . . . .
3 data sheet s18949ej1v0ds pd8875 pin configuration (top view) ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) pd8875cy-a 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 1 clb r 1 nc sel2 gnd v out 3 tg 1 v od 1 2l v out 2 2 2 nc 2 v out 1 gnd v od 2 1l sel1 1 10800 red 1 10800 green 1 10800 blue 1 10800 black & white reset feed-through level clamp clock output signal 3 (red, b&w_odd) reset gate clock no connection color/b&w selecto r shift register clock 1 ground shift register clock 2 output drain voltage 2 last gate shift register clock 1 ground output signal 2 (green, b&w_odd) output signal 1 (blue, b&w_even) no connection shift register clock 1 output drain voltage 1 mode selector shift register clock 2 last gate shift register clock 2 transfer gate clock shift register clock 2 shift register clock 1 caution connect the no connection pins (nc) to gnd.
4 pd8875 data sheet s18949ej1v0ds photocell structure diagram 2.75 m 2.5 m 3.2 m channel stopper aluminum shield 2.75 m 2.5 m 5.75 m channel stopper aluminum shield red, green, blue black & white photocell array structure diagram 63.0 m 63.0 m 52.5 m 5.75 m 4.75 m 5.75 m 52.5 m 10.5 m 10.5 m 5.75 m 4.75 m 5.75 m 5.75 m 4.75 m 5.75 m 31.5 m 63 m 10.5 m blue photocell array blue photocell array green photocell array green photocell array red photocell array red photocell array black & white photocell array black & white photocell array 3.2 m 3.2 m
5 data sheet s18949ej1v0ds pd8875 absolute maximum ratings (t a = +25c) parameter symbol ratings unit output drain voltage v od1 , v od2 ? 0.3 to +15 v shift register clock voltage v 1 , v 2 ? 0.3 to +8 v last gate shift register clock voltage v 1l , v 2l ? 0.3 to +8 v reset gate clock voltage v r ? 0.3 to +8 v reset feed-through level clamp clock voltage v clb ? 0.3 to +8 v mode select signal voltage v sel1 , v sel2 ? 0.3 to +8 v transfer gate clock voltage v tg ? 0.3 to +8 v operating ambient temperature note t a 0 to +55 ? c storage temperature t stg ? 40 to +70 ? c note use at the condition wi thout dew condensation. caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = +25c) parameter symbol min. typ. max. unit output drain voltage v od1 , v od2 11.4 12.0 12.6 v shift register clock high level v 1h , v 2h , v 1lh , v 2lh 4.75 5.0 5.5 v shift register clock low level v 1l , v 2l , v 1ll , v 2ll 0 0 +0.15 v reset gate clock high level v rh 4.75 5.0 5.5 v reset gate clock low level v rl 0 0 +0.15 v reset feed-through level clamp clock high level v clbh 4.75 5.0 5.5 v reset feed-through level clamp clock low level v clbl 0 0 +0.15 v mode select signal high level v sel1h , v sel2h 4.75 5.0 5.5 v mode select signal low level v sel1l , v sel2l 0 0 +0.15 v transfer gate clock high level v tgh 4.75 v 1h note v 1h note v transfer gate clock low level v tgl 0 0 +0.15 v data rate f r ? 2 20 mhz clock pulse frequency f 1 , f 2 ? 1 20 mhz note when transfer gate clock high level (v tgh ) is higher than shift register clock high level (v 1h ), image lag increases.
6 pd8875 data sheet s18949ej1v0ds electrical characteristics t a = +25c, v od = +12 v, data rate (f r ) = 2 mhz, storage time = 5.5 ms, input clock = 5 v p-p light source: 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm)+ ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 2.5 3.0 ? v red se_r ? 0.3 ? lx ? s green se_g ? 0.33 ? lx ? s blue se_b ? 0.6 ? lx ? s saturation exposure b&w se_b&w ? 0.24 ? lx ? s prnu_rgb ? 6.0 20.0 % photo response non-uniformity prnu_b&w v out = 1.0 v ? 10.0 25.0 % average dark signal ads light shielding ? 0.2 2.0 mv dark signal non-uniformity dsnu light shielding ? 1.5 10.0 mv power consumption p w light shielding ? 360 540 mw output impedance z o ? 0.2 0.4 k red r r 7.0 10.0 13.0 v/lx ? s green r g 6.3 9.0 11.7 v/lx ? s blue r b 3.5 5.0 6.5 v/lx ? s response b&w r b&w 8.7 12.3 16.1 v/lx ? s image lag il v out = 1.0 v ? 3.0 7.0 % offset level v os 6.5 7.5 8.5 v output fall delay time note t d v out = 1.0 v ? 15 ? ns total transfer efficiency note tte v out = 1.0 v, data rate = 20 mhz 92 98 ? % register imbalance ri v out = 1.0 v ? 1.0 4.0 % red ? 610 ? nm green ? 535 ? nm blue ? 460 ? nm response peak b&w ? 540 ? nm dr1 v sat /dsnu ? 2000 ? times dynamic range dr2 v sat / cds ? 1363 ? times rftn light shielding ?2000 ?100 500 mv reset feed-through noise prftn light shielding ? 500 800 mv random noise (cds) cds light shielding ? 2.2 ? mv note when the fall time of 1l and 2l (t1, t2) is typical value. (refer to timing chart 2-1 to 2-3 )
7 data sheet s18949ej1v0ds pd8875 input pin capacitance (t a = +25c, v od = +12 v) parameter symbol pin name pin no min. typ. max. unit 5 ? 600 ? pf 9 ? 600 ? pf c 1 1 14 ? 600 ? pf shift register clock pin capacitance 1 c 1 total capacitance ? 1800 ? pf 10 ? 600 ? pf 15 ? 600 ? pf c 2 2 17 ? 600 ? pf shift register clock pin capacitance 2 c 2 total capacitance ? 1800 ? pf last gate shift register clock pin capacitance 1 c 1l 1l 8 ? 10 ? pf last gate shift register clock pin capacitance 2 c 2l 2l 16 ? 10 ? pf reset gate clock pin capacitance c r r 3 ? 10 ? pf reset feed-through level clamp clock pin capacitance c clb clb 4 ? 10 ? pf c sel1 sel1 12 ? 10 ? pf select signal pin capacitance c sel2 sel2 7 ? 10 ? pf transfer gate clock pin capacitance c tg tg 13 ? 300 ? pf remark 1. pins 5, 9, 14 ( 1) and pins 10, 15, 17 ( 2) are each connected in side of the device. 2. c 1 and c 2 show the equivalent capacity of the r eal drive including the capacity of between 1 and 2.
pd8875 data sheet s18949ej1v0ds 8 timing chart 1-1 (color 1200 dpi mode, ( sel1 = ?h?, sel2 = ?h?)) tg 1, ( 1l) 2, ( 2l) r clb (at bit clamp) clb (at line clamp) note not e v out 1 to v out 3 d1 d2 d3 d15 d16 d17 d18 d58 d59 d60 d61 d62 d63 s10798 s10799 s10800 s1 s2 s3 s10797 d64 d65 d66 d67 valid photocell (10800 pixels) invalid photocell (4 pixels) optical black (43 pixels) dummy pixel (16 pixels) invalid photocell (4 pixels) ccd shift register signal note set the r to low level and the clb to high level during this period.
pd8875 data sheet s18949ej1v0ds 9 timing chart 1-2 (color 600 dpi mode, ( sel1 = ?l?, sel2 = ?h?)) v out 1 to v out 3 d1 d3 d63 d13 d57 d59 d61 d19 d15 d17 s2 s4 d67 d65 s10798 s10800 ccd shift register signal valid photocell (5400 pixels) invalid photocell (2 pixels) optical black (22 pixels) dummy pixel (8 pixels) invalid photocell (2 pixels) r tg 1, ( 1l) 2, ( 2l) clb (at bit clamp) clb (at line clamp) note note note set the r to low level and the clb to high level during this period.
pd8875 10 data sheet s18949ej1v0ds timing chart 1-3 (color 300 dpi mode, ( sel1 = ?l?, sel2 = ?h?)) v out 1 to v out 3 r tg 1, ( 1l) 2, ( 2l) clb (at bit clamp) clb (at line clamp) d17+d19 d13+d15 s2+s4 d65+d67 s10798 +s10800 d1+d3 d61+d63 d57+d59 valid photocell (2700 pixels) invalid photocell (1 pixel) optical black (11 pixels) dummy pixel (4 pixels) invalid photocell (1 pixel) ccd shift register signal note note note set the r to low level and the clb to high level during this period.
pd8875 data sheet s18949ej1v0ds 11 timing chart 1-4 (b&w mode, ( sel1 = n/a, sel2 = ?l?)) v out 1 (b&w_even) r tg clb (at bit clamp) 1, ( 1l) 2, ( 2l) v out 2 (b&w_odd) v out 3 (b&w_odd) clb (at line clamp) s5372 d65 s1 s5 d62 s3 d17 d34 d32 d16 d20 d56 d60 s7 d9 d11 d29 d31 d33 d35 d18 d58 d0 d4 d8 d12 d2 d6 d10 d14 d1 d3 d5 d7 d61 d63 s2 s4 s71 s67 s63 s59 s10789 s5368 s5370 s10797 d64 d66 s10791 s10795 s10799 s10800 s61 s57 s65 s69 s5364 s5366 s10793 valid photocell (5400 pixels) valid photocell (2700 pixels) valid photocell (2700 pixels) optical black (11 pixels) invalid photocell (1 pixel) optical black (10 pixels) dummy pixel (4 pixels) dummy pixel (5 pixels) invalid photocell (2 pixels) optical black (22 pixels) dummy pixel (8 pixels) invalid photocell (1 pixel) invalid photocell (1 pixel) ccd shift register signal ccd shift register signal ccd shift register signal note note invalid photocell (1 pixel) invalid photocell (1 pixel) note set the r to low level and the clb to high level during this period.
12 data sheet s18949ej1v0ds pd8875 timing chart 2-1 (color 1200 dpi mode, ( sel1 = ?h?, sel2 = ?h?)) r v out 90% 10% t4 t3 t5 t11 td t6 t8 t7 t9 t10 90% 10% 2 ( 2l) 1 ( 1l) 90% 10% 90% 10% 10% t10 t9 t7 t8 t6 t5 t3 t4 ?h? 10% td t1 t2 t11 clb (at bit clamp) clb (at line clamp) symbol min. typ. max. unit t1, t2 0 25 ? ns t3 10 50 ? ns t4, t5 0 20 ? ns t6 0 70 ? ns t7 15 50 ? ns t8, t9 0 20 ? ns t10 5 45 ? ns t11 10 70 ? ns note typ. is the case of r = 2 mhz
13 data sheet s18949ej1v0ds pd8875 timing chart 2-2 (color 600 dpi mode, ( sel1 = ?l?, sel2 = ?h?) / b&w mode, ( sel1 = n/a, sel2 = ?l?)) r v out t4 t3 t5 t11 td 10% clb (at bit clamp) t6 t8 t7 t9 t10 90% 2 ( 2l) 1 ( 1l) 90% 10% 90% 10% 10% 90% 10% clb (at line clamp) ?h? t1 t2 symbol min. typ. max. unit t1, t2 0 25 ? ns t3 10 50 ? ns t4, t5 0 20 ? ns t6 0 70 ? ns t7 15 50 ? ns t8, t9 0 20 ? ns t10 5 45 ? ns t11 10 70 ? ns note typ. is the case of r = 2 mhz
14 pd8875 data sheet s18949ej1v0ds timing chart 2-3 (color 300 dpi mode, ( sel1 = ?l?, sel2 = ?h?)) r v out clb (at bit clamp) 2 ( 2l) 1 ( 1l) clb (at line clamp) t1 t2 t4 t5 t11 t6 t8 t7 t9 t10 90% 10% 90% 10% ?h? td 10% 10% 90% 90% 10% 10% 90% t3 symbol min. typ. max. unit t1, t2 0 25 ? ns t3 10 50 ? ns t4, t5 0 20 ? ns t6 0 70 ? ns t7 15 50 ? ns t8, t9 0 20 ? ns t10 5 45 ? ns t11 10 70 ? ns note typ. is the case of r = 1 mhz
15 data sheet s18949ej1v0ds pd8875 tg, 1 ( 1l), 2 ( 2l) timing chart 1 ( 1l) tg 90% t16 10% 90% t14 t13 t17 clb (at line clamp) r t18 2 ( 2l) 10% t19 t6 note clb (at bit clamp) t6 t6 t11 t7 t20 t15 symbol min. typ. max. unit t6 0 70 ? ns t7 15 50 ? ns t11 10 50 ? ns t13 5000 10000 50000 ns t14, t15 0 50 ? ns t16, t17 900 1000 ? ns t18, t19 200 400 ? ns t20 10 350 ? ns note set the r to low level and the clb to high level during this period.
16 pd8875 data sheet s18949ej1v0ds 1, 2 cross point 2 1 1.5 v to 3.5 v 4.75 v 0.25 v t25 t26 t27 symbol min. typ. max. unit t25 50 ? ? ns t26, t27 20 ? ? ns 1, 2l cross point 2l 1 2.0 v or more 0.5 v or more 2, 1l cross point 1l 2 2.0 v or more 0.5 v or more
17 pd8875 data sheet s18949ej1v0ds tg, sel timing chart tg sel1 (high low) sel2 (high low) 90% t28 sel1 (low high) sel2 (low high) 90% 10% 10% t29 symbol min. typ. max. unit t28 0 0 ? ns t29 4500 9500 ? ns selection of resolution mode the upd8875cy-a has function of two readout modes, hi gh resolution mode and low resolution mode. these two modes can be selected by sel1 switch. mode description sel1 high resolution mode 1200 dpi (max.) high level low resolution mode 600 dpi (max.) (even line readout mode) low level (1) high resolution mode in this mode, both signals in odd lines and even li nes can be read out. this mode enables 1200 dpi (max.) resolution with a4 size (210 297 mm, shorter side). please refer to timing chart 1-1 and timing chart 2-1 . (2) low resolution mode in this mode, only signal output in even lines can be read out. signal output in even lines: can be read out signal output in odd lines: can not be read out this mode enables 600 dpi (max) resolution with a4 size. to use intermittent reset drive enable si gnal charges of adjacent pixels in ev en line to add at the charge to voltage conversion area. then it can achi eve low resolution with a4 size such as 300, 200, 150 dpi. please refer to timing chart 1-2 , 1-3 and timing chart 2-2 , 2-3 .
18 pd8875 data sheet s18949ej1v0ds definitions of characteristic 1. saturation voltage : v sat output signal voltage at which the response linearity is lost. 2. saturation exposure : se product of intensity of illuminati on (lx) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels w hen the photosensitive su rface is applied with the light of uniform illumination. this is calculated by the following formula. prnu (%) = x 100 x x j : output voltage of valid pixel number j x : maximum of | x j ? x | x = 10800 register dark dc level v out 10800 j=1 x j x x 4. average dark signal : ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. a ds (mv) = d j : dark signal of valid pixel number j 10800 10800 j=1 d j
19 pd8875 data sheet s18949ej1v0ds 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. dsnu (mv) : maximum of | dj ? ads | j = 1 to 10800 dj : dark signal of valid pixel number j register dark dc level a ds dsnu v out 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lx?s). note that the response varies with a li ght source (spectral characteristic). 8. image lag : il the rate between the last output voltage and t he next one after read out the data of a line. v out tg light v out on off v 1 il (%) = v out v 1 100
20 pd8875 data sheet s18949ej1v0ds 9. register imbalance : ri the rate of the difference between the averages of the out put voltage of odd and ev en pixels, against the average output voltage of all the valid pixels. ri (%) = 100 n j=1 v j n 1 n 2 (v 2j ? 1 ? v 2j ) j=1 2 n n : number of valid pixels v j : output voltage of each pixel 10. offset level : vos dc level of output signal is defined as follows. 11. reset feed-through noise : rftn, prftn reset feed-through noise (rftn) and peak of rftn (prftn) are defined as follows. v out rftn ? + v os prftn prftn
21 pd8875 data sheet s18949ej1v0ds 12. random noise (cds) : cds random noise cds is defined as the standard dev iation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). cds is calculated by the following procedure. 1. one valid photocell in one reading is fixed as measurement point. 2. the output level is measured duri ng the reset feed-through period which is averaged over 100 ns to get ?vd i ?. 3. the output level is measur ed during the video output time av eraged over 100 ns to get ?vo i ?. 4. the correlated double sampling output is defined by the following formula. vcds i = vd i ? vo i 5. repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. calculate the standard deviation cds using the following formula equation. cds (mv) = , v = i = 1 100 (vcds i ? v) 2 i = 1 100 vcds i 100 100 1 the following figure shows output wavefo rm (valid photocell under dark condition). reset feed-through video output
22 pd8875 data sheet s18949ej1v0ds standard characteristic curves (1) (reference value) dark output temperature characteristic relative output voltage 0 10 20 30 40 50 0.1 1 4 8 operating ambient temperature t a ( c) storage time output voltage characteristic (t a = +25 c) relative output voltage 1 5 10 0.1 0.2 1 2 storage time (ms) 2 0.25 0.5 total spectral response characteristics (without infrared cut filter and heat absorbing filter) (t a = +25 c) 0 20 40 60 80 100 400 500 600 700 800 wavelength(nm) response ratio(%) b g r b&w response ration (%) wavelength (nm)
23 pd8875 data sheet s18949ej1v0ds application circuit example v out 3 1 2 22 v out 2 v od 2 3 r 4 clb 5 1 6 nc 7 sel2 8 1l 9 1 10 2 11 gnd 21 v od 1 20 v out 1 19 gnd 18 nc 17 2 16 2l 15 2 14 1 13 tg 12 sel1 1 1 1 10800 10800 10800 red green blue b3 b2 b1 a a 47 f +12 v clb 47 47 4.7 r 1 + 2 2 3 2 47 4.7 4.7 1l 1 2 2 2l 2 1 tg sel1 + +5 v 47 f0.1 f + +5 v 47 f 0.1 f + +12 v 47 f 0.1 f a equivalent circuit 4.7 150 47 4.7 4.7 10 150 2 sel2 3 1 10800 black & white caution connect the no connection pins (nc) to gnd. remark the inverters are the 74ac04, and pins 5, 9, 10, 13, 14 and 17 connect two or three inverters in parallel. b1 to b3 equivalent circuit 47 f/25 v + ccd v out 110 1.5 k 2sa1206 +12 v
24 pd8875 data sheet s18949ej1v0ds package drawing ccd linear image sensor 22-pin plastic dip (10.16 mm (400)) pd8875cy-a 44.0 0.3 37.5 1st valid pixel 0.7 0.3 1 9.25 0.3 2.0 0.25 + 0.05 0.7 0.2 10.16 0.2 0.46 0.1 1.02 0.15 2.54 0.25 (5.42) 4.21 0.5 4.39 0.4 2.62 0.2 3 (1.72) 2 name dimensions refractive index plastic cap 42.7 8.35 0.8(0.7 ) 1.5 2 1 distance between the 1st valid pixel and the center of the pin1 distance between the bottom of the package and the surface of the ccd chip distance between the top of the cap and the surface of the ccd chip 3 22c-1ccd-pkg20 (unit : mm) 22 1 11 12 10.16 4 4 5 4 transparent window 5 thickness of the transparent window nec electronics corporation 2007
25 pd8875 data sheet s18949ej1v0ds recommended soldering conditions when soldering this product, it is highly recomm ended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8875cy-a: ccd linear image sensor 22- pin plastic dip (10.16 mm (400)) process conditions partial heating method pin temperature: 380c or bel ow, heat time: 3 seconds or less (per pin). cautions 1. during assembly care should be taken to pr event solder or flux fr om contacting the glass cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method may ha ve deleterious effects on prevention of glass cap soiling and heat resistance. so the method cannot be guaranteed.
26 pd8875 data sheet s18949ej1v0ds notes on handling the packages cleaning the plastic cap dust and dirt protecting mounting of the package operate and storage environments ethyl alcohol methyl alcohol isopropyl alcohol n-methyl pyrrolidone etoh meoh ipa nmp the optical characteristics of the ccd will be degraded if the cap is scratched during cleaning. don?t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. should dirt stick to a plastic cap surface, blow it off with an air blower. for dirt stuck through electricity ionized air is recommended. and if the plastic cap surface is grease stained, clean with our recommended solvents. care should be taken when cleaning the surface to prevent scratches. we recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. excessive pressure should not be applied to the cap during cleaning. if the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. the following are the recommended solvents for cleaning the ccd plastic cap. use of solvents other than these could result in optical or physical degradation in the plastic cap. please consult your sales office when considering an alternative solvent. the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with plastic cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) 1 2 electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m . 4 3 recommended solvents solvents symbol
27 pd8875 data sheet s18949ej1v0ds 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd8875 the information in this document is current as of september, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

▲Up To Search▲

Price & Availability of PD8875-15

	To Download PD8875-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .