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data sheet 2000 mos integrated circuit m pd17p228 description the m pd17p228 is a model of the m pd17228 with a one-time prom instead of an internal mask rom. since the user can write programs to the m pd17p228, it is ideal for experimental production or small-scale production of the m pd17225, 17226, 17227 or 17228 systems. when reading this document, also read the documents related to the m pd17225, 17226, 17227 and 17228. detailed functions are described in the following user's manual. read this manual when designing your system. m pd172 series user's manual: u12795e features ? pin compatible with m pd17225, 17226, 17227 and 17228 (except prom programming function) ? carrier generator circuit for infrared remote controller (rem output) ? 17k architecture: general-purpose register method ? program memory (one-time prom): 16 kbytes (8192 16) ? data memory (ram): 223 4 bits ? pull-up resistor can be connected to reset pin ? low-voltage detection circuit (wdout output) ? supply voltage: v dd = 2.2 to 3.6 v (fx = 4 mhz: high-speed mode, 4 m s) v dd = 3.0 to 3.6 v (fx = 8 mhz: high-speed mode, 2 m s) applications preset remote controllers, toys, and portable systems ordering information part number package m pd17p228mc-5a4 30-pin plastic ssop (7.62 mm (300)) document no. u14542ej1v0ds00 (1st edition) date published april 2000 n cp(k) printed in japan 4-bit single-chip microcontroller for small general-purpose infrared remote controller the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd17p228 2 data sheet u14542ej1v0ds00 gnd : ground ic1, ic2 : internally connected note int : external interrupt request signal input p0a 0 -p0a 3 : input port (cmos input) p0b 0 -p0b 3 : input port (cmos input) p0c 0 -p0c 3 : output port (n-ch open-drain output) p0d 0 -p0d 3 : output port (n-ch open-drain output) p0e 0 -p0e 3 : i/o port (cmos push-pull output) rem : remote controller output (cmos push-pull output) reset : reset input v dd : power supply wdout : hang-up/low voltage detection output (n-ch open-drain output) x in , x out : resonator connection note this pin cannot be used. leave unconnected. pin configuration (top view) 30-pin plastic ssop (7.62 mm (300)) m pd17p228mc-5a4 (1) normal oprating mode p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset wdout ic1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ic2 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0
m pd17p228 3 data sheet u14542ej1v0ds00 caution contents in parantheses indicate how to handle unused pins in prom programming mode. l :connect to gnd via a resistor (470 w ) separately. open:leave unconnected. clk : clock input for prom d 0 - d 7 : data input/output for prom gnd : ground md 0 - md 3 : mode select input for prom v dd : power supply v pp : power supply for prom writing (2) prom programming mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d 2 d 3 v pp (open) v dd (open) clk gnd (l) (open) (open) (open) d 1 d 0 d 7 d 6 d 5 d 4 md 3 md 2 md 1 md 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 (l) (l)
m pd17p228 4 data sheet u14542ej1v0ds00 block diagram p0a 0 p0a 1 p0a 2 p0a 3 p0a p0b 0 (md 0 ) p0b 1 (md 1 ) p0b 2 (md 2 ) p0b 3 (md 3 ) p0b p0c 0 (d 4 ) p0c 1 (d 5 ) p0c 2 (d 6 ) p0c 3 (d 7 ) p0c p0d 0 (d 0 ) p0d 1 (d 1 ) p0d 2 (d 2 ) p0d 3 (d 3 ) p0d p0e 0 p0e 1 p0e 2 p0e 3 p0e rf system reg. alu osc cpu clock reset wdout rem int (v pp ) v dd gnd x in (clk) x out instruction decoder power supply circuit remote control divider 8-bit timer interrupt controller program counter stack (5 levels) ram 223 4 bits one time prom 8192 16 bits basic interval/ watchdog timer remark ( ): during prom programming mode
m pd17p228 5 data sheet u14542ej1v0ds00 contents 1. diffrences among m pd17225, 17226, 17227, 17228 and m pd17p228 .......................... 6 2. pin functions ............................................................................................................... ........... 7 2.1 normal operation mode ....................................................................................................... ............. 7 2.2 prom programming mode ....................................................................................................... ........ 8 2.3 input/output circuits ....................................................................................................... .................. 9 2.4 processing of unused pins ................................................................................................... ........... 10 2.5 notes on using the reset and int pins ....................................................................................... .10 3. writing and verifying one-time prom (program memory) .............................. 11 3.1 operating mode when writing/verifying program memory .......................................................... 11 3.2 program memory writing procedure ............................................................................................ ... 12 3.3 program memory reading procedure ............................................................................................ .13 4. electrical specifications ................................................................................................ 14 5. package drawing ............................................................................................................. .... 21 6. recommended soldering conditions .......................................................................... 22 appendix. development tools ............................................................................................... 23
m pd17p228 6 data sheet u14542ej1v0ds00 1. differences among m pd17225, 17226, 17227, 17228 and m pd17p228 m pd17p228 is equipped with prom to which data can be written by the user instead of the internal mask rom (program memory) of the m pd17228. table 1-1 shows the differences between the m pd17225, 17226, 17227, 17228 and m pd17p228. the differences among these five models are the program memory and mask option, and their cpu functions and internal hardware are identical. therefore, the m pd17p228 can be used to evaluate the program developed for the m pd17225, 17226, 17227, and 17228 system. note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the m pd17p228 are different from those of the m pd17225, 17226, 17227, and 17228. table 1-1. differences among m pd17225, 17226, 17227, 17228 and m pd17p228 product name m pd17p228 m pd17225 m pd17226 m pd17227 m pd17228 item program memory one-time prom mask rom 16 k bytes 4 k bytes 8 k bytes 12 k bytes 16 k bytes (8192 16) (2048 16) (4096 16) (6144 16) (8192 16) (0000h-1fffh) (0000h-07ffh) (0000h-0fffh) (0000h-17ffh) (0000h-1fffh) data memory 223 4 bits 111 4 bits 223 4 bits pull-up resistor of reset pin provided any (mask option) low-voltage detector circuit note provided any (mask option) v pp pin, operation mode select pin provided not provided instruction execution time (t cy )2 m s2 m s (v dd = 2.2 to 3.6 v) (v dd = 3.0 to 3.6 v) 4 m s (v dd = 2.0 to 3.6 v) 4 m s (v dd = 2.2 to 3.6 v) 16 m s (v dd = 2.2 to 3.6 v) operation when p0c, p0d are standby retain output level immediately before standby mode supply voltage v dd = 2.0 to 3.6 v v dd = 2.0 to 3.6 v package 30-pin plastic 28-pin plastic sop (9.53 mm (375)) ssop 28-pin plastic sdip (10.16 mm (400)) (7.62 mm (300)) 30-pin plastic ssop (7.62 mm (300)) note although the circuit configuration is identical, its electrical characteristics differ depending on the product.
m pd17p228 7 data sheet u14542ej1v0ds00 2. pin functions 2.1 normal operation mode pin no. symbol function output format at reset 16 p0a 0 17 p0a 1 18 p0a 2 19 p0a 3 20 p0b 0 21 p0b 1 22 p0b 2 23 p0b 3 24 p0c 0 25 p0c 1 26 p0c 2 27 p0c 3 28 p0d 0 29 p0d 1 1 p0d 2 2 p0d 3 4 p0e 0 5 p0e 1 6 p0e 2 7 p0e 3 8 rem 13 reset 9v dd power supply 12 gnd ground 3 int external interrupt request signal input 14 wdout 11 x in connects ceramic resonator for system clock oscillation 10 x out 15 ic1 these pins cannot be used. 30 ic2 leave open. 4-bit cmos input port with pull-up resistor. can be used for key return input of key matrix. when at least one of these pins goes low, standby function is released. 4-bit input/output port. can be set in input or output mode in 1-bit units. in output mode, this port functions as a high current cmos output port. in input mode, function as cmos input and can be specified to connect pull-up resistor by program. 4-bit n-ch open-drain output port. can be used for key source output of key matrix. 4-bit cmos input port with pull-up resistor. can be used for key return input of key matrix. when at least one of these pins goes low, standby function is released. 4-bit n-ch open-drain output port. can be used for key source output of key matrix. e input e input system reset input. cpu can be reset when low-level signal is input to this pin. while low-level signal is input, oscillator is stopped. this pin connected to pull-up resistor by mask option. output detecting hang-up and drop in supply voltage. this pin outputs at low level either when an overflow occurs in the watch- dog timer, when an overflow/underflow occurs in the stack, or when the supply voltage drops below a specified level. connect this pin to the reset pin. e input ee ee e input outputs transfer signal for infrared remote controller. active-high output. n-ch low-level open-drain output n-ch low-level open-drain output cmos low-level push-pull output e (oscillation stops) cmos push-pull input high- impedance low-level output at low voltage detection n-ch open-drain ee
m pd17p228 8 data sheet u14542ej1v0ds00 2.2 prom programming mode pin no. symbol function output format at reset 3v pp 9v dd 11 clk inputs clock for prom programming. e e 12 gnd ground. e e 20 md 0 ?? 23 md 3 24 d 4 ?? 27 d 7 28 d 0 input/output 8-bit data for prom programming 29 d 1 1d 2 2d 3 power supply for prom programming. apply +12.5 v to this pin as the program voltage when writing/ verifying program memory. input pins used to select operation mode when prom is programmed. power supply. apply +6 v to this pin when writing/verifying program memory. ee ee cmos push-pull input e input remark the other pins are not used in the prom programming mode. how to handle the other opins are described in the section pin configuration (2) prom programming mode .
m pd17p228 9 data sheet u14542ej1v0ds00 2.3 input/output circuits the equivalent input/output circuit for each m pd17p228 pin is shown below. (1) p0a, p0b v dd input buffer (2) p0c, p0d output latch data n-ch (3) p0e (4) reset schmitt trigger input with hysteresis characteristics (5) int input buffer schmitt trigger input with hysteresis characteristics (6) rem data p-ch n-ch v dd output disable (7) wdout data n-ch v dd (mask option) input buffer v dd data data p-ch p-ch n-ch v dd input buffer output disable pull-up register output latch selector
m pd17p228 10 data sheet u14542ej1v0ds00 2.4 processing of unused pins process the unused pins as follows: table 2-1. processing of unused pins pin recommended connection p0a 0 -p0a 3 connect to v dd . p0b 0 -p0b 3 connect to v dd . p0c 0 -p0c 3 connect to gnd. p0d 0 -p0d 3 connect to gnd. p0e 0 -p0e 3 input : individually connect to v dd or gnd via resistor. output : leave open. rem leave open. int connect to gnd. wdout connect to v dd via resistor. ic1, ic2 these pins cannot be used. leave open. 2.5 notes on using the reset and int pins in addition to the functions shown in 2. pin function , the reset pin also has the function of setting a test mode (for ic testing) in which the internal operations of the m pd17p228 are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during normal operation, the m pd17p228 may be set in the test mode if noise exceeding v dd is applied. for example, if the wiring length of the reset or int pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. connect diode with low v f between v dd connect capacitor between v dd and reset/int pin and reset/int pin connect the wdout and reset pins since a low level is output after the test mode is set using the int pin. v dd v dd reset, int v dd v dd reset, int diode with low v f
m pd17p228 11 data sheet u14542ej1v0ds00 3. writing and verifying one-time prom (program memory) the program memory of the m pd17p228 is a one-time prom of 8192 16 bits. to write or verify this one-time prom, the pins shown in table 3-1 are used. note that no address input pin is used. instead, the address is updated by using the clock input from the clk pin. table 3-1. pins used to write/verify program memory pin name function v pp supplies voltage when writing/verifying program memory. apply +12.5 v to this pin. v dd power supply. supply +6 v to this pin when writing/verifying program memory. clk inputs clock to update address when writing/verifying program memory. by inputting pulse four times to clk pin, address of program memory is updated. md 0 -md 3 input to select operation mode when writing/verifying program memory. d 0 -d 7 inputs/outputs 8-bit data when writing/verifying program memory. 3.1 operating mode when writing/verifying program memory the m pd17p228 is set in the program memory write/verify mode when +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin after the m pd17p228 has been in the reset status (v dd = 5 v, reset = 0 v) for a specific time. in this mode, the operating modes shown in table 3-2 can be set by setting the md 0 through md 3 pins. leave all the pins other than those shown in table 3-1 unconnected or connect them to gnd via pull-down resistor (470 w ). (refer to pin connection (2) prom programming mode.) table 3-2. setting operation mode setting of operating mode operating mode v pp v dd md 0 md 1 md 2 md 3 +12.5 v +6 v h l h l program memory address 0 clear mode l h h h write mode l l h h verify mode h h h program inhibit mode : don?t care (l or h)
m pd17p228 12 data sheet u14542ej1v0ds00 3.2 program memory writing procedure the program memory is written at high speed in the following procedure. (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 m s. (4) set the program memory address 0 clear mode by using the mode setting pins. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) write data to the program memory in the 1-ms write mode. (8) set the program inhibit mode. (9) set the verify mode. if the data have been written to the program memory, proceed to (10). if not, repeat steps (7) through (9). (10) additional writing of (number of times of writing in (7) through (9): x) 1 ms. (11) set the program inhibit mode. (12) input a pulse to the clk pin four times to update the program memory address (+1). (13) repeat steps (7) through (12) up to the last address. (14) set the 0 clear mode of the program memory address. (15) change the voltages on the v dd and v pp pins to 5 v. (16) turn off power. the following figure illustrates steps (2) through (12) above. write repeated x time verify additional write address increment md 3 md 2 md 1 md 0 d 0 -d 7 clk gnd v dd v dd v dd +1 gnd v dd v pp v pp reset data input data output data input hi-z hi-z hi-z hi-z
m pd17p228 13 data sheet u14542ej1v0ds00 3.3 program memory reading procedure (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 m s. (4) set the program memory address 0 clear mode by using the mode setting pins. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) set the verify mode. data of each address is output sequentially each time the clock pulse is input to the clk pin four times. (8) set the program inhibit mode. (9) set the program memory address 0 clear mode. (10) change the voltage on the v dd and v pp pins to 5 v. (11) turn off power. the following figure illustrates steps (2) through (9) above. hi-z hi-z "l" md 3 md 2 md 1 md 0 d 0 -d 7 clk gnd v dd v dd v pp v pp reset v dd gnd v dd +1 data output data output
m pd17p228 14 data sheet u14542ej1v0ds00 4. electrical specifications absolute maximum ratings (t a = 25 c) item symbol conditions ratings unit supply voltage v dd e0.3 to +7.0 v prom power supply v pp e0.3 to +13.5 v input voltage v i e0.3 to v dd + 0.3 v output voltage v o e0.3 to v dd + 0.3 v high-level output current note i oh rem pin peak value e36.0 ma rms value e24.0 ma 1 pin (p0e pin) peak value e7.5 ma rms value e5.0 ma total of p0e pins peak value e22.5 ma rms value e15.0 ma low-level output current note i ol 1 pin (p0c, p0d, p0e, peak value 7.5 ma rem or wdout pin) rms value 5.0 ma total of p0c, p0d, peak value 22.5 ma wdout pins rms value 15.0 ma total of p0e pins peak value 30.0 ma rms value 20.0 ma operating temperature t a e40 to +85 c storage temperature t stg e65 to +150 c power dissipation p d t a = 85 c 180 mw note calculate rms value by this expression: [rms value] = [peak value] ? duty caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product.
m pd17p228 15 data sheet u14542ej1v0ds00 recommended operating ranges (t a = e40 to +85 c, v dd = 2.2 to 3.6 v) item symbol conditions min. typ. max. unit supply voltage v dd1 f x = 1 mhz high-speed mode 2.2 3.6 v (instruction execution time: 16 m s) v dd2 f x = 4 mhz ordinary mode (instruction execution time: 4 m s) v dd3 f x = 8 mhz high-speed mode (instruction execution time: 4 m s) v dd4 high-speed mode 3.0 3.6 v (instruction execution time: 2 m s) oscillation frequency f x 1.0 4.0 8.0 mhz operating temperature t a e40 +25 +85 c low-voltage detector circuit note t cy 432 m s note reset if the status of v dd = 2.05 v (typ.) lasts for 1 ms or longer. program hang-up does not occur even if the voltage drops, until the reset function is effected (when the reset pin and wdout pin are connected). some oscillators stop oscillating before the reset function is effected. remark the region indicated by the broken line in the above figure is the guaranteed operating range in the high- speed mode. f x vs v dd supply voltage: v dd (v) 0.4 2 1 3 4 5 6 7 8 9 10 2 0 2.2 3 3.6 4 (normal mode) system clock: f x (mh z ) (mh z ) operation guaranteed area
m pd17p228 16 data sheet u14542ej1v0ds00 system clock oscillator characteristics (t a = e40 to +85 c, v dd = 2.2 to 3.6 v) resonator recommended item conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 4.0 8.0 mhz resonator (f x ) note 1 oscillation after v dd reached min. 4 ms stabilization time note 2 in oscillation voltage range notes 1. the oscillation frequency only indicates the oscillator characteristics. 2. the oscillation stabilization time is necessary for oscillation to be stabilized, after v dd application or stop mode release. caution to use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: keep wiring length as short as possible. do not cross a signal line with some other signal lines. do not route the wiring in the vicinity of lines through which a large current flows. always keep the oscillator capacitor ground at the same potential as gnd. do not ground the capacitor to a ground pattern, through which a large current flows. do not extract signals from the oscillator. external circuit example remark to select a resonator and determine oscillator constants, please evaluate the oscillation yourself or request the resonator manufacturer to evaluate it. x in x out x in x out r1 c2 c1
m pd17p228 17 data sheet u14542ej1v0ds00 dc characteristics (t a = e40 to +85 c, v dd = 2.2 to 3.6 v) item symbol conditions min. typ. max. unit high-level input voltage v ih1 reset, int 0.8v dd v dd v v ih2 p0a, p0b 0.7v dd v dd v v ih3 p0e 0.8v dd v dd v low-level input voltage v il1 reset, int 0 0.2v dd v v il2 p0a, p0b 0 0.3v dd v v il3 p0e 0 0.35v dd v high-level input leakage i lih p0a, p0b, p0e, v ih = v dd 3 m a current reset, int low-level input leakage i lil1 int v il = 0 v e3 m a current i lil2 p0e v il = 0 v w/o pull-up resistor e3 m a high-level output leakage i loh p0c, p0d, p0e, v oh = v dd 3 m a current wdout low-level output leakage i lol p0e, wdout v ol = 0 v w/o pull-up resistor e3 m a current internal pull-up resistor r 1 p0e, reset 25 50 100 k w r 2 p0a, p0b 100 200 400 k w high-level output current i oh1 rem v oh = 1.0 v, v dd = 3 v e6 e13 e24 ma high-level output voltage v oh p0e, rem i oh = e0.5 ma v dd e0.3 v dd v low-level output voltage v ol1 p0c, p0d, rem, i ol = 0.5 ma 0 0.3 v wdout v ol2 p0e i ol = 1.5 ma 0 0.3 v low-voltage detector circuit v dt wdout = low v dt = v dd 2.05 2.2 v level data retention voltage v dddr reset = low level or stop mode 1.3 3.6 v supply current i dd1 operating mode v dd = 3 v 10% f x = 1 mhz 0.55 1.1 ma (high-speed) f x = 4 mhz 1.0 2.0 ma f x = 8 mhz 1.3 2.6 ma i dd2 operating mode v dd = 3 v 10% f x = 1 mhz 0.5 1.0 ma (low-speed) f x = 4 mhz 0.75 1.5 ma f x = 8 mhz 0.9 1.8 ma i dd3 halt mode v dd = 3 v 10% f x = 1 mhz 0.4 0.8 ma f x = 4 mhz 0.5 1.0 ma f x = 8 mhz 0.6 1.2 ma i dd4 stop mode v dd = 3 v 10% 2.0 20.0 m a built-in poc t a = 25 c 2.0 5.0 m a
m pd17p228 18 data sheet u14542ej1v0ds00 ac characteristics (t a = e40 to +85 c, v dd = 2.2 to 3.6 v) item symbol conditions min. typ. max. unit cpu clock cycle time note t cy1 3.8 33 m s (instruction execution time) t cy2 v dd = 3.0 to 3.6 v 1.9 33 m s int high/low level width t inth, t intl 20 m s reset low level lwidth t rsl 10 m s note the cpu clock cycle time (instruction execution time) is determined by the oscillation frequency of the reso- nator connected and sysck (rf: address 02h) of the register file. the figure on the right shows the cpu clock cycle time t cy vs. supply voltage v dd characteristics. t cy vs v dd supply voltage v dd (v) 2 1 3 4 5 6 7 8 9 10 33 40 2 01 3 4 cpu clock cycle time tc y ( m s) 3.8 1.9 2.2 3.6 operation guaranteed area
m pd17p228 19 data sheet u14542ej1v0ds00 dc programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol test conditions min. typ. max. unit high-level input voltage v ih1 other than clk 0.7 v dd v dd v v ih2 clk v dd e0.5 v dd v low-level input voltage v il1 other than clk 0 0.3 v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = e1 ma v dd e1.0 v low-level output voltage v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md 0 = v il , md 1 = v ih 30 ma cautions 1. keep v pp to within +13.5 v including overshoot. 2. apply v dd before v pp and turns it off after v pp . ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol test conditions min. typ. max. unit address setup time note (vs. md 0 )t as 2 m s md 1 setup time (vs. md 0 )t m1s 2 m s data setup time (vs. md 0 )t ds 2 m s address hold time note (vs. md 0 - )t ah 2 m s data hold time (vs. md 0 - )t dh 2 m s md 0 -? data output float delay time t df 0 130 ns v pp setup time (vs. md 3 - )t vps 2 m s v dd setup time (vs. md 3 - )t vds 2 m s initial program pulse width t pw 0.95 1.0 1.05 ms additional program pulse width t opw 0.95 21.0 ms md 0 setup time (vs. md 1 - )t mos 2 m s md 0 ? data output delay time t dv md0 = md1 = v il 1 m s md 1 hold time (vs. md 0 - )t m1h t m1h +t m1r 3 50 m s2 m s md 1 recovery time (vs. md 0 )t m1r 2 m s program counter reset time t pcr 10 m s clk input high-, low-level width t xh , t xl 0.125 m s clk input frequency f x 4.19 mhz initial mode set time t i 2 m s md 3 setup time (vs. md 1 - )t m3s 2 m s md 3 hold time (vs. md 1 )t m3h 2 m s md 3 setup time (vs. md 0 )t m3sr when program memory is read 2 m s address note ? data output delay time t dad when program memory is read 2 m s address note ? data output hold time t had when program memory is read 0 130 ns md 3 hold time (vs. md 0 - )t m3hr when program memory is read 2 m s md 3 ? data output float delay time t dfr when program memory is read 2 m s reset setup time t res 10 m s notes the internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks compreise one cycle. the internal clock is not connected to a pin.
m pd17p228 20 data sheet u14542ej1v0ds00 program memory write timing program memory read timing v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d 0 -d 7 md 0 md 1 md 2 md 3 t res t vps t vds t xh t xl t as t ah t dh t ds t opw t df t dv t mos t m1r t dh t ds t pw t i t m3h t m1h t m1s t pcr t m3s data input data output data input data input hi-z data output data output t m3sr t pcr t dv t i t xl t dad t had t vds t vps t xh t m3hr t dfr v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d 0 -d 7 md 0 md 1 "l" md 2 md 3 t res
m pd17p228 21 data sheet u14542ej1v0ds00 5. package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 - 0.07 1.0 0.2 3 + 5 - 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
m pd17p228 22 data sheet u14542ej1v0ds00 6. recommended soldering conditions for the m pd17p228 soldering must be performed under the following conditions. for details of recommended conditions for surface mounting, refer to information document "semiconductor device mounting technology manual" (c10535e) . for other soldering methods, please consult with nec personnel. table 6-1. soldering conditions of surface mount type m pd17p228mc-5a4: 30-pin plastic ssop (7.62 mm(300)) soldering method soldering conditions symbol infrated reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-103-2 number of times: 2 max. number of days: 3 (after that, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-103-2 number of times: 2 max. number of days: 3 (after that, prebaking is necessary at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max, time: 10 seconds max., number of times: ws-60-103-1 once, preheating temperature: 120 c max. (package surface temperature) number of days: 3 (after that, prebaking is necessary at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) ? note number of days in storage after the dry pack has been opened. the storage conditions are at 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except the partial heating method).
m pd17p228 23 data sheet u14542ej1v0ds00 appendix. development tools to develop the programs for the m pd17p228 subseries, the following development tools are available: hardware name remarks ie-17k and ie-17k-et are the in-circuit emulators used in common with the 17k series microcontroller. ie-17k and ie-17k-et are connected to a pc-9800 series or ibm pc/at tm compatible machines as the host machine with rs-232c. by using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. a higher level debugging environment can be provided by using man-machine interface simplehost tm . se board this is an se board for m pd17225 subseries. it can be used alone to evaluate a system (se-17225) or in combination with an in-circuit emulator for debugging. emulation probe ep-17k30gs is an emulation probe for 17k series 30-pin ssop (mc-5a4). when used (ep-17k30gs) with ev-9500gt-30 note 2 , it connects an se board to the target system. conversion adapter the ev-9500gt-30 is a conversion adapter for the 30-pin ssop (mc-5a4). it is used to (ev-9500gt-30 note 2 ) connect the ep-17k30gs and target system. prom programmer af-9706, af-9708, and af-9709 are prom programmers corresponding to m pd17p228. (af-9706 note 3 , af-9708 note 3 , by connecting program adapter pa-17p236 to this prom programmer, m pd17p228 can be af-9709 note 3 ) programmed. program adapter pa-17p236 are adapters that is used to program m pd17p228, and is used in combination (pa-17p236) with af-9706, af-9708, or af-9709. notes 1. low-cost model: external power supply type 2. two ev-9500gt-30 are supplied with the ep-17k30gs. five ev-9500gt-30s are optionally available as a set. 3. these are products from ando electric co., ltd. for details, consult ando electric co., ltd. (tel: 03- 3733-1166). in-circuit emulator ie-17k, ie-17k-et note 1
m pd17p228 24 data sheet u14542ej1v0ds00 software name outline host machine os supply order code 17k assembler pc-9800 japanese windows tm 3.5" 2hd m saa13ra17k (ra17k) series ibm pc/at japanese windows 3.5" 2hc m sab13ra17k compatible machine english windows m sbb13ra17k device file pc-9800 japanese windows 3.5" 2hd m saa13as17225 (as17225) series ibm pc/at japanese windows 3.5" 2hc m sab13as17225 compatible machine english windows m sbb13as17225 support pc-9800 japanese windows 3.5" 2hd m saa13id17k software series ( simplehost ) ibm pc/at japanese windows 3.5" 2hc m sab13id17k compatible machine english windows m sbb13id17k the ra17k is an assembler com- mon to the 17k series products. when developing the program of devices, ra17k is used in combi- nation with a device file (as17225). the as17225 is a device file for m pd17225, 17226, 17227, and 17228 and is used in combination with an assembler for the 17k series (ra17k). simplehost is a software pack- age that enables man-machine in- terface on the windows when a pro- gram is developed by using an in- circuit emulator and a personal com- puter.
m pd17p228 25 data sheet u14542ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd17p228 26 data sheet u14542ej1v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd17p228 27 data sheet u14542ej1v0ds00 [memo]
m pd17p228 simplehost is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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