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in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. 1 description the IR3Y48M is a cmos single-chip signal processing ic for ccd area sensors which includes correlated double sampling circuit (cds), clamp circuit, automatic gain control amplifier (agc), reference voltage generator, black level detection circuit, 20 mhz 10-bit analog-to-digital converter (adc), timing circuit for internally required pulses, and serial interface for internal circuits. features low power consumption : 110 mw (typ.) at 20 mhz mode wide agc range : 0 to 36 db (gain step : 0.094 db/step) high speed sample-and-hold circuits : pulse width 10 ns (min.) power save operation : 84 mw (typ.) at 15 mhz mode standby mode : less than 0.3 mw built-in serial interface 10-bit adc operating up to 20 mhz e non-linearity dnl : 0.6 lsb (typ.) inl : 1.5 lsb (typ.) maximum input level of ccd signals : 1.1 vp-p accepts a direct signal input to adc or agc (input level : 1 vp-p (typ.)) single +3 v power supply package : 48-pin qfp (qfp048-p-0707) 0.5 mm pin-pitch pin connections IR3Y48M ccd signal process & digital interface ic IR3Y48M 1 48 47 46 45 44 43 42 41 40 39 37 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 nc av dd4 nc v rn v rp av dd2 av dd2 av ss2 av ss2 v com ccdin refin op resetn av dd3 av ss3 stbyn csn sdata sck obp ccdclp blk adclp clpcap adin obcap monout nc aiset av dd1 av ss1 nc adck shr shd do 9 do 8 do 7 do 6 do 5 dv dd dv ss do 4 do 3 do 2 do 1 do 0 38 48-pin qfp top view (qfp048-p-0707)
IR3Y48M 2 block diagram 13 12 ccd adin adclp ccdclp 6 db/step (0 to 12 db) s/h obcap aiset adck 11 14 15 18 22 26 28 27 25 31 29 30 36 35 32 blk obp ccdclp timing generator serial register register (7-bit) compare 10-bit adc obp 0.094 db/step (0 to 6 db) 6 db/step (0 to 18 db) agc rough agc fine dac adclp csn sck sdata op resetn stbyn 42 43 33 20 2 34 19 4 10 5 6,7 8,9 dv ss dv dd av ss3 av ss2 av ss1 av dd4 av dd3 av dd2 av dd1 v rn v com bandgap v ref v rp do 0 to do 9 37 to 41, 44 to 48 monout 16 shd 24 shr clpcap dc refin ccdin clamp clpcap 23 cds +
IR3Y48M 3 pin description 1nc e no connection. pin no. symbol i/o equivalent circuit description supply of 2.7 to 3.6 v analog power. e av dd4 2 3 nc e no connection. v dd gnd adc internal negative reference voltage. (connect to av ss via 0.1 f.) o v rn 4 supply of 2.7 to 3.6 v analog power. e av dd2 6 5 v rp o 9 av ss2 e an analog grounding pin. 8 av ss2 e an analog grounding pin. 7 av dd2 e supply of 2.7 to 3.6 v analog power. adc internal common reference voltage. (connect to av ss via 0.1 f.) o v com 10 11 ccdin i cds circuit data input. i refin 12 adc internal positive reference voltage. (connect to av ss via 0.1 f.) cds circuit reference input. v dd gnd 10 v dd gnd clamp level output. (connect to av ss via 0.1 f.) o clpcap 13 14 15 16 internal gate adin obcap monout i o o adin signal input. black level integration voltage. (connect to av ss via 0.033 f.) monitor output of cds or agc. v dd gnd
4 IR3Y48M pin no. symbol i/o equivalent circuit description e nc 17 no connection. internal analog circuit bias input. (connect to av ss via 4.7 k$.) 18 aiset i no connection. 21 nc e an analog grounding pin. 33 av ss3 e an analog grounding pin. 20 av ss1 e supply of 2.7 to 3.6 v analog power. 19 av dd1 e i adck 22 adc sampling clock input. reference sampling pulse input. data sampling pulse input. clamp and black calibration control for adin signal. blanking pulse input. clamp control input. black level period pulse input. serial port clock input. serial port data input. serial port chip selection (active at low). standby control (standby at low). 23 24 25 26 27 28 29 30 31 32 shr shd adclp blk ccdclp obp sck sdata csn stbyn i i i i i i i i i i e av dd3 34 supply of 2.7 to 3.6 v analog power. v dd gnd 18 v dd gnd internal gate serial i/f operation code enable pin (active at low). 36 op i reset signal input (reset at low). 35 resetn i v dd gnd
IR3Y48M 5 pin no. symbol i/o equivalent circuit description o do 0 37 adc digital output (lsb). (capable of high-z) v dd gnd 41 do 4 o adc digital output. (capable of high-z) 40 do 3 o adc digital output. (capable of high-z) 39 do 2 o adc digital output. (capable of high-z) 38 do 1 o adc digital output. (capable of high-z) 43 dv dd e digital output driver power supply. (2.7 to 3.6 v) 42 dv ss e digital output driver gnd. a digital grounding pin. adc digital output (msb). (capable of high-z) o do 9 48 adc digital output. (capable of high-z) o do 8 47 adc digital output. (capable of high-z) o do 7 46 adc digital output. (capable of high-z) o do 6 45 adc digital output. (capable of high-z) o do 5 44 v dd gnd notes : nc pins are recommended to be connected to av ss on pcb even they are not connected electrically in the chip. high-z at standby.
IR3Y48M 6 functional description outline the configuration of IR3Y48M is described below. shr shd monout v ref clamp cds refin ccdin adin adck blk obp ccdclp adclp csn sdata sck ccd agc do 0 todo 9 black control serial register timing generator IR3Y48M + 10-bit adc ccd ob effective pixel (ob) blanking adck blk obp ccdclp data output black code do 0 -do 9 general timing
7 IR3Y48M reference clock (shr) data clock (shd) refin ccdin ccd cds cds output = v (cds) = v (dat) e v (prec) reset pulse reset pulse v (prec) v (dat) max. level shr shr shd shd sig f smax = 20 mhz / t smin = 50 ns sig v (cds) cds operation cds circuit cds circuit holds ccd precharge (reference) level at shr pulse, then it samples ccd pixel data at shd pulse. correlated (common) noise is removed by subtraction of precharge level from pixel data level. cds has the gain of maximum 12 db (6 db/step). this gain is a part of total gain and it is controlled by register value similar to gain in agc circuit. connect signal from ccd sensor to ccdin pin through c-coupling. place the same capacitor between refin and av ss .
8 IR3Y48M clamp circuit dc clamp dc level of the analog input is fixed by internal dc clamp circuit. dc level of c-coupled ccd signal at cds input is set to clpcap by dc clamping. normally clamp switch is turned on at black level calibration period. place 0.1 f external capacitance between clpcap and av ss . timing control (register conditions) refin ccdin shr shd ccdclp clamp source clpcap dc clamp function (ccdclp) clpcap ccdclp adck ccd clpcap level refin, ccdin clamp level clamp timing clamp of adin signal clamp operation for adin path is also available. note that clamp voltage [clpcap] is different between ccd input and adin. adclp signal is used for both clamp and black level control at adin input mode. it is also possible to turn off clamp operation by register setting. clamp control following items are selectable through register setting. a) clamp current normal or fast clamp is selectable for charge current. (select normal clamp in general) b) clamp target input signal (refin and ccdin) to be clamped is selectable. it is also possible to turn off the clamp function. adclp adin to agc or to adc timing control clpcap (adclp) adin dc clamp function
9 IR3Y48M cds refin s/h ccdin adin (path for adin) adclp adclp obp obp compare register (7-bit) obcap rough fine do 0 - do 9 agc agc + dac 10-bit adc black level calibration ccd adck obp obcap previous black level blanking blanking effective pixel signal effective pixel signal optical black period resulting black calibration level (hold) black level calibration timing black level cancel circuit the purpose of black level cancel is to adjust the agc input level which can equalize the adc output code to black level code written in the register. the black level cancelling is generally done during ob (optical black period) pulsed by obp pulse. the register value ((1 to) 16 to 127 lsb : default 64 lsb) is written by serial interface. black level cancel loop is established while obp is low (when pulse is not inverted). in this loop, adc output code is compared with register setting. during ob period, the obp voltage gradually terminates into certain voltage resulting the output code equal to the register setting. the obp voltage is discharged under following status : q set black level reset register to 1 w set reset pin low e power down (by stbyn or register control) the period to reach the final value depends on the status of chip. it may take more than one thousand pixels at start-up or after reset. it may take only several pixels when the status is not changed. dc clamp [ccdclp] is allowed during obp low. black level cancelling for adin signal (broken line in the chart) is controlled by adclp pulse (clamp and ob control are done simultaneously) instead of obp.
10 IR3Y48M gain control circuit the total gain for ccd input signal covers from 0 to 36 db. this range consists of cds (0 to 12 db (6 db/ step)), agc rough (0 to 18 db (6 db/step)), and agc fine (0 to 6 db (0.094 db/step)). total gain is controlled (as described below) by 9-bit gain control register. the gain is fixed to maximum gain when the code exceeds 382 (decimal). the gain of adin (which bypassing cds) is 0 to 24 db. 0d 0 db 35.91 db 0.094 db 1 step 383d cds 6 db/step (0 to 12 db) rough 6 db/step (0 to 18 db) agc block fine 0.094 db/step (0 to 6 db) total gain = 0 to 35.91 db gain control
a/d converter circuit IR3Y48M integrates 20 mhz 10-bit full pipeline a/d converter (adc). a/d conversion range the analog input range of the adc is determined by v ref circuit integrated in IR3Y48M. at adc direct input (adin) mode (mode (1) register d 5 = 1), feed 1 vp-p (full scale) signal based on clamp level as zero reference into adin input pin. a/d converter output code (at mode (1) register d 5 = 1) the digital output format is binary. thus, "all zero" digital output with zero reference input (adin = clpcap), "all one" digital output with full-scale input (adin = clpcap + 1 v (typ.)). clock, pipeline delay and output digital data timing the a/d conversion is performed based on the clock fed to adck pin. the track-and-hold operation is completed at falling (when not inverted) edge of adck. the 10-bit width parallel data is obtained at rising edge after 5.5 clock pipeline delay. (sampling edge is selectable by register setting.) code at clamp level (at mode (1) register d 5 = 0, d 4 = 1) the output code at clamp level can be set throughout (1 to) 16 to 127 lsb at the step of 1 lsb by register setting. adc output code logic adc digital output is high-z under following conditions : q set adc output register to 1 w set sybyn pin low e power down (by stbyn or register control) digital output code according to adin, digital codes are determined as follows : data output at straight binary [mode (1) register d 2 = 0, d 5 = 1] 11 IR3Y48M msb adin digital code lsb d 9 clamp reference 0 : :0 :1 : clamp reference + 1 v 11 0 1 0 d 0 1 0 1 0 d 1 1 0 1 0 d 2 1 0 1 0 d 3 1 0 1 0 d 4 1 : 0 1 : 0 d 5 1 0 1 0 d 6 1 0 1 0 d 7 1 0 1 0 d 8
12 IR3Y48M other functions adc direct input (adin mode) direct input path to adc or agc is realized by register setting. this direct path can be turned off by register. black level cancel and clamp are performed at the same timing of adclp low. these controls can be masked by register setting. blk, shr, and shd controls are ignored at adin mode. the signal at agc input is shown below. operation at adc direct input is shown below. the zero reference (clpcap) is established by adclp pulse. the adin input range is from clpcap + 1 v (typ.) (full scale). adin (n) n e 8 n e 7 n e 6 n e 5 n e 4 n e 3 n e 2 n e 1 n (n+1) (n+2) adck (when adck is inverted, signal (n) is sampled by this edge) adclp black cancel & clamp do 0 -do 9 adin signal processing (agc input) note : for adclp low, both black level cancel and clamp are active at agc input mode, and only clamp is active at adc input mode. clamp on full scale clpcap + 1 v adc dynamic range = 1 vp-p clpcap adin adclp adin signal input level standby mode the standby mode can be set either by register setting or stbyn pin. if one of the above is set, IR3Y48M powers down. ("or" logic)
13 IR3Y48M monitor output by setting the register, the signal from monout is selectable. alternatives are off, cds output, agc output, or refin/ccdin output. even at the cds gain is set to a certain gain, the cds output on monout is multiplied by 1/gain resulting the level before cds amplification. the output level of monout is shown below. the monout level is v com (1.1 v, typ.) at zero reference level. for the maximum amplitude (1.1 vp-p), the output level is 2.2 v (typ.). caution : v com pin does not have enough driving capabilities. polarity inversion following timing pulse of IR3Y48M control can be inverted by register setting : q adck (a/d converter sampling pulse) w shr, shd (cds sampling clock) e blk, obp, ccdclp, adclp (enable controls) power save power save mode is selectable for the sampling frequency below 15 mhz. the power consumption at this mode is lower than 20 mhz mode. general notice for power supply it is recommended to supply both av dd and dv dd supply from single regulator. (observe absolute maximum rating specification : dv dd 2 (av dd + 0.3 v) even at the power-up and power-down sequence.) refer to " application circuit example " against noise of power supply. ccd monout v 0 = no signal v 0 = no signal level mon reference level = v com = 1.1 v (typ.) v 1 v 2 max. signal = 1.1 v max. level = v com + 1.1 v = 2.2 v v 3 v 1 v 2 v 3 monitor output level
14 IR3Y48M serial interface circuit the internal registers of IR3Y48M are controlled through 3-wire serial interface. the 16-bit length control data consists of 2-bit operation code, 4-bit address, and 10-bit data. the controller should set each bit synchronizing to sck falling since IR3Y48M (receiver) acquire data at sck rising edge. the data is valid while csn is low. the written data comes effective at rising edge of csn. fix csn to high when no access is conducted. it is forbidden to write data to the address that is not listed. always give 16 times sck rising during csn low. all data are ignored when sck rising during csn low is less than 16. the effect of operation code is determined by op pin control. when op pin is high, the data are always valid regardless of o 0 and o 1 . when op pin is low, operation code control is active, and the data is written only when both o 0 = 0 and o 1 = 1 are true. 0 1 2 3 4 5 6 7 8 9 101112131415 csn sck sdata ope code address data o 0 o 1 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 serial write control
15 IR3Y48M registers IR3Y48M has 10-bit x 5 registers to control its operations. all registers are write only. the serial registers are written by serial interface. register map 1. reference name mode (1) 2. register address [write] 3. register bit assignment a 3 r/w address reference name major functions [data] a 2 a 1 a 0 0 0 1 test mode (adin coupling mode) test register 0 w 1 1 0 adc code at black level (1 lsb step) black level 0 w 0 1 0 total gain gain 0 w 1 0 0 clamp current/adin clamp/clamp target/s/h, enable logic/monitor selection mode (2) 0 w 0 0 0 adck polarity/adin connection/frequency mode/adc output/black level reset/standby mode (1) 0 w a 3 a 2 a 1 a 0 0 0 0 0 d 9 black level reset adc output frequency mode adin connection adck polarity x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 x d 7 x d 8 standby x : don't care <-> <-> <-> <----> <-> functions <-> default
16 IR3Y48M 4. register operations standby black level reset adc output frequency mode adin connection 0 0 0 0 0 0 0 adin function off 20 mhz mode normal operation [adc data output] normal operation normal operation normal operation as timing chart controls operations note d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 adck polarity adck clock inversion 1 adin signal to agc adin signal to adc 1 x 0 1 15 mhz mode 1 1 adc output high-z [or logic of stbyn] 1 2 black level reset [or logic of resetn] 1 standby [or logic of stbyn] 1 notes : x : don't care 1. adc output is set to high impedance if one of following case is true. case 1 : set "adc output" bit to "1". case 2 : set stbyn pin to low. case 3 : set "standby" bit to "1". 2. black level integral cap [obcap] is discharged if following case is true. case 1 : set "black level reset" to "1". case 2 : set resetn pin to low.
IR3Y48M 17 1. reference name mode (2) 2. register address [write] 3. register bit assignment 4. register operations a 3 a 2 a 1 a 0 1 0 0 0 d 9 monitor selection x : don't care s/h, enable logic clamp target adin clamp clamp current x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 0 d 7 x d 8 <----> <----> <----> <-> <-> functions default monitor selection s/h, enable logic clamp target adin clamp 0 00 10 0 0 clamp operation active for adin normal mode [clamp both refin & ccdin] clamp ccdin only normal operation as timing chart normal clamp 0 controls operations d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 clamp current fast clamp 1 no clamp for adin 1 1 clamp refin only 0 clamp off 1 1 s/h control polarity inversion 1 0 1 0 agc output monitor 0 1 cds signal to monitor 0 0 monitor off 1 1 both of s/h and enable inversion 1 0 enable control polarity inversion output refin and ccdin (for calibration) 1 1 note 1 2 3 4 notes : 1. the s/h signals are shr and shd. 2. the enable controls are blk, obp, ccdclp, and adclp. 3. at this mode, monitor output gain = 0 db regardless of cds gain. 4. at this mode, monitor output depends on cds gain.
18 IR3Y48M 1. reference name gain 2. register address [write] 3. register bit assignment 4. register operations x : don't care a 3 a 2 a 1 a 0 0 1 0 0 d 9 total gain x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 0 d 7 0 d 8 <-------------------------------------> functions default controls decimal note 0 total gain (for ccdin input) d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 0 0 0 0 0 0 0.000 hex total gain (db) 0.094 0.188 0.281 0.375 5.813 5.906 6.000 6.094 12.000 18.000 24.000 30.000 35.625 35.719 35.813 35.906 35.906 35.906 1 2 3 4 3e 3f 40 41 80 c0 100 140 17c 17d 17e 17f 180 1ff 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 3 4 62 63 64 65 128 192 256 320 380 381 382 383 384 511 1 00
19 IR3Y48M notes : 1. gain is always (35.90625 db, typ.) for code greater than 382 (decimal). 2. gain is always (23.906 db, typ.) for code greater than 254 (decimal). 1 1 1 12 1 0 010000 65 0 41 6.094 0 0 100000 128 0 80 12.000 0 0 110000 192 0 c0 18.000 0 0 010000 64 0 40 6.000 1 1 001111 63 0 3f 5.906 0 1 001111 62 0 3e 5.813 1 0 0 000001 4 0 4 0.375 1 1 000000 3 0 3 0.281 0 1 000000 2 0 2 0.188 1 0 000000 1 0 1 0.094 0 0 000000 0 0 0 0.000 controls decimal d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 total gain (for agc input) note hex total gain (db) 23.813 fe 0 254 1 1 1 1 1 110 1 1 111111 511 1 1ff 23.906 0 1 000000 258 1 102 23.906 1 0 000000 257 1 101 23.906 0 0 000000 256 1 100 23.906 1 1 111111 255 0 ff 23.906
20 IR3Y48M note : 1. codes 1 to 15 are available but not recommended black calibration period is specified under 15 < code < 128. 1. reference name black level 2. register address [write] a 3 a 2 a 1 a 0 1 1 0 0 3. register bit assignment 4. register operations d 9 black level x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 1 d 6 x d 7 x d 8 functions default <-----------------------------> x : don't care 0 0 01000 32 20 0 0 10000 64 40 0 0 11111 124 7c 1 1 00100 19 13 0 1 00100 18 12 1 0 0 0 17 11 0 0 00100 16 10 1 1 00011 15 f 1 11 1 0 00000 1 1 1 0 0 0 0 0 0 0 forbidden forbidden operations [adc code : binary] decimal b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 9 black level note hex 7e 126 1 1 1 1 110 1 1 11111 127 7f 1 1 1 1 0 11111 125 7d 1 0 0
IR3Y48M 21 1. reference name test register 2. register address [write] a 3 a 2 a 1 a 0 0 0 1 0 3. register bit assignment d 9 adin test mode x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 x d 7 x d 8 functions default <-> 4. register operations test register (d 6 ) is prepared for adin ac coupled input. using this mode the signal center is set to v com . no clamp signals are required at this mode. connect c-coupled output to adin. the resistance 50 k$ between adin (14 pin) and clpcap (13 pin) stabilize the dc level at adin pin. 0 normal operation controls operations d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 adin test mode v com centered adin for ac coupling 1 x : don't care note : d 5 to d 0 must always be "0".
22 IR3Y48M absolute maximum ratings (av ss = dv ss = 0 v, all voltages are with respect to gnd.) recommended operating conditions (av ss = dv ss = 0 v, all voltages are with respect to gnd.) parameter symbol conditions unit power supply voltage av dd v e0.3 to +4.5 rating dv dd e0.3 to +4.5 or av dd + 0.3 v ma 10 except ps i in 0.3 v dv dd e av dd v dlt voltage difference analog input voltage v ina v av ss e 0.3 to av dd + 0.3 av ss e 0.3 to av dd + 0.3 v v inl digital input voltage (input pin) v digital input voltage (output pin) av ss e 0.3 to av dd + 0.3 ?c v onl operating temperature ?c t opr storage temperature t stg e40 to +125 e30 to +85 2 1 note parameter symbol conditions typ. supply voltage at start-up, turn on av dd before (or at the same time as) turning on dv dd . 3.0 2.7 min. v unit 3.6 max. av dd analog digital output dv dd av dd v 2.7 3.0 notes : 1. the higher voltage of 4.5 v and av dd + 0.3 v specifies maximum value of dv dd absolute maximum rating. 2. the v onl limits the excess voltage applied to digital output pins. warning : operation at or beyond these limits may result in permanent damage to the device. normal operating specifications are not guaranteed at these extremes. input current electrical characteristics supply current (t a = +25 ?c, av dd = dv dd = 3.0 v) notes : 1. specified under monitor function off. 2. measured under no analog input and clock fixed at low. parameter symbol conditions typ. supply current at normal operation 28 min. ma unit 34 max. i a15 analog digital i d15 6ma 3 i d20 digital i a20 analog fs = 15 mhz (at 15 mhz mode) fs = 20 mhz (at 20 mhz mode) 3.5 ma 7 36 ma 44 note 1 supply current at monitor active i pe (at 20 mhz mode) 46 ma 38 ma 0.1 2 i pd supply current at power down
notes : 1. normally : signal path through cds / agc / adc in this case analog input range is downward from clamp voltage. adin : signal bypassing cds (direct agc or adc input) in this case analog input range is upward from clamp voltage. 2. specified at monout pin. the noise bandwidth is 100 khz to 5 mhz. 3. bandwidth from ccdin/refin to adc. the bandwidth is specified as the settling time of adc output for step input (full scale e 1 db) response (at gain = min.). 4. black calibration period is the period of stabilization of output code within 1 lsb (average) compared to register value for the black level code of 0 to 50% of the full scale input. (assuming external capacitance = 0.033 f.) external capacitor value to obcap pin determines the bandwidth of the black level cancel loop. since the gain of the loop depends on sampling frequency, the maximum frequency (settling within certain pixels) and the minimum frequency (avoiding oscillation of the circuit) are defined. 5. select the external capacitor referring the following list based on the minimum and maximum operating frequencies. if the black level settling specification (within 2 000 pixels) could be ignored, the maximum sampling frequency for 0.1 f and 0.33 f will extend according to the increment. IR3Y48M 23 analog specifications (unless otherwise specified, av dd = dv dd = 3.0 v, t a = +25 ?c, signal frequency f in = 1 mhz, signal level = e1 db (full scale)) the current direction flowing into the pin is positive direction. cds & clamp circuits (sampling frequency f s = 20 mhz) parameter symbol conditions typ. min. unit max. note analog input range v icds normally vp-p 1.1 100 v rms 1 at fs = 20 mhz ni input referred noise v iai at adin at gain = max. at gain = min. 1.1 400 vp-p v rms input capacitance c in ccdin, adin & refin pf 15 cbw 1 pixel 3 2 input bandwidth clamp voltage v 1.95 1.8 1.65 normally v clpcap at adin 1.3 v black calibration period 4, 5 pixel 2000 t bkcal 1.15 1.45 parameter mode obcap max. min. available sampling frequency 20 mhz mode 7.6 20 0.033 f mhz unit mhz 0.33 f 1.7 0.6 mhz 0.1 f 5.7 2.2 mhz 0.033 f 15 5.8 15 mhz mode
24 IR3Y48M notes : 1. gain is specified for gain between agc input and monout output. 2. gain measured at monout pin. parameter total gain symbol conditions typ. min. unit max. note at normal operation g mnn gain between refin/ccdin and monout 0.1 db e1.9 e0.9 1 g mxn 34.906 35.906 36.906 db min. gain max. gain gain step db 0.188 0.094 0 g st at adin operation g mnna gain between adin and monout 0.7 db e1.3 e0.3 1 g mxna 22.906 23.906 24.906 db min. gain max. gain gain step db 0.188 0.094 0 g sta cds and agc total gain relative accuracy er pa 1 lsb 2 parameter symbol conditions typ. min. unit max. note resolution res 10 bits s/n sn db 58 1.5 lsb 2.5 fs = 20 mhz (at 20 mhz mode) fs = 15 mhz (at 15 mhz mode) inl integral non-linearity differential non-linearity dnl 1.0 lsb 0.5 1 16 lsb 127 ccal adc output black level calibration code 1 lsb st cal black level step 0.85 0.75 v 0.95 v rn v ref voltage (negative) 1.35 1.25 v 1.45 v rp v ref voltage (positive) 1.1 1.0 v 1.2 v com adc common voltage 56 db snd s/ (n+d) a/d converter circuit (f s = 20 mhz. signal is given to adin.) note : 1. black level calibration period (t bkcal ) is specified for code = 16 to 127 lsb. although black level code of 1 to 15 could be set, t bkcal is not guaranteed for these codes.
25 IR3Y48M switching characteristics (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t opr = e30 to +85 ?c, c l < 10 pf) parameter symbol conditions typ. min. unit max. conversion speed f s 20 mhz 0.5 ns 35 t dl2 adc output data delay notes : 1. when shry is earlier than adckt, assumed positive. (in the above table, shry can be delayed a maximum of 3 ns behind adckt.) 2. when shdy is earlier than adcky, assumed positive. (in the above table, shdy can be delayed a maximum of 3 ns behind adcky.) 2ns t dl1 tristate enable delay 20 ns high-z / active t dle tristate disable delay 20 ns active / high-z t dld enable pulse hold 10 ns t he enable pulse setup 10 ns t sue data pulse hold 5 ns t hd data sampling delay ns 4 t dd reference sampling delay ns 4 t dr min. data pulse 10 ns t wd min. reference pulse 10 ns t wr clock high period 23 ns t h clock low period 23 ns t l clock fall time ns 2 (70% / 30%) av dd , dv dd t f ns 2 (30% / 70%) av dd , dv dd t r clock cycle period 50 ns t cyc clock rise time reference pulse setup t sur ns e3 1 note reference pulse hold data pulse setup e3 5 ns ns t sud t hr 2
IR3Y48M 26 timing chart adck adc input sampling point n n + 1 n e 6 n e 5 n e 2 n e 1 n n + 4 n + 5 n + 6 5.5 clk delay digital output t dl1 0.7dv dd 0.7av dd 0.3dv dd 0.3av dd t dl2 adin : adc direct input ccd reference sampling data sampling shr shd do 0 -do 9 t he t sue blk obp ccdclp adclp adck t dl t h t cyc t l t dr t dd t wr t wd t sud t hd t sur t hr
IR3Y48M 27 t f t l t h 0.7av dd 0.3av dd t cyc t r clock waveform adck [when adck inverted by register] adc input sampling point n n + 1 n e 6 n e 5 n e 2 n e 1 n n + 4 n + 5 n + 6 digital output t dl1 0.7dv dd 0.7av dd 0.3dv dd 0.3av dd t dl2 6.0 clk delay note : at default condition of adin mode, falling edge of sampling and rising edge of data out are selected. if each edge should be a rising edge, invert the adck by register setting. (the figure shown on the previous page is the default, the following is the inverted one.)
IR3Y48M 28 0.7dv dd v i oh = e1 ma v oh output "high" voltage input "high" voltage v 0.7av dd v ih1 parameter symbol conditions typ. min. unit max. sck clock cycle time f scyc 10 mhz serial data number 16 pcs snum sck, csn fall time ns 6 70% / 30% t sf sck, csn rise time ns 6 30% / 70% t sr hold time 20 ns t sh setup time 20 ns t ssu 40 ns t shi 40 ns t slo sck clock high width sck clock low width parameter symbol conditions typ. min. unit max. a 10 a 10 output "low" voltage v 0.3dv dd v 0.3av dd high-z leakage current i oz "high" leakage current i ling i ol = 1 ma v ol v il1 input "low" voltage 1 note control interface timing (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t opr = e30 to +85 ?c) t ssu o 0 o 1 a 0 1 snum d 8 d 9 f scyc t slo t shi t sh t ssu t sh csn sck sdata 50%dv dd 50%dv dd 50%dv dd serial i/f timing digital dc characteristics (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t opr = e30 to +85 ?c, measured as dc characteristics.) note : 1. specified for shd, shr, adck, blk, obp, ccdclp, adclp, csn, sck, sdata, resetn, stbyn, and op.
IR3Y48M 29 data output sequence pixel data readout sequence (1) : conversion start pixel data readout sequence (2) : conversion end ccd 012345678 shr shd blk black level code 01 2 3 adck do 0 -do 9 ccd (n ?1) (n) shr shd blk n ?8 n ?7 n ?6 n ?5 n ?4 n ?3 n ?2 n ?1 n adck do 0 -do 9
IR3Y48M 30 application circuit example the following schematic is the reference circuit for system design. optimize capacitance and resistance according to the system environment. 36 35 34 33 32 31 30 29 28 27 25 123456789101112 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 do 0 do 1 do 2 do 3 do 4 dv ss dv dd do 5 do 6 do 7 do 8 do 9 shd shr adck nc av ss1 av dd1 aiset nc monout obcap clpcap adin op resetn av dd3 av ss3 stbyn csn sdata sck obp ccdclp blk adclp 26 refin ccdin v com av ss2 av ss2 av dd2 av dd2 v rp v rn nc av dd4 nc analog digital chip control 0.1 f sio control pulse 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.033 f 4.7 k$ 0.1 f top view monitor adin sampling pulse ccd 3 v (typ.) 10 f digital out 0.1 f +
packages for ccd and cmos devices 31 36 25 37 48 12 1 0.15 0.05 0.1 0.1 9.0 0.3 7.0 0.2 7.0 0.2 (1.0) (1.0) (1.0) (1.0) 0.5 typ. 0.2 0.08 9.0 0.3 0.65 0.2 1.45 0.2 24 13 package base plane 8.0 0.2 0.08 0.1 m 48 qfp (qfp048-p-0707) package (unit : mm)

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