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august 2009 doc id 15418 rev 1 1/41 AN2937 application note power system demonstration ki t based on the pm6686 dual step-down controller with adjustable voltages and adjustable ldo introduction the pm6686 is a dual step-down controller with adjustable output voltages, adjustable ldo and charge pump circuit for notebook power systems. the pm6686 demonstration kit for system supply represents a typical application circuit, and allows testing of all the functions of the pm6686 device. it provides two switching sections with 5 v (out1) and 3.3 v (out2) outputs from 8 v to 28 v input battery voltage. the operating switching frequency of the two sections is 400 khz and 300 khz, respectively . each switching secti on delivers more than 5 a of output current. an internal linear regulator can provide 5 v at 100 ma peak current. the charge pump circuit provides an auxiliary 12 v output voltage. figure 1. pm6686 demonstration kit for system supply www.st.com
contents AN2937 2/41 doc id 15418 rev 1 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 demonstration kit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 quick start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 switching sections - operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.2 enable switching section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.3 enable switching section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4 switching sections - frequency selection (ton) . . . . . . . . . . . . . . . . . . . . 17 9.5 linear regulator ldo enable (en_ldo) . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.6 ldo regulation (ldorefin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.7 external bypass connections for the linear regulator (byp) . . . . . . . . . . . 18 9.8 out1 switching section regulation (fb1) . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.9 current limit of out1 switching section (ilim1) . . . . . . . . . . . . . . . . . . . . 19 9.10 out2 switching section regulation (refin2) . . . . . . . . . . . . . . . . . . . . . . 20 9.11 current limit of out2 switching section (ilim2) . . . . . . . . . . . . . . . . . . . . 20 9.12 connection of ldo output (5 v) to the pvcc pin (ldo5v_byp) . . . . . . 21 9.13 regulation of the charge pump cp (cp sel) . . . . . . . . . . . . . . . . . . . . . 21 9.14 output 1, virtual esr connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.15 output 2, virtual esr connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.16 lgate source for charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AN2937 contents doc id 15418 rev 1 3/41 9.17 mosfet dual option, high-side connection section 1 . . . . . . . . . . . . . . . 22 9.18 mosfet dual option, high-side connection section 2 . . . . . . . . . . . . . . . 23 10 test setup and performance summ ary . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 representative waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 operating modes - skip, na skip, pwm . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1.1 switching sections soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . 26 11.1.2 load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1.3 fault management: overvoltage and undervoltage . . . . . . . . . . . . . . . . 31 11.2 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2.1 out1 and out2 output efficiency vs. load current . . . . . . . . . . . . . . . . 33 11.2.2 out1 and out2 switching frequency vs. load current . . . . . . . . . . . . . 34 11.2.3 out1 and out2 output voltage vs. load current . . . . . . . . . . . . . . . . . . 35 11.2.4 power consumption analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables AN2937 4/41 doc id 15418 rev 1 list of tables table 1. component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. demonstration board test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. jumper s1 skip (connect skip pin to s1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. jumper s2 en2 (connect the en2 pin to s2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. jumper s3 en1 (connect en1 pin to s3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. jumper s4 ton (connect ton pin to s4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. jumper s5 en_ldo (connect en_ldo pin to s5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. jumper s6 ldorefin (connect ldorefin pin to s6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. jumper s7 byp (connect ldo_sw pin to s7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. jumper s8 fb1 (connect fb1 pin to s8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. jumper s9 ilim1 (connect ilim1 pin to s9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. jumper s10 refin2 (connect refin2 pin to s10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. jumper s11 ilim2 (connect ilim2 pin to s11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. jumper s12 ldo5v byp (connect pvcc pin to s12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. jumper s13 cp sel (connect cp_fb pin to s13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16. jumper s14 vesr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 17. jumper s15 vesr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. jumper s16 cp_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 19. jumper s17 dual_gate_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 table 20. jumper s18 dual_gate_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AN2937 list of figures doc id 15418 rev 1 5/41 list of figures figure 1. pm6686 demonstration kit for system supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pm6686 demonstration kit schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pm6686 demonstration board layout - top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. pm6686 demonstration board layout - inner layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. pm6686 demonstration board layout - inner layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. pm6686 demonstration board layout - bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. test setup connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. smps pulse skip mode, no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. smps no-audible skip mode, no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. smps pwm mode, no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. section 1 soft-start waveforms; 5 a constant current load applied . . . . . . . . . . . . . . . . . . . 27 figure 12. section 2 soft-start waveforms; 5 a constant current load applied . . . . . . . . . . . . . . . . . . . 28 figure 13. out1 soft-end, no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. out2 soft-end, no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. tracking soft-start en2 connected to vref2, no loads applied. . . . . . . . . . . . . . . . . . . . . 29 figure 16. tracking soft-end en2 connected to vref2, no loads applied . . . . . . . . . . . . . . . . . . . . . 30 figure 17. out1 = 5 v pwm load transient 2 a/s 0-5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. out2 = 5 v skip load transient 2 a/s 0-5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. out2 = 3.3 v pwm load transient 2 a/s 0-5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20. out2 = 3.3 v skip load transient 2 a/s 0 - 5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. undervoltage protection (uvp) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. overvoltage protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 23. overvoltage protection management: en pulled low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. efficiency vs. load current; out1=5 v, ton=vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. efficiency vs. load current; out2=3.3 v, ton=vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26. switching frequency vs. load current; out1=5 v, ton=vcc . . . . . . . . . . . . . . . . . . . . . . 35 figure 27. switching frequency vs. load current; out2=3.3 v, ton=vcc. . . . . . . . . . . . . . . . . . . . . 35 figure 28. output voltage vs. load current; out1=5 v, ton=vcc . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 29. output voltage vs. load current; out2=3.3 v, ton=vcc . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 30. input current vs input voltage, pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 31. input current vs. input voltage, na skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 32. input current vs. input voltage, skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 33. input current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 34. input current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
main features AN2937 6/41 doc id 15418 rev 1 1 main features 5.5 v to 28 v input voltage range dual fixed 1.05 v/3.3 v and 1.5 v/5.0 v outputs or adjustable 0.7 v to 5.5 v (smps1) and 0 v to 2.5 v (smps2), 1.5% accuracy over valley regulation low-side mosfet r ds(on) current sensing and programmable current limit constant on-time control selectable switching frequency soft-start (internally fixed at 2.8 ms) and soft-stop selectable pulse skip ping at light loads selectable minimum frequency (33 khz) in pulse skip mode independent power good and en signals latched ovp and uvp charge pump feedback fixed 3.3 v/5.0 v, or adjustable output 0.7 v to 4.5 v, 1.5% (ldo): 200 ma 3.3 v reference voltage 2.0%: 5 ma 2.0 v reference voltage 1.0%: 50 a
AN2937 demonstration kit schematic doc id 15418 rev 1 7/41 2 demonstration kit schematic figure 2. pm6686 demonstration kit schematic diagram 6%32 * /54 * /54 # u& 2%& 62%& 0(!3% * 2%& 3'.$ # u& , 6 2%& 2%& 3 *0) 0'.$ 6## # n& /54 6## 0'.$ 3'.$ 2%& 06## 3 *0? ,'!4% # n& 3 *0? 6). $ 3-! 0'.$ 06## /54 0'.$ # u& # n& 3 *0? 0'.$ 3'.$ ,'!4% /54? 0'.$ * 62%& 3 *0) 6). "//4 2 2 2 2 3 *0) * #0 2 + 3'.$ # u& ,'!4% 3 *0? * 0' .$ 2%& 0'.$ # n 2 2 "//4 # u& 3'.$ 2 + - -/3&%4 . 3/ - -/3&%4 . 3/ $ 3-! 3 *0? 3 *0? # u& 0'.$ 3 *0? 6## ,'!4% 2 0'.$ 0'.$ 2 + 3 *0? 3'.$ 2 + # u& # u& 2 + 6). 0'.$ * 6). # u& 0'.$ 2 * 6 ). 0'.$ 1 $5 !, -/3& %4 . 0(!3% 1 $5 !, -/3& %4 . 0'.$ 6). ('!4% - -/3&%4 . 3/ 2%& # u& 62%& # u& 6%32 6## 2 2 3'.$ ('!4% 2 2 - -/3&%4 . 3/ # u& 2 2 ,'!4% 06## # n 3 *0) 2 0'.$ $ 3-! 3 *0? $ 3-! 6%32 # u& * %842 %&). # n& 0'.$ 0'.$ * ,$/ 2 + 2 + 3'.$ 2 2 2 # n& # u& 0'.$ /54 3'.$ ('!4% 6## 2 2 3 *0? /54 0(!3% 1 $5 !, -/3& %4 . 1 $5 !,-/3&%4. 0'.$ 6). # u& 3'.$ # u& # u& 0'.$ 6%32 2 $ 3-! , 6 2 + 3'.$ "//4 6## 6## ('!4% * 0'// $ * 0'// $ 0'.$ 3'.$ 0(!3% 3 *0? 0'.$ 0- 5 "//4 5'!4% 0(!3% ),)- "9 0 /54 3%#& " %. ,$/2%&) . ,'!4% 0/+ 0/+ %.?,$/ %. 62%& 3+)0 2%& 6## 4/. 6). "//4 5'!4% 0(!3% ),)- 0'.$ '.$ /54 06## 2%&). &" ,$/ ,'!4% 0! $ 2 3'.$ 3 *0? 0'.$ /54? 2 3 *0) # u& 3'.$ /54 3 *0? 2 + 2%& * '.$ 6## 6## * /54 ,'!4% * /54 # n& # n& 2 2 # n& &" # u& 3'.$ * 6## 2 2 6## 2 + 2 + 6## 6## 6## /54? !-v
jumper settings AN2937 8/41 doc id 15418 rev 1 3 jumper settings s7 (byp jumper) shorted to out1 s8 (fb1 jumper) 1 shorted to gnd s9, s11 (ilim1, ilim2 jumper) shorted to resistors s12 (ldo to pvcc jumper) shorted s10 (refin2 jumper) shorted to vcc s6 (ldorefin jumper) shorted to gnd s13 (cp_sel jumper) floating s14 (vesr out1) open s15 (vesr out2) shorted to out2 s16 (cp connection) open s17-s18 (hs mos connections) shorted
AN2937 component list doc id 15418 rev 1 9/41 4 component list table 1. component list reference description value c1 ceramic capacitor 0603 6.3 v 100 nf c2 ceramic capacitor 0603 6.3 v 1 f c3 ceramic capacitor 0603 6.3 v nm c4 ceramic capacitor 0805 25 v 1 f c5 ceramic capacitor 0805 6.3 v 4.7 f c6 ceramic capacitor 0603 6.3 v 100 nf c7 ceramic capacitor 0603 6.3 v 1 f c8 ceramic capacitor 0805 16 v 100 nf c9 ceramic capacitor 0805 16 v 100 nf c10 ceramic capacitor 0805 16 v 100 nf c11 ceramic capacitor 0805 16 v 100 nf c12 ceramic capacitor 0603 6.3 v 100 nf c13 ceramic capacitor 10 f 1210 35 v umkk325bj106km taiyo yuden c14 ceramic capacitor 10 f 1210 35 v umkk325bj106km taiyo yuden c15 ceramic capacitor 10 f 1210 35 v umkk325bj106km taiyo yuden c16 ceramic capacitor 10 f 1210 35 v umkk325bj106km taiyo yuden c17 ceramic capacitor 0603 6.3 v 100 nf c18 poscap capacitor 6tpf220ml c19 poscap capacitor 12 m ? 220 f c20 ceramic capacitor 0805 50 v 1 nf nm c21 ceramic capacitor 0603 6.3 v 100 nf c22 poscap capacitor 6tpf220ml c23 poscap capacitor 220 f 12 m ? nm c24 ceramic capacitor 0805 50 v 1 nf nm c25 ceramic capacitor 0603 6.3 v 100 nf 100 nf c26 ceramic capacitor 10 f 1210 35 v nm c27 ceramic capacitor 0603 6.3 v 1 nf nm c28 ceramic capacitor 0603 6.3 v 1 nf nm c29 ceramic capacitor 10 f 1210 35 v nm
component list AN2937 10/41 doc id 15418 rev 1 d1 schottky diode stps1l30m d2 schottky diode stps1l30m d3 schottky diode bat54sfilm d4 schottky diode bat54sfilm d5 schottky diode bat54afilm nm l1 coilcraft mss1048-332 l2 coilcraft mss1048-332 m1 power nmos so-8 sts17nh3ll nm m2 power nmos so-8 sts17nh3ll nm m3 power nmos so-8 sts15n4llf3 nm m4 power nmos so-8 sts15n4llf4 nm q1 power so-8 dual sts9dnh3ll q2 power so-8 dual sts9dnh3ll r1 resistor 0603 220 k ? r2 resistor 0603 0.5% 51 k ? r3 resistor 0603 0.5% 11 k ? r4 resistor 0603 0.5% nm r5 resistor 0603 0.5% nm r6 resistor 0603 300 k ? r7 resistor 0805 nm r8 resistor 0805 2.2 ? r9 resistor 0805 nm r10 resistor 0603 200 k ? r11 resistor 0603 39 k ? r12 resistor 0805 nm r13 resistor 0805 2.2 ? r14 resistor 0805 nm r15 resistor 0603 220 k ? r16 resistor 0603 300 k ? r17 resistor 0805 3 ? nm r18 resistor 0805 3 ? nm r19 resistor 0603 150 k ? r20 resistor 0603 390 k ? r21 resistor 0805 0 ? r22 resistor 0805 0 ? table 1. component list (continued) reference description value
AN2937 component list doc id 15418 rev 1 11/41 r23 resistor 0805 0 ? r24 resistor 0805 0 ? r25 resistor 0603 nm r26 resistor 0603 nm r27 resistor 0603 nm r28 resistor 0603 nm table 1. component list (continued) reference description value
demonstration kit layout AN2937 12/41 doc id 15418 rev 1 5 demonstration kit layout figure 3. pm6686 demonstration board layout - top layer figure 4. pm6686 demonstration board layout - inner layer 1
AN2937 demonstration kit layout doc id 15418 rev 1 13/41 figure 5. pm6686 demonstration board layout - inner layer 2 figure 6. pm6686 demonstration board layout - bottom layer
i/o interface AN2937 14/41 doc id 15418 rev 1 6 i/o interface the demonstration board provides the following test points: table 2. demonstration board test points test point description vin+ input voltage vin- input voltage ground ldo 5 v linear regulator output vcc input of the 5 v supply of the device gnd_vcc ground of the 5 v supply of the device out1+ out1 switching section output out1- out1 switching section output ground pgood1 out1 switching section power good out2+ out2 switching section output out2+ out2 switching section output ground pgood2 out2 switching section power good pgnd junction pin between pgnd and sgnd planes vref3 3.3 v internal reference output vref2 2 v internal reference output cp charge pump output
AN2937 recommended equipment doc id 15418 rev 1 15/41 7 recommended equipment 6 v to 28 v power supply, notebook battery or ac adapter active loads digital multimeters 500 mhz four-trace oscilloscope 8 quick start 1. connect the vin+ and vin- test points of the demonstration board to an external 12 v power supply. 2. ensure that all jumpers en1, en2 and en_ldo are connected to gnd. in this condition all outputs are disabled (shutdown mode). 3. set jumper en_ldo at input resistor divider (en_ldo pin high). the ldo output (ldorefin = gnd) turns on (standby mode), providing a 5 v voltage. (a) 4. set jumper en1 at vcc (en1 pin high). the out1 switching controller brings its output into regulation. the pg1 pin goes high after soft-start. 5. set jumper en2 at vcc (en2 pin high). the out2 switching controller brings its output into regulation. the pg2 pin goes high after soft-start. 6. in order to load the switching outputs, the loads must be connected between the ?+? and the ?-? output test points, respectively. a. in this setup, the vcc external s upply is directly supplied by output ldo = 5 v. it is possible to disconnect ldo from vcc by disconnecting jumper ldo5v_byp , in this case the vcc ex ternal supply is needed before performing the ?quick start? procedure.
jumper settings AN2937 16/41 doc id 15418 rev 1 9 jumper settings it is possible to select different operating conditions by using the jumpers. note: please notice that jumpers s6, s7, s8, s9, s10, s11, s12 and s13 are already soldered on the demonstration board and do not need to be changed. refer to the schematic in figure 2 to check each connection. 9.1 switching sections - operating modes table 3. jumper s1 skip (connect skip pin to s1) position operating mode of switching sections gnd if the skip pin is tied to ground, a pulse-skip mode takes place at light loads. a zero - crossing comparator prevents the inductor current from going negative. vref2 if the skip pin is tied to the vref pin, a pulse-skip mode is enabled with a minimum switching frequency about 25 khz (ultrasonic mode). vcc if the skip pin is tied to 5 v, fixed pwm mode occurs. the switching output is in a position to sink and source current from the load.
AN2937 jumper settings doc id 15418 rev 1 17/41 9.2 enable switching section 2 9.3 enable switching section 1 table 4. jumper s2 en2 (connect the en2 pin to s2) position enable switching section 2 gnd the switching section out2 is turned off and all faults are cleared. vref2 the switching section out2 turns on afte r the switching section out1 reaches regulation. vcc the switching section out2 is turned on, r egardless of the status of the switching section out1. table 5. jumper s3 en1 (connect en1 pin to s3) position enable switching section 1 gnd the switching section out1 is turned off and all faults are cleared. vref2 the switching section out1 turns on afte r the switching section out2 reaches regulation. vcc the switching section out1 is turned on, r egardless of the status of the switching section out2.
jumper settings AN2937 18/41 doc id 15418 rev 1 9.4 switching sections - frequency selection (ton) 9.5 linear regulator ldo enable (en_ldo) table 6. jumper s4 ton (connect ton pin to s4) position smps out1 smps out2 gnd 400 khz 500 khz vref2 400 khz 300 khz vcc 200 khz 300 khz table 7. jumper s5 en_ldo (connect en_ldo pin to s5) position linear regulator ldo enable gnd the ldo is disabled. vin through resistor divider the ldo is enabled. en_ldo is connected to vin with a resistor divider. as soon as the input voltage overlaps 5.76 v typ. the ldo regulates the ldo output voltage.
AN2937 jumper settings doc id 15418 rev 1 19/41 9.6 ldo regulation (ldorefin) 9.7 external bypass connection s for the linear regulator (byp) table 8. jumper s6 ldorefin (connect ldorefin pin to s6) position ldo regulation gnd the ldo regulates 5 v. vref2 the ldo regulates a voltage equal to two times the voltage at ldorefin input. vcc the ldo regulates 3.3 v. table 9. jumper s7 byp (connect ldo_sw pin to s7) position external bypass connections for the linear regulator gnd the internal linear regulator ldo is always on. it can provide an output peak current of 100 ma. out1. if ldo regulates 5 v and byp goes higher than 4.74 v, an internal p-channel mosfet switch connects the byp pin to the ldo pin, shutting down the ldo internal linear regulator. it can provide an output peak current of 200 ma. out2 if ldo regulates 3.3 v and byp goes higher than 3.17 v, an internal p-channel mosfet switch connects the byp pin to the ldo pin, shutting down the ldo internal linear regulator. it can provide an output peak current of 100 ma.
jumper settings AN2937 20/41 doc id 15418 rev 1 9.8 out1 switching secti on regulation (fb1) 9.9 current limit of out1 switching section (ilim1) table 10. jumper s8 fb1 (connect fb1 pin to s8) position out1 regulation gnd. out1 regulates 5 v. ext divider. out1 regulates an adjustable voltage from 0.7 v to 5.5 v, programmable with the external divider r4, r5. vcc out1 regulates 1.5 v. table 11. jumper s9 ilim1 (connect ilim1 pin to s9) position out1 regulation external resistor the threshold voltage of ilim1 is compared with 1/10 th of the gnd-phase1 drop during the off time to determine a valley current limit. vref2 the internal threshold voltage of the curr ent limit comparator is set to 200 mv.
AN2937 jumper settings doc id 15418 rev 1 21/41 9.10 out2 switching secti on regulation (refin2) 9.11 current limit of out2 switching section (ilim2) table 12. jumper s10 refin2 (connect refin2 pin to s10) position out2 regulation gnd out2 regulates 1.05 v. reference ext refin2 out2 regulates the reference voltage at the ext_refin2 pin. vcc out2 regulates 3.3 v. table 13. jumper s11 ilim2 (connect ilim2 pin to s11) position out2 regulation external resistor the threshold voltage of ilim2 is compared with 1/10 th of the gnd-phase2 drop during the off time to determine a valley current limit. vref2 the internal threshold voltage of the curr ent limit comparator is set to 200 mv.
jumper settings AN2937 22/41 doc id 15418 rev 1 9.12 connection of ldo output (5 v) to the pvcc pin (ldo5v_byp) 9.13 regulation of the charge pump cp (cp sel) 9.14 output 1, virtual esr connection table 14. jumper s12 ldo5v byp (connect pvcc pin to s12) position connection of ldo output (5 v) to pvcc pin shorted if ldorefin = gnd, ldo regulates 5 v. in this case the pvcc and vcc pin of the device can be supplied with the ldo by setting the jumper in this position. open pvcc and vcc need to be supplied with an external 5 v source. the ldo is disconnected from the pvcc pin. table 15. jumper s13 cp sel (connect cp_fb pin to s13) position regulation of the charge pump cp vcc or left floating the charge pump controller is disabled. external divider the charge pump regulates the voltage set with the external divider. table 16. jumper s14 vesr1 position virtual esr enab le circuit for section 1 left floating virtual esr circuit is disabled. vesr1 virtual esr circuit is enabled.
AN2937 jumper settings doc id 15418 rev 1 23/41 9.15 output 2, virtual esr connection 9.16 lgate source for charge pump circuit 9.17 mosfet dual option, hi gh-side connection section 1 table 17. jumper s15 vesr2 position virtual esr enab le circuit for section 2 out2 virtual esr circuit is disabled. vesr2 virtual esr circuit is enabled. table 18. jumper s16 cp_source position source of the charge pump cp lgate1 the charge pump circuit is supplied by the low-side driver of section 1. lgate2 the charge pump circuit is supplied by the low-side driver of section 2. table 19. jumper s17 dual_gate_1 position connection of high-side mos (dual configuration) shorted short this jumper to connect the hgat e1 drive to the mosfet gate if dual mosfets are mounted. open leave this jumper open if mosfet in single package is used.
jumper settings AN2937 24/41 doc id 15418 rev 1 9.18 mosfet dual option, hi gh-side connection section 2 table 20. jumper s18 dual_gate_2 position connection of high-side mos (dual configuration) shorted short this jumper to connect the hgat e2 drive to the mosfet gate if dual mosfets are mounted. open leave this jumper open if mosfet in single package is used.
AN2937 test setup and performance summary doc id 15418 rev 1 25/41 10 test setup and performance summary 10.1 test setup the pm6686 demonstration board has the following input/output connections: 12 v input through vin+ and vin- connectors out1 output through out1+ and out1- connectors out2 output through out2+ and out2- connectors ldo linear regulator output through ldo connector charge pump output cp through cp connector. a power supply capable of supplying at least 6 a should be connected to vin+, vin- and two active loads should be connected respectively to out1+, out1- and out2+, out2-. figure 7. test setup connections
representative waveforms AN2937 26/41 doc id 15418 rev 1 11 representative waveforms 11.1 operating modes - skip, na skip, pwm the following illustrations show the relevant waveforms of a switching section and is provided to underline the behavior of the device in pulse skip mode, no-audible skip mode and forced pwm mode working conditions. figure 8. smps pulse skip mode, no load figure 9. smps no-audible skip mode, no load
AN2937 representative waveforms doc id 15418 rev 1 27/41 figure 10. smps pwm mode, no load 11.1.1 switching secti ons soft-start and soft-end figure 11 and figure 12 show the soft-start waveforms, while figure 13 and figure 14 show the soft-end waveforms. the pm6686 has an independent internal digital soft-start for each switching section. during the soft-start phase, the internal current limit increases from 25% to 100% in increments of 25% to prevent the inductor from reaching an excessive value. figure 11. section 1 soft-start waveforms; 5 a constant current load applied
representative waveforms AN2937 28/41 doc id 15418 rev 1 figure 12. section 2 soft-start waveforms; 5 a constant current load applied when the en pin is driven below the turn-off threshold, the section starts performing a soft- end. the output is connected to ground with an internal 24 ? (typ.) power mosfet, so the output is discharged softly. figure 13 and 14 show the soft-end for the two sections. figure 13. out1 soft-end, no load
AN2937 representative waveforms doc id 15418 rev 1 29/41 figure 14. out2 soft-end, no load a power-up sequence for the switching sections can be selected by connecting one en pin to vref2. the section with the en pin connected to vref2 begins the soft-start only when the other section is in regulation (its pgood is high) and makes a soft-end suddenly when the other section is turned off ( figure 15 and figure 16 ). figure 15. tracking soft-start en2 connected to vref2, no loads applied
representative waveforms AN2937 30/41 doc id 15418 rev 1 figure 16. tracking soft-end en2 connected to vref2, no loads applied 11.1.2 load transient the illustrations below show the load transient performa nce both in skip mo de and in forced pwm. figure 17. out1 = 5 v pwm load transient 2 a/s 0-5 a
AN2937 representative waveforms doc id 15418 rev 1 31/41 figure 18. out2 = 5 v skip load transient 2 a/s 0-5 a figure 19. out2 = 3.3 v pwm load transient 2 a/s 0-5 a figure 20. out2 = 3.3 v skip load transient 2 a/s 0 - 5 a
representative waveforms AN2937 32/41 doc id 15418 rev 1 11.1.3 fault management: overvoltage and undervoltage the pm6686 provides fault protection for the switching section against undervoltage and overvoltage. figure 21 shows the undervoltage fault management. if, during regulation, the output voltage drops below 70% of the nominal value, an undervoltage latched fault is detected. the controller performs a soft-end procedure. the undervoltage fault is reset by toggling the en pin or by cycling the vin (this action performs triggers a power on reset [por]). figure 21. undervoltage protection (uvp) management the pm6686 provides latched overvoltage protection (ovp). if the output voltage rises above the +111% (typ.) from the nominal value for section 1 and above the +116% typ. for section 2, latched ovp protection is activated. the controller attempts to pull down the output voltage to 0 v, working in pwm. the cu rrent is limited by th e negative current limit. the low-side mosfet is kept on when the output voltage is about 0 v. this management prevents high negative undervoltage of the output rail that may damage the load ( figure 22 ). if the en signal is pulled low, the low-side mosfet is still high, ke eping the output to ground, thus preventing any da mage to the load if the caus e of the overvoltage is still present ( figure 23 ). the protection is latched and this fault is cleared by toggling the en pin of the section, or cycling the v in .
AN2937 representative waveforms doc id 15418 rev 1 33/41 figure 22. overvoltage protection management figure 23. overvoltage protection management: en pulled low
representative waveforms AN2937 34/41 doc id 15418 rev 1 11.2 typical operating characteristics 11.2.1 out1 and out2 output efficiency vs. load current figure 24 and 25 show the efficiency versus load current in pwm mode, skip mode and no- audible skip mode for different input voltage values: green: 7 v blue: 12 v red: 18 v figure 24. efficiency vs. load current; out1=5 v, ton=vcc figure 25. efficiency vs. load current; out2=3.3 v, ton=vcc !-v /rdgfxuuhqw>$@ (iilflhqf\>@ 07- .!3+)0 3+)0 !-v /rdgfxuuhqw>$@ (iilflhqf\>@ 07- .!3+)0 3+)0
AN2937 representative waveforms doc id 15418 rev 1 35/41 11.2.2 out1 and out2 switch ing frequency vs. load current figure 26 and 27 show the switching frequency versus load current in pwm mode, skip mode, and na skip mode. t on is connected to vcc. figure 26. switching frequency vs. load current; out1=5 v, ton=vcc figure 27. switching frequency vs. load current; out2=3.3 v, ton=vcc !-v )uhtxhqf\>n+]@ /rdgfxuuhqw>$@ 6.,3 1$6.,3 3:0 !-v )uhtxhqf\>n+]@ /rdgfxuuhqw>$@ 6.,3 1$6.,3 3:0
representative waveforms AN2937 36/41 doc id 15418 rev 1 11.2.3 out1 and out2 output voltage vs. load current figure 28 and 29 show the load regulation of the output voltages of the switching sections. the output voltage is measured versus the load current. t on is connected to v cc . figure 28. output voltage vs. load current; out1=5 v, ton=vcc figure 29. output voltage vs. load current; out2=3.3 v, ton=vcc !-v 2xwsxwyrowdjh>9@ /rdgfxuuhqw>$@ 1$6.,39 3:09 6.,39 !-v 2xwsxwyrowdjh>9@ /rdgfxuuhqw>$@ 6.,39 3:09 1$6.,39
AN2937 representative waveforms doc id 15418 rev 1 37/41 11.2.4 power consumption analysis to measure the device consumption under real operating conditions, an external power supply (+5 v) is connected to pvcc. current absorption from vin and from vcc are measured in the three different operative modes with no load applied at the outputs. figure 30. input current vs input voltage, pwm mode figure 31. input current vs. input voltage, na skip mode !-v ,qsxwyrowdjh>9@ &xuuhqw>p$@ , 9 ,1 ,39&& !-v ,qsxwyrowdjh>9@ &xuuhqw>p$@ , 9 ,1 ,39&&
representative waveforms AN2937 38/41 doc id 15418 rev 1 figure 32. input current vs. input voltage, skip mode figure 33 and 34 represent the current absorption from vin in standby and shutdown condition. in standby mode, the switching sections are off, while the ldo is on (en1=en2=low, en_ldo = high). in shutdown mode, the switching sections and the ldo are off (en1=en2=en_ldo = low). figure 33. input current consumption vs. input voltage !-v ,qsxwyrowdjh>9@ &xuuhqw>p$@ , 9 ,1 ,39&& !-v ,qsxwyrowdjh>9@ ,qsxwfxuuhqw>x$@
AN2937 representative waveforms doc id 15418 rev 1 39/41 figure 34. input current consumption vs. input voltage !-v ,qsxwyrowdjh>9@ ,qsxwfxuuhqw>x$@
revision history AN2937 40/41 doc id 15418 rev 1 12 revision history table 21. document revision history date revision changes 20-aug-2009 1 initial release
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