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september 2014 docid18333 rev 3 1/21 1 AN3326 application note spc56el60x hardware design guideline introduction this application note serves as a guide line to hardware designers and provides configuration and layout recommendations for the spc56el60x microcontroller unit. the document covers the following topics: ? voltage regulator (v reg ) ? main oscillator ? supply pins ? analog input pins ? reference reset circuit www.st.com
contents AN3326 2/21 docid18333 rev 3 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 on-chip voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 recommended transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 power dissipation of external transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 ballast transistor junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 ballast transistor v ce(sat) (collection-emitter saturation voltage) . . . . . . . 8 2.1.4 ballast transistor inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 oscillator hardware re commendations . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 supply pins and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid18333 rev 3 3/21 AN3326 list of tables 3 list of tables table 1. recommended crystals and their main parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
list of figures AN3326 4/21 docid18333 rev 3 list of figures figure 1. block scheme of spc56el60x used with the internal ballast . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. block scheme of spc56el60x used with an external ballast . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. external npn ballast connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. external ballast decoupling capaci tors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. core logic decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. pll voltage supply decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. voltage regulator supply decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. io voltage supply decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. flash and oscillato r voltage supply decoup ling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. adc voltage supply filtering and decoupling capaci tors . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. impedance matching of the analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid18333 rev 3 5/21 AN3326 overview 20 1 overview spc56el60x devices are members of a new family of microcontrollers designed for safety integrity level 3 (sil3) and automotive sil d (asild) compliant chassis and safety applications. these microcontrollers are ba sed on two high-performance e200z4d cores built on power architecture ? technology. the device is supplied externally with a single voltage supply, 3.3 v. internally the chip operates with two supply voltages, namely the main supply (3.3 v) and the core logic supply (1.2 v). moreover, the analog reference voltage, which is supplied externally as well, can be either 3.3 v or 5 v depending on the application requirements. all spc56el60x electrical characteristics, including the absolute maximum ratings and recommended operating conditions (for ex ample, threshold voltages, maximum and minimum supply voltages, etc.), as well as th e package mechanical drawings, can be found in the device datasheet. pin assignments can be found in both the device reference manual and datasheet.
on-chip voltage regulator AN3326 6/21 docid18333 rev 3 2 on-chip voltage regulator the spc56el60x device is supplied with 3.3 v 10% (3.0?3.6 v). additionally, the device?s on-chip linear voltage regulator (v reg ) generates a reference voltage enabling the regulation of the 1.2 v via the internal or external ballast from the external 3.3 v voltage supply. the on-chip voltage regulator module provides the following main features: ? works with either an npn external ballast transistor or the internal one ? auto-detection of the external ballast (if external ballast is not detected, spc56el60x works with the internal one) ? low- and high-voltage detection on the 1.2 v supply ? low-voltage detection on the 3.3 v supply voltages spc56el60x can work using either the internal ballast (see figure 1 ) or an external one (see figure 2 ). figure 1. block scheme of spc56el 60x used with the internal ballast 1. grey blocks represent ex ternal passive components. 63&(/[[ 9 ''b/9b&25 9 %&75/ 9 ''b+9b95(* 9 9 *$3*06
docid18333 rev 3 7/21 AN3326 on-chip voltage regulator 20 figure 2. block scheme of spc56el60x used with an external ballast 1. grey blocks represent ex ternal passive components. the use of the internal ballast eliminates all external components shown in figure 5 (that is, the bipolar transistor used as ballast and two decoupling capacitors). however, in this configuration the consumption caused by the dr op in the externally supplied 3.3v, and 1.2v, used by the digital logic, is dissipated by th e package of spc56el60x itself. this dissipation does not permit a high consumption to be achieved. if an external ballast is used, the consumption d ue to this drop is dissipated by the external bipolar regulator. in such a way a higher consumption can be achieved. the selection between either external or internal ballast is done by the v reg module itself through its auto-detection feature: 1. after a destructive reset (for example, powe r on), spc56el60x always starts using the internal ballast. 2. external ballast detection begins. 3. if external ballast is detected, spc56e l60x switches to it; if not, spc56el60x continues working with the internal one. the device cannot be used with the 1.2 v supplied directly from the external regulator, but the 1.2 v has to be controlled by the internal regulator. 2.1 recommended transistor the v reg circuit is a classic emitter-follower conf iguration. the voltage regulator external npn ballast base control (bctrl) pin controls the the voltage on the 1.2 v pin by controlling the current on th e base of the transistor. the stabilization of the output voltage is achieved using an external capacitance of several f (see section 4 ). figure 3 shows how the external ballast has to be connected to the related spc56el60x pins. 131edoodvw 9 63&(/[[ 9 ''b/9b&25 9 %&75/ 9 ''b+9b95(* 9 *$3*06
on-chip voltage regulator AN3326 8/21 docid18333 rev 3 figure 3. external npn ballast connection the gain of the bipolar ballast must be high enough to start up the device and low enough to prevent the v reg becoming instable. the recommended external ballast transistor is the bipolar transistor bcp68 with the gain range of 85 up to 375 (for ic=500 ma, vce=1 v) provided by several suppliers. this includes the gain variations bcp68-10, bcp68-16 and bcp68-25. the most important parameters for the interoperability with the integrated volt age regulator are the dc current gain (hfe) and the temperature coefficient of the gain (xtb). while the specified gain range of most bc p68 vendors is the same, there are slight variations in the temperature coefficient parameter. spc56xl60/54 voltage regulator operation was simulated against the typical variation on temperature coefficient and against the spec ified gain range to have a robust design. 2.1.1 power dissipation of external transistor the power dissipation required by the bypass tr ansistor is dependent upon the voltage drop across it, the core current and the selected supply range. assuming the cpu draws 250 ma (a) and a 3.3 v supply, the worst case voltage drop with +10% 3.3 v supply is 2.5 v (that is, 3.6 v ? 1.08 v = 2.52 v). this leads to about 0.62 watts of power dissipation. 2.1.2 ballast transistor junction temperature the ballast transistor maximum junction temperature is typically 150 c, although in some transistors it may be as high as 165 c. depending on the maximum ambient temperature, the ballast transistor may have a limited allowed temperature rise and thus requires adequate heatsinking. th ermal characteristics of the board and heatsink are required for this calculation. 2.1.3 ballast transistor v ce(sat) (collection-emitter saturation voltage) to reduce the power dissipation in the transistor, a series resi stor that will drop the collector voltage can be added. if such a resistor is added, the user must ensure that the transistor 9 ''b/9b5(*&25 9 ''b+9b5(* %&75/ *$3*06 a. please check value for your configur ation in the latest spc56el60x datasheet.
docid18333 rev 3 9/21 AN3326 on-chip voltage regulator 20 does not enter saturation phase. the transisto r must remain out of saturation with the minimum expected supply and the maximum expected v core rail (that is, 1.32 v). 2.1.4 ballast transistor inductance spc56el60x boards must be designed carefu lly to decrease the parasitic inductance. two kinds of parasitic inductance are present: ? inductance due to the distance between the ballast transistor's heatsink rail and the microcontroller ? inductance due to the lengths of the 1.2 v traces and of the bctrl signal those inductances reduce the phase margin. it is recommended that: ? inductance on bctrl is kept below 15 nh ? inductance on 1.2 v is kept below 15 nh
main oscillator AN3326 10/21 docid18333 rev 3 3 main oscillator the spc56el60x uses an external crystal as input for both plls . the main oscillator provides the following main features: ? input frequency range: 4?40 mhz ? crystal input mode ? external reference clock (3.3 v) input mode ? fmpll reference for noise immunity r easons, the oscillator uses a dedicated 3.3 v supply. this supply is provided by the pins v dd_hv_osc and v ss_hv_osc (see section 4 ). table 1 shows a list of the recommended crystals and their main parameters. note: user shall configure the xosc_margin bit through the user option bit depending on the chosen crystal. xosc_margin must be set to ?0? if a 4 mhz crystal is chosen and set to ?1? in all other cases. 3.1 reference oscillator circuit this section describes the key items of the oscillator circuit. the oscillator circuit consists of the following components: ? crystal ? two capacitors figure 4 contains a schematic of the on-chip oscillator (b) . table 1 prov ides a list of recommended crystals and the suggested value of the two load capacitors c 1 and c 2 . no other external components (for ex ample, a bias resistor) are needed. table 1. recommended crystals and their main parameters nominal frequency [mhz] crystal model load on extal/xtal (1) c 1 = c 2 [pf] 1. c 1 and c 2 include the parasitic capacitors which must be ta ken into account to choose the proper external capacitors. 4.0 nx8045gb 4.7 8.0 nx5032ga 23.0 8.0 nx8045gb 23.0 10.0 nx5032ga 21.0 12.0 nx5032ga 19.0 16.0 nx5032ga 5.6 40.0 nx5032ga 8.0 40.0 nx3225ga 8.0
docid18333 rev 3 11/21 AN3326 main oscillator 20 figure 4. reference oscillator circuit b. main oscillator supply pins are not shown; see section 4: supply pins and decoupling for pin details. 63&(/[[ (;7$/ ;7$/ 9 66b+9b26& & & *$3*06
main oscillator AN3326 12/21 docid18333 rev 3 3.1.1 oscillator hardware recommendations to optimize performance and minimize emc (electromagnetic compatibility) susceptibility, the following recommendations are provided: ? use the crystal with the lowest frequency an d set the fmpll multiplication factor to obtain the chosen system operating frequency. ? keep the oscillator circuit as compact as poss ible in order to mini mize the amount of emissions generated by currents due to high order harmonics (c) . ? for the crystals listed in table 1 , the maximum pcb parasitic capacitance between extal and xtal shall not exceed 1.5 pf. ? connect v ss_hv_osc directly to the ground plane so th at return currents can flow easily between v ss_hv_osc and the two capacitors (c 1 and c 2 ). ? avoid other high frequency si gnals near the oscillator circ uitry as they can have an undesirable influence on the oscillator. ? lay out/configure the ground supply on the basis of low impedance. ? shield the crystal with an additional ground plane underneath the crystal. ? do not lay out sensitive signal s near the oscillator (analyze cross-talk between different layers). ? place capacitors at both ends of the crysta l, connected directly to the ground plane. ? the crystal package, when me tallic, should be connected directly to ground, while keeping the overall loop as small as possible. ? extal ? oscillator not in bypass mode: extal is the analog output of the oscillator amplifier circuit. ? oscillator in bypass mode: extal is the analog input for the clock generator. ? xtal is the analog in put of the oscillator amplifier ci rcuit. the xtal pin needs to be grounded (connected to v ss_hv_osc ) if the oscillator is used in bypass mode. c. the oscillator circuit has currents flowing at the crystal?s fundamental frequency. even if the oscillator is clipped, higher order harmoni cs are present as well.
docid18333 rev 3 13/21 AN3326 supply pins and decoupling 20 4 supply pins and decoupling the spc56el60x has different supply/decoupling pins: ? core logic pins (v dd_lv_corx and v ss_lv_corx ) ? voltage regulator pins (d) (v dd_hv_pmu and v dd_hv_regx ) ? adc 0 and adc 1 pins (v dd_hv_adv and v ss_hv_adv ) ? input/output pins (v dd_hv_io and v ss_hv_io ) ? crystal oscillator amplifier pins (v dd_hv_osc and v ss_hv_osc ) ? flash pins (v dd_hv_fla and v ss_hv_fla ) ? fmpll pins (v dd_lv_pll0_pll1 and v ss_lv_pll0_pll1 ) other pins which must by considered are: ? external npn ballast base control pin (bcrtl) ? adc 0 and adc 1 high voltage reference (v dd_hv_adr0 and v dd_hv_adr1 ) ? adc 0 and adc 1 low voltage reference (v dd_lv_adr0 and v dd_lv_adr1 ) please refer to the device reference manual and datasheet for complete details on these pins. 4.1 decoupling capacitors this section provides the values of the different recommended capacitors. hardware designers must pay particular attent ion to place the decoupling capacitors beside the respective pins. figure 5 shows the connection between the external ballast and spc56el60x. d. v dd_hv_pmu pin is the voltage supply of the internal regulator; v dd_hv_regx pins are the collector of the internal ballasts.
supply pins and decoupling AN3326 14/21 docid18333 rev 3 figure 5. external ballast decoupling capacitors 1. the 20 f capacitor shall be placed as close as possible to the collector of the ballast. in case the user would like to use the spc56e l60x with the internal ballast, the capacitor of figure 5 are not needed. note: a base capacitor is not needed in ex ternal or internal ballast configuration. figure 6 shows the decoupling capacitors nee ded by the logic supply pins (1.2 v). the number of these pins depends on the chosen spc56el60x package (for example, the 144- pin package includes six pairs of logic supply pins). figure 6. core logic decoupling capacitors 1. total value of these capacitor s shall be between 300nf and 900nf and total esr between 1mohm and 100mohm. 63&(/[[ 9 9 ?) %&75/ *$3*06 63&(/[[ 9 ''b/9b&25[ 9 66b/9b&25[ 9 ''b/9b&25\ 9 66b/9b&25\ q) ?) q) ?) 9 *$3*06
docid18333 rev 3 15/21 AN3326 supply pins and decoupling 20 figure 7 , figure 8 and figure 9 show the recommended decoupling capacitors for the following supply pins: ? pll ? voltage regulator ? io ? flash ? oscillator figure 7. pll voltage supply decoupling capacitors 1. the vdd_lv_pll pin must be connected at pcb level to the other 1.2 v pins. th is connection is required in both cases, leopard working with the internal or external ballast. figure 8. voltage regulator supply decoupling capacitors spc56el60x devices always start using the internal ballast, which means that the decoupling capacitors connected to v dd_hv_regx are needed even if the external ballast is present on the board. the number of v dd_hv_regx pins depends on the chosen package (for example, the 144- pin package includes three of these pins). 63&(/[[ 9 ''b/9b3// 9 66b/9b3// q) q) 9 *$3*06 63&(/[[ 9 ''b+9b5(*[ 9 ''b+9b308 q) ?) q) 9 *$3*06
supply pins and decoupling AN3326 16/21 docid18333 rev 3 figure 9. io voltage supply decoupling capacitors figure 10. flash and oscillator voltage supply decoupling capacitors spc56el60x adcs can be supplied either with 3.3 v or 5 v (both adcs must use the same voltage supplies). figure 11 shows the capacitors needed by the adc supply and reference. 63&(/[[ 9 ''b+9b,2[ 9 66b+9b,2[ 9 ''b+9b,2\ 9 66b+9b,2\ s) q) s) q) 9 *$3*06 63&(/[[ 9 ''b+9b26& 9 66b+9b26& 9 ''b+9b)/$ 9 66b+9b)/$ q) q) q) q) 9 *$3*06
docid18333 rev 3 17/21 AN3326 supply pins and decoupling 20 figure 11. adc voltage supply filtering and decoupling capacitors 1. electrolithic or tantalium. 2. this capacitor shall be placed closed to t he respective pads than the other capacitors. 4.2 layout recommendations some recommendations on the layout and co mponent distribution are listed below: ? each decoupling capacitor should be placed next to the respective pin. ? if possible use a small plane to distribute v core (1.2 v) with a low parasitic inductance to each pin. ? the parasitic inductance on the ballast output (1.2 v) must be kept below 15 nh. ? the parasitic inductance between the bctr l pin and the ballast input must be kept below 15 nh. ? low equivalent series resistance (esr) and low equivalent series inductance (esl) capacitors should be used fo r the 1.2 v stability capacitors (e) . use preferably ceramic capacitors. do not use electrolytic capacitors as stabilization capacitors. ? use a multi-layer printed circuit board with a separate layer dedicated to the ground and another one to the voltage supply. 63&(/[[ 9 ''b+9b$'9 9 66b+9b$'9 9 ''b+9b$'5[ 9 66b+9b$'5[ ?) q) ? ) q) $'& [ uhihuhqfh $'&vxsso\ *$3*06 q) q)

e. please refer to the device datasheet for the recommended maximum esr value.
analog input pins AN3326 18/21 docid18333 rev 3 5 analog input pins to maximize the performance of the internal adc without sacrificing conversion accuracy, hardware designers must take into account the impendance matching of the analog input pins. figure 12 shows the recommended circuit to ma tch this impedance. the external components (r f , c f and r l ) must be chosen accordingly to the application parameters (for example, conversion rate, internal resistance of the input signal (r s ), etc.). the device datasheet includes all needed steps and equations needed to choose these external components (please refer to the input impedance and adc accuracy section of the device datasheet). figure 12. impedance matching of the analog input pins 5 6: 5 $' 9 '' & 3 & 3 ,17(51$/&,5&8,76&+(0( 5 / 5 ) 5 6 9 $ & ) (;7(51$/&,5&8,76&+(0( &xuuhqw /lplwhu )lowhu 6rxufh *$3*06
docid18333 rev 3 19/21 AN3326 reference reset circuit 20 6 reference reset circuit the spc56el60x external reset pin is a bidirectional low active signal. for safety reasons an internal weak pull down structure is implemented. in such a configuration, if the reset pin is open (for exam ple, due to a faulty condition), the device is remains in reset state. this pin acts as an input to initialize the spc56el60x to a known start-up state and acts as an output when an internal device function causes a reset. the minimum reset pulse duration is 500 ns. figure 13 shows the suggested reset circuit. basic components are: ? external open-drain microprocessor reset device ? external pull-up resistor (r p ) ? nor gate digital port to m anage multiple reset sources figure 13. reference reset circuit the value of the pull-up resistor must be chosen according to the internal pull-down resistor integrated in spc56el60x and the external re set device component. for example, using the stm6315rdw13f as microproce ssor reset, a resistor of 2.2k ?? works properly. 63&(/[[ 2shqgudlq plfursurfhvvru uhvhw 5(6(7 5 s 9 567 05 125 uhvhw vrxufhv *$3*06
revision history AN3326 20/21 docid18333 rev 3 7 revision history table 2. document revision history date revision changes 17-dec-2010 1 initial release. 04-mar-2011 2 added the footnote under the figure 7. updated section 4.1: decoupling capacitors . added the footnote under the figure 5. modified the footnote under the fig 6. updates fig 5 and fig 6. 10-sep-2014 3 occurrences of spc56el60 changed with spc56el60x. updated section 2.1: recommended transistor . updated chapter 3: main oscillator . update table 1 . updated section 4.1: decoupling capacitors . updates figure 5 , figure 6 and figure 11 removed appendix a: reference document.
docid18333 rev 3 21/21 AN3326 21 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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