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1. introduction 1.1 about this document this document lists detailed information about the SJA2020 device. it focuses on factual information like pin information, register views, characteristics etc. short descriptions are used to outline the concept of the features and functions. more details and background on developing applications for this device is given in the SJA2020 user manual (see ref . 1 ). no explicit references are made to the user manual. please refer to the SJA2020 application note known issues (see ref . 2 ) for corrections and additional product information. 1.2 intended audience this document is written for engineers evaluating and/or developing systems, hard- and/or software for the SJA2020. some basic knowledge of arm processors and architecture and arm7 in particular is assumed (see ref . 3 ). 2. general description 2.1 architectural overview the SJA2020 consists of an arm7tdmi-s processor with real-time emulation support, the amba advanced high-performance bus (ahb) for interface to the on-chip memory controllers, a dtl bus (a universal philips interface) for interface to the interrupt controller and three vlsi peripheral buses (vpb - a compatible superset of arms amba advanced peripheral bus) for connection to the on-chip peripherals clustered in so-called subsystems. the SJA2020 con?gures the arm7tdmi-s processor in little endian byte order. all peripherals run on the same system clock frequency as the arm7tdmi-s processor to minimize the access latency time. the ahb2vpb bridge used in the subsystems contain a write-ahead buffer of 1 deep. this implies that when the arm7 writes to a register located at the vpb side of the bridge, it will continue even though the actual write may not yet have taken place. completion of a second write to the same subsystem will not be executed until the ?rst write is ?nished. 2.2 arm7tdmi-s processor the arm7tdmi-s is a general purpose 32-bit processor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers (cisc). this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core. SJA2020 arm7 microcontroller with can and lin controllers rev. 01 5 april 2006 objective data sheet
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 2 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? standard 32-bit arm set ? 16-bit thumb set the thumb set's 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arm's performance advantage over a traditional 16-bit controller using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm controller connected to a 16-bit memory system. the arm7tdmi-s processor is described in detail in the arm7tdmi-s data sheet (see ref . 3 ). 2.3 on-chip ?ash memory system the SJA2020 includes up to 384 kb ?ash memory system. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in-system via a serial port, like e.g. can. the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld upgrades. 2.4 on-chip static ram the SJA2020 includes a 24 kb static ram memory that may be used for code and/or data storage. 3. features 3.1 general n arm7tdmi-s processor at 60 mhz maximum n up to 384 kb on-chip ?ash program memory n 24 kb static ram n one 550 uart with 16 bytes tx and rx fifo depths n three full-duplex spis with 16 bits wide, 8 locations deep tx fifo and rx fifo n four 32-bit timers containing each four capture and compare registers linked to i/os n 10-bit, 400 ksample/s, 4-channel adc with external trigger start option n real time clock with on-chip 32 khz crystal oscillator and (battery) supply n 32-bit watchdog with timer change protection
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 3 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers n 94 general purpose i/o pins with programmable pull-up n vectored interrupt controller with 16 priority levels n external 8-bit, 16-bit or 32-bit bus with four memory banks n standard arm test and debug interface with real-time in-circuit emulator n dual power supply: u cpu operating voltage: 1.8 v 5 % u i/o operating voltage: 3.3 v u 5 v tolerant port pins (without pull-up) n con?gurable system power management n twelve level sensitive external interrupt pins n processor wake-up from power down via external interrupt pins, can or lin activity n on-chip low power ring-oscillator with operating range from 25 khz to 1 mhz n on-chip crystal oscillator with operating range from 10 mhz to 20 mhz n on-chip pll allows cpu operation up to maximum cpu rate of 60 mhz n automotive product quali?cation according aec-q100 rev-f: u temperature grade 2 compliant; ambient operating temperature from - 40 c to +105 c n boundary scan test supported n small 144-pin lqfp package 3.2 flash memory n consisting of sectors of 8 kb n supporting in-system and in-application programming n fast programming capability at 4 mbit/s n provisions against over-burning and over-erasing n source code protection 3.3 can gateway n six can controllers n full can mode for message reception n triple transmit buffers with automatic priority scheduling n extensive global can acceptance ?lter for high performance gateway functionality 3.4 lin master controller n four dedicated lin master controllers n four standard 450 uarts with lin enhancement for lin slaves or general purposes 4. ordering information table 1: ordering information type number package name description version SJA2020hl/623 [1] lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 4 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] SJA2020hl/623 has 384 kb ?ash consisting of 48 sectors of 8 kb. 5. block diagram fig 1. block diagram 001aaa165 ahb2vpb bridge peripheral subsystem arm7tdmi-s SJA2020 ahb wrapper 1149.1 jtag test and debug interface flash controller 384 kb flash static ram controller 24 kb flash ahb2dtl adapter vectored interrupt controller capture and compare timer 0, 1, 2, 3 general purpose i/o 0, 1, 2 550 uart ahb2vpb bridge ivn subsystem 2 kb static ram global acceptance filter can controller 0, 1, 2, 3, 4, 5 450 uart 0, 1, 2, 3 lin master controller 0, 1, 2, 3 jtagsel trst_n tms tck tdi rtck tdo cap0[0] to cap3[3] mat0[0] to mat3[3] p0[0:31] p2[0:29] p1[0:31] txdc0 to txdc5 rxdc0 to rxdc5 txdl0 to txdl3 rxdl0 to rxdl3 txd rxd ahb decoder external memory controller ahb2vpb bridge general subsystem spi 0, 1, 2 10-bit adc adc interface system control unit watchdog timer event router real time clock 32 khz oscillator power-on reset clock generation unit 10 mhz to 20 mhz oscillator low power pll low power ring oscillator power-on reset core supply 1.8 v i/o pins supply 3.3 v xout_osc xin_osc reset_n xout_rtc ai0 to ai3 xin_rtc cs0 to cs3 we_n oe_n bls0 to bls3 d[0:31] a[0:23] scs0 to scs2 sck0 to sck2 sdi0 to sci2 sdo0 to sdo2 v dd(adc) vrefn ei0 to ei3 rxdc0 to rxdc5 rxdl0 to rxdl3 v dd(rtc) v ss(rtc) v dd(osc_pll) v ss(osc) v ss(pll) v dd(core) v ss(core) v dd(io) v ss(io)
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 5 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for sot486-1 SJA2020hl 108 37 72 144 109 73 1 36 001aac517 table 2: lqfp144 pin assignment symbol pin description default function function 1 function 2 function 3 jtagsel 1 tap controller select input; low level selects arm debug mode and high level selects boundary scan and ?ash programming; pulled-up internally reset_n 2 external reset input; pulled-up internally (active low) v ss(rtc) 3 real time clock oscillator ground xout_rtc 4 real time clock crystal output xin_rtc 5 real time clock crystal input or external clock input v dd(rtc) 6 real time clock oscillator supply voltage v ss(osc) 7 oscillator ground xout_osc 8 oscillator crystal output xin_osc 9 oscillator crystal input or external clock input v dd(osc_pll) 10 oscillator and pll supply voltage v ss(pll) 11 pll ground p0[31]/sdo0 12 gpio 0; pin 31 gpio 0; pin 31 spi0 sdo spi0 sdo p0[30]/sdi0 13 gpio 0; pin 30 gpio 0; pin 30 spi0 sdi spi0 sdi p0[29]/sck0 14 gpio 0; pin 29 gpio 0; pin 29 spi0 sck spi0 sck p0[28]/scs0 15 gpio 0; pin 28 gpio 0; pin 28 spi0 scs spi0 scs v ss(io) 16 i/o pins ground p0[27]/sdo1 17 gpio 0; pin 27 gpio 0; pin 27 spi1 sdo spi1 sdo v dd(core) 18 core supply voltage 1.8 v v ss(core) 19 digital core ground p0[26]/sdi1 20 gpio 0; pin 26 gpio 0; pin 26 spi1 sdi spi1 sdi p0[25]/sck1 21 gpio 0; pin 25 gpio 0; pin 25 spi1 sck spi1 sck
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 6 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers p0[24]/scs1 22 gpio 0; pin 24 gpio 0; pin 24 spi1 scs spi1 scs v dd(io) 23 i/o pins supply voltage 3.3 v p0[23]/sdo2/a[23] 24 gpio 0; pin 23 spi2 sdo ext bus a23 ext bus a23 p0[22]/sdi2/a[22] 25 gpio 0; pin 22 spi2 sdi ext bus a22 ext bus a22 p0[21]/sck2/a[21] 26 gpio 0; pin 21 spi2 sck ext bus a21 ext bus a21 p0[20]/scs2/a[20] 26 gpio 0; pin 20 spi2 scs ext bus a20 ext bus a20 v ss(io) 28 i/o pins ground p0[19]/a[19] 29 gpio 0; pin 19 gpio 0; pin 19 ext bus a19 ext bus a19 p0[18]/a[18] 30 gpio 0; pin 18 gpio 0; pin 18 ext bus a18 ext bus a18 p0[17]/a[17] 31 gpio 0; pin 17 gpio 0; pin 17 ext bus a17 ext bus a17 p0[16]/a[16] 32 gpio 0; pin 16 gpio 0; pin 16 ext bus a16 ext bus a16 v dd(io) 33 i/o pins supply voltage 3.3 v p0[15]/a[15] 34 gpio 0; pin 15 gpio 0; pin 15 ext bus a15 ext bus a15 p0[14]/a[14] 35 gpio 0; pin 14 gpio 0; pin 14 ext bus a14 ext bus a14 tdi 36 test data input; pulled-up internally tdo 37 test data output p0[13]/a[13] 38 gpio 0; pin 13 gpio 0; pin 13 ext bus a13 ext bus a13 p0[12]/a[12] 39 gpio 0; pin 12 gpio 0; pin 12 ext bus a12 ext bus a12 v ss(io) 40 i/o pins ground p0[11]/a[11] 41 gpio 0; pin 11 gpio 0; pin 11 ext bus a11 ext bus a11 p0[10]/a[10] 42 gpio 0; pin 10 gpio 0; pin 10 ext bus a10 ext bus a10 p0[9]/a[9] 43 gpio 0; pin 9 gpio 0; pin 9 ext bus a9 ext bus a9 p0[8]/a[8] 44 gpio 0; pin 8 gpio 0; pin 8 ext bus a8 ext bus a8 v dd(io) 45 i/o pins supply voltage 3.3 v p0[7]/a[7] 46 gpio 0; pin 7 gpio 0; pin 7 ext bus a7 ext bus a7 p0[6]/a[6] 47 gpio 0; pin 6 gpio 0; pin 6 ext bus a6 ext bus a6 p0[5]/a[5] 48 gpio 0; pin 5 gpio 0; pin 5 ext bus a5 ext bus a5 p0[4]/a[4] 49 gpio 0; pin 4 gpio 0; pin 4 ext bus a4 ext bus a4 v ss(io) 50 i/o pins ground p0[3]/a[3] 51 gpio 0; pin 3 gpio 0; pin 3 ext bus a3 ext bus a3 p0[2]/a[2] 52 gpio 0; pin 2 gpio 0; pin 2 ext bus a2 ext bus a2 p0[1]/a[1] 53 gpio 0; pin 1 gpio 0; pin 1 ext bus a1 ext bus a1 v ss(core) 54 digital core ground v dd(core) 55 core supply voltage 1.8 v p0[0]/a[0] 56 gpio 0; pin 0 gpio 0; pin 0 ext bus a0 ext bus a0 v dd(io) 57 i/o pins supply voltage 3.3 v p2[29]/cs0 58 gpio 2; pin 29 gpio 2; pin 29 ext bus cs0 ext bus cs0 p2[28]/cs1 59 gpio 2; pin 28 gpio 2; pin 28 ext bus cs1 ext bus cs1 p2[27]/ei3/cs2 60 gpio 2; pin 27 extint3 ext bus cs2 ext bus cs2 p2[26]/ei2/cs3 61 gpio 2; pin 26 extint2 ext bus cs3 ext bus cs3 table 2: lqfp144 pin assignment continued symbol pin description default function function 1 function 2 function 3
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 7 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers p2[25]/ei1 62 gpio 2; pin 25 gpio 2; pin 25 extint1 extint1 p2[24]/ei0 63 gpio 2; pin 24 gpio 2; pin 24 extint0 extint0 p2[23]/cap1[0]/mat1[0] 64 gpio 2; pin 23 gpio 2; pin 23 timer1 cap0 timer1 mat0 p2[22]/cap2[0]/mat2[0] 65 gpio 2; pin 22 gpio 2; pin 22 timer2 cap0 timer2 mat0 v dd(adc) 66 adc supply voltage and high reference level vrefn 67 adc low reference level ai3 68 analog input for channel 3 and channel 7 ai2 69 analog input for channel 2 and channel 6 ai1 70 analog input for channel 1 and channel 5 ai0 71 analog input for channel 0 and channel 4 trst_n 72 test reset input; pulled-up internally (active low) v ss(io) 73 i/o pins ground p2[21]/rxdl0 74 gpio 2; pin 21 gpio 2; pin 21 lin0 rxdl lin0 rxdl p2[20]/txdl0 75 gpio 2; pin 20 gpio 2; pin 20 lin0 txdl lin0 txdl p2[19]/rxd/rxdl1 76 gpio 2; pin 19 uart rxd lin1 rxdl lin1 rxdl p2[18]/txd/txdl1 77 gpio 2; pin 18 uart txd lin1 txdl lin1 txdl p2[17]/rxdl2/rxdc5 78 gpio 2; pin 17 lin2 rxdl can5 rxdc can5 rxdc p2[16]/txdl2/txdc5 79 gpio 2; pin 16 lin2 txdl can5 txdc can5 txdc p2[15]/rxdl3/rxdc4 80 gpio 2; pin 15 lin3 rxdl can4 rxdc can4 rxdc p2[14]/txdl3/txdc4 81 gpio 2; pin 14 lin3 txdl can4 txdc can4 txdc v dd(io) 82 i/o pins supply voltage 3.3 v p2[13]/rxdc3 83 gpio 2; pin 13 gpio 2; pin 13 can3 rxdc can3 rxdc p2[12]/txdc3 84 gpio 2; pin 12 gpio 2; pin 12 can3 txdc can3 txdc p2[11]/rxdc2 85 gpio 2; pin 11 gpio 2; pin 11 can2 rxdc can2 rxdc p2[10]/txdc2 86 gpio 2; pin 10 gpio 2; pin 10 can2 txdc can2 txdc p2[9]/rxdc1 87 gpio 2; pin 9 gpio 2; pin 9 can1 rxdc can1 rxdc p2[8]/txdc1 88 gpio 2; pin 8 gpio 2; pin 8 can1 txdc can1 txdc p2[7]/rxdc0 89 gpio 2; pin 7 gpio 2; pin 7 can0 rxdc can0 rxdc v ss(core) 90 digital core ground v dd(core) 91 core supply voltage 1.8 v p2[6]/txdc0 92 gpio 2; pin 6 gpio 2; pin 6 can0 txdc can0 txdc v ss(io) 93 i/o pins ground p2[5]/bls3 94 gpio 2; pin 5 gpio 2; pin 5 ext bus bls3 ext bus bls3 p2[4]/bls2 95 gpio 2; pin 4 gpio 2; pin 4 ext bus bls2 ext bus bls2 p2[3]/bls1 96 gpio 2; pin 3 gpio 2; pin 3 ext bus bls1 ext bus bls1 p2[2]/bls0 97 gpio 2; pin 2 gpio 2; pin 2 ext bus bls0 ext bus bls0 p2[1]/we_n 98 gpio 2; pin 1 gpio 2; pin 1 ext bus wen ext bus wen p2[0]/oe_n 99 gpio 2; pin 0 gpio 2; pin 0 ext bus oen ext bus oen v dd(io) 100 i/o pins supply voltage 3.3 v p1[0]/d[0] 101 gpio 1; pin 0 gpio 1; pin 0 ext bus d0 ext bus d0 table 2: lqfp144 pin assignment continued symbol pin description default function function 1 function 2 function 3
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 8 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers p1[1]/d[1] 102 gpio 1; pin 1 gpio 1; pin 1 ext bus d1 ext bus d1 p1[2]/d[2] 103 gpio 1; pin 2 gpio 1; pin 2 ext bus d2 ext bus d2 p1[3]/d[3] 104 gpio 1; pin 3 gpio 1; pin 3 ext bus d3 ext bus d3 v ss(io) 105 i/o pins ground p1[4]/d[4] 106 gpio 1; pin 4 gpio 1; pin 4 ext bus d4 ext bus d4 p1[5]/d[5] 107 gpio 1; pin 5 gpio 1; pin 5 ext bus d5 ext bus d5 tms 108 test mode select input; pulled-up internally tck 109 test clock input p1[6]/d[6] 110 gpio 1; pin 6 gpio 1; pin 6 ext bus d6 ext bus d6 p1[7]/d[7] 111 gpio 1; pin 7 gpio 1; pin 7 ext bus d7 ext bus d7 v dd(io) 112 i/o pins supply voltage 3.3 v p1[8]/d[8] 113 gpio 1; pin 8 gpio 1; pin 8 ext bus d8 ext bus d8 p1[9]/d[9] 114 gpio 1; pin 9 gpio 1; pin 9 ext bus d9 ext bus d9 p1[10]/d[10] 115 gpio 1; pin 10 gpio 1; pin 10 ext bus d10 ext bus d10 p1[11]/d[11] 116 gpio 1; pin 11 gpio 1; pin 11 ext bus d11 ext bus d11 v ss(io) 117 i/o pins ground p1[12]/d[12] 118 gpio 1; pin 12 gpio 1; pin 12 ext bus d12 ext bus d12 p1[13]/d[13] 119 gpio 1; pin 13 gpio 1; pin 13 ext bus d13 ext bus d13 p1[14]/d[14] 120 gpio 1; pin 14 gpio 1; pin 14 ext bus d14 ext bus d14 p1[15]/d[15] 121 gpio 1; pin 15 gpio 1; pin 15 ext bus d15 ext bus d15 v dd(io) 122 i/o pins supply voltage 3.3 v p1[16]/cap3[3]/d[16]/mat3[3] 123 gpio 1; pin 16 timer3 cap3 ext bus d16 timer3 mat3 p1[17]/cap3[2]/d[17]/mat3[2] 124 gpio 1; pin 17 timer3 cap2 ext bus d17 timer3 mat2 p1[18]/cap3[1]/d[18]/mat3[1] 125 gpio 1; pin 18 timer3 cap1 ext bus d18 timer3 mat1 v dd(core) 126 core supply voltage 1.8 v v ss(core) 127 digital core ground p1[19]/cap3[0]/d[19]/mat3[0] 128 gpio 1; pin 19 timer3 cap0 ext bus d19 timer3 mat0 v ss(io) 129 i/o pins ground p1[20]/cap2[3]/d[20]/mat2[3] 130 gpio 1; pin 20 timer2 cap3 ext bus d20 timer2 mat3 p1[21]/cap2[2]/d[21]/mat2[2] 131 gpio 1; pin 21 timer2 cap2 ext bus d21 timer2 mat2 p1[22]/cap2[1]/d[22]/mat2[1] 132 gpio 1; pin 22 timer2 cap1 ext bus d22 timer2 mat1 p1[23]/cap1[3]/d[23]/mat1[3] 133 gpio 1; pin 23 timer1 cap3 ext bus d23 timer1 mat3 v dd(io) 134 i/o pins supply voltage 3.3 v p1[24]/cap1[2]/d[24]/mat1[2] 134 gpio 1; pin 24 timer1 cap2 ext bus d24 timer1 mat2 p1[25]/cap1[1]/d[25]/mat1[1] 136 gpio 1; pin 25 timer1 cap1 ext bus d25 timer1 mat1 p1[26]/cap0[3]/d[26]/mat0[3] 137 gpio 1; pin 26 timer0 cap3 ext bus d26 timer0 mat3 p1[27]/cap0[2]/d[27]/mat0[2] 138 gpio 1; pin 27 timer0 cap2 ext bus d27 timer0 mat2 v ss(io) 139 i/o pins ground p1[28]/cap0[1]/d[28]/mat0[1] 140 gpio 1; pin 28 timer0 cap1 ext bus d28 timer0 mat1 p1[29]/cap0[0]/d[29]/mat0[0] 141 gpio 1; pin 29 timer0 cap0 ext bus d29 timer0 mat0 table 2: lqfp144 pin assignment continued symbol pin description default function function 1 function 2 function 3
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 9 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 7. functional description 7.1 reset and power-up behavior the SJA2020 contains an external reset input and an internal power-up reset circuitry. this circuitry ensures a reset is internally extended until oscillators, pll and flash have reached a stable state. see section 12 for characteristics of the several start-up and initialization times. t ab le 3 shows the reset pin. 7.2 jtag interface and debug pins the SJA2020 contains boundary scan test logic according to ieee 1149.1, in this document further referred to as jtag. the jtag pins can be used to connect a debugger probe for the embedded arm processor. pin jtagsel selects between the boundary scan mode and debug mode. see user manual for more information (see ref . 1 ). t ab le 4 shows the jtag pins. 7.3 power supply pins description t ab le 5 shows the power supply pins. see user manual (see ref . 1 ) for more information on physical constraints and board design issues. p1[30]/rtck/d[30] 142 gpio 1; pin 30 rtck ext bus d30 ext bus d30 p1[31]/d[31] 143 gpio 1; pin 31 gpio 1; pin 31 ext bus d31 ext bus d31 v dd(io) 144 i/o pins supply voltage 3.3 v table 2: lqfp144 pin assignment continued symbol pin description default function function 1 function 2 function 3 table 3: reset pin symbol direction description reset_n in external reset input, active low; pulled-up internally table 4: jtag and debug interface symbol direction description jtagsel in tap controller select input; low level selects arm debug mode and high level selects boundary scan and ?ash programming; pulled-up internally trst_n in test reset input; pulled-up internally (active low) tms in test mode select input; pulled-up internally tdi in test data input, pulled-up internally tdo out test data output tck in test clock input rtck out synchronized arm debug return clock output (multiplexed with other functions on a device pin, see section 6 )
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 10 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 7.4 clock architecture as can be seen in figure 3 , the SJA2020 is partitioned into so called subsystems or blocks. the subsystems concept allows the several functional parts to be con?gured individually with respect to the power mode that is used in each of them. subsystems and or blocks are grouped into clock-domains. in this way clocks can be switched on or off and the response to sleep/wake-up events can be set per clock domain. in section 8.3.1 these features are described in more detail. figure 3 gives a simpli?ed view of how the SJA2020 is split into several clock-domains. table 5: power supplies symbol description v dd(core) core supply voltage 1.8 v v ss(core) core ground v dd(io) i/o supply voltage 3.3 v v ss(io) i/o ground v dd(osc_pll) oscillator and pll supply voltage 1.8 v v ss(osc) oscillator ground v dd(rtc) real time clock oscillator supply voltage 1.8 v v ss(rtc) real time clock oscillator ground v dd(adc) adc supply voltage 3.3 v v ss(pll) pll ground
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 11 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 7.5 memory maps arm7 processors have 4 gb address space. the SJA2020 has divided this memory space into 8 regions of 512 mb each. each region is used for a dedicated purpose. an exception to this is region 0; several of the other regions (or a part of it) can be shadowed in the memory map at this region. this shadowing can be controlled by software via the programmable re-mapping registers. figure 4 gives a graphical overview of the SJA2020 memory map. fig 3. clock domains in the SJA2020 001aac565 embedded flash memory up to 384 kb flash controller can lin vic spi scu watchdog timer event router adc rtc clock generation unit timers gpio uart in-vehicle networking subsystem peripheral subsystem general subsystem 2 0 1 3 arm7tdmi-s external memory controller embedded sram memory 24 kb sram controller
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 12 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 7.5.1 region 0: remap area the arm7tdmi-s processor has its exception vectors located at address logic 0. since ?ash is the only non-volatile memory available in the SJA2020, the exception vectors in the ?ash must be located at address logic 0 after reset. memory re-mapping from ?ash to sram is therefore introduced to improve performance. to enable memory re-mapping, the SJA2020 ahb system memory map provides a shadow area (region 0) starting at address logic 0. this is a virtual memory region, i.e. no actual memory is present at the shadow area addresses. a selectable region of the ahb system memory map is, apart from its own speci?c region, also accessible via this shadow area region. after reset, the region 1 embedded ?ash area is always available at the shadow area. after booting, any other region of the ahb system memory map (e.g. internal sram) can be re-mapped to region 0 by means of the shadow memory mapping register. for more details about the shadow area see section 8.3.2.4 . 7.5.2 region 1: embedded ?ash area figure 5 gives a graphical overview of the embedded ?ash memory map. fig 4. ahb system memory map graphical overview 001aaa167 region 7 bus peripherals region 6 (not used) region 5 external static memory controller region 4 (not used) region 3 internal sram region 1 embedded flash region 2 (not used) region 0 shadow area 3 gb c000 0000h e000 0000h a000 0000h 4 gb ffff ffffh 2 gb 8000 0000h 1 gb 6000 0000h 4000 0000h 2000 0000h 0000 0000h embedded flash region shadowed after reset programmable selection of shadowed region via re-map registers
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 13 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers region 1 is reserved for the embedded ?ash. for each embedded ?ash instance a data area of 2 mb (to be prepared for larger ?ash memory instance) and a con?guration area of 4 kb are reserved. although the SJA2020 contains only one embedded ?ash instance, the memory aperture per embedded ?ash instance is de?ned at 4 mb. 7.5.3 region 2: not used 7.5.4 region 3: internal sram area figure 6 gives a graphical overview of the internal sram memory map. address: 2000 0000h to 3fff ffffh. fig 5. region 1 embedded ?ash memory 001aaa168 1fff ffffh 0040 0000h 0020 0000h 0004 6000h (offset address) flash if1 data transfer area (384 kb) 0000 0000h flash if1 configuration area (4 kb) 0020 0fffh
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 14 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers region 3 is reserved for internal sram. for each internal sram instance a data area of 512 kb is reserved. although the SJA2020 has only one internal sram instance, the memory aperture per internal sram instance is de?ned at 512 kb. address: 6000 0000h to 7fff ffffh. fig 6. region 3 internal sram memory 001aaa169 1fff ffffh 0000 8000h 0000 6000h (offset address) internal sram interface 1 data transfer area (24 kb) 0000 0000h 0008 0000h internal sram interface 1 shadowed lower data area (8 kb) internal sram interface 1 (reserved for increased data area) internal sram interface 2 to n (not used)
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 15 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 7.5.5 region 4: not used 7.5.6 region 5: static memory controller area figure 7 gives a graphical overview of the static memory controller memory map. address: a000 0000h to bfff ffffh. fig 7. region 5 static memory controller 001aaa170 0400 0000h 0100 0000h (offset address) memory bank 0 (16 mb) 0000 0000h shadow memory bank 0 (16 mb) shadow memory bank 0 (16 mb) shadow memory bank 0 (16 mb) 0500 0000h memory bank 1 (16 mb) shadow memory bank 1 (16 mb) shadow memory bank 1 (16 mb) shadow memory bank 1 (16 mb) 0c00 0000h 0900 0000h memory bank 2 (16 mb) 0800 0000h shadow memory bank 2 (16 mb) shadow memory bank 2 (16 mb) shadow memory bank 2 (16 mb) 1000 0000h 0d00 0000h memory bank 3 (16 mb) shadow memory bank 3 (16 mb) shadow memory bank 3 (16 mb) shadow memory bank 3 (16 mb) 1fff f000h 1fff ffffh memory bank 4 to 7 (not used) configuration area (4 kb)
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 16 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers region 5 is reserved for the static memory controller. the SJA2020 provides i/o pins for 4 bank select signals and 24 address lines. this implies that 4 memory banks of 16 mb each can be externally addressed. due to the static memory controller hardware con?guration, each bank of 16 mb data area is mirrored four times in a 64 mb region memory map. the static memory controller con?guration area is located on top of region 5. 7.5.7 region 6: not used 7.5.8 region 7: bus peripherals area figure 8 gives a graphical overview of the bus peripherals area memory map. region 7 is reserved for all stand-alone memory mapped register interfaces. examples of such peripherals are dtl target modules connected to the ahb bus via ahb2dtl adapters and vpb peripherals connected via ahb2vpb bridges. the lower part of region 7 is again divided into vpb clusters. a vpb cluster is typically used as the address space for a set of vpb peripherals connected to a single ahb2vpb bridge, the slave on the ahb system bus. the clusters are aligned on 128 kb boundaries. in the SJA2020 three vpb clusters are in use. the vpb peripherals are aligned on 4 kb boundaries inside the vpb clusters. address: e000 0000h to ffff ffffh. fig 8. region 7 bus peripherals area memory 001aaa171 (offset address) vectored interrupt controller mmio area (not used) vpb cluster 5 to n (not used) vpb cluster 4 (ivn subsystem) vpb cluster 3 (not used) vpb cluster 1 (not used) vpb cluster 2 (peripheral subsystem) vpb cluster 0 (general subsystem) 1fff 0000h 000a 0000h 1fff ffffh 0008 0000h 0006 0000h 0004 0000h 0002 0000h 0000 0000h
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 17 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the upper part of region 7 is used as the memory area where memory mapped register interfaces of stand-alone ahb peripherals reside. each of these peripherals will be a slave on the ahb system bus. in the SJA2020 only one of such slave is present: the interrupt controller. it is a dtl target connected to the ahb system bus via an ahb2dtl adapter. 7.5.9 memory map concepts operation the basic concept on the SJA2020 is that each memory area has a natural location in the memory map. this is the address range for which code residing in that area is written. each memory space remains permanently ?xed in the same location, eliminating the need to have portions of the code designed to run in different address ranges. because of the location of the interrupt vectors on the arm7 processor (at addresses 0000 0000h through 0000 001ch) (see t ab le 6 ), the embedded ?ash, internal sram or even external memories can be re-mapped to the shadow memory area in order to allow alternative uses of interrupts in the different operating modes. after reset, the embedded ?ash is re-mapped into the shadow memory area by default. the SJA2020 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or not used address region and unassigned peripheral spaces. for these areas, both attempted data access and instruction fetch generate an exception. note that write access address should be word aligned in arm code or halfword aligned in thumb code. byte aligned writes are performed as word or halfword aligned writes without error signalling. within the address space of an existing peripheral, a data abort exception is not generated in response to an access to an unde?ned address. address decoding within each peripheral is limited to that needed to distinguish de?ned registers within the peripheral itself. details of address aliasing within a peripheral space are not de?ned in the SJA2020 documentation and are not a supported feature. note that the arm stores the prefetch abort ?ag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. this prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary. t ab le 7 gives the base address overview of all peripherals. table 6: interrupt vectors address table address exception 0000 0000h reset 0000 0004h unde?ned instruction 0000 0008h software interrupt 0000 000ch prefetch abort (instruction fetch memory fault) 0000 0010h data abort (data access memory fault) 0000 0014h reserved 0000 0018h irq 0000 001ch fiq
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 18 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 7: peripherals base address overview base address base name ahb peripherals memory region 0 to 6 0000 0000h shadow area memory 2000 0000h embedded ?ash memory 2020 0000h fmc regbase embedded ?ash controller con?guration registers 6000 0000h internal sram memory a000 0000h external static memory bfff f000h smc regbase static memory controller con?guration registers vpb cluster 0: general subsystem e000 0000h cgu regbase clock generation unit e000 1000h scu regbase system control unit e000 2000h spi regbase spi 0 e000 3000h spi regbase spi 1 e000 4000h spi regbase spi 2 e000 5000h adc regbase adc e000 6000h wd regbase watchdog e000 8000h er regbase event router e000 a000h rtc regbase real time clock vpb cluster 2: peripheral subsystem e004 0000h timer regbase timer 0 e004 1000h timer regbase timer 1 e004 2000h timer regbase timer 2 e004 3000h timer regbase timer 3 e004 4000h uart regbase 16c550 uart e004 5000h gpio regbase general purpose i/o 0 e004 6000h gpio regbase general purpose i/o 1 e004 7000h gpio regbase general purpose i/o 2 vpb cluster 4: in-vehicle networking subsystem e008 0000h canc regbase can controller 0 e008 1000h canc regbase can controller 1 e008 2000h canc regbase can controller 2 e008 3000h canc regbase can controller 3 e008 4000h canc regbase can controller 4 e008 5000h canc regbase can controller 5 e008 6000h canafm regbase can id-look-up table memory e008 7000h canafr regbase can acceptance ?lter registers e008 8000h cancs regbase can central status registers e008 9000h lin regbase lin master controller 0 e008 a000h lin regbase lin master controller 1 e008 b000h lin regbase lin master controller 2
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 19 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8. block description 8.1 flash memory controller 8.1.1 overview the flash memory controller (fmc) interfaces to the embedded ?ash memory with two tasks: ? providing memory data transfer ? memory con?guration via triggering, programming and erasing the ?ash memory has a 128-bit wide data interface and the ?ash controller offers two 128-bit buffer lines to improve the system performance. initially, the ?ash has to be programmed via jtag. in-system programming must be supported by the boot loader. in-application programming is possible. the ?ash memory contents can be protected by disabling the jtag access. suspending of burning or erasing is not supported. the key features are: ? programming by cpu via ahb ? programming by external programmer via jtag ? jtag access protection ? burn-?nished and erased-?nished interrupt after reset, the ?ash initialization is started which takes t init time. during this initialization ?ash access is not possible and ahb transfers to the ?ash are stalled, thus blocking the ahb bus. during the ?ash initialization, the index sector is read to identify the status of the jtag access protection and sector security. in case the jtag access protection is active, the ?ash is not accessible via jtag anymore and the arm debug facilities have been disabled to protect the ?ash memory contents against unwanted reading out externally. if the sector security is active, the concerning sector is read only. the ?ash can be read synchronously or asynchronously to the system clock. in synchronous operation, the ?ash goes into standby after returning the read data. started reads cannot be stopped and therefore speculative reading and dual buffering is not supported. with asynchronous reading, the transfer of the address to the ?ash, and read data from the ?ash are done asynchronously, yielding in the fastest possible response time. started reads can be stopped and therefore speculative reading and dual buffering is supported. e008 c000h lin regbase lin master controller 3 vector interrupt controller ffff f000h vic regbase vectored interrupt controller table 7: peripherals base address overview continued base address base name ahb peripherals
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 20 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers buffering is offered because the ?ash has a 128-bit wide data interface, while the ahb interface has only 32 bits. with buffering, a buffer line holds the complete 128 bits ?ash word, from which 4 words can be read. without buffering, every ahb data port read starts a ?ash read. a ?ash read is a slow process compared to the minimum ahb cycle time. with buffering, the average read time is reduced which can improve the system performance. with single buffering, the most recently read ?ash word stays available until the next ?ash read. when an ahb data port read transfer requires data from the same ?ash word as the previous read transfer, no new ?ash read is done, and the read data is given without wait cycles. when an ahb data port read transfer requires data from a different ?ash word as the previous read transfer, a new ?ash read is done, and wait states are given until the new read data is available. with dual buffering, a secondary buffer line is used. the output of the ?ash is considered as the primary buffer. on a primary buffer hit, data can be copied to the secondary buffer line, which allows the ?ash to start a speculative read of the next ?ash word. both buffer lines are invalidated after: ? initialization ? con?guration register access ? data latch reading ? index sector reading the modes of operation are listed in t ab le 8 . table 8: flash read modes buffering con?guration bit characteristics and features fs_ dcr fs_ cache byp cache2 en special ways synchronous timing no buffer line 0 1 x x for single (non linear) reads, one ?ash word read per word read single buffer line 0 0 x x default mode of operation; most recently read ?ash word is kept until another ?ash word is required asynchronous timing no buffer line 1 1 x x one ?ash word read per word read single buffer line 1 0 0 x most recently read ?ash word is kept until another ?ash word is required dual buffer line, single speculative 1 0 1 0 on a buffer miss, a ?ash read is done, followed by at most one speculative read; optimized for execution of code with small loops (< 8 words) from ?ash dual buffer line, always speculative 1 0 1 1 most recently used ?ash word is copied into second buffer line, next ?ash word read is started; highest performance for linear reads
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 21 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.2 flash memory controller pin description the ?ash memory controller has no external pins. 8.1.3 flash memory layout the arm processor can program the ?ash for isp and iap. note that the ?ash always has to be programmed by ?ash words (of 128-bit). the ?ash memory is organized in equal sectors of 8 kb that must be erased before data can be written into them. the ?ash memory also has sector wise protection. writing occurs per page which consists of 4096 bits (32 ?ash words). thus a sector contains 16 pages. t ab le 9 and t ab le 10 give an overview of the ?ash sector and page addressing. table 9: flash sector overview sector number sector base address 0 0000 0000h 1 0000 2000h 2 0000 4000h 3 0000 6000h 4 0000 8000h 5 0000 a000h 6 0000 c000h 7 0000 e000h 8 0001 0000h 9 0001 2000h 10 0001 4000h 11 0001 6000h 12 0001 8000h 13 0001 a000h 14 0001 c000h 15 0001 e000h 16 0002 0000h 17 0002 2000h 18 0002 4000h 19 0002 6000h 20 0002 8000h 21 0002 a000h 22 0002 c000h 23 0002 e000h 24 0003 0000h 25 0003 2000h 26 0003 4000h 27 0003 6000h 28 0003 8000h
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 22 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the index sector is a special sector in which the jtag access protection and sector security are located. the address space becomes visible by setting the fs_iss bit and overlaps the regular ?ash sectors address space. 29 0003 a000h 30 0003 c000h 31 0003 e000h 32 0004 0000h 33 0004 2000h 34 0004 4000h 35 0004 6000h 36 0004 8000h 37 0004 a000h 38 0004 c000h 39 0004 e000h 40 0005 0000h 41 0005 2000h 42 0005 4000h 43 0005 6000h 44 0005 8000h 45 0005 a000h 46 0005 c000h 47 0005 e000h table 10: page addressing overview page number page base address 0 0000 0000h 1 0000 0200h 2 0000 0400h 3 0000 0600h 4 0000 0800h 5 0000 0a00h 6 0000 0c00h 7 0000 0e00h 8 0000 1000h 9 0000 1200h 10 0000 1400h 11 0000 1600h 12 0000 1800h 13 0000 1a00h 14 0000 1c00h 15 0000 1e00h table 9: flash sector overview continued sector number sector base address
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 23 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers note that the index sector can not be erased and access to index sector has to be performed via code outside the ?ash. 8.1.4 register mapping the ?ash memory controller registers are shown in t ab le 11 . the ?ash memory controller registers have an offset to the base address fmc regbase which can be found in the memory map (see t ab le 7 ). table 11: flash memory controller register summary address offset type reset value name description reference 000h r/w 0005h fctr ?ash control register see t ab le 12 004h - - reserved reserved register; do not modify 008h r/w 0000h fptr ?ash program time register see t ab le 13 00ch - - reserved reserved register; do not modify 010h r/w c004h fbwst ?ash bridge wait state register see t ab le 14 014h - - reserved reserved register; do not modify 018h - - reserved reserved register; do not modify 01ch r/w 000h fcra ?ash clock divider register see t ab le 15 020h r/w 0000h fmsstart ?ash bist start address register see t ab le 16 024h r/w 0 0000h fmsstop ?ash bist stop address register see t ab le 17 028h - - reserved reserved register; do not modify 02ch r - fmsw0 ?ash 128-bit signature word 0 register see t ab le 18 030h r - fmsw1 ?ash 128-bit signature word 1 register see t ab le 19 034h r - fmsw2 ?ash 128-bit signature word 2 register see t ab le 20 038h r - fmsw3 ?ash 128-bit signature word 3 register see t ab le 21 fd8h w - int_clr_enable ?ash clear interrupt enable register see t ab le 27 fdch w - int_set_enable ?ash set interrupt enable register see t ab le 26 fe0h r 0h int_status ?ash interrupt status register see t ab le 22 fe4h r 0h int_enable ?ash interrupt enable register see t ab le 25 fe8h w - int_clr_status ?ash clear interrupt status register see t ab le 24 fech w - int_set_status ?ash set interrupt status register see t ab le 23
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 24 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.5 flash control register (fctr) the ?ash control register is used to select read modes, and to control the programming of the ?ash memory. the ?ash has data latches to store the data that is to be programmed into the ?ash. instead of reading the ?ash contents, the data latch contents of the ?ash can be read. data latch reading is always done without buffering, with the programmed number of wait states (wst) on every beat of the burst. data latch reading can be done both synchronously and asynchronously. data latch reading is selected with the fs_rld bit. index sector reading is always done without buffering, with the programmed number of wait states (wst) on every beat of the burst. index sector reading can be done both synchronously and asynchronously. index sector reading is selected with the fs_iss bit. t ab le 12 shows the bit assignment of the fctr register. table 12. fctr register bit description legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; do not modify, read as logic 0, write as logic 0 15 fs_loadreq r/w data load request 1 the ?ash is written if fs_wre has been set; the data load is automatically triggered after the last word was written to the load register; this bit is automatically cleared and thus always read as logic 0 0* 14 fs_cacheclr r/w buffer line clear 1 all bits of the data transfer register are set 0* 13 fs_cachebyp r/w buffering bypass 1 reading from ?ash is without buffering 0* the read buffering is active 12 fs_progreq r/w programming request 1 ?ash programming is requested 0* 11 fs_rls r/w select sector latches for reading 1 the sector latches are read 0* the ?ash array is read 10 fs_pdl r/w preset data latches 1 all bits in the data latches are set 0* 9 fs_pd r/w power down 1 the ?ash is in power down 0* the ?ash is not in power down 8 reserved - - reserved; do not modify, write as logic 0, read as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 25 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.6 flash program time register (fptr) the ?ash program time register controls the timer for burning and erasing the ?ash memory. it also allows to read the remaining burn or erase time. the erase time to be programmed can be calculated from the following formula: the burn time to be programmed can be calculated from the following formula: t ab le 13 shows the bit assignment of the fptr register. 7 fs_wpb r/w program and erase protection 1 program and erase have been enabled 0* program and erase have been disabled 6 fs_iss r/w index sector selection 1 the index sector will be read 0* the ?ash array will be read 5 fs_rld r/w read data latches 1 the data latches are read for veri?cation of data that is loaded to be programmed 0* the ?ash array is read 4 fs_dcr r/w dc read mode 1 asynchronous reading has been selected 0* synchronous reading has been selected 3 reserved - - reserved; do not modify, write as logic 0, read as logic 0 2 fs_web r/w program and erase enable 1* program and erase have been disabled 0 program and erase have been enabled 1 fs_wre r/w program and erase selection 1 program and data load have been selected 0* erase has been selected 0 fs_cs r/w ?ash chip select 1* the ?ash is active 0 the ?ash is in standby table 12. fctr register bit description continued legend: * reset value bit symbol access value description tr t er t sec () 512 t clk sys () --------------------------------- = tr t wr pg () 512 t clk sys () --------------------------------- =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 26 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.7 flash bridge wait states register (fbwst) the ?ash bridge wait states register controls the number of wait states that is inserted for ?ash read transfers. this register also controls the second buffer line for asynchronous reading. to eliminate the delay that is associated with synchronizing the ?ash read data, a prede?ned number of wait states has to be programmed which depends on the ?ash response time and the system clock period. the minimum wait states value wst can be calculated with the following formulas: ? synchronous reading: ? asynchronous reading: in case the programmed number of wait states is more than three, ?ash data reading cannot be performed at full speed if speculative reading is active. t ab le 14 shows the bit assignment of the fbwst register. table 13. fptr register bit description legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; do not modify, read as logic 0, write as logic 0 15 en_t r/w program timer enable 1 the ?ash program timer has been enabled 0* the ?ash program timer has been disabled 14 to 0 tr[14:0] r/w 0000h* program timer; the (remaining) burn and erase time is 512 tr clock cycles table 14. fbwst register bit description legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; do not modify, read as logic 0, write as logic 0 15 cache2en r/w dual buffering enable 1* the second buffer line has been enabled 0 the second buffer line has been disabled 14 specalways r/w speculative reading 1* always speculative reading is performed 0 single speculative reading is performed 13 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 wst[7:0] r/w 04h* number of wait states; contains the number of wait states to be inserted for ?ash reading; the minimum calculated value must be programmed for proper ?ash read operation wst t aclk () t clk sys () ----------------- - 1 C > wst t aa () t clk sys () ----------------- - 1 C >
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 27 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.8 flash clock divider register (fcra) the ?ash clock divider register controls the clock divider for the ?ash program and erase clock cra. this clock should be programmed to 66 khz during burning or erasing. the cra clock frequency fed to the ?ash memory is the system clock frequency divided by 3 (fcra + 1). the programmed value must result in a cra clock frequency of 66 khz 20 %. t ab le 15 shows the bit assignment of the fcra register. 8.1.9 flash bist control registers (fmsstart and fmsstop) the ?ash bist control registers control the embedded bist signature generation via the bist start address register fmsstart and the bist stop address register fmsstop. a signature can be generated for any part of the ?ash contents. the address range to be used for the generation is de?ned by writing the start address to the bist start address register and the stop address to the bist stop address register. the bist start and stop addresses must be ?ash word aligned and can be derived from the ahb byte addresses through division by 16. the signature generation is started by setting the bist start bit in the bist stop address register. setting the bist start bit is typically combined with de?ning the signature stop address. note that the ?ash access is blocked during the bist signature calculation. the duration of the ?ash bist is see section 12 for t ?(bist) . t ab le 16 and t ab le 17 show the bit assignment of the fmsstart and fmsstop registers, respectively. table 15. fcra register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 0 fcra[11:0] r/w 000h* clock divider setting; when logic 0, no cra clock is fed to the ?ash memory table 16. fmsstart register bit description legend: * reset value bit symbol access value description 31 to 17 reserved - - reserved; do not modify, read as logic 0, write as logic 0 16 to 0 fmsstart[16:0] r/w 0 0000h* bist start address (corresponds to ahb byte address [20:4]) t bist t fl bist () 3 + t clk sys () () fmsstop fmsstart C 1 + () =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 28 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.10 flash bist signature registers (fmsw0, fmsw1, fmsw2 and fmsw3) the ?ash bist signature registers return the signatures as produced by the embedded signature generator. there i s a a 128-bit signature re?ected by the four registers fmsw0, fmsw1, fmsw2 and fmsw3. the generated signature by the ?ash can be used to verify the ?ash contents. the generated signature can be compared with an expected signature and makes the more time and code consuming procedure of reading back all contents super?uous. t ab le 18 , t ab le 19 , t ab le 20 and t ab le 21 show the bit assignment of the fmsw0 and fmsw1, fmsw2, fmsw3 registers, respectively. 8.1.11 flash interrupt status register (int_status) the ?ash interrupt status register shows the active interrupt requests. the corresponding interrupt enable needs to be set. the int_status is read only. t ab le 22 shows the bit assignment of the int_status register. table 17. fmsstop register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 misr_start r/w bist start 1 the bist signatures generation is initiated 0* 16 to 0 fmsstop[16:0] r/w 0 0000h* bist stop address (corresponds to ahb byte address [20:4]) table 18. fmsw0 register bit description legend: * reset value bit symbol access value description 31 to 0 fmsw0[31:0] r - ?ash bist 128-bit signature (bits 31 to 0) table 19. fmsw1 register bit description legend: * reset value bit symbol access value description 31 to 0 fmsw1[63:32] r - ?ash bist 128-bit signature (bits 63 to 32) table 20. fmsw2 register bit description legend: * reset value bit symbol access value description 31 to 0 fmsw2[95:64] r - ?ash bist 128-bit signature (bits 95 to 64) table 21. fmsw3 register bit description legend: * reset value bit symbol access value description 31 to 0 fmsw3[127:96] r - ?ash bist 128-bit signature (bits 127 to 96)
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 29 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.12 flash set interrupt status (int_set_status) the ?ash set interrupt status register sets the bits in the ?ash interrupt status register. the int_set_status register is write only. t ab le 23 shows the bit assignment of the int_set_status register. 8.1.13 flash clear interrupt status (int_clr_status) the ?ash clear interrupt status register clears the bits in the ?ash interrupt status register. the int_clr_status register is write only. t ab le 24 shows the bit assignment of the int_clr_status register. table 22. int_status register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0 2 end_of_misr r signature interrupt 1 the bist signature generation has ?nished or logic 1 is written to bit int_set_status[2] 0* no interrupt is pending or logic 1 is written to bit int_clr_status[2] 1 end_of_burn r burn interrupt 1 the page burning has ?nished or logic 1 is written to bit int_set_status[1] 0* no interrupt is pending or logic 1 is written to bit int_clr_status[1] 0 end_of_erase r erase interrupt 1 the erasing of one or more sectors has ?nished or logic 1 is written to bit int_set_status[0] 0* no interrupt is pending or logic 1 is written to bit int_clr_status[0] table 23. int_set_status register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as write 2 to 0 int_set_status[2:0] w - 1 the corresponding bit in the ?ash interrupt status register is set 0 the corresponding bit in the ?ash interrupt status register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 30 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.14 flash interrupt enable (int_enable) the ?ash interrupt enable register determines when the ?ash interface gives an interrupt request if the corresponding interrupt enable has been set. the int_enable register is read only. t ab le 25 shows the bit assignment of the int_enable register. 8.1.15 flash set interrupt enable (int_set_enable) the ?ash set interrupt enable register sets the bits in the ?ash interrupt enable register. the int_set_enable register is write only. t ab le 26 shows the bit assignment of the int_set_enable register. table 24. int_clr_status register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as write 2 to 0 int_clr_status[2:0] w - 1 the corresponding bit in the ?ash interrupt status register is cleared 0 the corresponding bit in the ?ash interrupt status register is unchanged table 25. int_enable register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0 2 end_of_misr r bist signature interrupt enable 1 bit int_set_enable[2] is set to enable the bist signature interrupt 0* bit int_clr_enable[2] is reset to disable the interrupt 1 end_of_burn r bist signature interrupt enable 1 bit int_set_enable[1] is set to enable the bist signature interrupt 0* bit int_clr_enable[1] is reset to disable the interrupt 0 end_of_erase r bist signature interrupt enable 1 bit int_set_enable[0] is set to enable the bist signature interrupt 0* bit int_clr_enable[0] is reset to disable the interrupt
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 31 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.1.16 flash clear interrupt enable (int_clr_enable) the ?ash clear interrupt enable register clears the bits in the ?ash interrupt enable register. the int_clr_enable register is write only. t ab le 27 shows the bit assignment of the int_clr_enable register. 8.2 static memory controller 8.2.1 overview the static static memory controller (smc) provides an interface for external (off-chip) memory devices. the key features are: ? supports static memory-mapped devices including ram, rom, ?ash, burst rom and external i/o devices ? asynchronous page mode read operation in non-clocked memory subsystems ? asynchronous burst mode read access to burst mode rom devices ? independent con?guration for up to 4 banks, each up to 16 mb ? programmable bus turnaround (idle) cycles (1 to 16) ? programmable read and write wait states (up to 32), for static ram devices ? programmable initial and subsequent burst read wait state, for burst rom devices ? programmable write protection ? programmable burst mode operation ? programmable external data width: 8 bits, 16 bits or 32 bits ? programmable read byte lane enable control table 26. int_set_enable register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as write 2 to 0 set_enable[2:0] w - 1 the corresponding bit in the ?ash interrupt enable register is set 0 the corresponding bit in the ?ash interrupt enable register is unchanged table 27. int_clr_enable register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as write 2 to 0 clr_enable[2:0] w - 1 the corresponding bit in the ?ash interrupt enable register is cleared 0 the corresponding bit in the ?ash interrupt enable register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 32 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the static memory controller supports up to four independently con?gurable memory banks simultaneously. each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting sram, rom, ?ash eprom, burst rom memory or external i/o devices. a separate chip select output is available for each bank. the chip select lines are con?gurable to be active high or low. the memory bank selection is controlled by memory addressing. t ab le 28 shows the address mapping for the external memory banks; see also figure 7 . 8.2.2 external memory controller pin description the external memory controller module in the SJA2020 has the following pins. the pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 29 shows the external memory controller pins. 8.2.3 register mapping the static memory controller memory banks con?guration registers are shown in t ab le 30 . the memory banks con?guration registers have an offset to the base address smc regbase which can be found in the memory map (see t ab le 7 ). table 28. external memory bank address bit description bit symbol description 31 to 29 ba[2:0] external static memory base address; the base address can be found in the memory map (see t ab le 7 ). 28 - reserved; write as logic 0 27 to 26 cs[1:0] chip select address space for 4 memory banks 00: bank 0 01: bank 1 10: bank 2 11: bank 3 25 to 24 - reserved; write as logic 0 23 to 0 a[23:0] 16 mb memory banks address space table 29: external memory controller pins symbol direction description extbus csx out memory bank x select, x runs from 0 to 3 extbus blsy out byte lane select y, y runs from 0 to 3 extbus we_n out write enable (active low) extbus oe_n out output enable (active low) extbus a[23:0] out address bus extbus d[31:0] in/out data bus
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 33 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 30: static memory controller register summary address offset type width reset value name description reference bank 0 000h r/w 4 fh smbidcyr0 idle cycle control register for memory bank 0 see t ab le 31 004h r/w 5 1fh smbwst1r0 wait state 1 control register for memory bank 0 see t ab le 32 008h r/w 5 1fh smbwst2r0 wait state 2 control register for memory bank 0 see t ab le 33 00ch r/w 4 0h smbwstoenr0 output enable assertion delay control register for memory bank 0 see t ab le 34 010h r/w 4 1h smbwstwenr0 write enable assertion delay control register for memory bank 0 see t ab le 35 014h r/w 8 80h smbcr0 con?guration register for memory bank 0 see t ab le 36 018h r/w 2 0h smbsr0 status register for memory bank 0 see t ab le 37 bank 1 01ch r/w 4 fh smbidcyr1 idle cycle control register for memory bank 1 see t ab le 31 020h r/w 5 1fh smbwst1r1 wait state 1 control register for memory bank 1 see t ab le 32 024h r/w 5 1fh smbwst2r1 wait state 2 control register for memory bank 1 see t ab le 33 028h r/w 4 0h smbwstoenr1 output enable assertion delay control register for memory bank 1 see t ab le 34 02ch r/w 4 1h smbwstwenr1 write enable assertion delay control register for memory bank 1 see t ab le 35 030h r/w 8 00h smbcr1 con?guration register for memory bank 1 see t ab le 36 034h r/w 2 0h smbsr1 status register for memory bank 1 see t ab le 37 bank 2 038h r/w 4 fh smbidcyr2 idle cycle control register for memory bank 2 see t ab le 31 03ch r/w 5 1fh smbwst1r2 wait state 1 control register for memory bank 2 see t ab le 32 040h r/w 5 1fh smbwst2r2 wait state 2 control register for memory bank 2 see t ab le 33 044h r/w 4 0h smbwstoenr2 output enable assertion delay control register for memory bank 2 see t ab le 34 048h r/w 4 1h smbwstwenr2 write enable assertion delay control register for memory bank 2 see t ab le 35 04ch r/w 8 40h smbcr2 con?guration register for memory bank 2 see t ab le 36 050h r/w 2 0h smbsr2 status register for memory bank 2 see t ab le 37 bank 3 054h r/w 4 fh smbidcyr3 idle cycle control register for memory bank 3 see t ab le 31 058h r/w 5 1fh smbwst1r3 wait state 1 control register for memory bank 3 see t ab le 32 05ch r/w 5 1fh smbwst2r3 wait state 2 control register for memory bank 3 see t ab le 33 060h r/w 4 0h smbwstoenr3 output enable assertion delay control register for memory bank 3 see t ab le 34 064h r/w 4 1h smbwstwenr3 write enable assertion delay control register for memory bank 3 see t ab le 35 068h r/w 8 00h smbcr3 con?guration register for memory bank 3 see t ab le 36 06ch r/w 2 0h smbsr3 status register for memory bank 3 see t ab le 37
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 34 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.2.4 bank idle cycle control registers (smbidcyr) the bank idle cycle control register con?gures the external bus turn around cycles between read and write memory accesses to avoid bus contention on the external memory data bus. the bus turn-around wait time is inserted between external bus transfers in case of: ? read-to-read, to different memory banks ? read-to-write, to the same memory bank ? read-to-write, to different memory banks t ab le 31 shows the bit assignment of the smbidcyr0 to smbidcyr3 registers. 8.2.5 bank wait state 1 control registers (smbwst1r) the bank wait state 1 control register con?gures the external transfer wait states in read accesses. the bank con?guration register contains the enable and polarity setting for the external wait. the minimum wait states value wst1 can be calculated from the following formula: where: t a(r)int = internal read access time, see section 12 . t d(r)em = external memory read delay. t ab le 32 shows the bit assignment of the smbwst1r0 to smbwst1r3 registers. table 31. smbidcyrn register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 0 idcy[3:0] r/w fh* idle or turn-around cycles; this register contains the number of bus turn-around cycles added between read and write accesses; the turn-round time is the programmed number of cycles times the system clock period table 32. smbwst1rn register bit description legend: * reset value bit symbol access value description 31 to 5 reserved - - reserved; do not modify, read as logic 0, write as logic 0 4 to 0 wst1[4:0] r/w 1fh* wait state 1; this register contains the length of read accesses, except for burst rom where it de?nes the length of the ?rst read access only; the read access time is the programmed number of wait states times the system clock period wst1 t ar () int t dr () em + t clk sys () --------------------------------------- - 1 C =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 35 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.2.6 bank wait state 2 control registers (smbwst2r) the bank wait state 2 control register con?gures the external transfer wait states in write accesses or the external transfer wait states in burst read accesses. the bank con?guration register contains the enable and polarity setting for the external wait. sequential access burst reads from burst ?ash devices of the same type of as for burst rom are supported. due to sharing of the smbwst2r register between write and burst read transfers, it is only possible to have one setting at a time for burst ?ash, either write delay or the burst read delay. this means that for write transfer the smbwst2r register must be programmed with the write delay value, and for a burst read transfer the smbwst2r register must be programmed with the burst access delay. the minimum wait states value wst2 can be calculated from the following formula: where: t a(w)int = internal write access time, see section 12 . t d(w)em = external memory write delay. t ab le 33 shows the bit assignment of the smbwst2r0 to smbwst2r3 registers. 8.2.7 bank output enable assertion delay control register (smbwstoenr) the bank output enable assertion delay control register con?gures the delay between the assertion of the chip select and the output enable. this delay is used to reduce the power consumption for memories that are not able to provide valid data immediately after the chip select is asserted. the programmed value must be equal to, or less than the bank wait state 1 programmed value, as the access is timed by the wait states. the output enable is always de-asserted at the same time as the chip select, at the end of the transfer. the bank con?guration register contains the enable for output assertion delay. t ab le 34 shows the bit assignment of the smbwstoenr register. table 33. smbwst2rn register bit description legend: * reset value bit symbol access value description 31 to 5 reserved - - reserved; do not modify, read as logic 0, write as logic 0 4 to 0 wst2[4:0] r/w 1fh* wait state 2; this register contains the length of write accesses, except for burst rom where it de?nes the length of the burst read accesses; the write access time c.q. the burst rom read access time is the programmed number of wait states times the system clock period wst2 t aw () int t dw () em + t clk sys () ------------------------------------------ 1 C =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 36 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.2.8 bank write enable assertion delay control register (smbwstwenr) the bank write enable assertion delay control register con?gures the delay between the assertion of the chip select and the write enable. this delay is used to reduce the power consumption for memories. the programmed value must be equal to, or less than the bank wait state 2 programmed value, as the access is timed by the wait states. the write enable is asserted half a system clock cycle after the assertion of the chip select for logic 0 wait states. the write enable is de-asserted half a system clock cycle before the chip select, at the end of the transfer. the byte lane select outputs have the same timing as the write enable output for writes to 8-bit devices that use the byte lane selects instead of the write enables. the bank con?guration register contains the enable for output assertion delay. t ab le 35 shows the bit assignment of the smbwstwenr register. 8.2.9 bank con?guration register (smbcr) the bank con?guration register de?nes the memory bank access for the connected memory device. it is allowed to initiate a wider data transfer to the external memory than the width of the external memory data bus. in this case the external transfer is automatically split up into several transfers to complete. t ab le 36 shows the bit assignment of the smbcr register. table 34. smbwstoenr register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 0 wstoen r/w 0h* output enable assertion delay; this register contains the length of the output enable delay after the chip select assertion; the output enable assertion delay time is the programmed number of wait states times the system clock period table 35. smbwstwenr register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 0 wstwen r/w 1h* write enable assertion delay; this register contains the length of the write enable delay after the chip select assertion; the write enable assertion delay time is the programmed number of wait states times the system clock period table 36. smbcr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 37 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.2.10 bank status register (smbsr) the bank status register re?ects the status ?ags of each memory bank. t ab le 37 shows the bit assignment of the smbsr register. 7 to 6 mw[1:0] r/w bank default* memory width; memory width con?guration including the default memory width after reset 00 8-bit, bank 3 and bank 1 reset (default) 01 16-bit, bank 2 reset (default) 10 32-bit, bank 0 reset (default) 11 reserved 5 bm r/w burst mode 1 sequential access burst reads to a maximum of four consecutive locations is supported to increase the bandwidth by using reduced access time; however, bursts crossing quad boundaries are split up so that the ?rst transfer after the boundary uses the slow wait state 1 read timing 0* the memory bank is con?gured for nonburst memory 4 wp r/w write protect 1 the connected device is write protected e.g. (burst) rom, read only ?ash, or sram 0* no write protection is required e.g. sram or write enabled ?ash 3 cspol r/w chip select polarity 1 the chip select input is active high 0* the chip select input is active low 2 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 rble r/w read byte lane enable 1 the byte lane select pins are held asserted (logic 0) during a read access; this is for 16-bit or 32-bit devices where the separate write enable signal is used and the byte lane selects must be held asserted during a read; the write enable pin wen is used as the write enable in this con?guration 0* the byte lane select pins blsn are all de-asserted (logic 1) during a read access; this is for 8-bit devices where the byte lane enable is connected to the write enable pin, so it must be de-asserted during a read access (default at reset); the byte lane select pins are used as write enables in this con?guration table 36. smbcr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 38 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3 general subsystem 8.3.1 clock generation unit 8.3.1.1 overview the key features are: ? power mode management ? reset control ? control oscillator ? control pll ? fractional clock divider for adc clock ? watchdog bark register 8.3.1.2 description the clock generation unit con?gures all internal clocks. there are four options for the source for the system clock: ? crystal/external oscillator ? pll ? ring oscillator (ringo) ? real time clock furthermore, the control of the oscillators and pll takes part here, generally also used for power mode management. the clock switching between the several sources is performed in a safe way (glitch free). 8.3.1.3 cgu pin description the cgu module in the SJA2020 has the following pins. t ab le 38 shows the cgu pins. table 37. smbsr register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 writeproterr r/w write protect error 1 a write access to a write protected memory device was initiated; writing logic 1 to this register clears the write protect status ?ag 0* writing a logic 0 has no effect 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 39 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.4 register mapping the clock generation unit registers are shown in t ab le 39 . the clock generation unit registers have an offset to the base address cgu regbase which can be found in the memory map (see t ab le 7 ). note: any clock frequency adjustment has direct impact on the timing of on-board peripherals such as uart, spi, watchdog, timers, can controller, lin master controller, adc, ?ash memory interface. table 38: cgu pins symbol direction description reset_n in external reset input, active low; pulled-up internally xout_osc out oscillator crystal output xin_osc in oscillator crystal input or external clock input table 39: cgu register summary address type reset value name description reference 000h r/w 1h csc clock switch con?guration register see t ab le 40 004h r/w 0h cfs1 clock frequency select 1 register see t ab le 41 008h r/w 0h cfs2 clock frequency select 2 register see t ab le 41 00ch r 1h css clock switch status register see t ab le 43 010h r/w 1h cpc0 ahb clock power control register see t ab le 44 014h r/w 1h cpc1 ?ash clock power control register see t ab le 44 018h r/w 1h cpc2 general and peripheral subsystem clock power control register see t ab le 44 01ch r/w 1h cpc3 in-vehicle networking subsystem clock power control register see t ab le 44 020h r/w 0h cpc4 adc clock power control register see t ab le 44 024h - - reserved reserved register; do not modify 028h r 3h cps0 ahb clock power status register see t ab le 46 02ch r 3h cps1 ?ash clock power status register see t ab le 46 030h r 3h cps2 general and peripheral subsystem clock power status register see t ab le 46 034h r 3h cps3 in-vehicle networking subsystem clock power status register see t ab le 46 038h r 2h cps4 adc clock power status register see t ab le 46 03ch - - reserved reserved register; do not modify 040h - - reserved reserved register; do not modify 044h - - reserved reserved register; do not modify 048h - - reserved reserved register; do not modify 04ch - - reserved reserved register; do not modify 050h r/w 0h cfce4 adc fractional clock enable register see t ab le 47 054h - - reserved reserved register; do not modify 058h r/w 7ffc 3fech cfd fractional clock divider register see t ab le 48
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 40 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.5 clock switch con?guration register (csc) the clock switch con?guration register con?gures the side of the clock switch to be used as the system clock. there are two clock switch sides to avoid clock glitches when switching between the four clock source inputs: the oscillator frequency, the pll frequency, the ringo and the real time clock. t ab le 40 shows the bit assignment of the csc register. c00h r/w 1h cpm power mode register see t ab le 49 c04h r 0h cwdb watchdog bark register see t ab le 51 c08h r/w 1h crtcopm real time clock oscillator power mode register see t ab le 52 c0ch - - reserved reserved register; do not modify c10h r/w 1h copm oscillator power mode register see t ab le 53 c14h - - reserved reserved register; do not modify c18h r 1h cols oscillator lock status register see t ab le 54 c1ch - - reserved reserved register; do not modify c20h - - reserved reserved register; do not modify c24h - - reserved reserved register; do not modify c28h - - reserved reserved register; do not modify c2ch - - reserved reserved register; do not modify c30h - - reserved reserved register; do not modify c34h - - reserved reserved register; do not modify c38h - - reserved reserved register; do not modify c3ch - - reserved reserved register; do not modify c40h r/w 0h cpcss pll clock source select register see t ab le 55 c44h r/w 1h cppdm pll power-down mode register see t ab le 56 c48h - - reserved reserved register; do not modify c4ch r 0h cpls pll lock status register see t ab le 57 c50h - - reserved reserved register; do not modify c54h r/w 0h cpmr pll multiplication ratio register see t ab le 58 c58h r/w 0h cppd pll post divider register see t ab le 60 c5ch r/w 0h crpm ring oscillator power mode register see t ab le 62 c60h r/w 18h crpd ring oscillator post divider register see t ab le 63 c64h r/w 5h crfs ring oscillator frequency select register see t ab le 65 table 39: cgu register summary continued address type reset value name description reference table 40. csc register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 41 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.6 clock frequency select registers (cfs1 and cfs2) the clock frequency select registers determines the input clock source of side 1 and side 2 respectively of the frequency switch. t ab le 41 shows the bit assignment of the cfs1 and cfs2 registers. 8.3.1.7 clock switch status register (css) the clock switch status control register represents the selected input clock source and clock switch status. t ab le 43 shows the bit assignment of the css register. 1 to 0 enf r/w switch select 3h reserved, do not use 2h the clock switch uses side 2 as source clock 1h* the clock switch uses side 1 as source clock 0h reserved, do not use table 40. csc register bit description continued legend: * reset value bit symbol access value description table 41. cfs1 and cfs2 register bit assignment legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 to 0 fs1 for cfs1 fs2 for cfs2 r/w 0h* input frequency select; see t ab le 42 table 42: input clock frequency sources fs[1:0] function 00 oscillator frequency 01 pll frequency 10 ring oscillator frequency (ringo) 11 rtc frequency table 43. css register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 2 fss r 0h* frequency select status; see t ab le 42 1 to 0 fs_select r switch select 3h reserved 2h the clock switch uses side 2 as source clock 1h* the clock switch uses side 1 as source clock 0h reserved
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 42 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.8 clock power control registers (cpc0, cpc1, cpc2, cpc3 and cpc4) the ahb clock power control register (cpc0) con?gures the clock operation for the arm processor, sram and static memory controller. the ?ash clock power control register (cpc1) con?gures the clock operation for the ?ash. the general and peripheral subsystem clock power control register (cpc2) con?gures the clock operation for the general subsystem, the peripheral subsystem and the modulation and sampling control subsystem. the in-vehicle networking subsystem clock power control register (cpc3) con?gures the clock operation for the in-vehicle networking subsystem vpb cluster. the adc clock power control register (cpc4) con?gures the clock operation for the adc. t ab le 44 shows the bit assignment of the cpc registers. 8.3.1.9 clock power status registers (cps0, cps1, cps2, cps3 and cps4) the ahb clock power status register (cps0) re?ects the operational status of the clock for the arm processor, sram and static memory controller. table 44. cpc register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0, write as logic 0 2 to 1 wake r/w 0h* wake mode; see t ab le 45 0 in cpc0 reserved - 1* reserved; do not modify, read as logic 1, write as logic 1 0 in cpc1 run r/w run enable 1* the clock is enabled 0 the clock is disabled 0 in cpc2 reserved - 1* reserved; do not modify, read as logic 1, write as logic 1 0 in cpc3 run r/w run enable 1* the clock is enabled 0 the clock is disabled 0 in cpc4 run r/w run enable 1 the clock is enabled 0* the clock is disabled table 45: wake mode con?guration bits pm[1:0] function 00 wake up disabled, the clock is not switched off when entering a low power mode and not switched on an a wake up event 01 unsupported, results in unpredicted behavior 10 unsupported, results in unpredicted behavior 11 wake up enabled, the clock is switched off when entering a low power mode and switched on an a wake up event
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 43 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the ?ash clock power status register (cps1) re?ects the operational status of the clock for the ?ash. the general and peripheral subsystem clock power status register (cps2) re?ects the operational status of the clock for the general and peripheral subsystem vpb clusters. the in-vehicle networking subsystem clock power status register (cps3) re?ects the operational status of the clock for the in-vehicle networking subsystem vpb cluster. the adc clock power status register (cps4) re?ects the operational status of the clock for the adc. t ab le 46 shows the bit assignment of the cps0 register. 8.3.1.10 fractional clock enable register (cfce4) the fractional clock enable register con?gures the fractional clock as clock source instead of the clock from the selected switch side. the fractional clock is only targeted for the adc. t ab le 47 shows the bit assignment of the cfce4 register. 8.3.1.11 fractional clock divider register (cfd) the fractional clock divider register determines the clock input frequency for the adc which may be maximum 4.5 mhz for correct operation. table 46. cps register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 wakeup r wake up 1* the wake up condition is activated 0 the wake up condition is not activated 0 active r 1* for cps0, cps1, cps2 and cps3; 0* for cps4 active 1 the clock is functional 0 the clock is not functional table 47. cfce4 register bits legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 fce r/w fractional clock enable 1 the fractional clock is the clock source 0* the clock from the selected switch side is the clock source
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 44 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the adc clock frequency is determined by the following formula: to minimize the power consumption the values for n and m should be selected as large as possible. note that the system clock frequency is at least twice adc clock frequency: t ab le 48 shows the bit assignment of the cfd register. 8.3.1.12 power mode register (cpm) the power mode register con?gures the operation mode and wake up mechanism. t ab le 49 shows the bit assignment of the cpm register. table 48. cfd register bit description legend: * reset value bit symbol access value description 31 reserved - - reserved; do not modify, read as logic 0, write as logic 0 30 to 17 msub[13:0] r/w 3ffeh* fractional clock divider parameter msub; signed value de?ned by ( - n) 16 to 3 madd[13:0] r/w 07fdh* fractional clock divider parameter madd; unsigned value de?ned by (m - n) 2 stretch r/w clock stretching 1* must be set to logic 1 to feed the required approximately 50 % duty cycle clock to the adc 0 1 reset r/w fractional divider reset 1 the fractional clock divider is reset asynchronously; the reset must be active while changing the adc clock frequency 0* 0 en r/w enable 1 the fractional clock divider is running to serve as the adc clock if the adc fractional clock is enabled in the fractional clock enable register 0* f i adc () f clk sys () n m --- - = f i adc () f clk sys () 1 2 -- - table 49. cpm register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 to 0 pm[1:0] r/w 1h* power mode; see t ab le 50
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 45 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.13 watchdog bark register (cwdb) the watchdog bark register indicates whether a system reset was caused by the watchdog or not. this register is cleared only by an external or power-on reset. t ab le 51 shows the bit assignment of the cwdb register. 8.3.1.14 real time clock oscillator power mode register (crtcopm) the real time clock oscillator power mode register can switch off the 32 khz oscillator. this is recommended in case the real time clock is not used. it is not allowed to switch on the real time clock oscillator again once switched off. t ab le 52 shows the bit assignment of the crtcopm register. 8.3.1.15 oscillator power mode register (copm) the oscillator power mode register is used to switch on and off the system oscillator. t ab le 53 shows the bit assignment of the copm register. table 50: power mode con?guration bits pm[1:0] function 00 unsupported 01 normal operation mode, this mode is automatically set after wake-up 10 unsupported, results in unpredicted behavior 11 idle mode, wake-up event results in resume table 51. cwdb register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 wdb r watchdog bark 1 a watchdog reset occurred 0* an external or power-on reset occurred table 52. crtcopm register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 rtcopm r/w real time clock oscillator power mode 1* the 32 khz oscillator is active 0 the 32 khz oscillator is inactive and in power-down mode table 53. copm register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 46 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.16 oscillator lock status register (cols) the oscillator lock status register represents the status of the oscillator clock frequency stability. the lock detector goes high after a delay based on a gray code counter. t ab le 57 shows the bit assignment of the cols register. 8.3.1.17 pll clock source select register (cpcss) the pll clock source select register determines the input frequency for the pll. t ab le 55 shows the bit assignment of the cpcss register. 8.3.1.18 pll power-down mode register (cppdm) the pll power-down mode register is used to switch on and off the pll. the pll must be in power-down mode during con?guration change. t ab le 56 shows the bit assignment of the cppdm register. 0 opm r/w oscillator power mode 1* the oscillator is active 0 the system oscillator is inactive and in power-down mode table 53. copm register bit description continued legend: * reset value bit symbol access value description table 54. cols register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 ols r oscillator lock status 1* the oscillator is locked 0 the oscillator is not in lock or in power-down mode table 55. cpcss register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 pcss r/w pll clock source select 1 the oscillator frequency is the input frequency for the pll 0* no clock is fed to the pll table 56. cppdm register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 ppdm r/w pll power-down mode 1* the pll is inactive and in power-down mode 0 the pll is active
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 47 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.19 pll lock status register (cpls) the pll lock status register represents the status of the pll clock frequency stability. the lock detector measures the phase difference between the rising edges of the input and feedback clocks. only when this difference is smaller than the so called lock criterion for more than eight consecutive input clock periods, the lock output switches from low to high. a single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). requiring eight phase measurements in a row to be below a certain ?gure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. this effectively prevents false lock indications, and thus ensures a glitch free lock signal. t ab le 57 shows the bit assignment of the cpls register. 8.3.1.20 pll multiplication ratio register (cpmr) the pll multiplication ratio register de?nes the ratio between the pll output clock and the input clock. the multiplication ratio can be calculated from the following formula: t ab le 58 shows the bit assignment of the cpmr register. table 57. cpls register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 pls r pll lock status 1 the pll is locked 0* the pll is not in lock or in power-down mode table 58. cpmr register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0, write as logic 0 2 to 0 pmr[2:0] r/w 00h* pll multiplication ratio; see t ab le 59 table 59: multiplication ratio con?guration bits pmr[2:0] function 000 input frequency multiplication by 1 001 input frequency multiplication by 2 010 input frequency multiplication by 3 011 input frequency multiplication by 4 100 input frequency multiplication by 5 101 input frequency multiplication by 6 110 unsupported, results in unpredicted behavior 111 unsupported, results in unpredicted behavior pmr f clk sys () f iosc () ------------------- =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 48 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.21 pll post divider register (cppd) the pll post divider register de?nes division ratio between the pll cco frequency and pll output clock frequency. the post division guarantees an output clock with a 50 % duty cycle. the cco frequency must ful?l the speci?ed limits. the post division ratio can be calculated from the following formula: t ab le 60 shows the bit assignment of the cppd register. 8.3.1.22 ring oscillator power mode register (crpm) the ring oscillator power mode register is used to switch on and off the ring oscillator. figure 9 shows the structure of the ring oscillator. t ab le 62 shows the bit assignment of the crpm register. table 60. cppd register bits legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 to 0 ppd[1:0] r/w 0h* pll post divider; see t ab le 61 table 61: pll post divider con?guration bits ppd[1:0] function 00 post division by 2 01 post division by 4 10 post division by 8 11 post division by 16 ppd f cco f clk sys () ------------------- = fig 9. ring oscillator block diagram table 62. crpm register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 rpm r/w oscillator power mode 1 the ring oscillator is active 0* the ring oscillator is inactive and in power-down mode 001aae433 low power ring oscillator rpm f ref(ro) rfs[3:0] rpd[4:0] f i(ro) f o(ro) frequency select multiply by 0.45 to 1.73 post divider divide by 2 to 64
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 49 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.23 ring oscillator post divider register (crpd) the ring oscillator post divider register de?nes division ratio between the calibrated internal ring oscillator frequency (see section 8.3.1.24 ) and ring oscillator output clock frequency. the post division guarantees an output clock with a 50 % duty cycle. the post division ratio can be calculated from the following formula: t ab le 63 shows the bit assignment of the crpd register. 8.3.1.24 ring oscillator frequency select register (crfs) the ring oscillator frequency select ratio register is used to calibrate the internal ring oscillator frequency f i(ro) to compensate for frequency variation in the internal ring oscillator reference frequency f ref(ro) . see section 12 for the speci?ed range of f ref(ro) . t ab le 65 shows the bit assignment of the crfs register. table 63. crpd register bit description legend: * reset value bit symbol access value description 31 to 5 reserved - - reserved; do not modify, read as logic 0, write as logic 0 4 to 0 rpd[4:0] r/w 18h* ring oscillator post divider; see t ab le 64 table 64: ring oscillator post divider con?guration bits rpd[4:0] function 00000 post division by 2 00001 post division by 4 00010 post division by 6 00011 post division by 8 ... ... 11110 post division by 62 11111 post division by 64 f oro () f iro () 2 rpd 1 + () ----------------------------------- - = table 65. crfs register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 0 rfs[3:0] r/w 5h* ring oscillator frequency select; see t ab le 66 table 66. ring oscillator frequency select con?guration bits rfs[3:0] function 0000 f i(ro) = 0 hz 0001 f i(ro) = f ref(ro) 0.45 0010 f i(ro) = f ref(ro) 0.63 0011 f i(ro) = f ref(ro) 0.77 0100 f i(ro) = f ref(ro) 0.89
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 50 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.2 system control unit 8.3.2.1 overview the system control unit takes care of system related functions. the key features are: ? shadow memory remapping ? con?guration of i/o port pins multiplexer firstly, the mapping of a (partially) region into the shadow memory area. after reset, the ?ash region is shadowed. to increase the overall system performance, (a part of) the internal sram region is advised to shadow for interrupt handling. secondly, the function of each i/o pin. the i/o pin con?guration should be consistent with the peripheral function usage. 8.3.2.2 scu pin description the scu has no external pins. 8.3.2.3 register mapping the system control unit registers are shown in t ab le 67 . the system control unit registers have an offset to the base address scu regbase which can be found in the memory map (see t ab le 7 ). 0101 f i(ro) = f ref(ro) 1.00 0110 f i(ro) = f ref(ro) 1.10 0111 f i(ro) = f ref(ro) 1.18 1000 f i(ro) = f ref(ro) 1.26 1001 f i(ro) = f ref(ro) 1.34 1010 f i(ro) = f ref(ro) 1.41 1011 f i(ro) = f ref(ro) 1.48 1100 f i(ro) = f ref(ro) 1.55 1101 f i(ro) = f ref(ro) 1.61 1110 f i(ro) = f ref(ro) 1.67 1111 f i(ro) = f ref(ro) 1.73 table 66. ring oscillator frequency select con?guration bits continued rfs[3:0] function table 67: scu register summary address type reset value name description reference 00h r/w 2000 0000h ssmm shadow memory mapping register see t ab le 68 04h r/w 0000 0000h sfsap0 function select a port 0 register see t ab le 70 08h r/w 0000 0000h sfsbp0 function select b port 0 register see t ab le 71 0ch r/w 0000 0000h sfsap1 function select a port 1 register see t ab le 70 10h r/w 0000 0000h sfsbp1 function select b port 1 register see t ab le 71 14h r/w 0000 0000h sfsap2 function select a port 2 register see t ab le 70
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 51 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.2.4 shadow memory mapping register (ssmm) the shadow memory mapping register de?nes which part of the memory region is present in the shadow memory area. the shadow memory mapping start address is the pointer within a region indicating the for shadowing in the shadow area starting at location 0000 0000h. in this way a whole region or only a part of the ?ash, sram or external memory bank can be remapped to the shadow area. t ab le 68 shows the bit assignment of the ssmm register. 8.3.2.5 port function select registers (sfsap0 to sfsap2 and sfsbp0 to sfsbp2) the port function select register con?gures the pin functions individually on the corresponding i/o port. the function select a registers de?ne the lower 16 port pins and the function select b registers de?ne the upper 16 port pins. for port 2, the two most upper port pins are reserved. see t ab le 72 to t ab le 74 for the pin function multiplex content. the pin function selection is done with 2 bits in the port function select registers (see t ab le 69 ). t ab le 70 shows the bit assignment of the sfsap0, sfsap1 and sfsap2 registers and t ab le 71 shows the bit assignment of the sfsbp0, sfsbp1 and sfsbp2 registers. at 18h r/w 0000 0000h sfsbp2 function select b port 2 register see t ab le 71 1ch r/w 0000 0000h spucp0 pull-up control port 0 register see t ab le 75 20h r/w 0000 0000h spucp1 pull-up control port 1 register see t ab le 75 24h r/w 0000 0000h spucp2 pull-up control port 2 register see t ab le 75 table 67: scu register summary continued address type reset value name description reference table 68. ssmm register bit description legend: * reset value bit symbol access value description 31 to 10 smmsa[21:0] r/w 2000 0000h* shadow memory map start address; memory start address for mapping (a part of) a region to the shadow area; the start address is aligned on 1 kb boundaries and therefore the lowest 10 bits must be always logic 0 9 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 69: pin function select con?guration bits value bits [1:0] function 00 select pin function 0 from corresponding i/o port con?guration 01 select pin function 1 from corresponding i/o port con?guration 10 select pin function 2 from corresponding i/o port con?guration 11 select pin function 3 from corresponding i/o port con?guration
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 52 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 70. sfsap0, sfsap1 and sfsap2 register bit description legend: * reset value bit symbol access value description 31 to 30 pfsp15[1:0] r/w 0h* port pin 15 function select 29 to 28 pfsp14[1:0] r/w 0h* port pin 14 function select 27 to 26 pfsp13[1:0] r/w 0h* port pin 13 function select 25 to 24 pfsp12[1:0] r/w 0h* port pin 12 function select 23 to 22 pfsp11[1:0] r/w 0h* port pin 11 function select 21 to 20 pfsp10[1:0] r/w 0h* port pin 10 function select 19 to 18 pfsp9[1:0] r/w 0h* port pin 9 function select 17 to 16 pfsp8[1:0] r/w 0h* port pin 8 function select 15 to 14 pfsp7[1:0] r/w 0h* port pin 7 function select 13 to 12 pfsp6[1:0] r/w 0h* port pin 6 function select 11 to 10 pfsp5[1:0] r/w 0h* port pin 5 function select 9 to 8 pfsp41:0] r/w 0h* port pin 4 function select 7 to 6 pfsp3[1:0] r/w 0h* port pin 3 function select 5 to 4 pfsp2[1:0] r/w 0h* port pin 2 function select 3 to 2 pfsp1[1:0] r/w 0h* port pin 1 function select 1 to 0 pfsp0[1:0] r/w 0h* port pin 0 function select table 71. sfsbp0, sfsbp1 and sfsbp2 register bit description legend: * reset value bit symbol access value description 31 to 30 pfsp31[1:0] r/w 0h* port pin 31 function select; reserved for port 2 29 to 28 pfsp30[1:0] r/w 0h* port pin 30 function select; reserved for port 2 27 to 26 pfsp29[1:0] r/w 0h* port pin 29 function select 25 to 24 pfsp28[1:0] r/w 0h* port pin 28 function select 23 to 22 pfsp27[1:0] r/w 0h* port pin 27 function select 21 to 20 pfsp26[1:0] r/w 0h* port pin 26 function select 19 to 18 pfsp25[1:0] r/w 0h* port pin 25 function select 17 to 16 pfsp24[1:0] r/w 0h* port pin 24 function select 15 to 14 pfsp23[1:0] r/w 0h* port pin 23 function select 13 to 12 pfsp22[1:0] r/w 0h* port pin 22 function select 11 to 10 pfsp21[1:0] r/w 0h* port pin 21 function select 9 to 8 pfsp20[1:0] r/w 0h* port pin 20 function select 7 to 6 pfsp19[1:0] r/w 0h* port pin 19 function select 5 to 4 pfsp18[1:0] r/w 0h* port pin 18 function select 3 to 2 pfsp17[1:0] r/w 0h* port pin 17 function select 1 to 0 pfsp16[1:0] r/w 0h* port pin 16 function select
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 53 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 72: port 0 function assignment symbol description default function function 1 function 2 function 3 p0.0 gpio 0; pin 0 gpio 0; pin 0 ext bus a0 ext bus a0 p0.1 gpio 0; pin 1 gpio 0; pin 1 ext bus a1 ext bus a1 p0.2 gpio 0; pin 2 gpio 0; pin 2 ext bus a2 ext bus a2 p0.3 gpio 0; pin 3 gpio 0; pin 3 ext bus a3 ext bus a3 p0.4 gpio 0; pin 4 gpio 0; pin 4 ext bus a4 ext bus a4 p0.5 gpio 0; pin 5 gpio 0; pin 5 ext bus a5 ext bus a5 p0.6 gpio 0; pin 6 gpio 0; pin 6 ext bus a6 ext bus a6 p0.7 gpio 0; pin 7 gpio 0; pin 7 ext bus a7 ext bus a7 p0.8 gpio 0; pin 8 gpio 0; pin 8 ext bus a8 ext bus a8 p0.9 gpio 0; pin 9 gpio 0; pin 9 ext bus a9 ext bus a9 p0.10 gpio 0; pin 10 gpio 0; pin 10 ext bus a10 ext bus a10 p0.11 gpio 0; pin 11 gpio 0; pin 11 ext bus a11 ext bus a11 p0.12 gpio 0; pin 12 gpio 0; pin 12 ext bus a12 ext bus a12 p0.13 gpio 0; pin 13 gpio 0; pin 13 ext bus a13 ext bus a13 p0.14 gpio 0; pin 14 gpio 0; pin 14 ext bus a14 ext bus a14 p0.15 gpio 0; pin 15 gpio 0; pin 15 ext bus a15 ext bus a15 p0.16 gpio 0; pin 16 gpio 0; pin 16 ext bus a16 ext bus a16 p0.17 gpio 0; pin 17 gpio 0; pin 17 ext bus a17 ext bus a17 p0.18 gpio 0; pin 18 gpio 0; pin 18 ext bus a18 ext bus a18 p0.19 gpio 0; pin 19 gpio 0; pin 19 ext bus a19 ext bus a19 p0.20 gpio 0; pin 20 spi2 scs ext bus a20 ext bus a20 p0.21 gpio 0; pin 21 spi2 sck ext bus a21 ext bus a21 p0.22 gpio 0; pin 22 spi2 sdi ext bus a22 ext bus a22 p0.23 gpio 0; pin 23 spi2 sdo ext bus a23 ext bus a23 p0.24 gpio 0; pin 24 gpio 0; pin 24 spi1 scs spi1 scs p0.25 gpio 0; pin 25 gpio 0; pin 25 spi1 sck spi1 sck p0.26 gpio 0; pin 26 gpio 0; pin 26 spi1 sdi spi1 sdi p0.27 gpio 0; pin 27 gpio 0; pin 27 spi1 sdo spi1 sdo p0.28 gpio 0; pin 28 gpio 0; pin 28 spi0 scs spi0 scs p0.29 gpio 0; pin 29 gpio 0; pin 29 spi0 sck spi0 sck p0.30 gpio 0; pin 30 gpio 0; pin 30 spi0 sdi spi0 sdi p0.31 gpio 0; pin 31 gpio 0; pin 31 spi0 sdo spi0 sdo table 73: port 1 function assignment symbol description default function function 1 function 2 function 3 p1.0 gpio 1; pin 0 gpio 1; pin 0 ext bus d0 ext bus d0 p1.1 gpio 1; pin 1 gpio 1; pin 1 ext bus d1 ext bus d1 p1.2 gpio 1; pin 2 gpio 1; pin 2 ext bus d2 ext bus d2 p1.3 gpio 1; pin 3 gpio 1; pin 3 ext bus d3 ext bus d3
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 54 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers p1.4 gpio 1; pin 4 gpio 1; pin 4 ext bus d4 ext bus d4 p1.5 gpio 1; pin 5 gpio 1; pin 5 ext bus d5 ext bus d5 p1.6 gpio 1; pin 6 gpio 1; pin 6 ext bus d6 ext bus d6 p1.7 gpio 1; pin 7 gpio 1; pin 7 ext bus d7 ext bus d7 p1.8 gpio 1; pin 8 gpio 1; pin 8 ext bus d8 ext bus d8 p1.9 gpio 1; pin 9 gpio 1; pin 9 ext bus d9 ext bus d9 p1.10 gpio 1; pin 10 gpio 1; pin 10 ext bus d10 ext bus d10 p1.11 gpio 1; pin 11 gpio 1; pin 11 ext bus d11 ext bus d11 p1.12 gpio 1; pin 12 gpio 1; pin 12 ext bus d12 ext bus d12 p1.13 gpio 1; pin 13 gpio 1; pin 13 ext bus d13 ext bus d13 p1.14 gpio 1; pin 14 gpio 1; pin 14 ext bus d14 ext bus d14 p1.15 gpio 1; pin 15 gpio 1; pin 15 ext bus d15 ext bus d15 p1.16 gpio 1; pin 16 timer3 cap3 ext bus d16 timer3 mat3 p1.17 gpio 1; pin 17 timer3 cap2 ext bus d17 timer3 mat2 p1.18 gpio 1; pin 18 timer3 cap1 ext bus d18 timer3 mat1 p1.19 gpio 1; pin 19 timer3 cap0 ext bus d19 timer3 mat0 p1.20 gpio 1; pin 20 timer2 cap3 ext bus d20 timer2 mat3 p1.21 gpio 1; pin 21 timer2 cap2 ext bus d21 timer2 mat2 p1.22 gpio 1; pin 22 timer2 cap1 ext bus d22 timer2 mat1 p1.23 gpio 1; pin 23 timer1 cap3 ext bus d23 timer1 mat3 p1.24 gpio 1; pin 24 timer1 cap2 ext bus d24 timer1 mat2 p1.25 gpio 1; pin 25 timer1 cap1 ext bus d25 timer1 mat1 p1.26 gpio 1; pin 26 timer0 cap3 ext bus d26 timer0 mat3 p1.27 gpio 1; pin 27 timer0 cap2 ext bus d27 timer0 mat2 p1.28 gpio 1; pin 28 timer0 cap1 ext bus d28 timer0 mat1 p1.29 gpio 1; pin 29 timer0 cap0 ext bus d29 timer0 mat0 p1.30 gpio 1; pin 30 rtck ext bus d30 ext bus d30 p1.31 gpio 1; pin 31 gpio 1; pin 31 ext bus d31 ext bus d31 table 74: port 2 function assignment symbol description default function function 1 function 2 function 3 p2.0 gpio 2; pin 0 gpio 2; pin 0 ext bus oen ext bus oen p2.1 gpio 2; pin 1 gpio 2; pin 1 ext bus wen ext bus wen p2.2 gpio 2; pin 2 gpio 2; pin 2 ext bus bls0 ext bus bls0 p2.3 gpio 2; pin 3 gpio 2; pin 3 ext bus bls1 ext bus bls1 p2.4 gpio 2; pin 4 gpio 2; pin 4 ext bus bls2 ext bus bls2 p2.5 gpio 2; pin 5 gpio 2; pin 5 ext bus bls3 ext bus bls3 p2.6 gpio 2; pin 6 gpio 2; pin 6 can0 txdc can0 txdc p2.7 gpio 2; pin 7 gpio 2; pin 7 can0 rxdc can0 rxdc table 73: port 1 function assignment continued symbol description default function function 1 function 2 function 3
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 55 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.2.6 pull-up control registers (spucp0, spucp1 and spucp2) the pull-up control register con?gures the pull-up per pin on the corresponding i/o port. for port 2, the two most upper port pins are reserved. note that the pull-up must be switched off before a 5 v signal is applied to the respective port pin. t ab le 70 shows the bit assignment of the spucp0, spucp1 and spucp2 registers. [1] puc[31:30] are reserved for port 2. 8.3.3 spi 8.3.3.1 overview three spis are included to enable synchronous serial communication with slave or master peripherals. p2.8 gpio 2; pin 8 gpio 2; pin 8 can1 txdc can1 txdc p2.9 gpio 2; pin 9 gpio 2; pin 9 can1 rxdc can1 rxdc p2.10 gpio 2; pin 10 gpio 2; pin 10 can2 txdc can2 txdc p2.11 gpio 2; pin 11 gpio 2; pin 11 can2 rxdc can2 rxdc p2.12 gpio 2; pin 12 gpio 2; pin 12 can3 txdc can3 txdc p2.13 gpio 2; pin 13 gpio 2; pin 13 can3 rxdc can3 rxdc p2.14 gpio 2; pin 14 lin3 txdl can4 txdc can4 txdc p2.15 gpio 2; pin 15 lin3 rxdl can4 rxdc can4 rxdc p2.16 gpio 2; pin 16 lin2 txdl can5 txdc can5 txdc p2.17 gpio 2; pin 17 lin2 rxdl can5 rxdc can5 rxdc p2.18 gpio 2; pin 18 uart txd lin1 txdl lin1 txdl p2.19 gpio 2; pin 19 uart rxd lin1 rxdl lin1 rxdl p2.20 gpio 2; pin 20 gpio 2; pin 20 lin0 txdl lin0 txdl p2.21 gpio 2; pin 21 gpio 2; pin 21 lin0 rxdl lin0 rxdl p2.22 gpio 2; pin 22 gpio 2; pin 22 timer2 cap0 timer2 mat0 p2.23 gpio 2; pin 23 gpio 2; pin 23 timer1 cap0 timer1 mat0 p2.24 gpio 2; pin 24 gpio 2; pin 24 extint0 extint0 p2.25 gpio 2; pin 25 gpio 2; pin 25 extint1 extint1 p2.26 gpio 2; pin 26 extint2 ext bus cs3 ext bus cs3 p2.27 gpio 2; pin 27 extint3 ext bus cs2 ext bus cs2 p2.28 gpio 2; pin 28 gpio 2; pin 28 ext bus cs1 ext bus cs1 p2.29 gpio 2; pin 29 gpio 2; pin 29 ext bus cs0 ext bus cs0 table 74: port 2 function assignment continued symbol description default function function 1 function 2 function 3 table 75. spucp0, spucp1 and spucp2 register bit description legend: * reset value bit symbol access value description 31 to 0 puc[31:0] [1] r/w 0000 0000h* port pin pull-up control 1 corresponding port pin is ?oating when 3-state 0 corresponding port pin is pulled-up
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 56 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the key features are: ? master or slave operation ? programmable clock bit rate and prescale ? separate transmit and receive ?rst-in, ?rst-out memory buffers, 16-bit wide, 8 locations deep ? programmable choice of interface operation: motorola spi, national semiconductors microwire or texas instruments (synchronous serial) ? programmable data frame size from 4 bits to 16 bits ? independent masking of transmit fifo, receive fifo, and receive overrun interrupts ? internal loopback test mode note that in case the receive fifo is not empty and the serial port remains idle for a ?xed 32-bit period of the system clock, the receive time-out is asserted to ensure proper servicing of the received data. more information about spi can also be found in arm primecell documentation (see ref . 4 ). 8.3.3.2 spi pin description the three spi modules in the SJA2020 have the following pins. the pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 76 shows the spi pins, x runs from 0 to 2. [1] direction depends on master or slave mode. 8.3.3.3 register mapping the spi registers are shown in t ab le 77 . the spi registers have an offset to the base address spi regbase which can be found in the memory map (see t ab le 7 ). table 76: spi pins symbol direction description spix scs in/out [1] spi x chip select spix sck in/out [1] spi x clock spix sdi in spi x data input spix sdo out spi x data output table 77: spi register summary address type reset value name description reference 00h r/w 0000h sspcr0 control register 0 see t ab le 78 04h r/w 0h sspcr1 control register 1 see t ab le 81 08h r/w - sspdr fifo data register see t ab le 82 0ch r 03h sspsr status register see t ab le 83 10h r/w 00h sspcpsr clock prescale register see t ab le 84 14h r/w 0h sspimsc interrupt enable register see t ab le 85
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 57 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.4 spi control register 0 (sspcr0) the spi control register 0 con?gures the spi operation mode. in all modes, the spi clock is only active during transmission and reception of data. the spi clock idle state is utilized to provide time-out indication that occurs when the receive fifo still contains data after a time-out period. t ab le 78 shows the bit assignment of the sspcr0 register. [1] the transmit and receive bit rate is determined by following formula: where: f clk(sys) = system clock frequency; spsdvsr = clock prescale divisor, see t ab le 84 ; scr = serial clock rate, see t ab le 78 . 18h r 8h sspris raw interrupt status register see t ab le 86 1ch r 0h sspmis masked interrupt status register see t ab le 87 20h w 0h sspicr interrupt clear register see t ab le 88 table 77: spi register summary continued address type reset value name description reference table 78. sspcr0 register bit description legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; do not modify, read as logic 0, write as logic 0 15 to 8 scr[7:0] r/w 00h* serial clock rate [1] 7 sph r/w clock phase which is applicable to motorola frame format only; the clock phase bit selects the clock edge that captures data after the chip select scsn becomes active low 1 data is captured on the second clock edge 0* data is captured on the ?rst clock edge 6 spo r/w clock polarity which is applicable to motorola frame format only; the clock polarity bit selects the spi clock steady state level 1 the spi clock output is high when no data is being transferred 0* the spi clock output is low when no data is being transferred 5 to 4 frf[1:0] r/w 0h* frame format; see t ab le 79 3 to 0 dss[2:0] r/w 0h* data size select; see t ab le 80 bit rate f clk sys () spsdvsr 1 scr + () --------------------------------------------------------- - =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 58 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.5 spi control register 1 (sspcr1) the spi control register 1 controls several spi con?guration functions. t ab le 81 shows the bit assignment of the sspcr1 register. table 79: spi frame format con?guration frf[1:0] function 00 motorola spi frame format. full-duplex, 4-wire synchronous transfers; the transmit data line sdon is arbitrarily forced logic 0 if inactive; the chip select line scsn is active logic 0 and is asserted during the entire frame transmission; continuous transfers are separated by a one spi clock period idle (high) state of the chip select line scsn; the clock phase and polarity are programmable 01 texas instruments synchronous serial frame format. full-duplex, 4-wire synchronous transfer; transmit data line sdon is 3-stateable when not transmitting; the chip select line scsn is always pulsed high for one serial clock starting at its rising edge, prior to the transmission of each frame; for this frame format the output data is driven on the rising edge of the spi clock and latches the data on the falling edge 10 national semiconductors microwire frame format. half-duplex transfer using 8-bit control message; the transmit data line sdon is arbitrarily forced logic 0 if inactive; the chip select line scsn is active logic 0 and is asserted during the entire frame transmission; continuous transfers keep the chip select line logic 0; the frame starts with transmitting an 8-bit control message to the slave device; after this message has been sent, the slave device decodes it and, after waiting one serial clock after the 8-bit control message has been sent, responds with the requested data; the returned data can be 4 bits to 16 bits in length, making a total frame length anywhere from 13 bits to 25 bits 11 reserved; unde?ned operation table 80: spi data size select con?guration dss[3:0] function 0000 reserved; unde?ned operation 0001 reserved; unde?ned operation 0010 reserved; unde?ned operation 0011 4-bit data 0100 5-bit data 0101 6-bit data 0110 7-bit data 0111 8-bit data 1000 9-bit data 1001 10-bit data 1010 11-bit data 1011 12-bit data 1100 13-bit data 1101 14-bit data 1110 15-bit data 1111 16-bit data
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 59 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.6 spi fifo data register (sspdr) the spi fifo data register written is 16 bits wide. when read, the data entry in the receive fifo is accessed. when written, the data is written to the entry in the transmit fifo. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores unused bits. received data less than 16 bits is automatically right-justi?ed in the receive buffer; unused bits are unde?ned and should be discarded. when programmed for national semiconductors microwire frame format, the default size for transmit data is eight bits. the receive data size is programmable. the transmit fifo and the receive fifo are not cleared even when the serial port enable bit is set to logic 0. this allows the software to ?ll the transmit fifo before enabling the serial port. t ab le 82 shows the bit assignment of the sspdr register. table 81. sspcr1 register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 sod r/w slave mode output disable; this bit is relevant only in the slave mode (bit ms = 1); in multiple slave systems, it is possible for a master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line; to operate in such systems, the slave output mode bit can be set if the slave is not supposed to drive the data output line 1 the slave must not drive the data output line sdon 0* the slave can drive to data output line sdon 2 ms r/w master or slave mode select; this bit can be modi?ed only when the serial port is disabled (bit sse = 0) 1 the device is con?gured as slave 0* the device is con?gured as master 1 sse r/w synchronous serial port enable 1 the serial port is enabled 0* the serial port is disabled 0 lbm r/w loop back mode; when logic 1 the output of the transmit serial shifter is connected to the input of the receive serial shifter internally; when logic 0, normal serial port operation is enabled 1 the output of the transmit serial shifter is connected to the input of the receive serial shifter internally 0* normal serial port operation is enabled
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 60 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.7 spi status register (sspsr) the spi status register re?ects the fifo status and the serial port busy status. the sps register is read only. t ab le 83 shows the bit assignment of the sps register. 8.3.3.8 spi clock prescale register (sspcpsr) the spi clock prescale register speci?es the system clock frequency prescale division factor. t ab le 84 shows the bit assignment of the sspcpsr register. table 82. sspdr register bit description legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; do not modify, read as logic 0, write as logic 0 15 to 0 data[15:0] r/w - transmit or receive fifo data; when read, data from the receive fifo is accessed; when written, data is written into the transmit fifo table 83. spsr register bit description legend: * reset value bit symbol access value description 31 to 5 reserved - - reserved; do not modify, read as logic 0, write as logic 0 4 bsy r busy ?ag 1 the serial port is transmitting and/or receiving a frame or the transmit fifo is not empty 0* the serial port is idle 3 rff r receive fifo full 1 the receive fifo is full 0* the receive fifo is not full 2 rne r receive fifo not empty 1 the receive fifo is not empty 0* the receive fifo is empty 1 tnf r transmit fifo not full 1* the transmit fifo is not full 0 the transmit fifo is full 0 tfe r transmit fifo empty 1* the transmit fifo is empty 0 the transmit fifo is not empty
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 61 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.9 spi interrupt enable register (sspimsc) the spi interrupt enable register is used to enable the four types of interrupts referred to in the interrupt status register. t ab le 85 shows the bit assignment of the sspimsc register. 8.3.3.10 spi raw interrupt status register (sspris) the spi raw interrupt status register re?ects the raw interrupt status prior to interrupt masking. the sspris register is read only. t ab le 86 shows the bit assignment of the sspris register. table 84. sspcpsr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 spsdvsr r/w 00h* clock prescale divisor; the system clock frequency is divided by the clock prescale value which must be an even number from 2 to 254; the least signi?cant bit always returns logic 0 on reads table 85. sspimsc register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 txim r/w transmit fifo interrupt enable 1 the transmit fifo half empty or less condition interrupt is not masked 0* the transmit fifo half empty or less condition interrupt is masked 2 rxim r/w receive fifo interrupt enable 1 the receive fifo half full or less condition interrupt is not masked 0* the receive fifo half full or less condition interrupt is masked 1 rtim r/w receive time-out interrupt enable 1 the receive fifo not empty and no read prior to time-out period interrupt is not masked 0* the receive fifo not empty and no read prior to time-out period interrupt is masked 0 rorim r/w receive overrun interrupt enable 1 the receive fifo written to while full condition interrupt is not masked 0* the receive fifo written to while full condition interrupt is masked
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 62 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.11 spi masked interrupt status register (sspmis) the spi masked interrupt status register re?ects the masked interrupt status. the sspmis register is read only. t ab le 87 shows the bit assignment of the sspmis register. table 86. sspris register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 txris r transmit fifo raw interrupt status 1* the transmit fifo half empty or less condition interrupt prior to masking has occurred 0 2 rxris r receive fifo raw interrupt status 1 the receive fifo half full or less condition interrupt prior to masking has occurred 0* 1 rtris r receive time-out raw interrupt status 1 the receive fifo not empty and no read prior to time-out period interrupt prior to masking has occurred 0* 0 rorris r receive overrun raw interrupt status 1 the receive fifo written to while full condition interrupt prior to masking has occurred 0* table 87. sspmis register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 txmis r transmit fifo masked interrupt status 1 the transmit fifo interrupt enable was set and the transmit fifo half empty or less condition interrupt has occurred 0* 2 rxmis r receive fifo masked interrupt status 1 the receive fifo interrupt enable was set and the receive fifo half full or less condition interrupt has occurred 0* 1 rtmis r receive time-out masked interrupt status 1 the receive time-out interrupt enable was set and the receive fifo not empty and no read prior to time-out period interrupt has occurred 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 63 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.3.12 spi interrupt clear register (sspicr) the spi interrupt clear register clears the set raw and masked interrupt status. the sspicr register is write only. t ab le 88 shows the bit assignment of the sspmicr register. 8.3.4 watchdog 8.3.4.1 overview the purpose of the watchdog is to reset the arm7 processor within a reasonable amount of time if it enters an erroneous state. the watchdog will generate a system reset if the user program fails to trigger the watchdog correctly within a predetermined amount of time. the key features are: ? internally chip reset if not periodically triggered ? debug mode with interrupt instead of reset ? watchdog time period change protected with access sequence ? programmable 32-bit watchdog timer period the watchdog consists of a 32-bit counter. the clock is directly fed to the timer. the timer increments when clocked. the watchdog should be used in the following manner: ? for debugging purposes the watchdog debug mode in the watchdog mode register should be set before the watchdog has been locked. the debug mode is locked by programming a new watchdog reload value 0 rormis r receive overrun masked interrupt status 1 the receive fifo overrun interrupt enable was set and the receive fifo written to while full condition interrupt has occurred 0* table 87. sspmis register bit description continued legend: * reset value bit symbol access value description table 88. sspicr register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 rtic w receive time-out clear interrupt 1 the raw and masked receive time-out interrupt are cleared 0 writing logic 0 has no effect 0 roric w receive overrun masked interrupt status 1 the raw and masked receive fifo overrun interrupt are cleared 0 writing logic 0 has no effect
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 64 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers ? enable access to the watchdog reload value register by writing aaaa aaaah followed by 5555 5555h ? program the watchdog timer reload value in watchdog reload value register ? trigger the watchdog by writing the watchdog trigger register periodically before the watchdog counter over?ows to generate watchdog interrupts in the watchdog debug mode, the interrupt has to be enabled via the watchdog interrupt status enable register. a watchdog over?ow interrupt can be cleared by writing the watchdog interrupt clear status register. in case a watchdog over?ow occurred in the watchdog debug mode, clearing the watchdog over?ow interrupt is the only way to trigger the watchdog again resulting in restart of counting the programmed watchdog period. if the watchdog interrupt is not enabled in watchdog debug mode, the watchdog can be triggered again by writing the watchdog trigger register. the watchdog is stalled when the ahb clock or the general and peripheral subsystem clock is stopped for entering power saving modes. in this case the watchdog counter value is maintained. therefore, it is recommended to trigger the watchdog before switching off the ahb clock or the general and peripheral subsystem clock to avoid unexpected watchdog reset after leaving power savings modes. a watchdog reset is equal to an external reset: the program counter will start from 0000 0000h and registers are cleared. the clock generation unit contains a watchdog bark register to distinguish between both events. 8.3.4.2 watchdog pin description the watchdog has no external pins. 8.3.4.3 register mapping the watchdog registers are shown in t ab le 89 . the watchdog registers have an offset to the base address wd regbase which can be found in the memory map (see t ab le 7 ). 8.3.4.4 watchdog mode register (wdmod) the watchdog debug bit can be set after reset only before the watchdog reload value has been programmed. after setting this bit, it can always be cleared to enable normal watchdog operation. table 89: watchdog register summary address type reset value name description reference 00h r/w 0h wdmod watchdog mode register see t ab le 90 04h r/w 00ff ffffh wdrv watchdog timer reload value see t ab le 91 08 r/w 0000 0000h wdcv watchdog timer counter value see t ab le 92 0ch w - wdtrig watchdog trigger see t ab le 93 10h w - wdiss watchdog interrupt set status see t ab le 94 14h w - wdics watchdog interrupt clear status see t ab le 95 18h r 0h wdie watchdog interrupt enable see t ab le 96 1ch r 0h wdis watchdog interrupt status see t ab le 97 20h w - wdise watchdog interrupt set enable see t ab le 98 24h w - wdice watchdog interrupt clear enable see t ab le 99
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 65 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers t ab le 90 shows the bit assignment of the wdmod register. 8.3.4.5 watchdog reload value register (wdrv) the watchdog reload value register contains the watchdog value which is reloaded into the watchdog timer on a trigger. the actual watchdog time period depends on the clock frequency. the watchdog reload value register is protected against erroneously changing. programming a new watchdog value is only accepted after the write sequence aaaa aaaah followed by 5555 5555h to this register. t ab le 91 shows the bit assignment of the wdrv register. 8.3.4.6 watchdog counter value register (wdcv) the watchdog counter value register contains the actual watchdog timer counter value. t ab le 92 shows the bit assignment of the wdcv register. table 90. wdmod register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 wdtof r time out ?ag 1 a watchdog time out has occurred in debug mode 0* 2 wdcef r counter enable ?ag 1 the watchdog timer is active 0* the watchdog timer is inactive 1 wddblck r debug lock 1 the watchdog debug mode has been locked and can not be entered again; the lock is activated after writing a new value in watchdog reload value register 0* 0 wddb r/w debug mode 1 a watchdog over?ow results in an interrupt 0* a watchdog over?ow results in a reset; this bit can be reset any time but only be set when the debug lock is not active table 91. wdrv register bit description legend: * reset value bit symbol access value description 31 to 0 wdrv[31:0] r/w 00ff ffffh* watchdog reload value; reading this register shows programmed watchdog value table 92. wdcv register bit description legend: * reset value bit symbol access value description 31 to 0 wdcv[31:0] r 00ff ffffh* watchdog counter value; reading this register shows the current value of the watchdog timer counter
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 66 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.4.7 watchdog trigger register (wdtrig) the watchdog trigger register is used to (re)start the watchdog time-out period as programmed in the watchdog reload value register. t ab le 93 shows the bit assignment of the wdtrig register. 8.3.4.8 watchdog interrupt set status (wdiss) the watchdog interrupt set status register sets the bits in the watchdog interrupt status register. the wdiss register is write only. t ab le 94 shows the bit assignment of the wdiss register. 8.3.4.9 watchdog interrupt clear status (wdics) the watchdog interrupt clear status register clears the bits in the watchdog interrupt status register. the wdics register is write only. t ab le 95 shows the bit assignment of the wdics register. table 93. wdtrig register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 kickdog w watchdog trigger 1 triggers the watchdog resulting in (re)start of counting the programmed watchdog period 0 writing logic 0 has no effect table 94. wdiss register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as write 0 int_set_status[0] w 1 the corresponding bit in the watchdog interrupt status register is set 0 the corresponding bit in the watchdog interrupt status register is unchanged table 95. wdics register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as write 0 int_clr_status[0] w 1 the corresponding bit in the watchdog interrupt status register is cleared 0 the corresponding bit in the watchdog interrupt status register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 67 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.4.10 watchdog interrupt enable (wdie) the watchdog interrupt enable register determines when the watchdog gives an interrupt request if the corresponding interrupt enable has been set. the wdie register is read only. t ab le 96 shows the bit assignment of the wdie register. 8.3.4.11 watchdog interrupt status register (wdis) the watchdog interrupt status register determines when the watchdog gives an interrupt request if the corresponding interrupt enable has been set. the wdis is read only. t ab le 97 shows the bit assignment of the wdis register. 8.3.4.12 watchdog interrupt set enable (wdise) the watchdog interrupt set enable register sets the bits in the watchdog interrupt enable register. the wdise register is write only. t ab le 98 shows the bit assignment of the wdise register. table 96. wdie register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0 0 overflow r watchdog over?ow interrupt enable 1 bit int_set_enable[0] is set to enable the watchdog over?ow interrupt 0* bit int_clr_enable[0] is reset to disable the interrupt table 97. wdis register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0 0 overflow r watchdog over?ow interrupt 1 a watchdog over?ow occurred in watchdog debug mode or logic 1 is written to bit int_set_status[0] 0* no interrupt is pending or logic 1 is written to bit int_clr_status[0] table 98. wdise register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as write 0 set_enable[0] w - 1 the corresponding bit in the watchdog interrupt enable register is set 0 the corresponding bit in the watchdog interrupt enable register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 68 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.4.13 watchdog interrupt clear enable (wdice) the watchdog interrupt clear enable register clears the bits in the watchdog interrupt status enable register. the wdice register is write only. t ab le 99 shows the bit assignment of the wdice register. 8.3.5 analog-to-digital converter 8.3.5.1 overview the SJA2020 includes a 10-bit successive approximation analog-to-digital converter. the basic characteristics of the adc interface module are: ? four dedicated analog inputs for eight channels, selected by an analog multiplexer ? measurement range up to 3.6 v ? 400 ksample/s at 10-bit resolution up to 1500 ksample/s at 2-bit resolution ? programmable resolution from 2 bits to 10 bits ? single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode ? optional conversion on transition on gpio pin, external input or timer capture/match signal ? converted digital values are stored in a register per channel ? power-down mode the adc clock must be less than half the system clock frequency, but is limited to 4.5 mhz as maximum frequency. the clock generation unit provides a programmable fractional system clock divider dedicated for the adc clock to ful?l this constraint or to select the desired lower sampling frequency. the conversion rate is determined by the adc clock frequency divided by the number of resolution bits plus one. accessing adc registers requires an enabled adc clock which is controllable via the clock generation unit. the analog inputs 0 3 are connected to channel 0 3 and 4 7 respectively. 8.3.5.2 adc pin description the adc has the following pins. some pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 100 shows the adc pins. table 99. wdice register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as write 0 clr_enable[0] w - 1 the corresponding bit in the watchdog interrupt enable register is cleared 0 the corresponding bit in the watchdog interrupt enable register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 69 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.5.3 register mapping the adc registers are shown in t ab le 101 . the adc registers have an offset to the base address adc regbase which can be found in the memory map (see t ab le 7 ). 8.3.5.4 adc channel conversion data registers (acd0 to acd7) the SJA2020 contains a conversion data register for each of the eight adc channel inputs. these eight registers store the result of an analog-to-digital conversion scan through all active channels. the selected bit resolution in the adcn (n from 0 to 7) channel con?guration register simultaneously de?nes the number of valid most signi?cant conversion data bits in the adc channel conversion data registers. the remaining conversion data bits become logic 0 accordingly. the acd registers are read only. t ab le 102 shows the bit assignment of the acd registers. table 100: analog-to-digital converter pins symbol direction description vrefn in adc low reference level ai0 in analog input for channel 0 and channel 4 ai1 in analog input for channel 1 and channel 5 ai2 in analog input for channel 2 and channel 6 ai3 in analog input for channel 3 and channel 7 tr0 in adc start trigger 0 input tr1 in adc start trigger 1 input table 101: ad converter register summary address type reset value name description reference 00h r 000h acd0 adc channel 0 conversion data register see t ab le 102 04h r 000h acd1 adc channel 1 conversion data register see t ab le 102 08h r 000h acd2 adc channel 2 conversion data register see t ab le 102 0ch r 000h acd3 adc channel 3 conversion data register see t ab le 102 10h r 000h acd4 adc channel 4 conversion data register see t ab le 102 14h r 000h acd5 adc channel 5 conversion data register see t ab le 102 18h r 000h acd6 adc channel 6 conversion data register see t ab le 102 1ch r 000h acd7 adc channel 7 conversion data register see t ab le 102 20h r/w 00h acon adc control register see t ab le 103 24h r/w 0000h acc adc channel con?guration register see t ab le 105 28h r/w 0h aie adc interrupt enable register see t ab le 107 2ch r 0h ais adc interrupt status register see t ab le 108 30h w - aic adc interrupt clear register see t ab le 109
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 70 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.5.5 adc control register (acon) the adc control register provides the con?guration of adc operation mode and re?ects the analog-to-digital conversion status. t ab le 103 shows the bit assignment of the acon register. table 102. acd register bit description legend: * reset value bit symbol access value description 31 to 10 reserved - - reserved; do not modify, read as logic 0, write as logic 0 9 to 0 acd[9:0] r 000h* conversion data; the value represents the voltage on the corresponding channel input pin, divided by the voltage on the v dd(adc) pin table 103. acon register bit description legend: * reset value bit symbol access value description 31 to 7 reserved - - reserved; do not modify, read as logic 0, write as logic 0 6 as r adc status 1 the analog-to-digital conversion scan is in progress 0* the adc is idle 5 to 3 asc[2:0] r/w 0h* adc scan con?guration; see t ab le 104 2 asm r/w adc scan mode 1 a repetitive conversion scan is performed after the start trigger as con?gured in the adc scan con?guration bits (asc); the adc conversion data registers are updated continuously; a continuous scan process is terminated by clearing the adc scan mode bit 0* a single conversion scan is performed after the start trigger as con?gured in the adc scan con?guration; the results are stored in the adc conversion data registers 1 aen r/w adc enable 1 the adc is enabled for conversion scans 0* the adc will be switched into low power mode; starting a new conversion scan is not possible; an ongoing conversion scan is completed before disabling 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 104: conversion scan con?guration bits asc[2:0] function 000 adc in inactive operational mode 001 adc in inactive operational mode 010 start conversion scan through all active channels [1] 011 start conversion scan through all active channels [1] 100 start conversion scan through all active channels after rising edge on pin 64 (p2[23]/cap1[0]/mat1[0])
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 71 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] in single scan conversion mode (asm = 0), the asc value should be set to inactive as soon as the adc conversion is started. this is because in single scan mode, a new conversion will be started according the trigger condition de?ned by the asc bits when the aen bit is set after the conversion has completed. 8.3.5.6 adc channel con?guration register (acc) the adc channel con?guration register de?nes which analog input channels are included during an analog-to-digital conversion scan. furthermore, the resolution per channel can be de?ned from 2 bits to 10 bits. t ab le 105 shows the bit assignment of the acc register. 101 start conversion scan through all active channels after falling edge on pin 64 (p2[23]/cap1[0]/mat1[0]) 110 start conversion scan through all active channels after rising edge on pin 65 (p2[22]/cap2[0]/mat2[0]) 111 start conversion scan through all active channels after falling edge on pin 65 (p2[22]/cap2[0]/mat2[0]) table 104: conversion scan con?guration bits continued asc[2:0] function table 105. acc register bit description legend: * reset value bit symbol access value description 31 to 28 acc7[3:0] r/w 0h* channel 7 con?guration; see t ab le 106 27 to 24 acc6[3:0] r/w 0h* channel 6 con?guration; see t ab le 106 23 to 20 acc5[3:0] r/w 0h* channel 5 con?guration; see t ab le 106 19 to 16 acc4[3:0] r/w 0h* channel 4 con?guration; see t ab le 106 15 to 12 acc3[3:0] r/w 0h* channel 3 con?guration; see t ab le 106 11 to 8 acc2[3:0] r/w 0h* channel 2 con?guration; see t ab le 106 7 to 4 acc1[3:0] r/w 0h* channel 1 con?guration; see t ab le 106 3 to 0 acc0[3:0] r/w 0h* channel 0 con?guration; see t ab le 106 table 106: channel selection and resolution value bits accn[3:0] function 0000 channel not selected 0001 reserved 0010 2-bit resolution 0011 3-bit resolution 0100 4-bit resolution 0101 5-bit resolution 0110 6-bit resolution 0111 7-bit resolution 1000 8-bit resolution 1001 9-bit resolution 1010 10-bit resolution 1011 reserved 1100 reserved
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 72 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.5.7 adc interrupt enable register (aie) the adc interrupt enable register contains the enable for the scan interrupt. t ab le 107 shows the bit assignment of the aie register. 8.3.5.8 adc interrupt status register (ais) the adc interrupt status register indicates the presence of the scan interrupt. the ais register is read only. t ab le 108 shows the bit assignment of the ais register. 8.3.5.9 adc interrupt clear register (aic) the adc interrupt clear register provides the mechanism to clear scan interrupt. the aic register is write only. t ab le 109 shows the bit assignment of the aic register. 1101 reserved 1110 reserved 1111 reserved table 106: channel selection and resolution value bits continued accn[3:0] function table 107. aie register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 asie r/w adc scan interrupt enable 1 an interrupt is generated if a single conversion scan has ?nished 0* table 108. ais register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; read as logic 0 0 asi r adc scan interrupt 1 an interrupt is pending due to a completed conversion scan 0* table 109. aic register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, write as logic 0 0 asic w - analog-to-digital conversion scan interrupt clear 1 the scan interrupt ?ag is cleared 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 73 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.6 event router 8.3.6.1 overview the event router provides bus controlled routing of input events to the vectored interrupt controller for use as interrupt or wake up signals. the key features are: ? input events can be used either directly or latched (edge detected) as interrupt source ? direct events will disappear when the event becomes inactive ? latched events will remain active until they are explicitly cleared ? programmable input level and edge polarity ? event detection maskable ? event detection is fully asynchronous, thus no clock is required the event router allows the event source to be de?ned, its polarity to be selected, its activation type to be selected and the interrupt to be masked or enabled. the event router can be used to start a clock on an external event. the real-time clock tick interrupt event needs to be captured on the rising edge. the vectored interrupt controller interrupt inputs are active high. 8.3.6.2 event router pin description and mapping to register bit positions the event router module in the SJA2020 is connected to the following pins. the pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 110 shows the pins connected to the event router. it also shows the corresponding bit position in the event router registers and the default polarity, see t ab le 118 . table 110: event router pin connections symbol direction bit position description default polarity, see t ab le 118 extint0 in 0 external interrupt input 0 1 extint1 in 1 external interrupt input 1 1 extint2 in 2 external interrupt input 2 1 extint3 in 3 external interrupt input 3 1 can0 rxdc in 4 can0 receive data input and wake-up 0 can1 rxdc in 5 can1 receive data input and wake-up 0 can2 rxdc in 6 can2 receive data input and wake-up 0 can3 rxdc in 7 can3 receive data input and wake-up 0 can4 rxdc in 8 can4 receive data input and wake-up 0 can5 rxdc in 9 can5 receive data input and wake-up 0 lin0 rxdc in 10 lin0 receive data input and wake-up 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 74 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.6.3 register mapping the event router registers are shown in t ab le 111 . the event router registers have an offset to the base address er regbase which can be found in the memory map (see t ab le 7 ). 8.3.6.4 event status register (pend) the event status register determines when the event router forwards an interrupt request to the vectored interrupt controller if the corresponding event enable has been set. t ab le 112 shows the bit assignment of the pend register. lin1 rxdc in 11 lin1 receive data input and wake-up 0 lin2 rxdc in 12 lin2 receive data input and wake-up 0 lin3 rxdc in 13 lin3 receive data input and wake-up 0 - in 14 rtc tick event 1 - n.a. 15 can interrupt (internal), combined general interrupt of all can controllers and the can look-up table, see section 8.5.1.33 1 - n.a. 16 vic irq (internal) 1 - n.a. 17 vic fiq (internal) 1 table 110: event router pin connections continued symbol direction bit position description default polarity, see t ab le 118 table 111: event router register summary address type reset value name description reference c00h r 0 0000h pend event status register see t ab le 112 c20h w - int_clr event status clear register see t ab le 113 c40h w - int_set event status set register see t ab le 114 c60h r 3 ffffh mask event enable register see t ab le 115 c80h w - mask_clr event enable clear register see t ab le 116 ca0h w - mask_set event enable set register see t ab le 117 cc0h r/w 3 c00fh apr activation polarity register see t ab le 118 ce0h r/w 3 ffffh atr activation type register see t ab le 119 d00h - - reserved reserved; do not modify d20h r/w 0 0000h rsr raw status register see t ab le 120 table 112. pend register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 75 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.6.5 event status clear register (int_clr) the event status clear register clears the bits in the event status register. t ab le 113 shows the bit assignment of the int_clr register. 8.3.6.6 event status set register (int_set) the event status set register sets the bits in the event status register. t ab le 114 shows the bit assignment of the int_set register. 8.3.6.7 event enable register (mask) the event enable register determines when the event router sets the event status and forwards this to the vectored interrupt controller if the corresponding event enable has been set. t ab le 115 shows the bit assignment of the mask register. 17 to 0 pend[17:0] r 1 an event on corresponding pin x has occurred or logic 1 is written to the corresponding bit in the int_set register 0* no event is pending or logic 1 has been written to the corresponding bit in the int_clr register table 112. pend register bit description continued legend: * reset value bit symbol access value description table 113. int_clr register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 int_clr[17:0] w - 1 the corresponding bit in the event status register is cleared 0 the corresponding bit in the event status register is unchanged table 114. int_set register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 int_set[17:0] w - 1 the corresponding bit in the event status register is set 0 the corresponding bit in the event status register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 76 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.6.8 event enable clear register (mask_clr) the event enable clear register clears the bits in the event enable register. t ab le 116 shows the bit assignment of the mask_clr register. 8.3.6.9 event enable set register (mask_set) the event enable set register sets the bits in the event enable register. t ab le 117 shows the bit assignment of the mask_set register. 8.3.6.10 activation polarity register (apr) the activation polarity register is used to con?gure which level is the active state for the event source. table 115. mask register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 mask[17:0] r 3 ffffh* event enable; this bit is set by writing a logic 1 to the corresponding bit in the mask_set register; this bit is cleared by writing a logic 1 to the corresponding bit in the mask_clr register 1 the event router sets the event status and forwards the corresponding event to the vectored interrupt controller 0 the event router masks the event status and does not forward the corresponding event to the vectored interrupt controller table 116. mask_clr register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 mask_clr[17:0] w 1 the corresponding bit in the event enable register is cleared 0 the corresponding bit in the event enable register is unchanged table 117. mask_set register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 mask_set[17:0] w - 1 the corresponding bit in the event enable register is set 0 the corresponding bit in the event enable register is unchanged
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 77 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers t ab le 118 shows the bit assignment of the apr register. 8.3.6.11 activation type register (atr) the activation type register is used to con?gure whether an event is used directly or if it is latched. if it is latched, the interrupt will persist after its event source has become inactive until it is cleared by an interrupt clear write action. the event router includes an edge detection circuit which prevents reassertion of an event interrupt if the input remains at the active level after the latch is cleared. level sensitive events are expected to be held and removed by the event source. t ab le 119 shows the bit assignment of the atr register. 8.3.6.12 raw status register (rsr) the raw status shows unmasked events including latched events. level sensitive events are removed by the event source. edge sensitive events need to be cleared via the event clear register. t ab le 120 shows the bit assignment of the rsr register. table 118. apr register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 apr[17:0] r/w 3 c00fh* 1 the corresponding event is high sensitive (high level or rising edge) 0 the corresponding event is low sensitive (low level or falling edge) table 119. atr register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 atr[17:0] r/w 3 ffffh* 1 the corresponding event is latched (edge sensitive) 0 the corresponding event is directly forwarded (level sensitive) table 120. rsr register bit description legend: * reset value bit symbol access value description 31 to 18 reserved - - reserved; do not modify, read as logic 0, write as logic 0 17 to 0 rsr[17:0] r 0 0000h* 1 the corresponding event has occurred 0 the corresponding event has not occurred
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 78 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.7 real-time clock 8.3.7.1 overview the real time clock is driven by a dedicated low power, low frequency crystal oscillator. battery backed solutions are enabled by separated voltage domains on-chip. the key features are: ? real time and date ? separate voltage domain to enable separate battery solutions ? optimized for accurate 32.678 khz crystal oscillator frequency ? minute tick for interrupt handling the real time clock is capable to represent the real time and date via standard c library functions. every minute, a tick is generated for interrupt handling purposes. the real time clock is initialized via an on-chip power-on reset within its own voltage domain only. accessing the real-time clock registers requires a running 32 khz oscillator and a system clock frequency of at least twice the real time clock frequency. in case of no rtc supply, the registers content is unde?ned. 8.3.7.2 rtc pin description the rtc in the SJA2020 has the following pins, see t ab le 121 . 8.3.7.3 register mapping the real-time clock registers are shown in t ab le 122 . the real-time clock registers have an offset to the base address rtc regbase which can be found in the memory map (see t ab le 7 ). 8.3.7.4 rtc elapsed time seconds register (rtc_time_seconds) the rtc elapsed time seconds register re?ects the time in seconds since power-up. table 121: real time clock pins symbol direction description xin_rtc in real time clock crystal input or external clock input xout_rtc out real time clock crystal output table 122. real-time clock register summary address type reset value name description reference 000h r 0000 0000h rtc_time_seconds elapsed time seconds register see t ab le 123 010h r 0000h rtc_time_fraction seconds fraction register see t ab le 124 020h r/w 0000 0000h rtc_portime real-time offset register see t ab le 125 fc0h r/w 1h rtc_control real-time control register see t ab le 126
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 79 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the rtc_time_seconds register is read only. t ab le 123 shows the bit assignment of the rtc_time_seconds register. 8.3.7.5 rtc seconds fraction register (rtc_time_fraction) the rtc seconds fraction register re?ects the passed number of clock cycles from the current second. note that the rtc seconds fraction register is only updated when reading the rtc elapsed time seconds register. the rtc_time_fraction register is read only. t ab le 124 shows the bit assignment of the rtc_time_fraction register. 8.3.7.6 rtc real time offset register (rtc_portime) the rtc real time offset register holds the offset to the real time and date. providing the offset of power-up time in elapsed seconds since 1 january 1970, standard c libraries can be used in order to easily access the current time and date. t ab le 125 shows the bit assignment of the rtc_portime register. 8.3.7.7 rtc real time control register (rtc_control) the rtc real time control register provides the minute tick enable for real time clock applications. t ab le 126 shows the bit assignment of the rtc_control register. table 123. rtc_time_seconds register bit description legend: * reset value bit symbol access value description 31 to 0 rtc_time_ seconds[31:0] r 0000 0000h* elapsed time in seconds; provides the number of seconds passed after power-on event occurred table 124. rtc_time_fraction register bit description legend: * reset value bit symbol access value description 31 to 15 reserved - - reserved; read as logic 0 14 to 0 rtc_time_ fraction[14:0] r 0000h* seconds fraction register; provides the fractional part of a second in clock ticks table 125. rtc_portime register bit description legend: * reset value bit symbol access value description 31 to 0 rtc_portime[31:0] r/w 0000 0000h* real time offset value; contains the real time offset value in seconds at power-on event
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 80 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4 peripheral subsystem 8.4.1 timer 8.4.1.1 overview four identical timers are present which are designed to count cycles of the clock and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. they also include capture inputs to trap the timer value when a transition occurs in an input signal, optionally generating an interrupt the key features are: ? 32-bit timer/counter with programmable 32-bit prescaler ? up to four 32-bit capture channels per timer, that take a snapshot of the timer value when a transition occurs in an input signal; a capture event may also optionally generate an interrupt ? four 32-bit match registers per timer that allow: C continuous operation with optional interrupt generation on match C stop timer on match with optional interrupt generation C reset timer on match with optional interrupt generation ? up to four external outputs per timer corresponding to match registers, with the following capabilities: C set low on match C set high on match C toggle on match C do nothing on match 8.4.1.2 timer pin description the four timers in the SJA2020 have the following pins. the timer pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 127 shows the timer pins, x runs from 0 to 3. table 126. rtc_control register bit description legend: * reset value bit symbol access value description 31 rtc_tick_enable r/w real time clock tick enable 1* the minute tick is inactive 0 the real time clock sends every minute a tick interrupt request to the event router 30 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 127: timer pins symbol direction description timerx cap[0] in timer x capture input 0 timerx cap[1] in timer x capture input 1 timerx cap[2] in timer x capture input 2
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 81 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.1.3 register mapping the timer registers are shown in t ab le 128 . the timer registers have an offset to the base address tmr regbase which can be found in the memory map (see t ab le 7 ). 8.4.1.4 timer interrupt register (ir) the timer interrupt register consists of 4 bits for the interrupts on the match register matches and 4 bits for the interrupts on capture events. if an interrupt is being generated, then the corresponding bit in the timer interrupt register will be logic 1. otherwise, the bit will be logic 0. writing a logic 1 to the corresponding timer interrupt register bit will reset the interrupt. writing logic 0 has no effect. writing a logic 1 instead of logic 0 allows to write the contents of the interrupt register to itself thus providing a quick method of clearing. an interrupt is generated if one of the match registers matches the contents of the timer counter and the interrupt is enabled through the match control register or the concerned capture input satis?es one of the conditions in the capture control register and the interrupts are enabled via the capture control register. t ab le 129 shows the bit assignment of the ir register. timerx cap[3] in timer x capture input 3 timerx mat[0] out timer x match output 0 timerx mat[1] out timer x match output 1 timerx mat[2] out timer x match output 2 timerx mat[3] out timer x match output 3 table 127: timer pins continued symbol direction description table 128: timer register summary address type reset value name description reference 00h r/w 00h ir timer interrupt register see t ab le 129 04h r/w 0h tcr timer control register see t ab le 130 08h r/w 0000 0000h tc timer counter value see t ab le 131 0ch r/w 0000 0000h pr prescale register see t ab le 132 10h r/w 0000 0000h pc prescale counter value see t ab le 133 14h r/w 000h mcr match control register see t ab le 134 18h r/w 0000 0000h mr0 match register 0 see t ab le 135 1ch r/w 0000 0000h mr1 match register 1 see t ab le 135 20h r/w 0000 0000h mr2 match register 2 see t ab le 135 24h r/w 0000 0000h mr3 match register 3 see t ab le 135 28h r/w 000h ccr capture control register see t ab le 136 2ch r 0000 0000h cr0 capture register 0 see t ab le 137 30h r 0000 0000h cr1 capture register 1 see t ab le 137 34h r 0000 0000h cr2 capture register 2 see t ab le 137 38h r 0000 0000h cr3 capture register 3 see t ab le 137 3ch r/w 000h emr external match register see t ab le 138
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 82 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.1.5 timer control register (tcr) the timer control register maintains 2 bits which are used to control the operation of the timer counter. bit counter_enable switches on and off the timer and prescale counter. bit counter_reset clears the timer and prescale counter. t ab le 130 shows the bit assignment of the tcr register. 8.4.1.6 timer counter (tc) the timer counter represents the timer count value which is incremented every prescale cycle. t ab le 131 shows the bit assignment of the tc register. table 129. ir register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 intr_c3 r/w 0* interrupt bit for a cr3 load on capture 3 event; writing logic 1 clears the interrupt ?ag 6 intr_c2 r/w 0* interrupt bit for a cr2 load on capture 2 event; writing logic 1 clears the interrupt ?ag 5 intr_c1 r/w 0* interrupt bit for a cr1 load on capture 1 event; writing logic 1 clears the interrupt ?ag 4 intr_c0 r/w 0* interrupt bit for a cr0 load on capture 0 event; writing logic 1 clears the interrupt ?ag 3 intr_m3 r/w 0* interrupt bit for a mr3 and tc match; writing logic 1 clears the interrupt ?ag 2 intr_m2 r/w 0* interrupt bit for a mr2 and tc match; writing logic 1 clears the interrupt ?ag 1 intr_m1 r/w 0* interrupt bit for a mr1 and tc match; writing logic 1 clears the interrupt ?ag 0 intr_m0 r/w 0* interrupt bit for a mr0 and tc match; writing logic 1 clears the interrupt ?ag table 130. tcr register bit description legend: * reset value bit symbol access value description 31 to 2 reserved - - reserved; do not modify, read as logic 0, write as logic 0 1 counter_ reset r/w 0* reset timer and prescale counter; if this bit is set, the counters remain reset until this bit is cleared again 0 counter_ enable r/w 0* enable timer and prescale counter; if this bit is set, the counters are running table 131. tc register bit description legend: * reset value bit symbol access value description 31 to 0 tc[31:0] r/w 0000 0000h* timer counter; it is advised not to access this register
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 83 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.1.7 prescale register (pr) the prescale register determines the number of clock cycles as prescale value for the timer counter clock. t ab le 132 shows the bit assignment of the pr register. 8.4.1.8 prescale counter (pc) the prescale counter represents the prescale count value which is incremented every clock cycle. t ab le 133 shows the bit assignment of the pc register. 8.4.1.9 match control register (mcr) each match register can be con?gured through the match control register to stop both the timer counter and prescale counter thus maintaining their value at the time of the match, to restart the timer counter at logic 0, to allow the counters to continue counting and/or generate an interrupt when its contents match those of the timer counter. a stop on match has higher priority than reset on match. an interrupt is generated if one of the match registers matches the contents of the timer counter and the interrupt is enabled through the match control register. the match control register is used to control what operations are performed when one of the match registers matches the timer counter. t ab le 134 shows the bit assignment of the mcr register. table 132. pr register bit description legend: * reset value bit symbol access value description 31 to 0 pr[31:0] r/w 0000 0000h* prescale register; this register speci?es the maximum value for the prescale counter table 133. pc register bit description legend: * reset value bit symbol access value description 31 to 0 pc[31:0] r 0000 0000h* prescale counter; this register re?ects the prescale counter value table 134. mcr register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 stop_3 r/w stop on match mr3 and tc 1 the timer and prescale counter stop counting and bit counter_enable will be cleared if mr3 matches tc 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 84 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 10 reset_3 r/w reset on match mr3 and tc 1 the timer counter is reset if mr3 matches tc 0* 9 intr_3 r/w interrupt on match mr3 and tc 1 an interrupt is generated if mr3 matches tc 0* 8 stop_2 r/w stop on match mr2 and tc 1 the timer and prescale counter stop counting and bit counter_enable will be cleared if mr2 matches tc 0* 7 reset_2 r/w reset on match mr2 and tc 1 the timer counter is reset if mr2 matches tc 0* 6 intr_2 r/w interrupt on match mr2 and tc 1 an interrupt is generated if mr2 matches tc 0* 5 stop_1 r/w stop on match mr1 and tc 1 the timer and prescale counter stop counting and bit counter_enable will be cleared if mr1 matches tc 0* 4 reset_1 r/w reset on match mr1 and tc 1 the timer counter is reset if mr1 matches tc 0* 3 intr_1 r/w interrupt on match mr1 and tc 1 an interrupt is generated if mr1 matches tc 0* 2 stop_0 r/w stop on match mr0 and tc 1 the timer and prescale counter stop counting and bit counter_enable will be cleared if mr0 matches tc 0* 1 reset_0 r/w reset on match mr0 and tc 1 the timer counter is reset if mr0 matches tc 0* 0 intr_0 r/w interrupt on match mr0 and tc 1 an interrupt is generated if mr0 matches tc 0* table 134. mcr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 85 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.1.10 match registers (mr0 to mr3) the match registers determine the timer counter match value. four match registers are available per timer. t ab le 135 shows the bit assignment of the mrn registers, n from 0 to 3. 8.4.1.11 capture control register (ccr) the capture control register is used to control when one of the possible four capture registers is loaded with the value in the timer counter and if an interrupt is generated, when the capture occurs. a rising edge is detected if the sequence of logic 0 followed by logic 1 is found. a falling edge is detected if the sequence of logic 1 followed by logic 0 is found. the capture control register maintains 2 bits for each of the counter registers to allow the sequence detection to be enabled for each of the capture registers. if the enabled sequence is detected, the timer counter value is loaded in the capture register. if enabled through the capture control register, then an interrupt is generated. setting both the rising and falling bits at the same time is a valid con?guration. a reset clears the ccr register. t ab le 136 shows the bit assignment of the ccr register. table 135. mr register bit description legend: * reset value bit symbol access value description 31 to 0 mr[31:0] r/w 0000 0000h* match register; this register speci?es the match value for the timer counter table 136. ccr register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 event_3 r/w interrupt on capture event by input 3 1 a cr3 load due to a capture event on input 3 will generate an interrupt 0* 10 fall_3 r/w capture on capture input 3 falling 1 a sequence of logic 1 followed by logic 0 from capture input 3 will cause cr3 to be loaded with the contents of tc 0* 9 rise_3 r/w capture on capture input 3 rising 1 a sequence of logic 0 followed by logic 1 from capture input 3 will cause cr3 to be loaded with the contents of tc 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 86 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8 event_2 r/w interrupt on capture event by input 2 1 a cr2 load due to a capture event on input 2 will generate an interrupt 0* 7 fall_2 r/w capture on capture input 2 falling 1 a sequence of logic 1 followed by logic 0 from capture input 2 will cause cr2 to be loaded with the contents of tc 0* 6 rise_2 r/w capture on capture input 2 rising 1 a sequence of logic 0 followed by logic 1 from capture input 2 will cause cr2 to be loaded with the contents of tc 0* 5 event_1 r/w interrupt on capture event by input 1 1 a cr1 load due to a capture event on input 1 will generate an interrupt 0* 4 fall_1 r/w capture on capture input 1 falling 1 a sequence of logic 1 followed by logic 0 from capture input 1 will cause cr1 to be loaded with the contents of tc 0* 3 rise_1 r/w capture on capture input 1 rising 1 a sequence of logic 0 followed by logic 1 from capture input 1 will cause cr1 to be loaded with the contents of tc 0* 2 event_0 r/w interrupt on capture event by input 0 1 a cr0 load due to a capture event on input 0 will generate an interrupt 0* 1 fall_0 r/w capture on capture input 0 falling 1 a sequence of logic 1 followed by logic 0 from capture input 0 will cause cr0 to be loaded with the contents of tc 0* 0 rise_0 r/w capture on capture input 0 rising 1 a sequence of logic 0 followed by logic 1 from capture input 0 will cause cr0 to be loaded with the contents of tc 0* table 136. ccr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 87 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.1.12 capture registers (cr0 to cr3) the capture registers are loaded with the timer counter value when there is an event on the concerned capture input. four capture registers are available per timer. t ab le 137 shows the bit assignment of the crn registers, n from 0 to 3. 8.4.1.13 external match register (emr) the external match register provides both control and status of the external match pins. the external match ?ags and the match outputs can either toggle, go logic 0, go logic 1 or maintain state when the contents of match register is equal to the contents of timer counter. writing directly to external match bits is allowed to change the level of the ?ags and outputs. t ab le 138 shows the bit assignment of the emr register. table 137. cr register bit description legend: * reset value bit symbol access value description 31 to 0 cr[31:0] r 0000 0000h* capture register; this register re?ects after a capture event the timer counter captured value table 138. emr register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 10 ctrl_3[1:0] r/w 0h* external match control 3; see t ab le 139 9 to 8 ctrl_2[1:0] r/w 0h* external match control 2; see t ab le 139 7 to 6 ctrl_1[1:0] r/w 0h* external match control 1; see t ab le 139 5 to 4 ctrl_0[1:0] r/w 0h* external match control 0; see t ab le 139 3 emr_3 r/w 0* external match 3; when mr3 matches tc, the external match ?ag 3 can either toggle, go logic 0, go logic 1, or do nothing; bit ctrl_3 controls the functionality of this output; this bit can also be driven onto the match output 3 in a positive-logic manner (logic 0 = low, logic 1 = high)
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 88 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2 uart 8.4.2.1 overview the uart is commonly used to implement a serial interface such as an rs232. the SJA2020 contains an industry standard 550 uart with 16-byte transmit and receive fifos, but can also be put into 450 mode without fifos. the key features are: ? 16-byte receive and transmit fifos ? register locations conform to 550 industry standard ? receiver fifo trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes ? built-in baud rate generator note that each lin controller has also a standard 450 uart without fifos. 8.4.2.2 uart pin description the uart in the SJA2020 have the following pins. the uart pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 140 shows the uart pins. 2 emr_2 r/w 0* external match 2; when mr2 matches tc, the external match ?ag 2 can either toggle, go logic 0, go logic 1, or do nothing; bit ctrl_2 controls the functionality of this output; this bit can also be driven onto the match output 2 in a positive-logic manner (logic 0 = low, logic 1 = high) 1 emr_1 r/w 0* external match 1; when mr1 matches tc, the external match ?ag 1 can either toggle, go logic 0, go logic 1, or do nothing; bit ctrl_1 controls the functionality of this output; this bit can also be driven onto the match output 1 in a positive-logic manner (logic 0 = low, logic 1 = high) 0 emr_0 r/w 0* external match 0; when mr0 matches tc, the external match ?ag 0 can either toggle, go logic 0, go logic 1, or do nothing; bit ctrl_0 controls the functionality of this output; this bit can also be driven onto the match output 0 in a positive-logic manner (logic 0 = low, logic 1 = high) table 139: external match control bit description ctrl_n[1:0] function 00 do nothing 01 set logic 0 10 set logic 1 11 toggle table 138. emr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 89 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.3 register mapping the uart registers are shown in t ab le 142 . the uart registers have an offset to the base address uart regbase which can be found in the memory map (see t ab le 7 ). some uart registers are dependent on the setting of bit dlab, see t ab le 149 . [1] reserved for future expansion; write all logic 0 only. 8.4.2.4 receive buffer register (rbr) the receive buffer register is the top byte of the receive fifo. the top byte of the receive fifo contains the oldest character received and can be read via the bus interface. in 450 mode, received data is passed from the receive shift register to the top byte of the receive buffer register, essentially producing an 1-byte rx fifo. the least signi?cant bit represents the oldest received data bit. if the character received is less than 8 bits, the unused most signi?cant bits are padded with logic 0. the rbr register is read only and the divisor latch access bit dlab must be logic 0 for access. t ab le 142 shows the bit assignment of the rbr register. table 140: uart pins symbol direction description uartx txd out uart channel x transmit data output uartx rxd in uart channel x receive data input table 141: uart register summary address bit type reset value name description reference 00h dlab = 0 r - rbr receiver buffer register see t ab le 142 w - thr transmit holding register see t ab le 143 dlab = 1 r/w 01h dll divisor latch lsb register see t ab le 154 04h dlab = 0 r/w 0h ier interrupt enable register see t ab le 144 dlab = 1 r/w 00h dlm divisor latch msb register see t ab le 155 08h r 01h iir interrupt id register see t ab le 145 w 00h fcr fifo control register see t ab le 147 0ch r/w 00h lcr line control register see t ab le 149 10h - - - [1] 14h r 60h lsr line status register see t ab le 152 18h - - - [1] 1ch r/w 00h scr scratch register see t ab le 153 table 142. rbr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; read as logic 0 7 to 0 rbr[7:0] r - receive buffer register; contains the oldest received byte in the receive fifo
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 90 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.5 transmit holding register (thr) the transmit holding register is the top byte of the transmit fifo. the top byte is the newest character in the transmit fifo and can be written via the bus interface. in 450 mode, data is passed from the thr to the transmit shift register, essentially producing a 1-byte transmit fifo. the least signi?cant bit represents the ?rst bit to transmit. the thr register is write only and the divisor latch access bit dlab must be logic 0 for access. t ab le 143 shows the bit assignment of the thr register. 8.4.2.6 interrupt enable register (ier) the interrupt enable register is used to enable the four types of interrupts referred to in the interrupt identi?cation register. the divisor latch access bit dlab must be logic 0 in order to access the ier register. t ab le 144 shows the bit assignment of the ier register. 8.4.2.7 interrupt id register (iir) the interrupt id register provides a status code that denotes the priority and source of a pending interrupt. when an interrupt is generated, the interrupt id register indicates that an interrupt is pending and encodes the type in its three least signi?cant bits. the interrupts are frozen during an access to the interrupt id register. if an interrupt occurs during an access, the interrupt is recorded for the next interrupt id register access. the iir register is read only. t ab le 145 shows the bit assignment of the iir register. table 143. thr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0 7 to 0 thr[7:0] w - transmit holding register; writing to the transmit holding register causes the data to be stored in the transmit fifo; the byte will be sent when it reaches the bottom of the fifo and the transmitter is available table 144. ier register bits legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0, write as logic 0 2 lsie r/w receiver line status interrupt enable 1 the receive line status interrupt is enabled 0* 1 tbeie r/w transmit holding register empty interrupt enable 1 the transmit holding register empty interrupt is enabled 0* 0 rbie r/w receive buffer register interrupt register enable 1 the receive data available interrupt is enabled 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 91 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.8 fifo control register (fcr) the fifo control register enables and clears the fifos, sets the receiver fifo level, and selects the type of dma signalling. the fcr register is write only. t ab le 147 shows the bit assignment of the fcr register. table 145. iir register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; read as logic 0 7 fifo_ en r 0* fifos enabled; represents fifo enable bit of the fifo control register; in 450 mode this bit is always logic 0 6 fifo_ en r 0* fifos enabled; represents fifo enable bit of the fifo control register; in 450 mode this bit is always logic 0 5 to 4 reserved - - reserved; read as logic 0 3 to 0 int_id[3:0] r 1h* interrupt identi?cation; see t ab le 146 table 146: interrupt identi?cation con?guration bits int_id[3:0] priority level interrupt type source reset method 0001 none none none none 0110 1 receiver line status overrun error, parity error, framing error, or break interrupt read line status register 0100 2 received data available receiver data available in 450 mode or trigger level reached in 550 mode read receive buffer register 1100 2 character time-out indication no characters have been removed from or input to receiver fifo during the last four character times, and there is at least one character in it during this time read receive buffer register 0010 3 transmitter holding register empty transmit holding register empty read interrupt id register (if source of interrupt) or writing into transmitter holding register table 147. fcr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0 7 to 6 rev_trig[1:0] w 0h* trigger level for receiver fifo interrupt; see t ab le 148 5 to 4 reserved - - reserved; write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 92 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.9 line control register (lcr) the line control register controls the format of the asynchronous data communication exchange. t ab le 149 shows the bit assignment of the lcr register. 3 dma_m w dma mode 1 when logic 1 and in fifo mode, multiple character transfers are performed until the transmitter fifo is ?lled or the receiver fifo is empty; the receiver direct memory access becomes active when the receive fifo trigger level is reached or a character time-out occurred 0* only single character transfers are done as default in 450 mode 2 tx_fifo_r w transmitter fifo reset 1 when logic 1 and in fifo mode, all bytes in the transmitter fifo and the transmitter fifo pointer are cleared; the shift register is not cleared; the transmitter fifo reset bit is self clearing 0* 1 rx_fifo_r w receiver fifo reset 1 when logic 1 and in fifo mode, all bytes in the receiver fifo and the receiver fifo pointer are cleared; the shift register is not cleared; the receiver fifo reset bit is self clearing 0* 0 fifo_en w 1 the transmitter and receiver fifos are enabled and the uart operates in fifo mode; the fifo enable bit must be set when other fifo control register bits are written to or they are not programmed; changing this bit clears the fifos 0* the uart operates in 450 mode table 148: receiver trigger level con?guration bits rev_trig [1:0] function 00 receiver fifo contains 1 byte 01 receiver fifo contains 4 bytes 10 receiver fifo contains 8 bytes 11 receiver fifo contains 14 bytes table 147. fcr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 93 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.10 line status register (lsr) the line status register provides the information concerning the data transfers. the lsr register is read only. t ab le 152 shows the bit assignment of the lsr register. table 149. lcr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 dlab r/w divisor latch access bit 1 the divisor latch registers of the baud rate generator can be accessed 0* the receiver buffer register, the transmit holding register, and the interrupt enable register can be accessed 6 bc r/w break control 1 a break transmission condition is forced which puts the txd output to low 0* the break transmission condition is disabled; the break condition has no affect on the transmitter logic; it only affects the txd line 5 to 4 ps[1:0] r/w 0h* parity select; see t ab le 150 3 pen r/w parity enable 1 a parity bit is generated in transmitted data between the last data word bit and the ?rst stop bit; in received data the parity is checked 0* 2 stb r/w number of stop bits 1 the number of generated stop bits are 2; except the word length is 5 bits, then 1.5 stop bits are generated 0* only 1 stop bit is generated 1 to 0 wls[1:0] r/w 0h* word length select; see t ab le 151 table 150: parity select con?guration bits ps [1:0] function 00 odd parity: an odd number of logic 1 in the data and parity bits 01 even parity: an even number of logic 1 in the data and parity bits 10 forced logic 1 stick parity 11 forced logic 0 stick parity table 151: word length con?guration bits wls [1:0] function 00 5-bit character length 01 6-bit character length 10 7-bit character length 11 8-bit character length
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 94 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 152. lsr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; read as logic 0 7 rxfe r error in receiver fifo 1 the receiver fifo contains at least one parity, framing, or break error; in 450 mode the error in receiver fifo bit is always cleared 0* 6 temt r transmitter empty 1* the transmitter holding register, transmitter fifo and the transmitter shift register are both empty; the transmitter empty bit is cleared when either the transmitter holding register or the transmitter shift register contains a data character 0 5 thre r transmitter holding register empty 1* the transmitter holding register or transmitter fifo is empty; if the transmitter holding register empty interrupt enable is set, an interrupt is generated; the transmitter holding register empty bit is set when the contents of the transmitter holding register is transferred to the transmitter shift register; the transmitter holding register empty bit is cleared concurrently with loading the transmitter holding register or transmitter fifo 0 4 bi r break interrupt 1 the received data input was held low for longer than a full-word transmission time; a full-word transmission time is de?ned as the total time to transmit the start, data, parity, and stop bits; the break interrupt bit is cleared upon reading; in fifo mode, this error is associated with the particular character in the receiver fifo to which it applies; this error is revealed when its associated character is at the top of the receiver fifo; when a break occurs, only one logic 0 is loaded into the receiver fifo; the uart tries to resynchronize after a framing error; to accomplish this, it is assumed that the framing error is due to the next start bit; the uart samples this start bit twice and then accepts the input data 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 95 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.11 scratch register (scr) the scratch register is intended for the programmers use as scratch pad in the sense that it temporarily holds the programmers data without affecting any other uart operation. t ab le 153 shows the bit assignment of the scr register. 3 fe r framing error 1 the received character did not have a valid (set) stop bit; the framing error is cleared upon ring; in fifo mode, this error is associated with the particular character in the receiver fifo to which it applies; this error is revealed when its associated character is at the top of the receiver fifo; when a break occurs, only one logic 0 is loaded into the receiver fifo; the next character transfer is enabled after the rxd input line goes to the marking state (all logic 1) for at least two sample times and then receives the next valid start bit 0* 2 pe r parity error 1 the parity of the received data character does not match the parity selected in the line control register; the parity error is cleared upon reading; in fifo mode, this error is associated with the particular character in the receiver fifo to which it applies; this error is revealed when its associated character is at the top of the receiver fifo 0* 1 oe r overrun error 1 the character in the receiver buffer register was overwritten by the next character transferred into this register before it was read; the overrun error is cleared upon reading; if the fifo mode data continues to ?ll the receiver fifo beyond the trigger level, an overrun error occurs only after the receiver fifo is full and the next character has been completely received in the shift register; an overrun error is signalled as soon it happens; the character in the shift register is overwritten, but not transferred to the receiver fifo 0* 0 dr r data ready 1 a complete incoming character has been received and transferred to the receiver buffer register or the receiver fifo; the data ready bit is cleared by reading all of the data in the receiver buffer register or the receiver fifo 0* table 152. lsr register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 96 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.12 divisor latch lsb and divisor latch msb registers (dll and dlm) the two divisor latch registers store the divisor in 16-bit binary format for the programmable baud generator. the output frequency of the baud generator is 16 times the baud rate. the input frequency of the baud generator is the system clock frequency divided by the divisor value. a written value of 0000h into the divisor will be treated like value 0001h. the divisor latch access bit dlab must be set in order to access the dll and dlm register. t ab le 154 and t ab le 155 show the bit assignment of respective the dll and dlm register. 8.4.3 general purpose i/o 8.4.3.1 overview three general purpose i/o ports provide individual control over each bidirectional port pin. there are two registers to control the i/o direction and output level. the inputs are synchronized to achieve stable read levels. the i/o pad behavior depends on the con?guration programmed in the i/o pad multiplex register. the key features are: ? general purpose parallel inputs and outputs ? direction control of individual bits ? synchronized input sampling for stable input data values ? all i/o defaults to input at reset to avoid any possible bus con?icts to generate an open-drain output, set the bit in the output register to the desired value. table 153. scr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0, read as logic 0 7 to 0 scr[7:0] r/w 00h* scratch register; this register can be written and/or read at users discretion table 154. dll register bits legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0, read as logic 0 7 to 0 dll r/w 01h* divisor latch lsb register; the divisor latch lsb register contains the lower byte of the 16-bit divisor table 155. dlm register bits legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0, read as logic 0 7 to 0 dlm r/w 00h* divisor latch msb register; the divisor latch msb register contains the higher byte of the 16-bit divisor
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 97 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers use the direction register to control the signal. when set to output, the output driver will actively drive the value on the output; when set to input, the signal is ?oating and can be pulled externally. 8.4.3.2 gpio pin description the three gpio ports in the SJA2020 have the following pins. the gpio pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 157 shows the gpio pins. 8.4.3.3 register mapping the general purpose i/o registers have an offset to the base address gpio regbase which can be found in the memory map (see t ab le 7 ). the general purpose i/o registers are shown in t ab le 157 . 8.4.3.4 port input register (pins) the port input register is used to re?ect the synchronized input level on each i/o pin individually. in case of writing to the port input register, the contents is written into the port output register. t ab le 158 shows the bit assignment of the pins register. 8.4.3.5 port output register (or) the port output register is used to de?ne the output level on each i/o pin individually in case this pin is con?gured as output by the port direction register. if the port input register is written, the port output register is written. t ab le 159 shows the bit assignment of the or register. table 156: gpio pins symbol direction description gpio0 pin[31:0] in/out gpio port 0, pins 31 to 0 gpio1 pin[31:0] in/out gpio port 1, pins 31 to 0 gpio2 pin[29:0] in/out gpio port 2, pins 29 to 0 table 157: general purpose i/o register summary address type reset value name description reference 0h r - pins port input register see t ab le 158 4h r/w 0000 0000h or port output register see t ab le 159 8h r/w 0000 0000h dr port direction register see t ab le 160 table 158. pins register bit description legend: * reset value bit symbol access value description 31 to 0 pins[31:0] r/w - port input value; bit 0 corresponds to pin pn[0], etc.; if a input pin is high, then the respective bit is logic 1 and if a input pin is low, then the respective bit is logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 98 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.3.6 port direction register (dr) the port direction register is used to control each i/o pin output driver enable individually. t ab le 160 shows the bit assignment of the dr register. 8.5 in-vehicle networking subsystem 8.5.1 can 8.5.1.1 overview controller area network (can) is the de?nition of a high performance communication protocol for serial data communication. the six can controllers in the SJA2020 provide a full implementation of the can protocol according to the can speci?cation version 2.0b. the gateway concept is fully scalable with the number of can controllers and always operates together with a separated powerful and ?exible hardware acceptance ?lter. the key features are: ? supports 11-bit identi?er as well as 29-bit identi?er ? double receive buffer and triple transmit buffer ? programmable error warning limit and error counters with read/write access ? arbitration lost capture and error code capture with detailed bit position ? single shot transmission (no re-transmission) ? listen only mode (no acknowledge, no active error ?ags) ? reception of own messages (self reception request) 8.5.1.2 can pin description the six can controllers in the SJA2020 have the following pins. the can pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 161 shows the can pins, x runs from 0 to 5. table 159. or register bits legend: * reset value bit symbol access value description 31 to 0 or[31:0] r/w 0000 0000h* port output value; bit 0 corresponds to pin pn[0], etc.; if con?gured as output, then a logic 1 drives the respective port to high table 160. dr register bit legend: * reset value bit symbol access value description 31 to 0 dr[31:0] r/w 0000 0000h* port direction control; bit 0 corresponds to pin pn[0], etc.; if the bit is logic 1, then the respective port pin is con?gured as output table 161: can pins symbol direction description canx txdc out can channel x transmit data output canx rxdc in can channel x receive data input
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 99 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.3 register mapping the can registers are shown in t ab le 162 . the can registers have an offset to the can base addresses which can be found in the memory map (see t ab le 7 ). table 162: can register summary address type reset value name description reference can controller; canc regbase offset 00h r/w 01h ccmode can controller mode register see t ab le 163 04h w 00h cccmd can controller command register see t ab le 164 08h r/w 0000 003ch ccgs can controller global status register see t ab le 165 0ch r 0000 0000h ccic can controller interrupt and capture register see t ab le 166 10h r/w 000h ccie can controller interrupt enable register see t ab le 169 14h r/w 1c 0000h ccbt can controller bus timing register see t ab le 170 18h r/w 60h ccewl can controller error warning limit register see t ab le 171 1ch r 3c 3c3ch ccstat can controller status register see t ab le 172 20h r/w 0000 0000h ccrxbmi can controller receive buffer message info register see t ab le 173 24h r/w 0000 0000h ccrxbid can controller receive buffer identi?er register see t ab le 174 28h r/w 0000 0000h ccrxbda can controller receive buffer data a register see t ab le 175 2ch r/w 0000 0000h ccrxbdb can controller receive buffer data b register see t ab le 176 30h r/w 0000 0000h cctxb1mi can controller transmit buffer 1 message info register see t ab le 177 34h r/w 0000 0000h cctxb1id can controller transmit buffer 1 identi?er register see t ab le 178 38h r/w 0000 0000h cctxb1da can controller transmit buffer 1 data a register see t ab le 179 3ch r/w 0000 0000h cctxb1db can controller transmit buffer 1 data b register see t ab le 180 40h r/w 0000 0000h cctxb2mi can controller transmit buffer 2 message info register see t ab le 177 44h r/w 0000 0000h cctxb2id can controller transmit buffer 2 identi?er register see t ab le 178 48h r/w 0000 0000h cctxb2da can controller transmit buffer 2 data a register see t ab le 179 4ch r/w 0000 0000h cctxb2db can controller transmit buffer 2 data b register see t ab le 180 50h r/w 0000 0000h cctxb3mi can controller transmit buffer 3 message info register see t ab le 177
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 100 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the following can controller register tables have a soft reset mode value besides the reset value: ? a hardware reset overrules the soft reset mode ? if no soft reset value is speci?ed the content is unchanged by the soft reset mode ? bit ?elds with x means that the content is unchanged upon setting the soft reset mode the reset value shows the result of hardware reset, while the soft reset mode value indicates the result when the rm bit is set either by software or due to a bus-off condition. 54h r/w 0000 0000h cctxb3id can controller transmit buffer 3 identi?er register see t ab le 178 58h r/w 0000 0000h cctxb3da can controller transmit buffer 3 data a register see t ab le 179 5ch r/w 0000 0000h cctxb3db can controller transmit buffer 3 data b register see t ab le 180 can id-look-up table memory; canafm regbase offset 000h to 7fch r/w - cafmem can id-look-up table memory see t ab le 181 can acceptance ?lter; canafr regbase offset 00h r/w 1h camode can acceptance ?lter mode register see t ab le 188 04h r/w 000h casfesa can acceptance ?lter standard frame explicit start address register see t ab le 189 08h r/w 000h casfgsa can acceptance ?lter standard frame group start address register see t ab le 190 0ch r/w 000h caefesa can acceptance ?lter extended frame explicit start address register see t ab le 191 10h r/w 000h caefgsa can acceptance ?lter extended frame group start address register see t ab le 192 14h r/w 000h caeota can acceptance ?lter end of table address register see t ab le 193 18h r 000h calutea can acceptance ?lter look-up table error address register see t ab le 194 1ch r 0h calute can acceptance ?lter look-up table error register see t ab le 195 can central status; cancs regbase offset 0h r 3f 3f3fh cccts can controllers central transmit status register see t ab le 196 4h r 00 003fh cccrs can controllers central receive status register see t ab le 197 8h r 0000h cccms can controllers central miscellaneous status register see t ab le 198 table 162: can register summary continued address type reset value name description reference
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 101 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.4 can controller mode register (ccmode) the can controller mode register is used to change the behavior of the can controller. t ab le 163 shows the bit assignment of the ccmode register. table 163: ccmode register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 6 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 5 rpm [1] r/w x reverse polarity mode 1 rxdc and txdc pins are high for a dominant bit 0* rxdc and txdc pins are low for a dominant bit 4 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 3 tpm [1] [2] r/w x transmit priority mode 1 the priority depends on the contents of the transmit priority register within the transmit buffer 0* the transmit priority depends on the can identi?er 2 stm [1] r/w x self test mode; this bit is only writable in soft reset mode 1 the controller will consider a transmitted message successful if there is no acknowledgment; use this state in conjunction with the self reception request bit in the can controller command register 0* a transmitted message must be acknowledged to be considered successful 1 lom [1] [3] r/w x listen only mode; this bit is only writable in soft reset mode 1 the controller gives no acknowledgment on can, even if a message is successfully received; messages cannot be sent, and the controller operates in error passive mode 0* the can controller acknowledges a successfully-received message
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 102 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] a write access to the rpm, tpm, stm and lom registers is possible only if the soft reset mode is entered previously. [2] in cases where the same transmit priority or the same id is chosen for more than one buffer, then the transmit buffer with the lowest buffer number is sent ?rst. [3] this mode of operation forces the can controller to be error passive. message transmission is not possible. [4] during a hardware reset or when the bus status bit is set 1 (bus-off), the soft reset mode bit is set 1 (present). after the soft reset mode bit is set 0 the can controller will wait for: a) one occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by a hardware reset or a cpu-initiated reset. b) 128 occurrences of bus-free, if the preceding reset has been caused by a can controller initiated bus-off, before re-entering the bus-on mode. [5] when entering soft reset mode, it is not possible to access any other register within the same instruction. 8.5.1.5 can controller command register (cccmd) the can controller command register initiates an action within the transfer layer of the can controller. the cccmd register is write only. t ab le 164 shows the bit assignment of the cccmd register. 0rm [4] [5] r/w 1 soft reset mode 1* soft reset mode active; can operation is disabled, and writable registers can be written. bits having a soft reset mode value are being reset. 0 soft reset mode inactive; the can controller in normal operation and certain registers can not be written table 163: ccmode register bit description continued legend: * reset value bit symbol access value soft reset mode value description table 164: cccmd register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 8 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 7 stb3 w - - select transmit buffer 3; when logic 1, transmit buffer 3 is selected for transmission 6 stb2 w - - select transmit buffer 2; when logic 1, transmit buffer 2 is selected for transmission 5 stb1 w - - select transmit buffer 1; when logic 1, transmit buffer 1 is selected for transmission
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 103 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] upon self reception request a message is transmitted and simultaneously received if the acceptance ?lter is set to the corresponding identi?er. a receive and a transmit interrupt will indicate correct self reception (see also self test mode in mode register). [2] it is possible to select more than one message buffer for transmission. if more than one buffer is selected for transmission (tr = 1 or srr = 1) the internal transmit message queue is organized such as that depending on the transmit priority mode (tpm) the transmit buffer with the lowest can identi?er (id) or the lowest local priority (txprio) wins the prioritization and is sent ?rst. [3] setting the command bits tr and at simultaneously results in transmitting a message once. no re-transmission will be performed in case of an error or arbitration lost (single shot transmission). setting the command bits srr and at simultaneously results in sending the transmit message once using the self-reception feature. no re-transmission will be performed in case of an error or arbitration lost. setting the command bits tr, at and srr simultaneously results in transmitting a message once as described for tr and at. the moment the transmit status bit is set within the status register, the internal transmission request bit is cleared automatically. setting tr and srr simultaneously will ignore the set srr bit. [4] after reading the contents of the receive buffer, the cpu can release this memory space by setting the release receive buffer bit to 1. this may result in another message becoming immediately available. if there is no other message available, the receive interrupt bit is reset. if the rrb command is given, it will take at least 2 internal clock cycles before a new interrupt is generated. 4 srr [1] [2] [3] w - - self reception request; when logic 1, a message shall be transmitted from the selected transmit buffer and received simultaneously; transmission and self reception request has to be set simultaneously with stb3, stb2 or stb1 3 cdo w - - clear data overrun; when logic 1, the data overrun bit in the can controller status register is cleared; this command bit is used to clear the data overrun condition signalled by the data overrun status bit; as long as the data overrun status bit is set no further data overrun interrupt is generated 2 rrb [4] w - - release receive buffer; when logic 1, the receive buffer, representing the message memory space in the double receive buffer is released 1at [5] [3] w - - abort transmission; when logic 1, if not already in progress, a pending transmission request is cancelled; if the abort transmission and transmit request bits are set in the same write operation, frame transmission is attempted once and no retransmission is attempted if an error is ?agged nor if arbitration is lost 0tr [2] [6] [3] w - - transmission request; when logic 1, a message from the selected transmit buffer is queued for transmission table 164: cccmd register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 104 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [5] the abort transmission bit is used when the cpu requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. a transmission already in progress is not stopped. in order to see if the original message has been either transmitted successfully or aborted, the transmission complete status bit should be checked. this should be done after the transmit buffer status bit has been set 1 or a transmit interrupt has been generated. [6] if the transmission request or the self-reception request bit was set 1 in a previous command, it cannot be cancelled by resetting the bits. the requested transmission may only be cancelled by setting the abort transmission bit. 8.5.1.6 can controller global status register (ccgs) the can controller global status register re?ects the global status of the can controller including the transmit and receive error counter values. t ab le 165 shows the bit assignment of the ccgs register. table 165: ccgs register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 txerr[7:0] r/w 00h* x transmit error counter; this register re?ects the current value of the transmit error counter; this register is only writable in soft reset mode; if a bus off event occurs, the transmit error counter is initialized to 127 to count the minimum protocol-de?ned time (128 occurrences of the bus free signal); reading the transmit error counter during this time gives information about the status of the bus off recovery; if bus off is active, a write access to transmit error counter in the range of 0 to 254 clears the bus off ?ag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of soft reset mode bit 23 to 16 rxerr[7:0] r/w 00h* x receive error counter; this register re?ects the current value of the receive error counter; this register is only writable in soft reset mode; if a bus off event occurs, the receive error counter is initialized to 00h; as long as the bus off condition is valid, writing to this register has no effect 15 to 8 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 7bs [1] r 0 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 105 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 6es [2] r 0 error status 1 one or both of the transmit and receive error counters has reached the limit set in the error warning limit register 0* 5ts [3] r 1 transmit status 1* the can controller is transmitting a message 0 4rs [3] r 1 receive status 1* the can controller is receiving a message 0 3 tcs [4] r x transmission complete status 1* all requested message transmissions have been successfully completed 0 at least one of the previously requested transmission is not yet completed 2 tbs r 1 transmit buffer status 1* all transmit buffers are available for the cpu 0 at least one of the transmit buffers contains a previously queued message that has not yet been sent 1 dos [5] r 0 data overrun status 1 a message was lost because the preceding message to this can controller was not read and released quickly enough 0* no data overrun has occurred 0 rbs [6] r 0 receive buffer status 1 at least one complete message is available in the double receive buffer; this bit is cleared by the release receive buffer command in the can controller command register if no subsequent received message is available 0* no message is available in the double receive buffer table 165: ccgs register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 106 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] when the transmit error counter exceeds the limit of 255, the bus status bit is set 1 (bus-off), the can controller will set the soft reset mode bit to 1 (present) and an error warning interrupt is generated, if enabled. afterwards the transmit error counter is set to 127 and the receive error counter is cleared. it will stay in this mode until the cpu clears the soft reset mode bit. once this is completed the can controller will wait the minimum protocol-de?ned time (128 occurrences of the bus-free signal) counting down the transmit error counter. after that the bus status bit is cleared (bus-on), the error status bit is set 0 (ok), the error counters are reset and an error warning interrupt is generated, if enabled. reading the tx error counter during this time gives information about the status of the bus-off recovery. [2] errors detected during reception or transmission will affect the error counters according to the can speci?cation. the error status bit is set when at least one of the error counters has reached or exceeded the error warning limit. an error warning interrupt is generated, if enabled. the default value of the error warning limit after hardware reset is 96 decimal, see also ccewl register bits. [3] if both the receive status and the transmit status bits are 0 (idle) the can-bus is idle. if both bits are set the controller is waiting to become idle again. after hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. after bus-off this will take 128 times of 11 consecutive recessive bits. [4] the transmission complete status bit is set 0 (incomplete) whenever the transmission request bit or the self reception request bit is set 1 at least for one of the three transmit buffers. the transmission complete status bit will remain 0 until all messages are transmitted successfully. [5] if there is not enough space to store the message within the receive buffer, that message is dropped and the data overrun condition is signalled to the cpu in the moment this message becomes valid. if this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. [6] after reading all messages and releasing their memory space with the command release receive buffer this bit is cleared. 8.5.1.7 can controller interrupt and capture register (ccic) the can controller interrupt and capture register allows the identi?cation of an interrupt source. reading the interrupt register clears all interrupt bits except the receive interrupt bit which requires release receive buffer command. if there is another message available within the receive buffer after the release receive buffer command, the receive interrupt is set again. otherwise the receive interrupt keeps cleared. bus errors are captured in a detailed error report. when a transmitted message loses arbitration, the bit where the arbitration has lost is captured. once either of these registers is captured, its value will remain the same until it is read, at which time it is released to capture a new value. the ccic register is read only. t ab le 166 shows the bit assignment of the ccic register. table 166: ccic register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 29 reserved - - - reserved; do not modify, read as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 107 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 28 to 24 alcbit[4:0] r 00h* x arbitration lost bit; in case the arbitration is lost while transmitting a message, the bit number within the frame is captured into this register) 00h* arbitration lost in the ?rst, most signi?cant bit of the identi?er :: 0bh 11: arbitration lost in srtr bit (rtr bit for standard frame messages) 0ch 12: arbitration lost in ide bit 13: arbitration lost in 12th bit of identi?er (extended frame only) :: 1eh 30: arbitration lost in last bit of identi?er (extended frame only) 0fh 31: arbitration lost in rtr bit (extended frames only) 23 to 22 errt[1:0] r 0h* x error type; the bus error type is captured in this register; see t ab le 167 21 errdir r x error direction 1 he bus error is captured during receiving 0* the bus error is captured during transmitting 20 to 16 errcc[4:0] r 00h* x error code capture; the location of the error within the frame is captured in this register; see t ab le 168 15 to 11 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 10 ti3 r 0 transmit interrupt 3 1 the transmit buffer status 3 is released (transition from logic 0 to logic 1) and the transmit interrupt enable 3 is set 0* 9 ti2 r 0 transmit interrupt 2 1 the transmit buffer status 2 is released (transition from logic 0 to logic 1) and the transmit interrupt enable 2 is set 0* 8 idi r 0 id ready interrupt 1 a can identi?er has been received and the id ready interrupt enable is set 0* table 166: ccic register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 108 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] the receive interrupt bit is not cleared upon a read access to the interrupt register. giving the command release receive buffer will clear ri temporarily. if there is another message available within the receive buffer after the release command, ri is set again. otherwise ri keeps cleared. 7 bei r x bus error interrupt 1 a can controller has detected a bus error and the bus error interrupt enable is set 0* 6 ali r 0 arbitration lost interrupt 1 the can controller has lost arbitration while attempting to transmit and the arbitration lost interrupt enable is set 0* 5 epi r 0 error passive interrupt 1 the can controller has reached the error passive status (at least one error counter exceeds the can protocol de?ned level of 127) or if the can controller is in error passive status and enters the error active status again and the error passive interrupt enable is set 0* 4 reserved - - - reserved; read as logic 0 3 doi r 0 data overrun interrupt 1 the data overrun occurred and the data overrun interrupt enable is set 0* 2 ewi r x error warning interrupt 1 a change of either the error status or bus status occurred and the error warning interrupt enable is set 0* 1 ti1 r 0 transmit interrupt 1 1 the transmit buffer status 1 is released (transition from logic 0 to logic 1) and the transmit interrupt enable 1 is set 0* 0ri [1] r 0 receive interrupt 1 the receive buffer status is logic 1 and the receive interrupt enable is set 0* table 166: ccic register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 109 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 167: bus error type values errt[1:0] function 00 bit error 01 form error 10 stuff error 11 other error table 168: bus error capture code values errcc [4:0] function 0 0000 reserved 0 0001 reserved 0 0010 identi?er bits 21 to 28 0 0011 start of frame 0 0100 standard frame rtr bit 0 0101 ide bit 0 0110 reserved 0 0111 identi?er bits 13 to 17 0 1000 crc sequence 0 1001 reserved bit 0 0 1010 data ?eld 0 1011 data length code 0 1100 extended frame rtr bit 0 1101 reserved bit 1 0 1110 identi?er bits 0 to 4 0 1111 identi?er bits 5 to 12 1 0000 reserved 1 0001 active error ?ag 1 0010 intermission 1 0011 tolerate dominant bits 1 0100 reserved 1 0101 reserved 1 0110 passive error ?ag 1 0111 error delimiter 1 1000 crc delimiter 1 1001 acknowledge slot 1 1010 end of frame 1 1011 acknowledge delimiter 1 1100 overload ?ag 1 1101 reserved 1 1110 reserved 1 1111 reserved
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 110 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.8 can controller interrupt enable register (ccie) the can controller interrupt enable register allows enabling the different types of can controller interrupts. t ab le 169 shows the bit assignment of the ccie register. table 169: ccie register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 11 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 10 ti3e r/w x transmit interrupt enable 3 1 an interrupt is generated if the transmit buffer status 3 is released (transition from logic 0 to logic 1) 0* 9 ti2e r/w x transmit interrupt enable 2 1 an interrupt is generated if the transmit buffer status 2 is released (transition from logic 0 to logic 1) 0* 8 idie r/w x id ready interrupt enable 1 an interrupt is generated if a can identi?er has been received 0* 7 beie r/w x bus error interrupt enable 1 an interrupt is generated if a can controller has detected a bus error 0* 6 alie r/w x arbitration lost interrupt enable 1 an interrupt is generated if the can controller has lost arbitration while attempting to transmit 0* 5 epie r/w x error passive interrupt enable 1 an interrupt is generated if the can controller has reached the error passive status (at least one error counter exceeds the can protocol de?ned level of 127) or if the can controller is in error passive status and enters the error active status again 0* 4 reserved - - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 111 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.9 can controller bus timing register (ccbt) the can controller bus timing register de?nes the timing characteristics of the can bus. the bus timing register is only writable in soft reset mode. t ab le 170 shows the bit assignment of the ccbt register. 3 doie r/w x data overrun interrupt enable 1 an interrupt is generated if the data overrun occurred 0* 2 ewie r/w x error warning interrupt enable 1 an interrupt is generated if a change of either the error status or bus status occurred 0* 1 tie1 r/w x transmit interrupt enable 1 1 an interrupt is generated if the transmit buffer status 1 is released (transition from logic 0 to logic 1) 0* 0 rie r/w x receive interrupt enable 1 an interrupt is generated if the receive buffer is not empty 0* table 169: ccie register bit description continued legend: * reset value bit symbol access value soft reset mode value description table 170: ccbt register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 23 sam r/w x 1 the bus is sampled three times; recommended for low/medium speed buses, where ?ltering spikes on the bus-line is bene?cial 0* the bus is sampled once; recommended for high speed buses 22 to 20 tseg2[2:0] r/w 1h* x timing segment 2; time segment after the sample point which is determined by the formula of [1] 19 to 16 tseg1[3:0] r/w ch* x timing segment 1; time segment before the sample point which is determined by the formula of [2]
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 112 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] t seg2 =t scl (tseg2 + 1) [2] t seg1 =t scl (tseg1 + 1) [3] t sjw =t scl (sjw + 1) [4] 8.5.1.10 can controller error warning limit register (ccewl) the can controller error warning limit register sets the limit on the transmit or receive errors at which an interrupt can occur. this register is only writable in soft reset mode. t ab le 171 shows the bit assignment of the ccewl register. 8.5.1.11 can controller status register (ccstat) the can controller status register re?ects the transmit status of all three transmit buffers including the global status of the can controller. the ccstat register is read only. t ab le 172 shows the bit assignment of the ccstat register. 15 to 14 sjw[1:0] r/w 0h* x synchronization jump width; the synchronization jump length is determined by the formula of [3] 13 to 10 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 9 to 0 brp[9:0] r/w 000h* x baud rate prescaler; the baud rate prescaler derives the can clock t scl from the system clock f clk(sys) ; the can controller clock period is calculated by the formula of [4] table 170: ccbt register bit description continued legend: * reset value bit symbol access value soft reset mode value description t scl brp 1 + f clk sys () -------------------- - = table 171: ccewl register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 8 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 ewl[7:0] r/w 60h* x error warning limit; during can operation, this value is compared to both the transmit and receive error counters; if either of these counters matches this value, the error status bit is set
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 113 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 172: ccstat register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 23 bs r 0 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 22 es r 0 error status 1 one or both of the transmit and receive error counters has reached the limit set in the error warning limit register 0* 21 ts3 r 1 transmit status 3 1* the can controller is transmitting a message from transmit buffer 3 0 20 rs r 1 receive status 1* the can controller is receiving a message 0 19 tcs3 [1] r x transmission complete status 3 1* the last requested message transmissions from transmit buffer 3 has been successfully completed 0 the previously requested transmission is not yet completed 18 tbs3 [2] r 1 transmit buffer status 3 1* transmit buffer 3 is available for the cpu 0 transmit buffer 3 contains a previously queued message that has not yet been sent 17 dos r 0 data overrun status 1 a message was lost because the preceding message to this can controller was not read and released quickly enough 0* no data overrun has occurred
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 114 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 16 rbs r 0 receive buffer status 1 at least one complete message is available in the double receive buffer; this bit is cleared by the release receive buffer command in the can controller command register if no subsequent received message is available 0* no message is available in the double receive buffer 15 bs r 0 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 14 es r 0 error status 1 one or both of the transmit and receive error counters has reached the limit set in the error warning limit register 0* 13 ts2 r 1 transmit status 2 1* the can controller is transmitting a message from transmit buffer 2 0 12 rs r 1 receive status 1* the can controller is receiving a message 0 11 tcs2 [1] r x transmission complete status 2 1* the requested message transmission from transmit buffer 2 has been successfully completed 0 the previously requested transmission from transmit buffer 2 is not yet completed 10 tbs2 [2] r 1 transmit buffer status 2 1* transmit buffer 2 is available for the cpu 0 transmit buffer 2 contains a previously queued message that has not yet been sent table 172: ccstat register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 115 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 9 dos r 0 data overrun status; when logic 1, a message was lost because the preceding message to this can controller was not read and released quickly enough; when logic 0, no data overrun has occurred 1 a message was lost because the preceding message to this can controller was not read and released quickly enough 0* no data overrun has occurred 8 rbs r 0 receive buffer status 1 at least one complete message is available in the double receive buffer; this bit is cleared by the release receive buffer command in the can controller command register if no subsequent received message is available 0* no message is available in the double receive buffer 7 bs r 0 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 6 es r 0 error status 1 one or both of the transmit and receive error counters has reached the limit set in the error warning limit register 0* 5 ts1 r 1 transmit status 1 1* the can controller is transmitting a message from transmit buffer 1 0 4 rs r 1 receive status 1* the can controller is receiving a message 0 3 tcs1 [1] r x transmission complete status 1 1* the requested message transmission from transmit buffer 1 has been successfully completed 0 the previously requested transmission from transmit buffer 1 is not yet completed table 172: ccstat register bit description continued legend: * reset value bit symbol access value soft reset mode value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 116 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] the transmission complete status bit is set 0 (incomplete) whenever the transmission request bit or the self reception request bit is set 1 for this tx buffer. the transmission complete status bit will remain 0 until a message is transmitted successfully. [2] if the cpu tries to write to this transmit buffer when the transmit buffer status bit is 0 (locked), the written byte will not be accepted and will be lost without this being signalled. 8.5.1.12 can controller receive buffer message info register (ccrxbmi) the can controller receive buffer message info register re?ects the characteristics of the received message. this register is read only. t ab le 173 shows the bit assignment of the ccrxbmi register. 2 tbs1 [2] r 1 transmit buffer status 1* transmit buffer 1 is available for the cpu 0 transmit buffer 1 contains a previously queued message that has not yet been sent 1 dos r 0 data overrun status 1 a message was lost because the preceding message to this can controller was not read and released quickly enough 0* no data overrun has occurred 0 rbs r 0 receive buffer status 1 at least one complete message is available in the double receive buffer; this bit is cleared by the release receive buffer command in the can controller command register if no subsequent received message is available 0* no message is available in the double receive buffer table 172: ccstat register bit description continued legend: * reset value bit symbol access value soft reset mode value description table 173: ccrxbmi register bit description legend: * reset value bit symbol access value soft reset mode value description 31 ff r x frame format 1 an extended frame format message has been received 0* a standard frame format message has been received 30 rtr r x remote frame request 1 a remote frame has been received 0* a data frame has been received 29 to 20 reserved - - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 117 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.13 can controller receive buffer identi?er register (ccrxbid) the can controller receive buffer identi?er register contains the identi?er ?eld of the received message. this register is read only. t ab le 174 shows the bit assignment of the ccrxbid register. 8.5.1.14 can controller receive buffer data a register (ccrxbda) the can controller receive buffer data a register contains the ?rst four data bytes of the received message. this register is read only. t ab le 175 shows the bit assignment of the ccrxbda register. 19 to 16 dlc[3:0] r 0h* x data length code; this register contains the number of data bytes received in case bit rtr is logic 0 or the requested number of data bytes in case bit rtr is logic 1; values larger than eight are handled as eight data bytes 15 to 11 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 10 bp r x bypass mode 1 the message was received in the acceptance ?lter bypass mode which makes the identi?er index ?eld meaningless 0* 9 to 0 idi[9:0] r 000h* x identi?er index; in case bit bp is not set, this register contains the zero-based number of the look-up table entry at which the acceptance ?lter matched the received identi?er; disabled entries in the standard tables are included in this numbering, but will not be considered for ?ltering table 173: ccrxbmi register bit description continued legend: * reset value bit symbol access value soft reset mode value description table 174: ccrxbid register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 29 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 28 to 0 id[28:0] r 0000 0000h* x identi?er; this register contains the identi?er of received can message; in case a standard frame format has been received, the least signi?cant 11 bits represent the 11-bit identi?er
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 118 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.15 can controller receive buffer data b register (ccrxbdb) the can controller receive buffer data b register contains the second four data bytes of the received message. this register is read only. t ab le 176 shows the bit assignment of the ccrxbdb register. 8.5.1.16 can controller transmit buffer message info register (cctxb1mi, cctxb2mi and cctxb3mi) the can controller transmit buffer message info register re?ects the characteristics of the transmit message. this register is only writable when the transmit buffer is released (corresponding transmit buffer status bit is logic 1). t ab le 177 shows the bit assignment of the cctxb1mi, cctxb2mi and cctxb3mi registers. table 175: ccrxbda register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 db4[7:0] r 00h* x data byte 4; if the data length code value is four or more, this register contains the fourth data byte of the received message 23 to 16 db3[7:0] r 00h* x data byte 3; if the data length code value is three or more, this register contains the third data byte of the received message 15 to 8 db2[7:0] r 00h* x data byte 2; if the data length code value is two or more, this register contains the second data byte of the received message 7 to 0 db1[7:0] r 00h* x data byte 1; if the data length code value is one or more, this register contains the ?rst data byte of the received message table 176: ccrxbdb register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 db8[7:0] r 00h* x data byte 8; if the data length code value is eight or more, this register contains the eighth data byte of the received message 23 to 16 db7[7:0] r 00h* x data byte 7; if the data length code value is seven or more, this register contains the seventh data byte of the received message 15 to 8 db6[7:0] r 00h* x data byte 6; if the data length code value is six or more, this register contains the sixth data byte of the received message 7 to 0 db5[7:0] r 00h* x data byte 5; if the data length code value is ?ve or more, this register contains the ?fth data byte of the received message
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 119 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.17 can controller transmit buffer identi?er register (cctxb1id, cctxb2id and cctxb3id) the can controller transmit buffer identi?er register contains the identi?er ?eld of the transmit message. this register is only writable when the transmit buffer is released (corresponding transmit buffer status bit is logic 1). t ab le 178 shows the bit assignment of the cctxb1id, cctxb2id and cctxb3id registers. table 177: cctxb1mi, cctxb2mi and cctxb3mi register bit description legend: * reset value bit symbol access value soft reset mode value description 31 ff r/w x frame format 1 an extended frame format message is transmitted 0* a standard frame format message is transmitted 30 rtr r/w x remote frame request 1 a remote frame format message is transmitted 0* a data frame format message is transmitted 29 to 20 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 19 to 16 dlc[3:0] r/w 0h* x data length code; this register contains the number of data bytes to be transmitted in case bit rtr is logic 0 or the requested number of data bytes in case bit rtr is logic 1; values larger than eight are handled as eight data bytes 15 to 8 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 txprio[7:0] r/w 00h* x transmit priority; if the transmit priority mode bit in the can controller mode register is set, the transmit buffer with the lowest transmit priority value wins the prioritization and is sent ?rst; in cases where the same transmit priority or the same id is chosen for more than one transmit buffer, then the transmit buffer with the lowest buffer number is send ?rst
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 120 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.18 can controller transmit buffer data a register (cctxb1da, cctxb2da and cctxb3da) the can controller transmit buffer data a register contains the ?rst four data bytes of the transmit message. this register is only writable when the transmit buffer is released (corresponding transmit buffer status bit is logic 1). t ab le 179 shows the bit assignment of the cctxb1da, cctxb2da and cctxb3da registers. 8.5.1.19 can controller transmit buffer data b register (cctxb1db, cctxb2db and cctxb3db) the can controller transmit buffer data b register contains the second four data bytes of the transmit message. this register is only writable when the transmit buffer is released (corresponding transmit buffer status bit is logic 1). t ab le 180 shows the bit assignment of the cctxb1db, cctxb2db and cctxb3db registers. table 178: cctxb1id, cctxb2id and cctxb3id register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 29 reserved - - - reserved; do not modify, read as logic 0, write as logic 0 28 to 0 id[28:0] r/w 0000 0000h* x identi?er; this register contains the identi?er of transmit can message; in case a standard frame format is transmitted, the least signi?cant 11 bits must represent the 11-bit identi?er table 179: cctxb1da, cctxb2da and cctxb3da register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 db4[7:0] r/w 00h* x data byte 4; if the data length code value is four or more, this register contains the fourth data byte of the received message 23 to 16 db3[7:0] r/w 00h* x data byte 3; if the data length code value is three or more, this register contains the third data byte of the received message 15 to 8 db2[7:0] r/w 00h* x data byte 2; if the data length code value is two or more, this register contains the second data byte of the received message 7 to 0 db1[7:0] r/w 00h* x data byte 1; if the data length code value is one or more, this register contains the ?rst data byte of the received message
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 121 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.20 global acceptance ?lter the global acceptance ?lter provides look-up for received identi?ers, called acceptance ?ltering in can terminology, for all the can controllers. it includes a can id look-up table memory, in which software maintains one to ?ve sections of identi?ers. the can id look-up table memory is 2 kb large (512 words each 32 bits). it can contain up to 1024 standard frame identi?ers (sff) or 512 extended frame identi?ers (eff) or a mixture of both types. note that the whole can id look-up table memory is only word accessible. the can id look-up table memory is structured into up to ?ve sections. in each section the identi?ers of a certain can message type are listed, see t ab le 181 . to indicate the boundaries of the different sections within the id look-up table memory, ?ve start address registers exist. in those start address registers the offset regarding the base address canafm (see t ab le 7 ) is stored. the standard frame format fullcan identi?er section always starts at the offset 00h, the following sections start as de?ned in the start address registers. the look-up table ends with the fullcan message object section, starting at the offset caeota. a non-existing section is indicated by equal values in consecutive start-address registers. table 180: cctxb1db, cctxb2db and cctxb3db register bit description legend: * reset value bit symbol access value soft reset mode value description 31 to 24 db8[7:0] r/w 00h* x data byte 8; if the data length code value is eight or more, this register contains the eighth data byte of the received message 23 to 16 db7[7:0] r/w 00h* x data byte 7; if the data length code value is seven or more, this register contains the seventh data byte of the received message 15 to 8 db6[7:0] r/w 00h* x data byte 6; if the data length code value is six or more, this register contains the sixth data byte of the received message 7 to 0 db5[7:0] r/w 00h* x data byte 5; if the data length code value is ?ve or more, this register contains the ?fth data byte of the received message table 181. overview of sections in can id look-up table memory name of section reception method can message frame format explicit ids or group of ids standard frame format fullcan identi?er section stored directly in memory standard frame format (sff) explicit standard frame format explicit identi?er section buffered standard frame format (sff) explicit standard frame format group identi?er section buffered standard frame format (sff) group extended frame format explicit identi?er section buffered extended frame format (eff) explicit extended frame format group identi?er section buffered extended frame format (eff) group
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 122 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers see figure 10 for the structure of the can id look-up table memory. 8.5.1.21 standard frame format fullcan identi?er section if the can acceptance ?lter is set into fullcan mode (efcan = 1) the fullcan identi?er section in the look-up table is enabled. otherwise the acceptance ?lter ignores this section. the entries of the fullcan identi?er section must be arranged in ascending numerical order, one per half word, two per word (see figure 10 ). since each can controller has its own address map, each table entry also contains the number of the can controller to which it applies. this section starts at the offset 00h and contains identi?ers index 0 to (h - 1). the bit allocation is given in t ab le 182 . fig 10. id look-up table memory 001aaa175 29-bit index (h + i + j + k + l - 1) lower bound 29-bit index (h + i + j + k) upper bound : : : 11-bit index (h + i) lower bound 11-bit index (h + i) upper bound 11-bit index (h + i + j - 1) lower bound 11-bit index (h + i + j - 1) upper bound 11-bit index (h + i - 2) 11-bit index (h - 2) : 11-bit index 2 11-bit index 0 29-bit index (h + i + j + k) lower bound 29-bit index (h + i + j + k + l - 1) upper bound 29-bit index (h + i + j + 1) 29-bit index (h + i + j + k - 1) 29-bit index (h + i + j) 11-bit index (h + i - 1) 11-bit index (h - 1) : 11-bit index 3 11-bit index 1 :: :: 11-bit index (h) 11-bit index (h + 1) standard frame format fullcan identifier section h entries i entries j groups k entries l groups extended frame format explicit identifier section extended frame format group identifier section fullcan message object section standard frame format explicit identifier section standard frame format group identifier section casfesa casfgsa caefesa caefgsa caeota table 182. sff fullcan identi?er section bit description bit symbol description 31 to 29 scc even index: can controller number 28 mdb even index: message disable bit; logic 0 is message enabled and logic 1 is message disabled 27 - not used
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 123 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers if an incoming message is detected, the acceptance ?lter tries to ?nd the id in the fullcan section ?rst and continues searching in the following sections. in case of an identi?er match during the acceptance ?lter process, the received fullcan message object data is moved from the receive buffer of the appropriate can controller into the fullcan message object section. t ab le 183 shows the detailed layout structure of one fullcan message stored in the fullcan message object section of the look-up table. the base address of a speci?c message object data can be calculated by the contents of the caeota and the index i of the id in the section (see figure 10 ). message object data address = caeota + (12 i). since the fullcan message object section of the look-up table ram can be accessed both by the acceptance ?lter internal state machine and the cpu, there is a method for insuring that no cpu reads from a fullcan message object occurs while the internal state machine is writing to that object. 26 to 16 id[28:18] even index: 11-bit can 2.0 b identi?er 15 to 13 scc odd index: can controller number 12 mdb odd index: message disable bit; logic 0 is message enabled and logic 1 is message disabled 11 - not used 10 to 0 id[28:18] odd index: 11-bit can 2.0 b identi?er table 183. fullcan message object layout bit symbol description msg_objaddr + 0 31 ff can frame format 30 rtr remote frame request 29 to 26 - not used 25 to 24 sem[1:0] semaphore bits 23 to 23 - not used 22 to 16 rxdlc[6:0] data length code 15 to 11 - not used 10 to 0 id[28:18] identi?er bits 28 to 18 msg_objaddr + 4 31 to 24 rxdata4[7:0] receive data 4 23 to 16 rxdata3[7:0] receive data 3 15 to 8 rxdata2[7:0] receive data 2 7 to 0 rxdata1[7:0] receive data 1 msg_objaddr + 8 31 to 24 rxdata8[7:0] receive data 8 23 to 16 rxdata7[7:0] receive data 7 15 to 8 rxdata6[7:0] receive data 6 7 to 0 rxdata5[7:0] receive data 5 table 182. sff fullcan identi?er section bit description continued bit symbol description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 124 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers for this purpose the acceptance ?lter uses a 3-state semaphore, encoded with the two semaphore bits sem[1:0] for each message object. this mechanism provides the cpu with information about the current state of the acceptance ?lter internal state machine activity in the fullcan message object section. the semaphore operates in the following manner: ? sem[1:0] = 01: acceptance ?lter is in the process of updating the buffer ? sem[1:0] = 11: acceptance ?lter has ?nished updating the buffer ? sem[1:0] = 00: cpu is in the process of reading from the buffer / no update since last reading from the buffer before writing the ?rst data byte into a message object sem[1:0] is set to 01. after having written the last data byte into the message object, the acceptance ?lter internal state will update the semaphore bits by setting sem[1:0] = 11. before reading from a message object, the cpu should read sem[1:0] to determine the current state of the message object. if sem[1:0] = 01, the internal state machine is currently active in this message object. if sem[1:0] = 11, the message object is available to be read. before the cpu begins reading from the message object, it should clear sem[1:0] = 00. when the cpu has ?nished reading, it should check sem[1:0] again. in case of sem[1:0] unequal to 00, the message object has been changed during reading. therefore the contents of the message object should be read out once again. if, on the other hand, sem[1:0] = 00 as expected, the valid data has been successfully read by the cpu. conditions to activate the fullcan mode: ? the efcan bit in the camode register has to be set ? the start address offset of the standard frame format explicit identi?er section casfesa has to be larger than logic 0 ? the available space for the fullcan message object section must be large enough to store one fullcan object for any fullcan identi?er 8.5.1.22 standard frame format explicit identi?er section the entries of the sff explicit identi?er section must be arranged in ascending numerical order, one per half word, two per word (see figure 10 ). since each can controller has its own address map, each entry also contains the number of the can controller to which it applies. this section starts with the casfesa start address register and contains the identi?ers index h to index (h + i - 1). the bit allocation of the ?rst word is given in t ab le 184 . table 184. sff explicit identi?er section bit description bit symbol description 31 to 29 scc even index: can controller number 28 mdb even index: message disable bit; logic 0 is message enabled and logic 1 is message disabled 27 - not used 26 to 16 id[28:18] even index: 11-bit can 2.0 b identi?er
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 125 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers by means of the message disable bits particular can identi?ers can be turned on and off dynamically from acceptance ?ltering. when the acceptance ?lter function is enabled, only the message disable bits in the acceptance ?lter look-up table memory can be changed by software. disabled entries must maintain the ascending sequence of identi?ers. 8.5.1.23 standard frame format group identi?er section the table of sff group identi?er section contains paired upper and lower bounds, one pair per word. these pairs must be arranged in ascending numerical order (see figure 10 ). this section starts with the casfgsa start address register and contains the identi?ers index (h + i) lower bound to index ( h+i+j - 1) upper bound. the bit allocation of the ?rst word is given in t ab le 185 . by means of the message disable bits particular can identi?er groups can be turned on and off dynamically from acceptance ?ltering. when the acceptance ?lter function is enabled, only the message disable bits in the acceptance ?lter look-up table memory can be changed by software. note that in this section the lower bound and upper bound message disable bit must always have the same value. disabled entries must maintain the ascending sequence of identi?ers. 8.5.1.24 extended frame format explicit identi?er section if extended identi?ers (29-bit) are used in the application, at least one of the other two tables in acceptance ?lter look-up table must not be empty, one for explicit extended identi?ers and one for ranges of extended identi?ers. the table of explicit extended identi?ers must be arranged in ascending numerical order (see figure 10 ). this section with start address eff contains the identi?ers id ( i+j+1) to id(i+j+k). the bit allocation of the ?rst word is given in t ab le 186 . 15 to 13 scc odd index: can controller number 12 mdb odd index: message disable bit; logic 0 is message enabled and logic 1 is message disabled 11 - not used 10 to 0 id[28:18] odd index: 11-bit can 2.0 b identi?er table 184. sff explicit identi?er section bit description continued bit symbol description table 185. sff group identi?er section bit description bit symbol description 31 to 29 scc lower bound: can controller number 28 mdb lower bound: message disable bit; logic 0 is message enabled and logic 1 is message disabled 27 - not used 26 to 16 id[28:18] lower bound: 11-bit can 2.0 b identi?er 15 to 13 scc upper bound: can controller number 12 mdb upper bound: message disable bit; logic 0 is message enabled and logic 1 is message disabled 11 - not used 10 to 0 id[28:18] upper bound: 11-bit can 2.0 b identi?er
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 126 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.25 extended frame format group identi?er section the extended frame format (eff) group identi?er section must contain an even number of entries, of the same form as in the eff explicit identi?er section (see figure 10 ). like the eff explicit identi?er section, the eff group identi?er section must be arranged in ascending numerical order. the upper and lower bounds in the section are implicitly paired as an inclusive group of extended addresses, such that any received address that falls in the inclusive group is accepted and received. software must maintain the section to consist of such word pairs. this section starts with caefgsa start address register and contains the identi?ers index (h+i+j+k) lower bound to index ( h+i+j+k+l - 1) upper bound. the bit allocation is given in t ab le 187 . 8.5.1.26 can acceptance ?lter mode register (camode) the can acceptance ?lter mode register is used to change the behavior of the acceptance ?lter. t ab le 188 shows the bit assignment of the camode register. table 186. eff explicit identi?er section bit description bit symbol description 31 to 29 scc can controller number 28 to 0 id[28:0] 29-bit can 2.0 b identi?er table 187. eff group identi?er section bit description bit symbol description caefgsa start address 31 to 29 scc lower bound: can controller number 28 to 0 id[28:0] lower bound: 29-bit can 2.0 b identi?er caefgsa start address + 4 31 to 29 scc upper bound: can controller number 28 to 0 id[28:0] upper bound: 29-bit can 2.0 b identi?er table 188. camode register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0, write as logic 0 2 efcan r/w fullcan extension mode 1 the fullcan functionality is enabled 0* the fullcan functionality is disabled
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 127 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.27 can acceptance ?lter standard frame explicit start address register (casfesa) the can acceptance ?lter standard frame explicit start address register. t ab le 189 shows the bit assignment of the casfesa register. 8.5.1.28 can acceptance ?lter standard frame group start address register (casfgsa) the can acceptance ?lter standard frame group start address register. t ab le 190 shows the bit assignment of the casfgsa register. 1 accbp r/w acceptance ?lter bypass 1 all rx messages are accepted on enabled can controllers; software must set this bit before modifying the contents of any of the acceptance ?lter registers, and before modifying the contents of look-up table ram in any way other than setting or clearing disable bits in standard identi?er entries 0* when both this bit and bit accoff are logic 0, the acceptance ?lter operates to screen received can identi?ers 0 accoff r/w acceptance ?lter off 1* if bit accbp = 0, the acceptance ?lter is not operational; all received can messages are ignored 0 the acceptance ?lter is operational table 188. camode register bit description continued legend: * reset value bit symbol access value description table 189. casfesa register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 2 sfesa[9:0] r/w 00h* standard frame explicit start address; this register de?nes the start address of the section of explicit standard identi?ers in acceptance ?lter look-up table; if the section is empty, write the same value in this register and the sfgsa register; if bit efcan = 1, this value also indicates the size of the section of standard identi?ers which the acceptance ?lter will search and (if found) automatically store received messages in acceptance ?lter section; write access is only possible during the acceptance ?lter bypass or acceptance ?lter off mode; read access is possible in acceptance ?lter on and off mode; the standard frame explicit start address is aligned on word boundaries and therefore the lowest 2 bits must be always logic 0 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 128 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.29 can acceptance ?lter extended frame explicit start address register (caefesa) the can acceptance ?lter extended frame explicit start address register. t ab le 191 shows the bit assignment of the caefesa register. 8.5.1.30 can acceptance ?lter extended frame group start address register (caefgsa) the can acceptance ?lter extended frame group start address register. t ab le 192 shows the bit assignment of the caefgsa register. table 190. casfgsa register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 2 sfgsa[9:0] r/w 00h* standard frame group start address; this register de?nes the start address of the section of grouped standard identi?ers in acceptance ?lter look-up table; if the section is empty, write the same value in this register and the efesa register; the largest value that should be written to this register is 7fch, when only the standard explicit section is used, and the last word (address 7f8h) in acceptance ?lter look-up table is used; write access is only possible during the acceptance ?lter bypass or acceptance ?lter off mode; read access is possible in acceptance ?lter on and off mode; the standard frame group start address is aligned on word boundaries and therefore the lowest 2 bits must be always logic 0 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 191. caefesa register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 2 efesa[9:0] r/w 00h* extended frame explicit start address; this register de?nes the start address of the section of explicit extended identi?ers in acceptance ?lter look-up table; if the section is empty, write the same value in this register and the efgsa register; the largest value that should be written to this register is 7fch, when both extended sections are empty and the last word (address 7f8h) in acceptance ?lter look-up table is used; write access is only possible during the acceptance ?lter bypass or acceptance ?lter off mode; read access is possible in acceptance ?lter on and off mode; the extended frame explicit start address is aligned on word boundaries and therefore the lowest 2 bits must be always logic 0 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 129 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.31 can acceptance ?lter end of look up table address register (caeota) the can acceptance ?lter end of look up table address register. t ab le 193 shows the bit assignment of the caeota register. table 192. caefgsa register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 2 efgsa[9:0] r/w 00h* extended frame group start address; this register de?nes the start address of the section of grouped extended identi?ers in acceptance ?lter look-up table; if the section is empty, write the same value in this register and the eota register; the largest value that should be written to this register is 7fch, when this section is empty and the last word (address 7f8h) in acceptance ?lter look-up table is used; write access is only possible during the acceptance ?lter bypass or acceptance ?lter off mode; read access is possible in acceptance ?lter on and off mode; the extended frame group start address is aligned on word boundaries and therefore the lowest 2 bits must be always logic 0 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 193. caeota register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; do not modify, read as logic 0, write as logic 0 11 to 2 eota[9:0] r/w 00h* end of look-up table address. the largest value of the register caeota should never exceed 7fc. if bit efcan = 0, the register should contain the next address above the last active acceptance ?lter identi?er section. if bit efcan = 1, the register contains the start address of the fullcan message object section. in case of an identi?er match in the standard frame format fullcan identi?er section during the acceptance ?lter process, the received fullcan message object data is moved from the receive buffer of the appropriate can controller into the fullcan message object section. each de?ned fullcan message needs three address lines for the message data in the fullcan message object data section. write access is only possible during the acceptance ?lter bypass or acceptance ?lter off mode; read access is possible in acceptance ?lter on and off mode. 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 130 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.32 can acceptance ?lter look-up table error address register (calutea) the can acceptance ?lter look-up table error address register represents the address in the look-up table at which a problem has been detected when the look-up table error bit is set. the calutea register is read only. t ab le 194 shows the bit assignment of the calutea register. 8.5.1.33 can acceptance ?lter look-up table error register (calute) the can acceptance ?lter look-up table error register provides the con?guration status of the look-up table contents. in case of an error an interrupt is generated via the general can interrupt input source of the vectored interrupt controller. the calute register is read-only. t ab le 195 shows the bit assignment of the calute register. 8.5.1.34 can controllers central transmit status register (cccts) the can controllers central transmit status register provides bundled access to transmission status of all the can controllers. the status ?ags are the same as present in the status register of the corresponding can controller. the cccts register is read only. t ab le 196 shows the bit assignment of the cccts register. table 194. calutea register bit description legend: * reset value bit symbol access value description 31 to 11 reserved - - reserved; do not modify, read as logic 0, write as logic 0 10 to 2 lutea[8:0] r 00h* look-up table error address; this register contains the address in the look-up table at which the acceptance ?lter encountered an error in the content of the tables; this address is valid when the look-up table error bit is set; reading this register clears the lute look-up table error bit 1 to 0 reserved - - reserved; do not modify, read as logic 0, write as logic 0 table 195. calute register bit description legend: * reset value bit symbol access value description 31 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 lute r look-up table error 1 the acceptance ?lter has encountered an error in the content of the look-up table; reading the lutea register clears this bit; this error condition is part of the general can interrupt input source 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 131 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 196. cccts register bit description legend: * reset value bit symbol access value description 31 to 22 reserved - - reserved; do not modify, read as logic 0, write as logic 0 21 tcs5 r can controller 5 transmission completed status 1* the transmission was completed successfully 0 20 tcs4 r can controller 4 transmission completed status 1* the transmission was completed successfully 0 19 tcs3 r can controller 3 transmission completed status 1* the transmission was completed successfully 0 18 tcs2 r can controller 2 transmission completed status 1* the transmission was completed successfully 0 17 tcs1 r can controller 1 transmission completed status 1* the transmission was completed successfully 0 16 tcs0 r can controller 0 transmission completed status 1* the transmission was completed successfully 0 15 to 14 reserved - - reserved; do not modify, read as logic 0, write as logic 0 13 tbs5 r can controller 5 transmit buffer status 1* the transmit buffers are empty 0 12 tbs4 r can controller 4 transmit buffer status 1* the transmit buffers are empty 0 11 tbs3 r can controller 3 transmit buffer status 1* the transmit buffers are empty 0 10 tbs2 r can controller 2 transmit buffer status 1* the transmit buffers are empty 0 9 tbs1 r can controller 1 transmit buffer status 1* the transmit buffers are empty 0 8 tbs0 r can controller 0 transmit buffer status 1* the transmit buffers are empty 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 132 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.1.35 can controllers central receive status register (cccrs) the can controllers central receive status register provides bundled access to reception status of all the can controllers. the status ?ags are the same as present in the status register of the corresponding can controller. the cccrs register is read only. t ab le 197 shows the bit assignment of the cccrs register. 7 to 6 reserved - - reserved; do not modify, read as logic 0, write as logic 0 5 ts5 r can controller 5 transmit status 1* a message is being transmitted 0 4 ts4 r can controller 4 transmit status 1* a message is being transmitted 0 3 ts3 r can controller 3 transmit status 1* a message is being transmitted 0 2 ts2 r can controller 2 transmit status 1* a message is being transmitted 0 1 ts1 r can controller 1 transmit status 1* a message is being transmitted 0 0 ts0 r can controller 0 transmit status 1* a message is being transmitted 0 table 196. cccts register bit description continued legend: * reset value bit symbol access value description table 197. cccrs register bit description legend: * reset value bit symbol access value description 31 to 22 reserved - - reserved; do not modify, read as logic 0, write as logic 0 21 dos5 [1] r can controller 5 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0* 20 dos4 [1] r can controller 4 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 133 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 19 dos3 [1] r can controller 3 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0* 18 dos2 [1] r can controller 2 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0* 17 dos1 [1] r can controller 1 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0* 16 dos0 [1] r can controller 0 data overrun status 1 the received message was lost due to not fast enough read out of preceding message 0* 15 to 14 reserved - - reserved; do not modify, read as logic 0, write as logic 0 13 rbs5 [1] r can controller 5 receive buffer status 1 the receive buffers contains a received message 0* 12 rbs4 [1] r can controller 4 receive buffer status 1 the receive buffers contains a received message 0* 11 rbs3 [1] r can controller 3 receive buffer status 1 the receive buffers contains a received message 0* 10 rbs2 [1] r can controller 2 receive buffer status 1 the receive buffers contains a received message 0* 9 rbs1 [1] r can controller 1 receive buffer status 1 the receive buffers contains a received message 0* 8 rbs0 [1] r can controller 0 receive buffer status 1 the receive buffers contains a received message 0* 7 to 6 reserved - - reserved; do not modify, read as logic 0, write as logic 0 5 rs5 r can controller 5 receive status 1* a message is being received 0 table 197. cccrs register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 134 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] this bit is unchanged in case a fullcan message is received. 8.5.1.36 can controllers central miscellaneous status register (cccms) the can controllers central miscellaneous status register provides bundled access to the bus and error status of all the can controllers. the status ?ags are the same as present in the status register of the corresponding can controller. the cccms register is read only. t ab le 198 shows the bit assignment of the cccms register. 4 rs4 r can controller 4 receive status 1* a message is being received 0 3 rs3 r can controller 3 receive status 1* a message is being received 0 2 rs2 r can controller 2 receive status 1* a message is being received 0 1 rs1 r can controller 1 receive status 1* a message is being received 0 0 rs0 r can controller 0 receive status 1* a message is being received 0 table 197. cccrs register bit description continued legend: * reset value bit symbol access value description table 198. cccms register bit description legend: * reset value bit symbol access value description 31 to 14 reserved - - reserved; do not modify, read as logic 0, write as logic 0 13 bs5 r can controller 5 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 12 bs4 r can controller 4 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 135 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 11 bs3 r can controller 3 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 10 bs2 r can controller 2 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 9 bs1 r can controller 1 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 8 bs0 r can controller 0 bus status 1 the can controller is currently prohibited from bus activity because the transmit error counter reached its limiting value of ffh 0* 7 to 6 reserved - - reserved; do not modify, read as logic 0, write as logic 0 5 es5 r can controller 5 error status 1 error warning limit has been exceeded 0* 4 es4 r can controller 4 error status; when logic 1, error warning limit has been exceeded 1 error warning limit has been exceeded 0* 3 es3 r can controller 3 error status 1 error warning limit has been exceeded 0* 2 es2 r can controller 2 error status 1 error warning limit has been exceeded 0* 1 es1 r can controller 1 error status 1 error warning limit has been exceeded 0* 0 es0 r can controller 0 error status 1 error warning limit has been exceeded 0* table 198. cccms register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 136 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2 lin 8.5.2.1 overview the SJA2020 contains four lin master controllers which can be used as dedicated lin master controller or as standard 450 uart with additional support for the sync break generation. the key features are: ? complete lin message handling and transfer ? one interrupt per lin message ? slave response time out detection ? programmable sync break length ? automatic sync ?eld generation ? programmable inter byte space ? hardware of software parity generation ? automatic checksum generation ? fault con?nement ? fractional baud rate generator ? con?gurable as standard uart 8.5.2.2 lin pin description the four lin controllers in the SJA2020 have the following pins. the lin pins are combined with other functions on the port pins of the SJA2020, see section 8.3.2 . t ab le 199 shows the lin pins, x runs from 0 to 3. 8.5.2.3 register mapping the lin master controller registers are shown in t ab le 200 . the lin master controller registers have an offset to the base address lin regbase which can be found in the memory map (see t ab le 7 ). the function of a register is dependent on the lin master controller mode (bit lm). table 199: lin controller pins symbol direction description linx txdl out lin channel x transmit data output linx rxdl in lin channel x receive data input table 200. lin register summary address type reset value name description reference lin master controller common registers 00h r/w 01h lmode lin master controller mode register see t ab le 201 04h r/w 00h lcfg lin master controller con?guration register see t ab le 202 08h r/w 00h lcmd lin master controller command register see t ab le 205
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 137 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.4 lin master controller mode register (lmode) the lin master controller mode register provides the selection between the lin master controller and uart con?guration. t ab le 201 shows the bit assignment of the lmode register. 0ch r/w 0 0001h lfbrg lin master controller fractional baud rate generator register see t ab le 206 lin master controller registers (bit lm = 0) 10h r 342h lstat lin master controller status register see t ab le 207 14h r 000h lic lin master controller interrupt and capture register see t ab le 208 18h r/w 10h lie lin master controller interrupt enable register see t ab le 210 1ch - - reserved reserved for future expansion 20h r/w 00h lcs lin master controller check sum register see t ab le 211 24h r/w 00h lto lin master controller time-out register see t ab le 212 28h r/w 000 0000h lid lin master controller message buffer identi?er register see t ab le 213 2ch r/w 0000 0000h ldata lin master controller message buffer data a register see t ab le 214 30h r/w 0000 0000h ldatb lin master controller message buffer data b register see t ab le 215 34h r/w 0000 0000h ldatc lin master controller message buffer data c register see t ab le 216 38h r/w 0000 0000h ldatd lin master controller message buffer data d register see t ab le 217 lin uart registers (bit lm = 1) 10h r - rbr receiver buffer register see t ab le 218 w - thr transmit holding register see t ab le 219 14h r/w 0h ier interrupt enable register see t ab le 220 18h r 1h iir interrupt id register see t ab le 221 1ch r/w 00h lcr line control register see t ab le 223 20h - - reserved reserved for future expansion 24h r 60h lsr line status register see t ab le 226 28h - - reserved reserved for future expansion 2ch r/w 00h scr scratch register see t ab le 227 table 200. lin register summary continued address type reset value name description reference
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 138 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.5 lin master controller con?guration register (lcfg) the lin master controller con?guration register is used to change the length for the sync break ?eld, the inter byte space and contains software enable bits for the identi?er parity and checksum calculation. in lin master controller mode, the register is only writable if the lin master controller is in reset mode. t ab le 202 shows the bit assignment of the lcfg register. table 201. lmode register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 lm r/w lin master controller mode. changing from lin master controller mode to uart mode is only possible if the lin reset mode was set before and should be done with bit lm = 1 and bit lrm = 1; changing from uart mode to lin master controller mode should be done with bit lm = 0 and bit lrm=1 1 the lin master controller operates in uart mode 0* the lin master controller operates as lin master controller 6 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 lrm r/w lin reset mode; only writable in lin master controller mode 1* the lin master controller is in reset mode and the current message transmission or reception is aborted; the registers lcmd, lstat, lic, lcs, lid, ldata, ldatb, ldatc and ldatd get their reset value 0 the lin master controller is in normal operation mode table 202. lcfg register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 swpa r/w software id parity 1 the software generated id parity from the message buffer is used to send onto the lin bus 0* only the hardware generated parity is used to send onto the lin bus 6 swcs r/w software checksum 1 the checksum is generated by software 0* the checksum is generated by hardware 5 reserved - - reserved; do not modify, read as logic 0, write as logic 0 4 to 3 ibs[1:0] r/w 0h* inter byte space length; the inter byte space length is inserted during transmission; see t ab le 203 2 to 0 sbl[2:0] r/w 0h* sync break logic 0 length; writing a value of 7h will always read as 6h; see t ab le 204
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 139 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.6 lin master controller command register (lcmd) the lin master controller command register is used to initiate a lin message transmission. in lin master controller mode, the register is only writable if the lin master controller is in reset mode. a dedicated sync break generator is added to the standard uart functionality to ease the sync break generation for lin messages with a standard uart. a break interrupt is generated after the sync break delimiter has been transmitted if enabled. t ab le 205 shows the bit assignment of the lcmd register. table 203: inter byte space length con?guration bits ibs[1:0] function 00 0 bits inter byte space length 01 1 bits inter byte space length 10 2 bits inter byte space length 11 3 bits inter byte space length table 204: sync break length con?guration bits sbl[2:0] function 000 10 bits sync break length 001 11 bits sync break length 010 12 bits sync break length 011 13 bits sync break length 100 14 bits sync break length 101 15 bits sync break length 110 16 bits sync break length 111 16 bits sync break length table 205: lcmd register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 ssb r/w send sync break; only writable in lin uart mode 1 a sync break is send onto the lin bus; this bit is automatically cleared 0* 6 to 1 reserved - - reserved; do not modify, read as logic 0, write as logic 0 0 tr r/w transmit request; only writable in lin master controller mode 1 a transmission of a complete lin message will be initiated; this bit is automatically cleared 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 140 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.7 lin master controller fractional baud rate generator register (lfbrg) the lin master controller fractional baud rate generator register stores the divisor in 16-bit binary format and the fraction in 4-bit binary format for the programmable baud generator. the output frequency of the baud generator is 16 times the baud rate. the input frequency of the baud generator is the system clock frequency f clk(sys) divided by the divisor plus fraction value. in lin master controller mode this register is only writeable in reset mode. the baud rate can be calculated from the following formula: t ab le 206 shows the bit assignment of the lfbrg register. 8.5.2.8 lin master controller status register (lstat) the lin master controller status register re?ects the status of the lin master controller. figure 11 shows the status ?ag handling in terms of transmitting and receiving header and response ?elds. the lstat register is read only. t ab le 207 shows the bit assignment of the lstat register. table 206. lfbrg register bit description legend: * reset value bit symbol access value description 31 to 20 reserved - - reserved; do not modify, read as logic 0, write as logic 0 19 to 16 frac r/w 0h* fractional value; in lin uart mode only writable if in reset mode; contains the 4-bit fraction of the baud division 15 to 0 int r/w 0001h* integer value; in lin uart mode only writable if in reset mode; contains the 16-bit baud rate divisor baudrate f clk sys () 16 int frac + -------------------------------------------- - =
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 141 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers fig 11. lin master controller status ?ag handling table 207. lstat register bit description legend: * reset value bit symbol access value description 31 to 10 reserved - - reserved; read as logic 0 9 ttl r txd line level 1* the current txd line level is dominant 0 the current txd line level is recessive 8 rll r rxd line level 1* the current rxd line level is dominant 0 the current rxd line level is recessive 7 reserved - - reserved; read as logic 0 001aaa173 hs is = mba mr rs ts case 2 rs ts case 1 cleared with transmit message complete or bit error or line clamped error condition cleared with receive message complete or bit error or line clamped error condition or time-out condition released/idle with transmit message complete or receive message complete or bit error or line clamped error condition or time-out condition case 2: dd = 1 case 1: dd = 0 master: sending, slave: receiving master: sending, slave: receiving header fields master: sending, slave: receiving master: sending, slave: receiving response fields receive message complete interrupt transmit message complete interrupt
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 142 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.9 lin master controller interrupt and capture register (lic) the lin master controller interrupt and capture register determines when the lin master controller gives an interrupt request if the corresponding interrupt enable has been set. reading the interrupt register clears the interrupt source. a detailed bus error capture is reported. the lic register is read only. t ab le 208 shows the bit assignment of the lic register. 6 is r idle status 1* the lin bus is idle 0 the lin bus is active 5 es r error status 1 a bit-error of line clamped error condition was detected 0* no errors have been detected; the error status is cleared automatically when a new transmission is initiated 4 ts r transmit status 1 the lin master controller is transmitting lin response ?elds 0* 3 rs r receive status 1 the lin master controller is receiving lin response ?elds 0* 2 hs r header status 1 the lin master controller is transmitting the lin header ?elds 0* 1 mba r message buffer access 1* the message buffer is released and available for cpu access 0 the message buffer is locked and the cpu cannot access the message buffer; a message is either waiting for transmission or is in transmitting process or receiving a message 0 mr r message received 1 the message buffer contains a valid received message 0* the message buffer does not contain a valid message; the message received status is cleared automatically with a write access to the message buffer or by a new transmission request table 207. lstat register bit description continued legend: * reset value bit symbol access value description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 143 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 208. lic register bit description legend: * reset value bit symbol access value description 31 to 12 reserved - - reserved; read as logic 0 11 to 8 ec[3:0] r 0h* error capture; see t ab le 209 7 reserved - - reserved; read as logic 0 6 wpi r wake-up and lin protocol error interrupt 1 a dominant bus level has been detected when the lin bus was idle; a dominant bus level on the lin bus can be caused by a wake-up message of a slave node as well as by arbitrary created or faulty generated messages of lin slaves or by a stuck dominant level 0* 5 rtlcei r line clamped error interrupt 1 no valid message can be generated on the lin bus due to clamped dominant or recessive rxd or txd line 0* 4 nri r slave not responding error interrupt 1 the slave response is not completed within a certain time out period; the time out period is con?gurable via the time out register 0* 3 csi r checksum error interrupt 1 the received checksum ?eld does not match with the calculated checksum 0* 2 bei r 0* bit error interrupt; the error capture bits represent the detailed status in case of (when this bit is logic 1): a difference between transmit and receive bit stream is detected the con?gured inter byte space length is violated a stop bit of ?elds from received slave responses was not recessive 1 ti r transmit message complete interrupt 1 a complete lin message frame was transmitted or in cases where data length code is set to logic 0 (no response ?elds can be expected) 0* 0 ri r receive message complete interrupt 1 the last byte, the checksum ?eld of the incoming bit stream is moved from receive shift register into the message buffer 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 144 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.10 lin master controller interrupt enable register (lie) the lin master controller interrupt enable register determines when the lin master controller gives an interrupt request if the corresponding interrupt enable has been set. t ab le 210 shows the bit assignment of the lie register. table 209: bus error capture interpretation bits ec[3:0] function 0000 bit error in sync break ?eld 0001 bit error in sync ?eld 0010 bit error in identi?er ?eld 0011 bit error in data ?eld 0100 bit error in checksum ?eld 0101 bit error in inter byte space 0110 bit error in stop bit of received slave responses 0111 reserved 1000 recessive line clamped error; rxd / txd line stuck recessive 1001 dominant line clamped error; rxd / txd line stuck dominant 1010 reserved :: 1111 reserved table 210. lie register bit description legend: * reset value bit symbol access value description 31 to 7 reserved - - reserved; do not modify, read as logic 0, write as logic 0 6 wpie r/w wake up and lin protocol error interrupt enable 1 detection of a dominant bus level when the lin bus was idle results in the respective interrupt 0* 5 rtlceie r/w line clamped error interrupt enable; when logic 1, whenever no valid message can be generated on the lin bus results in the respective interrupt 1 whenever no valid message can be generated on the lin bus results in the respective interrupt 0* 4 nrie r/w slave not responding error interrupt enable 1* whenever the slave response is not completed within the con?gured time out period results in the respective interrupt 0 3 csie r/w checksum error interrupt enable 1 whenever the received checksum ?eld does not match with the calculated checksum results in the respective interrupt 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 145 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.11 lin master controller checksum register (lcs) the lin master controller lin master controller checksum register contains the checksum value. in cases when the lin master controller is transmitting the response ?elds, the checksum register contains the checksum value to be transmitted onto the lin bus. in cases when the lin master controller is receiving the response ?elds, the checksum register contains the received checksum from the slave. if the software checksum bit in the con?guration register is set to logic 0, the checksum register appears to the cpu as a read only memory. by setting the software checksum bit the checksum register appears to the cpu as a read/write memory. in this case and before a transmission is initiated, the software has to provide the checksum to the checksum register. t ab le 211 shows the bit assignment of the lcs register. 8.5.2.12 lin master controller time-out register (lto) the lin master controller time-out register is used to de?ne the maximum number of bit times (t bit ) within a response from all lin slaves connected to one node should be completed. the time-out starts as soon as the lin header was transmitted (the value of the time-out register is decremented with every bit time) and a slave response is expected. when enabled, the slave not responding error interrupt (nri) gets asserted as soon as the time-out limit is exceeded. 2 beie r/w bit error interrupt enable 1 detection of a bit error results in the respective interrupt 0* 1 tie r/w transmit message complete interrupt enable 1 whenever a complete lin message frame was transmitted or in cases where data length code is set to logic 0 (no response ?elds can be expected) results in the respective interrupt 0* 0 rie r/w receive message complete interrupt enable 1 whenever the last byte, the checksum ?eld of the incoming bit stream is moved from receive shift register into the message buffer results in the respective interrupt 0* table 210. lie register bit description continued legend: * reset value bit symbol access value description table 211. lcs register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 cs r/w 00h* lin message checksum; when the lin master controller is transmitting, the checksum register contains the hardware or software calculated checksum value depending on the software checksum bit; when the lin master controller is receiving, the checksum register contains the received checksum value from the slave node
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 146 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the time-out (t to ) time to be programmed can be calculated from the following formulas: with note: t bit is the nominal time required to transmit a bit, as de?ned in lin physical layer; n data is the number of data ?elds sent with the slave response. t ab le 212 shows the bit assignment of the lto register. 8.5.2.13 lin master controller message buffer registers (lid, ldata, ldatb, ldatc and ldatd) the access to the message buffer is limited and controlled by the message buffer access bit of the status register. the access to the lin master controller message buffer registers is only possible when the lin master controller ip is in operating mode. before accessing the message buffer the cpu should always read the message buffer access bit ?rst to determine whether an access is possible or not. in cases where the message buffer is locked a write access is not successful whereas a read delivers logic 0 as result. the ?rst part of the message buffer is the lin message identi?er register (lid) containing the header information and control format of the lin message. t ab le 213 shows the bit assignment of the lid register. fig 12. time-out period for all lin slave nodes table 212. lto register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 to 0 to r/w 00h* lin message time-out; this register de?nes the maximum number of bit times when a response from all slave nodes should be completed t to t resp max () t bit ---------------------- 1.4 t resp nom () t bit ---------------------- - == t resp nom () 10 n data 1 + t bit ---------------------- - = 001aaa220 header response data field(s) + checksum field data field(s) + checksum field expected message complete time frame minimum frame length maximum frame length time-out period slave is sending and master is receiving
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 147 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers the rest of the message buffer contains the lin message data registers (ldata, ldatb, ldatc and ldatd). t ab le 214 , t ab le 215 , t ab le 216 and t ab le 217 show the bit assignment of the ldata, ldatb, ldatc and ldatd registers, respectively. table 213. lid register bits legend: * reset value bit symbol access value description 31 to 26 reserved - - reserved; do not modify, read as logic 0, write as logic 0 25 csid r/w checksum id inclusion 1 the identi?er ?eld is included in the checksum calculation 0* the identi?er ?eld is not included in the checksum calculation 24 dd r/w data direction 1 the response ?eld is expected to be send by a slave node 0* the response ?eld is sent by the lin master controller 23 to 21 reserved - - reserved; do not modify, read as logic 0, write as logic 0 20 to 16 dlc[4:0] r/w 00h* data length code; represents the binary number of data bytes in the lin message response ?eld; data length code values larger than 16 are handled as the maximum number of 16 15 to 8 reserved - - reserved; do not modify, read as logic 0, write as logic 0 7 p1 r/w 0* lin message parity bit 1 6 p0 r/w 0* lin message parity bit 0 5 to 0 id r/w 00h* lin message identi?er table 214. ldata register bits legend: * reset value bit symbol access value description 31 to 24 df4[7:0] r/w 00h* lin message data ?eld 4 23 to 16 df3[7:0] r/w 00h* lin message data ?eld 3 15 to 8 df2[7:0] r/w 00h* lin message data ?eld 2 7 to 0 df1[7:0] r/w 00h* lin message data ?eld 1 table 215. ldatb register bits legend: * reset value bit symbol access value description 31 to 24 df8[7:0] r/w 00h* lin message data ?eld 8 23 to 16 df7[7:0] r/w 00h* lin message data ?eld 7 15 to 8 df6[7:0] r/w 00h* lin message data ?eld 6 7 to 0 df5[7:0] r/w 00h* lin message data ?eld 5
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 148 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.14 receive buffer register (rbr) the receive buffer register is a 1-byte buffer and can be read via the bus interface. the received data is passed from the receive shift register to the receive buffer. the least signi?cant bit represents the oldest received data bit. if the character received is less than 8 bits, the unused most signi?cant bits are padded with logic 0. the rbr register is read only. t ab le 218 shows the bit assignment of the rbr register. 8.5.2.15 transmit holding register (thr) the transmit holding register is a 1-byte transmit buffer and can be written via the bus interface. the data is passed from the transmit holding register to the transmit shift register when the last one is idle. the least signi?cant bit represents the ?rst bit to transmit. the thr register is write only. t ab le 219 shows the bit assignment of the thr register. table 216. ldatc register bits legend: * reset value bit symbol access value description 31 to 24 df12[7:0] r/w 00h* lin message data ?eld 12 23 to 16 df11[7:0] r/w 00h* lin message data ?eld 11 15 to 8 df10[7:0] r/w 00h* lin message data ?eld 10 7 to 0 df9[7:0] r/w 00h* lin message data ?eld 9 table 217. ldatd register bits legend: * reset value bit symbol access value description 31 to 24 df16[7:0] r/w 00h* lin message data ?eld 16 23 to 16 df15[7:0] r/w 00h* lin message data ?eld 15 15 to 8 df14[7:0] r/w 00h* lin message data ?eld 14 7 to 0 df13[7:0] r/w 00h* lin message data ?eld 13 table 218. rbr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; read as logic 0 7 to 0 rbr[7:0] r - receive buffer register; contains the received byte table 219. thr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0 7 to 0 thr[7:0] w - transmit holding register; writing to the transmit holding register causes the data to be stored in the transmit buffer; the byte will be sent when the transmitter is available
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 149 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.16 interrupt enable register (ier) the interrupt enable register is used to enable the three types of interrupts referred to in the interrupt identi?cation register. t ab le 220 shows the bit assignment of the ier register. 8.5.2.17 interrupt id register (iir) the interrupt id register provides a status code that denotes the priority and source of a pending interrupt. when an interrupt is generated, the interrupt id register indicates that an interrupt is pending and encodes the type in its three bits. the interrupts are frozen during an access to the interrupt id register. if an interrupt occurs during an access, the interrupt is recorded for the next interrupt id register access. the iir register is read only. t ab le 221 shows the bit assignment of the iir register. table 220. ier register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; do not modify, read as logic 0, write as logic 0 2 lsie r/w receiver line status interrupt enable 1 the receive line status interrupt is enabled 0* 1 tbeie r/w transmit holding register empty interrupt enable 1 the transmit holding register empty interrupt is enabled 0* 0 rbie r/w receive buffer register interrupt register enable 1 the receive data available interrupt is enabled 0* table 221. iir register bit description legend: * reset value bit symbol access value description 31 to 3 reserved - - reserved; read as logic 0 2 to 0 int_id[2:0] r 1h* interrupt identi?cation; see t ab le 222 table 222: interrupt identi?cation control functions details int_id[2:0] priority level interrupt type source method 001 none none none none
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 150 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.18 line control register (lcr) the line control register controls the format of the asynchronous data communication exchange. t ab le 223 shows the bit assignment of the lcr register. 110 1 receiver line status overrun error, parity error, framing error, or break interrupt read the line status register lsr 100 2 received data available receiver data available read the receive buffer register rbr 010 3 transmitter holding register empty transmit holding register empty read the interrupt identi?cation register (if source of interrupt) or writing into the transmitter holding register thr table 222: interrupt identi?cation control functions details continued int_id[2:0] priority level interrupt type source method table 223. lcr register bit description legend: * reset value bit symbol access value description 31 to 7 reserved - - reserved; do not modify, read as logic 0, write as logic 0 6 bc r/w break control 1 a break transmission condition is forced which puts the txd output low 0* the break transmission condition is disabled; the break condition has no affect on the transmitter logic; it only affects the txd line 5 to 4 ps[5:4] r/w 0h* parity select; see t ab le 224 3 pen r/w parity enable 1 a parity bit is generated in transmitted data between the last data word bit and the ?rst stop bit; in received data the parity is checked 0* 2 stb r/w number of stop bits 1 the number of generated stop bits are 2; except the word length is 5 bits, then 1.5 stop bits are generated 0* 1 stop bit is generated 1 to 0 wls[1:0] r/w 0h* word length select; see t ab le 225 table 224: parity select con?guration bits ps[5:4] function 00 odd parity (an odd number of logic 1s in the data and parity bits) 01 even parity (an even number of logic 1s in the data and parity bits) 10 forced logic 1 stick parity 11 forced logic 0 stick parity
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 151 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.19 line status register (lsr) the line status register provides the information concerning the data transfers. the lsr register is read only. t ab le 226 shows the bit assignment of the lsr register. table 225: word length con?guration wls[1:0] function 00 5-bit character length 01 6-bit character length 10 7-bit character length 11 8-bit character length table 226. lsr register bit description legend: * reset value bit symbol access value description 31 to 7 reserved - - reserved; read as logic 0 6 temt r transmitter empty 1* the transmitter holding register and the transmitter shift register are both empty; the transmitter empty bit is cleared when either the transmitter holding register or the transmitter shift register contains a data character 0 5 thre r transmitter holding register empty 1* the transmitter holding register is empty; if the transmitter holding register empty interrupt enable is set, an interrupt is generated; the transmitter holding register empty bit is set when the contents of the transmitter holding register is transferred to the transmitter shift register; the transmitter holding register empty bit is cleared concurrently with loading the transmitter holding register 0 4 bi r break interrupt 1 the received data input was held low for longer than a full-word transmission time; a full-word transmission time is de?ned as the total time to transmit the start, data, parity, and stop bits; the break interrupt bit is cleared upon reading; the uart tries to resynchronize after a framing error; to accomplish this, it is assumed that the framing error is due to the next start bit; the uart samples this start bit twice and then accepts the input data 0* 3 fe r framing error 1 the received character did not have a valid (set) stop bit; the framing error is cleared upon reading; the next character transfer is enabled after the rxd input line goes to the marking state (1s) for at least two sample times and then receives the next valid start bit 0*
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 152 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.5.2.20 scratch register (scr) the scratch register is intended for the programmers use as scratch pad in the sense that it temporarily holds the programmers data without affecting any other uart operation. t ab le 227 shows the bit assignment of the scr register. 8.6 vectored interrupt controller 8.6.1 overview the sja 2020 contains a very ?exible and powerful vectored interrupt controller (vic) to interrupt the arm processor on request. the key features are: ? level active interrupt request with programmable polarity ? 31 interrupt requests inputs ? software interrupt request capability associated to each request input ? observability of interrupt request state before masking ? software programmable priority assignments to interrupt request up to 15 levels ? software programmable routing of interrupt requests towards the arm processor inputs irq and fiq 2 pe r parity error 1 the parity of the received data character does not match the parity selected in the line control register; the parity error is cleared upon reading 0* 1 oe r overrun error 1 the character in the receiver buffer register was overwritten by the next character transferred into this register before it was read; the overrun error is cleared upon reading 0* 0 dr r data ready 1 a complete incoming character has been received and transferred to the receiver buffer register; the data ready bit is cleared by reading the data in the receiver buffer register 0* table 226. lsr register bit description continued legend: * reset value bit symbol access value description table 227. scr register bit description legend: * reset value bit symbol access value description 31 to 8 reserved - - reserved; do not modify, write as logic 0, read as logic 0 7 to 0 scr[7:0] r/w 00h* scratch register; this register can be written and/or read at the discretion of the user
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 153 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers ? fast identi?cation of interrupt request through vector ? support for nesting of interrupt service routines the vectored interrupt controller routes incoming interrupt requests to the arm processor. the interrupt target is con?gured for each interrupt request input of the interrupt controller. the targets are de?ned as follows: ? target 0 is arm processor irq (standard interrupt service) ? target 1 is arm processor fiq (fast interrupt service) interrupt request masking is performed individually per interrupt target by comparing the priority level assigned to a speci?c interrupt request with a target speci?c priority threshold. the priority levels are de?ned as follows: ? priority level 0 corresponds to masked; interrupt requests with priority 0 will never lead to an interrupt request ? priority 1 corresponds to the lowest priority ? priority 15 corresponds to the highest priority software interrupt support is provided and can be supplied for: ? test the rtos interrupt handling without using device speci?c interrupt service routines ? software emulation of an interrupt requesting device, including interrupts 8.6.2 vic pin description the vectored interrupt controller module in the SJA2020 has no external pins. 8.6.3 register mapping the vectored interrupt controller registers are shown in t ab le 228 . the vectored interrupt controller registers have an offset to the base address vic regbase which can be found in the memory map (see t ab le 7 ). table 228: vectored interrupt controller register summary address access reset value name description reference 000h r/w - int_priority mask_0 target 0 priority mask register see t ab le 229 004h r/w - int_priority mask_1 target 1 priority mask register see t ab le 229 100h r/w - int_vector_0 target 0 vector register see t ab le 230 104h r/w - int_vector_1 target 1 vector register see t ab le 230 200h r - int_ pending_1_31 interrupt pending status register see t ab le 231 300h r 1 0f1fh int_features interrupt controller features register see t ab le 232 404h r/w - int_request_1 interrupt request 1 control register see t ab le 234
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 154 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 408h r/w - int_request_2 interrupt request 2 control register see t ab le 234 40ch r/w - int_request_3 interrupt request 3 control register see t ab le 234 410h r/w - int_request_4 interrupt request 4 control register see t ab le 234 414h r/w - int_request_5 interrupt request 5 control register see t ab le 234 418h r/w - int_request_6 interrupt request 6 control register see t ab le 234 41ch r/w - int_request_7 interrupt request 7 control register see t ab le 234 420h r/w - int_request_8 interrupt request 8 control register see t ab le 234 424h r/w - int_request_9 interrupt request 9 control register see t ab le 234 428h r/w - int_request_10 interrupt request 10 control register see t ab le 234 42ch r/w - int_request_11 interrupt request 11 control register see t ab le 234 430h r/w - int_request_12 interrupt request 12 control register see t ab le 234 434h r/w - int_request_13 interrupt request 13 control register see t ab le 234 438h r/w - int_request_14 interrupt request 14 control register see t ab le 234 43ch r/w - int_request_15 interrupt request 15 control register see t ab le 234 440h r/w - int_request_16 interrupt request 16 control register see t ab le 234 444h r/w - int_request_17 interrupt request 17 control register see t ab le 234 448h r/w - int_request_18 interrupt request 18 control register see t ab le 234 44ch r/w - int_request_19 interrupt request 19 control register see t ab le 234 450h r/w - int_request_20 interrupt request 20 control register see t ab le 234 454h r/w - int_request_21 interrupt request 21 control register see t ab le 234 458h r/w - int_request_22 interrupt request 22 control register see t ab le 234 45ch r/w - int_request_23 interrupt request 23 control register see t ab le 234 460h r/w - int_request_24 interrupt request 24 control register see t ab le 234 table 228: vectored interrupt controller register summary continued address access reset value name description reference
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 155 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.6.4 interrupt priority mask register (int_prioritymask) the interrupt priority mask registers de?ne the thresholds for priority level masking. each interrupt target has its own priority limiter. the priority limiter can be used to de?ne the minimum priority level for nesting interrupts; typically, the priority limiter is set to the priority level of the interrupt service routine that is currently being executed. by doing this, only interrupt requests at a higher priority level will lead to a nested interrupt service. nesting can be disabled by setting the priority level to fh in the interrupt request register. t ab le 229 shows the bit assignment of the int_prioritymask_n registers. 8.6.5 interrupt vector register (int_vector) the interrupt vector registers identify, individually for each interrupt target, the highest priority enabled pending interrupt request that is present at the time when the register is being read. the software interrupt service routine must always read the vector register that corresponds to the interrupt target. the interrupt vector content can be used as vector into a memory based table like shown in figure 13 . this table has 32 entries. to be able to use the register content as a full 32-bit address pointer, the table must be aligned to a 256 byte address boundary (or 2 048 to be future proof). if only the index variable is used as offset into the table, then this address alignment is not required. each table entry has 64-bit width. it is recommended to pack per table entry: ? the start address of a peripheral speci?c interrupt service routine, plus 464h r/w - int_request_25 interrupt request 25 control register see t ab le 234 468h r/w - int_request_26 interrupt request 26 control register see t ab le 234 46ch r/w - int_request_27 interrupt request 27 control register see t ab le 234 470h r/w - int_request_28 interrupt request 28 control register see t ab le 234 474h r/w - int_request_29 interrupt request 29 control register see t ab le 234 478h r/w - int_request_30 interrupt request 30 control register see t ab le 234 47ch r/w - int_request_31 interrupt request 31 control register see t ab le 234 table 228: vectored interrupt controller register summary continued address access reset value name description reference table 229. int_prioritymask register bit description legend: * reset value bit symbol access value description 31 to 4 reserved - - reserved; do not modify, read as logic 0, write as logic 0 3 to 0 priority_limiter[3:0] r/w - priority limiter; this register determines a priority threshold that incoming interrupt requests must exceed to trigger interrupt requests towards the cpu and the event router
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 156 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers ? the associated priority limiter value (if nesting of interrupt service routine shall be performed) a vector with index 0 indicates that no interrupt with priority above the priority threshold is pending. the vector table should implement for this entry a no interrupt handler to treat this special case. t ab le 230 shows the bit assignment of the int_vector register. fig 13. memory based interrupt vector and priority table table 230. int_vector register bit description legend: * reset value bit symbol access value description 31 to 11 table_addr[20:0] r/w - table start address; indicates the lower address boundary of a 256 byte aligned vector table in memory; to be compatible with future extension an address boundary of 2048 byte is recommended 10 to 8 reserved - - reserved; read as logic 0 7 to 3 index[4:0] r - index; indicates the interrupt request line of the interrupt request to be served by the controller: index = 0 means no interrupt request to be served index = 1 means serve interrupt request at input 1 index = n means serve interrupt request at input n 2 to 0 null[2:0] r - always re?ecting logic 0s 001aaa172 priority limiter 2 vector 2 priority limiter 1 vector 1 vector 0 unused interrupt vector table in memory 010h 00ch 008h 004h table_addr + 000h index no interrupt handler entry point device specific interrupt service routine in memory interrupt service routine 1 entry point interrupt service routine 2 entry point pointer
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 157 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.6.6 interrupt pending register (int_pending_1_31) the interrupt pending register gathers the pending bits of all interrupt request registers. software can make use of the interrupt pending to gain a faster overview on pending interrupts than by reading the individual interrupt request registers. the int_pending_1_31 register is read only. t ab le 231 shows the bit assignment of the int_pending_1_31 register. 8.6.7 interrupt controller features register (int_features) the interrupt controller features register indicates the vectored interrupt controller con?guration of which an isr can make use of for implementing interrupt controller con?guration speci?c behavior. the int_features register is read only. t ab le 232 shows the bit assignment of the int_features register. 8.6.8 interrupt request register (int_request) the reference between the interrupt source and interrupt request line is re?ected in t ab le 233 . table 231. int_pending_1_31 register bit description legend: * reset value bit symbol access value description 31 to 1 pending r - pending interrupt request; the bit position re?ects the pending state of the corresponding interrupt request line 1 an interrupt request is pending 0 there is no interrupt request 0 reserved - - reserved; read as logic 0 table 232. int_features register bits legend: * reset value bit symbol access value description 31 to 16 reserved - - reserved; read as dont care 21 to 16 t r 01h* number of targets (minus one) 15 to 8 p r 0fh* number of priorities (minus one) 7 to 0 n r 1fh* number of interrupt requests table 233: interrupt source and request reference interrupt request interrupt source activation level description 1 timer 0 low capture or match interrupt from timer 0 2 timer 1 low capture or match interrupt from timer 1 3 timer 2 low capture or match interrupt from timer 2 4 timer 3 low capture or match interrupt from timer 3 5 uart high general interrupt from 16c550 uart 6 spi 0 high general interrupt from spi 0 7 spi 1 high general interrupt from spi 1
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 158 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] combined general interrupt of all can controllers and the can look-up table; the following interrupts are combined here: error warning interrupt (ewi), data overrun interrupt (doi), error passive interrupt (epi), arbitration lost interrupt (ali), bus error interrupt (bei) and look-up table error interrupt (calute); see section 8.5.1.7 and section 8.5.1.33 for details. [2] message received interrupt from can controller x; the receive interrupt (ri) and the id ready interrupt (idi) are combined here; see section 8.5.1.7 for details. the interrupt request registers hold the con?guration information related to interrupt request inputs of the interrupt controller and allow to issue software interrupt requests. each interrupt line has its own interrupt request register. t ab le 234 shows the bit assignment of the int_request register. 8 spi 2 high general interrupt from spi 2 9 event router high event, wake-up or real time clock tick interrupt from event router 10 adc high conversion scan completed interrupt from adc 11 ?ash high signature, burn or erase ?nished interrupt from ?ash 12 watchdog low debug under?ow interrupt from watchdog 13 embedded rt-ice high communications rx for arm debug mode 14 embedded rt-ice high communications tx for arm debug mode 15 lin master controller 0 high general interrupt from lin master controller 0 16 lin master controller 1 high general interrupt from lin master controller 1 17 lin master controller 2 high general interrupt from lin master controller 2 18 lin master controller 3 high general interrupt from lin master controller 3 19 all can controllers high combined general interrupt of all can controllers and the can look-up table [1] 20 can controller 0 high message received interrupt from can controller 0 [2] 21 can controller 1 high message received interrupt from can controller 1 [2] 22 can controller 2 high message received interrupt from can controller 2 [2] 23 can controller 3 high message received interrupt from can controller 3 [2] 24 can controller 4 high message received interrupt from can controller 4 [2] 25 can controller 5 high message received interrupt from can controller 5 [2] 26 can controller 0 high message transmitted interrupt from can controller 0 27 can controller 1 high message transmitted interrupt from can controller 1 28 can controller 2 high message transmitted interrupt from can controller 2 29 can controller 3 high message transmitted interrupt from can controller 3 30 can controller 4 high message transmitted interrupt from can controller 4 31 can controller 5 high message transmitted interrupt from can controller 5 table 233: interrupt source and request reference continued interrupt request interrupt source activation level description
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 159 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers table 234. int_request register bit description legend: * reset value bit symbol access value description 31 pending r/w pending interrupt request; re?ects the state of the interrupt source channel; the pending status is also visible in the interrupt pending register. writing this bit has no effect. 1 an interrupt request is pending 0 there is no interrupt request 30 set_swint r/w set software interrupt request 1 writing logic 1 sets the local software interrupt request state 0 writing a logic 0 has no effect on the local software interrupt request state; this bit is always read as logic 0 29 clr_swint r/w clear software interrupt request 1 writing logic 1 clears the local software interrupt request state 0 writing a logic 0 has no effect on the local software interrupt request state; this bit is always read as logic 0 28 we_priority_level r/w write enable priority level 1 writing logic 1 enables the bit state change during the same register access 0 writing logic 0 does not change the bit state; this bit is always read as logic 0 27 we_target r/w write enable target 1 writing logic 1 enables the bit state change during the same register access; for changing the bit state, software must ?rst disable the interrupt request (bit enable = 0), then change this bit and ?nally re-enable the interrupt request (bit enable = 1) again 0 writing logic 0 does not change this bit state; this bit is always read as logic 0 26 we_enable r/w write enable 1 writing logic 1 enables this bit state change during the same register access 0 writing logic 0 does not change this bit state; this bit is always read as logic 0 25 we_active_low r/w write enable active low 1 writing logic 1 enables the bit state change during the same register access 0 writing logic 0 does not change the bit state; this bit is always read as logic 0 24 to 18 reserved - reserved; do not modify, write as logic 0, read as logic 0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 160 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 9. limiting values 17 active_low r/w active low interrupt line; selects the polarity of the interrupt request line; state changing is only possible if the corresponding write enable bit has been set 1 the interrupt request is active low 0* the interrupt request is active high 16 enable r/w enable interrupt request; controls the interrupt request processing by the interrupt controller; state changing is only possible if the corresponding write enable bit has been set 1 the interrupt request may cause an arm processor interrupt request if further conditions for this become true 0* the interrupt request is discarded and will not cause an arm processor interrupt 15 to 9 reserved - - reserved; do not modify, write as logic 0, read as logic 0 8 target r/w interrupt target; de?nes the interrupt target of an interrupt request; state changing is only possible if the corresponding write enable bit has been set 1 the target is the fiq 0* the target is the irq 7 to 4 reserved - - reserved; do not modify, write as logic 0, read as logic 0 3 to 0 priority_level[3:0] r/w - interrupt priority level; determines the priority level of the interrupt request; state changing is only possible if the corresponding write enable bit has been set 1 priority level 0 masks the interrupt request, thus it is ignored 0 priority level 1 has the lowest priority level and 15 the highest table 234. int_request register bit description continued legend: * reset value bit symbol access value description table 235: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit supply pins p tot total power dissipation [1] -1w v dd(core) core supply voltage - 0.5 +2.0 v v dd(osc_pll) oscillator and pll supply voltage - 0.5 +2.0 v v dd(rtc) rtc supply voltage - 0.5 +2.0 v
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 161 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] based on package heat transfer, not device power consumption. [2] peak current must be limited at 25 times average current. [3] v dd(io) must be present. v dd(adc) adc supply voltage - 0.5 +3.6 v v dd(io) i/o supply voltage - 0.5 +4.6 v i dd supply current average value per supply pin [2] -98ma i ss ground current average value per ground pin [2] -98ma input pins and i/o pins v xin_osc voltage on pin xin_osc - 0.5 +2.0 v v xin_rtc voltage on pin xin_rtc - 0.5 +2.0 v v i(io) i/o input voltage dc input voltage on 5 v tolerant port pins [3] [4] [5] - 0.5 v dd(io) + 3.0 v dc input voltage on all other i/o and input pins - 0.5 v dd(io) + 0.5 v v i(adc) adc input voltage - 0.5 +3.6 v v vrefn voltage on pin vrefn - 0.5 +3.6 v i i(adc) adc input current average value per input pin [2] -35ma output pins and i/o pins con?gured as output i ohs high-state short-circuit output current drive high, output shorted to v ss(io) [6] -33ma i ols low-state short-circuit output current drive low, output shorted to v dd(io) [6] - - 38 ma general t stg storage temperature - 40 +150 c t amb ambient temperature - 40 +105 c t vj virtual junction temperature [7] - 40 +125 c memory n endu(?) endurance of ?ash memory - 1000 cycle t ret(?) ?ash memory retention time - 20 year esd v esd electrostatic discharge voltage on all pins hbm [8] - 2000 +2000 v mm [9] - 200 +200 v cdm [10] [11] - 500 +500 v on corner pins cdm [10] - 750 +750 v table 235: limiting values continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 162 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [4] not 5 v tolerant when pull-up is on. [5] 6 v should not be exceeded. [6] 112 ma per v dd(io) or v ss(io) should not be exceeded. [7] in accordance with iec 60747-1. an alternative de?nition of the virtual junction temperature is: t vj =t amb +p tot r th(j-a) where r th(j-a) is a ?xed value (see section 10 ). the rating for t vj limits the allowable combinations of power dissipation and ambient temperature. [8] human body model: according aec-q100 rev-f, h2. [9] machine model: according aec-q100 rev-f, m3. [10] charged device model: according aec-q100 rev-f, c3b. [11] except for the v dd(osc_pll) pin, which is guaranteed up to 375 v. 10. thermal characteristics 11. static characteristics table 236: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 62 k/w table 237: static characteristics v dd(core) =v dd(osc_pll) =v dd(rtc) = 1.8 v 5 %; v dd(io) = 2.7 v to 3.6 v; v dd(adc) = 3.0 v to 3.6 v; t vj = - 40 c to +125 c; all voltages are measured with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed [1] . symbol parameter conditions min typ max unit supplies core supply v dd(core) core supply voltage 1.71 1.80 1.89 v i dd(core) core supply current arm7 and all peripherals active - 1.1 2.0 ma/mhz all clocks off [2] - 10 300 m a i/o supply v dd(io) i/o supply voltage 2.7 - 3.6 v oscillator v dd(osc_pll) oscillator and pll supply voltage 1.71 1.80 1.89 v i dd(osc_pll) oscillator and pll supply current start-up 1.5 - 3 ma normal - - 1 ma power-down - - 1 m a real time clock v dd(rtc) rtc supply voltage 1.71 1.80 1.89 v i dd(rtc) rtc supply current normal - - 6 m a power-down - - 1 m a analog-to-digital converter v dd(adc) adc supply voltage 3.0 3.3 3.6 v
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 163 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers i dd(adc) adc supply current normal - - 400 m a power-down - - 1 m a input pins and i/o pins con?gured as input v i input voltage all port pins and v dd(io) applied [3] - 0.5 - +5.5 v all port pins and v dd(io) not applied - 0.5 - +3.6 v all other i/o pins, reset_n, trst_n, tdi, jtagsel, tms, tck - 0.5 - v dd(io) v v ih high-state input voltage all port pins, reset_n, trst_n, tdi, jtagsel, tms, tck 2.0 - - v v il low-state input voltage all port pins, reset_n, trst_n, tdi, jtagsel, tms, tck - - 0.8 v v hys hysteresis voltage 0.4 - - v i lih high-state input leakage current --1 m a i lil low-state input leakage current --1 m a i i(pd) pull-down input current all port pins, v i = 3.3 v; v i = 5.5 v 25 50 100 m a i i(pu) pull-up input current all port pins, reset_n, trst_n, tdi, jtagsel, tms: v i = 0 v; v i > 3.6 v is not allowed - 25 - 50 - 100 m a c i input capacitance - - 8 pf output pins and i/o pins con?gured as output v o output voltage 0 - v dd(io) v v oh high-state output voltage tdo: i oh = - 8 ma; all other pins: i oh = - 4ma v dd(io) C 0.4 - - v v ol low-state output voltage tdo: i ol = 8 ma; all other pins: i ol =4ma - - 0.4 v analog-to-digital converter v vrefn voltage on pin vrefn 0 - v dd(adc) - 2 v v i input voltage at pins ai0, ai1, ai2, ai3 v vrefn -v dd(adc) v z i input impedance between v vrefn and v dd(adc) -30-k w c i input capacitance at pins ai0, ai1, ai2, ai3 - - 1 pf fsr full scale range 2 - 10 bit inl integral non-linearity [4] - 1 - +1 lsb table 237: static characteristics continued v dd(core) =v dd(osc_pll) =v dd(rtc) = 1.8 v 5 %; v dd(io) = 2.7 v to 3.6 v; v dd(adc) = 3.0 v to 3.6 v; t vj = - 40 c to +125 c; all voltages are measured with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed [1] . symbol parameter conditions min typ max unit
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 164 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] all parameters are guaranteed over the virtual junction temperature range by design. production testing is performed at t amb = 125 c on wafer level. cased products are tested at t amb =25 c. production testing uses correlated test conditions to cover the speci?ed temperature and power supply voltage range. [2] leakage current is exponential to temperature; worst case value is at t vj = 125 c. [3] not 5 v tolerant when pull-up is on. [4] inl and dnl are indirectly measured during production test by measuring the dynamic noise reduction (dnr) and effective numbers of bits (enb). [5] c xtal is crystal load capacitance and c l(ext) are the two external load capacitors. [6] the power-up reset has a time ?lter: v dd(core) must be above v trip(high) for 2 m s before the internal reset is de-asserted; v dd(core) must be below v trip(low) for 11 m s before internal reset is asserted. dnl differential non-linearity [4] - 1 - +1 lsb v err(offset) offset error voltage - 20 - +20 mv v err(fs) full-scale error voltage - 20 - +20 mv oscillator r s(xtal) crystal series resistance f osc = 10 mhz to 15 mhz [5] c xtal =10pf; c l(ext) =18pf - - 160 w c xtal =20pf; c l(ext) =39pf --60 w f osc = 15 mhz to 20 mhz [5] c xtal =10pf; c l(ext) =18pf --80 w real time clock r s(xtal) crystal series resistance c xtal = 11 pf; c l(ext) =18pf [5] - - 100 w c xtal = 13 pf; c l(ext) =22pf [5] - - 100 w c xtal = 15 pf; c l(ext) =27pf [5] - - 100 w power-up reset v trip(high) high trip level voltage on v dd(core) [6] 1.2 1.4 1.6 v v trip(low) low trip level voltage on v dd(core) [6] 1.1 1.3 1.5 v v trip(dif) difference between high and low trip level voltage [6] 50 120 180 mv table 237: static characteristics continued v dd(core) =v dd(osc_pll) =v dd(rtc) = 1.8 v 5 %; v dd(io) = 2.7 v to 3.6 v; v dd(adc) = 3.0 v to 3.6 v; t vj = - 40 c to +125 c; all voltages are measured with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed [1] . symbol parameter conditions min typ max unit
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 165 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 12. dynamic characteristics table 238: dynamic characteristics v dd(core) =v dd(osc_pll) =v dd(rtc) = 1.8 v 5 %; v dd(io) = 2.7 v to 3.6 v; v dd(adc) = 3.0 v to 3.6 v; t vj = - 40 c to +125 c; all voltages are de?ned with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed [1] . symbol parameter conditions min typ max unit i/o pins t thl high-to-low transition time 30 pf load capacitance 4 - 13.8 ns t tlh low-to-high transition time 30 pf load capacitance 4 - 13.8 ns internal clock f clk(sys) system clock frequency 10 - 60 mhz t clk(sys) system clock period 16 - 100 ns ring oscillator f ref(ro) ro reference frequency before ringo calibration (crfs) and post (crpd) dividers 1.0 - 1.80 mhz t startup start-up time at maximum frequency [2] - 6 100 m s t jit(cc)(p-p) cycle-to-cycle jitter (peak-to-peak value) [2] --1ns oscillator f i(osc) oscillator input frequency 10 - 20 mhz t startup start-up time [3] - 500 - m s t jit(cc)(p-p) cycle-to-cycle jitter (peak-to-peak value) [2] - - 240 ps pll f o(pll) pll output frequency 10 - 60 mhz f cco cco frequency 156 - 320 mhz t startup start-up time [2] - - 100 m s t jit(cc)(p-p) cycle-to-cycle jitter (peak-to-peak value) [2] - - 300 ps real time clock f i(rtc) rtc input frequency - 32.768 - khz t startup start-up time [2] --1s t jit(cc)(p-p) cycle-to-cycle jitter (peak-to-peak value) [2] - - 20 ns analog-to-digital converter f i(adc) adc input frequency - - 4.5 mhz
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 166 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [1] all parameters are guaranteed over the virtual junction temperature range by design. pre-testing is performed at t amb = 125 c on wafer level. cased products are tested at t amb =25 c. production testing uses correlated test conditions to cover the speci?ed temperature and power supply voltage range. [2] this parameter is not part of production test; worst case ?gure stated is based on simulations. [3] oscillator start-up time depends on the quality of the crystal. for most crystals it takes about 1000 clock pulses until the clock is fully stable. [4] maximum deviation should be within 5%. f s sampling frequency f i(adc) = 4.5 mhz; f s =f i(adc) / (n+1) with n = resolution in kilo samples per second 400 - 1500 ksample/s in bits 10 - 2 bit t conv conversion time in number of adc clock cycles 3 - 11 cycle in number of bits 2 - 10 bit flash t init initialization time - - 150 m s t a(clk) clock access time - - 67.5 ns t a(a) address access time - - 49 ns t wr(pg) page write time [4] -1-ms t er(sect) sector erase time [4] - 100 - ms t ?(bist) ?ash word bist time [2] -4270ns static memory controller t a(r)int internal read access time [2] - - 18 ns t a(w)int internal write access time [2] - - 19 ns uart f uart uart frequency 1/65024f clk(sys) - 1/2f clk(sys) mhz spi f spi spi operating frequency master operation 1/65024f clk(sys) - 1/2f clk(sys) mhz slave operation 1/65024f clk(sys) - 1/12f clk(sys) mhz table 238: dynamic characteristics continued v dd(core) =v dd(osc_pll) =v dd(rtc) = 1.8 v 5 %; v dd(io) = 2.7 v to 3.6 v; v dd(adc) = 3.0 v to 3.6 v; t vj = - 40 c to +125 c; all voltages are de?ned with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed [1] . symbol parameter conditions min typ max unit
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 167 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 13. package outline fig 14. package outline sot486-1 (lqfp144) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.08 0.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 168 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 14.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 169 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 239. suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 170 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 15. references [1] um SJA2020 user manual, um10141_1 [2] anki SJA2020 application note known issues, an10383_1 [3] arm arm web site [4] arm-ssp arm primecell synchronous serial port (pl022) technical reference manual [5] can iso 11898-1: 2002 road vehicles - controller area network (can) - part 1: data link layer and physical signalling [6] lin lin speci?cation package, revision 2.0
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 171 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 16. revision history table 240. revision history document id release date data sheet status change notice supersedes SJA2020_1 (9397 750 12148) 20060405 objective data sheet - -
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 172 of 176 philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .semiconductors .philips .com. 17.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. philips semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local philips semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general information in this document is believed to be accurate and reliable. however, philips semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes philips semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use philips semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a philips semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. philips semiconductors accepts no liability for inclusion and/or use of philips semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale philips semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .semiconductors .philips .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by philips semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 173 of 176 continued >> philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 19. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 about this document . . . . . . . . . . . . . . . . . . . . . 1 1.2 intended audience . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 2.1 architectural overview. . . . . . . . . . . . . . . . . . . . 1 2.2 arm7tdmi-s processor. . . . . . . . . . . . . . . . . . 1 2.3 on-chip ?ash memory system . . . . . . . . . . . . . 2 2.4 on-chip static ram. . . . . . . . . . . . . . . . . . . . . . 2 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.2 flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3 can gateway . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.4 lin master controller . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 reset and power-up behavior. . . . . . . . . . . . . . 9 7.2 jtag interface and debug pins . . . . . . . . . . . . . 9 7.3 power supply pins description . . . . . . . . . . . . . 9 7.4 clock architecture . . . . . . . . . . . . . . . . . . . . . . 10 7.5 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5.1 region 0: remap area . . . . . . . . . . . . . . . . . . . 12 7.5.2 region 1: embedded ?ash area . . . . . . . . . . . 12 7.5.3 region 2: not used . . . . . . . . . . . . . . . . . . . . . 13 7.5.4 region 3: internal sram area . . . . . . . . . . . . 13 7.5.5 region 4: not used . . . . . . . . . . . . . . . . . . . . . 15 7.5.6 region 5: static memory controller area. . . . . 15 7.5.7 region 6: not used . . . . . . . . . . . . . . . . . . . . . 16 7.5.8 region 7: bus peripherals area. . . . . . . . . . . . 16 7.5.9 memory map concepts operation . . . . . . . . . . 17 8 block description. . . . . . . . . . . . . . . . . . . . . . . 19 8.1 flash memory controller . . . . . . . . . . . . . . . . . 19 8.1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1.2 flash memory controller pin description. . . . . 21 8.1.3 flash memory layout . . . . . . . . . . . . . . . . . . . 21 8.1.4 register mapping . . . . . . . . . . . . . . . . . . . . . . 23 8.1.5 flash control register (fctr) . . . . . . . . . . . . . 24 8.1.6 flash program time register (fptr) . . . . . . . . 25 8.1.7 flash bridge wait states register (fbwst) . . . 26 8.1.8 flash clock divider register (fcra) . . . . . . . . 27 8.1.9 flash bist control registers (fmsstart and fmsstop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.10 flash bist signature registers (fmsw0, fmsw1, fmsw2 and fmsw3) . . . . . . . . . . . . . . . . . . 28 8.1.11 flash interrupt status register (int_status) 28 8.1.12 flash set interrupt status (int_set_status) 29 8.1.13 flash clear interrupt status (int_clr_status) . . . . . . . . . . . . . . . . . . . 29 8.1.14 flash interrupt enable (int_enable) . . . . . . 30 8.1.15 flash set interrupt enable (int_set_enable) . . . . . . . . . . . . . . . . . . . 30 8.1.16 flash clear interrupt enable (int_clr_enable) . . . . . . . . . . . . . . . . . . . 31 8.2 static memory controller . . . . . . . . . . . . . . . . 31 8.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2.2 external memory controller pin description . . 32 8.2.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 32 8.2.4 bank idle cycle control registers (smbidcyr) 34 8.2.5 bank wait state 1 control registers (smbwst1r) . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2.6 bank wait state 2 control registers (smbwst2r) . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.7 bank output enable assertion delay control register (smbwstoenr) . . . . . . . . . . . . . . . 35 8.2.8 bank write enable assertion delay control register (smbwstwenr) . . . . . . . . . . . . . . . . . . . . . 36 8.2.9 bank con?guration register (smbcr) . . . . . . 36 8.2.10 bank status register (smbsr) . . . . . . . . . . . . 37 8.3 general subsystem . . . . . . . . . . . . . . . . . . . . 38 8.3.1 clock generation unit . . . . . . . . . . . . . . . . . . . 38 8.3.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3.1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3.1.3 cgu pin description . . . . . . . . . . . . . . . . . . . . 38 8.3.1.4 register mapping . . . . . . . . . . . . . . . . . . . . . . 39 8.3.1.5 clock switch con?guration register (csc) . . . 40 8.3.1.6 clock frequency select registers (cfs1 and cfs2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3.1.7 clock switch status register (css) . . . . . . . . . 41 8.3.1.8 clock power control registers (cpc0, cpc1, cpc2, cpc3 and cpc4) . . . . . . . . . . . . . . . . 42 8.3.1.9 clock power status registers (cps0, cps1, cps2, cps3 and cps4) . . . . . . . . . . . . . . . . 42 8.3.1.10 fractional clock enable register (cfce4). . . . 43 8.3.1.11 fractional clock divider register (cfd) . . . . . . 43 8.3.1.12 power mode register (cpm) . . . . . . . . . . . . . . 44 8.3.1.13 watchdog bark register (cwdb) . . . . . . . . . . 45 8.3.1.14 real time clock oscillator power mode register (crtcopm). . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.1.15 oscillator power mode register (copm) . . . . 45 8.3.1.16 oscillator lock status register (cols) . . . . . . 46
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 174 of 176 continued >> philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.3.1.17 pll clock source select register (cpcss) . . . 46 8.3.1.18 pll power-down mode register (cppdm) . . . 46 8.3.1.19 pll lock status register (cpls) . . . . . . . . . . . 47 8.3.1.20 pll multiplication ratio register (cpmr). . . . . 47 8.3.1.21 pll post divider register (cppd) . . . . . . . . . . 48 8.3.1.22 ring oscillator power mode register (crpm) . 48 8.3.1.23 ring oscillator post divider register (crpd) . . 49 8.3.1.24 ring oscillator frequency select register (crfs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3.2 system control unit . . . . . . . . . . . . . . . . . . . . . 50 8.3.2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3.2.2 scu pin description . . . . . . . . . . . . . . . . . . . . 50 8.3.2.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 50 8.3.2.4 shadow memory mapping register (ssmm). . 51 8.3.2.5 port function select registers (sfsap0 to sfsap2 and sfsbp0 to sfsbp2) . . . . . . . . 51 8.3.2.6 pull-up control registers (spucp0, spucp1 and spucp2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.3.2 spi pin description . . . . . . . . . . . . . . . . . . . . . 56 8.3.3.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 56 8.3.3.4 spi control register 0 (sspcr0) . . . . . . . . . . 57 8.3.3.5 spi control register 1 (sspcr1) . . . . . . . . . . 58 8.3.3.6 spi fifo data register (sspdr) . . . . . . . . . . 59 8.3.3.7 spi status register (sspsr). . . . . . . . . . . . . . 60 8.3.3.8 spi clock prescale register (sspcpsr). . . . . 60 8.3.3.9 spi interrupt enable register (sspimsc) . . . . 61 8.3.3.10 spi raw interrupt status register (sspris). . . 61 8.3.3.11 spi masked interrupt status register (sspmis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.3.12 spi interrupt clear register (sspicr) . . . . . . . 63 8.3.4 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3.4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3.4.2 watchdog pin description . . . . . . . . . . . . . . . . 64 8.3.4.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 64 8.3.4.4 watchdog mode register (wdmod) . . . . . . . . 64 8.3.4.5 watchdog reload value register (wdrv) . . . . 65 8.3.4.6 watchdog counter value register (wdcv) . . . 65 8.3.4.7 watchdog trigger register (wdtrig) . . . . . . . 66 8.3.4.8 watchdog interrupt set status (wdiss) . . . . . 66 8.3.4.9 watchdog interrupt clear status (wdics). . . . 66 8.3.4.10 watchdog interrupt enable (wdie) . . . . . . . . . 67 8.3.4.11 watchdog interrupt status register (wdis) . . . 67 8.3.4.12 watchdog interrupt set enable (wdise). . . . . 67 8.3.4.13 watchdog interrupt clear enable (wdice) . . . 68 8.3.5 analog-to-digital converter . . . . . . . . . . . . . . . 68 8.3.5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.3.5.2 adc pin description . . . . . . . . . . . . . . . . . . . . 68 8.3.5.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 69 8.3.5.4 adc channel conversion data registers (acd0 to acd7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.3.5.5 adc control register (acon) . . . . . . . . . . . . . 70 8.3.5.6 adc channel con?guration register (acc). . . 71 8.3.5.7 adc interrupt enable register (aie) . . . . . . . . 72 8.3.5.8 adc interrupt status register (ais). . . . . . . . . 72 8.3.5.9 adc interrupt clear register (aic) . . . . . . . . . 72 8.3.6 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.6.2 event router pin description and mapping to register bit positions . . . . . . . . . . . . . . . . . . . . 73 8.3.6.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 74 8.3.6.4 event status register (pend) . . . . . . . . . . . . . 74 8.3.6.5 event status clear register (int_clr) . . . . . . 75 8.3.6.6 event status set register (int_set). . . . . . . . 75 8.3.6.7 event enable register (mask) . . . . . . . . . . . . 75 8.3.6.8 event enable clear register (mask_clr) . . . 76 8.3.6.9 event enable set register (mask_set) . . . . . 76 8.3.6.10 activation polarity register (apr) . . . . . . . . . . 76 8.3.6.11 activation type register (atr). . . . . . . . . . . . . 77 8.3.6.12 raw status register (rsr) . . . . . . . . . . . . . . . 77 8.3.7 real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.7.2 rtc pin description . . . . . . . . . . . . . . . . . . . . 78 8.3.7.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 78 8.3.7.4 rtc elapsed time seconds register (rtc_time_seconds) . . . . . . . . . . . . . . . . 78 8.3.7.5 rtc seconds fraction register (rtc_time_fraction). . . . . . . . . . . . . . . . 79 8.3.7.6 rtc real time offset register (rtc_portime) . . . . . . . . . . . . . . . . . . . . . . 79 8.3.7.7 rtc real time control register (rtc_control) . . . . . . . . . . . . . . . . . . . . . 79 8.4 peripheral subsystem. . . . . . . . . . . . . . . . . . . 80 8.4.1 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.1.2 timer pin description . . . . . . . . . . . . . . . . . . . 80 8.4.1.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 81 8.4.1.4 timer interrupt register (ir) . . . . . . . . . . . . . . 81 8.4.1.5 timer control register (tcr) . . . . . . . . . . . . . 82 8.4.1.6 timer counter (tc). . . . . . . . . . . . . . . . . . . . . 82 8.4.1.7 prescale register (pr) . . . . . . . . . . . . . . . . . . 83 8.4.1.8 prescale counter (pc) . . . . . . . . . . . . . . . . . . 83 8.4.1.9 match control register (mcr) . . . . . . . . . . . . . 83 8.4.1.10 match registers (mr0 to mr3) . . . . . . . . . . . . 85 8.4.1.11 capture control register (ccr) . . . . . . . . . . . 85 8.4.1.12 capture registers (cr0 to cr3). . . . . . . . . . . 87 8.4.1.13 external match register (emr). . . . . . . . . . . . 87 8.4.2 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4.2.2 uart pin description . . . . . . . . . . . . . . . . . . . 88
SJA2020_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. objective data sheet rev. 01 5 april 2006 175 of 176 continued >> philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers 8.4.2.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 89 8.4.2.4 receive buffer register (rbr). . . . . . . . . . . . . 89 8.4.2.5 transmit holding register (thr) . . . . . . . . . . . 90 8.4.2.6 interrupt enable register (ier) . . . . . . . . . . . . 90 8.4.2.7 interrupt id register (iir). . . . . . . . . . . . . . . . . 90 8.4.2.8 fifo control register (fcr) . . . . . . . . . . . . . . 91 8.4.2.9 line control register (lcr) . . . . . . . . . . . . . . . 92 8.4.2.10 line status register (lsr) . . . . . . . . . . . . . . . . 93 8.4.2.11 scratch register (scr) . . . . . . . . . . . . . . . . . . 95 8.4.2.12 divisor latch lsb and divisor latch msb registers (dll and dlm) . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3 general purpose i/o . . . . . . . . . . . . . . . . . . . . 96 8.4.3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3.2 gpio pin description . . . . . . . . . . . . . . . . . . . 97 8.4.3.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 97 8.4.3.4 port input register (pins) . . . . . . . . . . . . . . . . 97 8.4.3.5 port output register (or) . . . . . . . . . . . . . . . . 97 8.4.3.6 port direction register (dr) . . . . . . . . . . . . . . . 98 8.5 in-vehicle networking subsystem . . . . . . . . . . 98 8.5.1 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1.2 can pin description . . . . . . . . . . . . . . . . . . . . 98 8.5.1.3 register mapping . . . . . . . . . . . . . . . . . . . . . . 99 8.5.1.4 can controller mode register (ccmode) . . 101 8.5.1.5 can controller command register (cccmd) 102 8.5.1.6 can controller global status register (ccgs) 104 8.5.1.7 can controller interrupt and capture register (ccic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.5.1.8 can controller interrupt enable register (ccie). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.1.9 can controller bus timing register (ccbt). . 111 8.5.1.10 can controller error warning limit register (ccewl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.5.1.11 can controller status register (ccstat) . . . 112 8.5.1.12 can controller receive buffer message info register (ccrxbmi) . . . . . . . . . . . . . . . . . . . 116 8.5.1.13 can controller receive buffer identi?er register (ccrxbid) . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1.14 can controller receive buffer data a register (ccrxbda) . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1.15 can controller receive buffer data b register (ccrxbdb) . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.5.1.16 can controller transmit buffer message info register (cctxb1mi, cctxb2mi and cctxb3mi) . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.5.1.17 can controller transmit buffer identi?er register (cctxb1id, cctxb2id and cctxb3id) . . 119 8.5.1.18 can controller transmit buffer data a register (cctxb1da, cctxb2da and cctxb3da) 120 8.5.1.19 can controller transmit buffer data b register (cctxb1db, cctxb2db and cctxb3db) 120 8.5.1.20 global acceptance ?lter . . . . . . . . . . . . . . . . 121 8.5.1.21 standard frame format fullcan identi?er section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.5.1.22 standard frame format explicit identi?er section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.5.1.23 standard frame format group identi?er section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5.1.24 extended frame format explicit identi?er section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.5.1.25 extended frame format group identi?er section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.5.1.26 can acceptance ?lter mode register (camode) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.5.1.27 can acceptance ?lter standard frame explicit start address register (casfesa) . . . . . . . . . . . . 127 8.5.1.28 can acceptance ?lter standard frame group start address register (casfgsa). . . . . . . . . . . . 127 8.5.1.29 can acceptance ?lter extended frame explicit start address register (caefesa) . . . . . . . . 128 8.5.1.30 can acceptance ?lter extended frame group start address register (caefgsa). . . . . . . . . . . . 128 8.5.1.31 can acceptance ?lter end of look up table address register (caeota) . . . . . . . . . . . . . 129 8.5.1.32 can acceptance ?lter look-up table error address register (calutea) . . . . . . . . . . . . . . . . . . . 130 8.5.1.33 can acceptance ?lter look-up table error register (calute). . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.1.34 can controllers central transmit status register (cccts) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.1.35 can controllers central receive status register (cccrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.5.1.36 can controllers central miscellaneous status register (cccms). . . . . . . . . . . . . . . . . . . . . 134 8.5.2 lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.5.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.5.2.2 lin pin description . . . . . . . . . . . . . . . . . . . . 136 8.5.2.3 register mapping . . . . . . . . . . . . . . . . . . . . . 136 8.5.2.4 lin master controller mode register (lmode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.5.2.5 lin master controller con?guration register (lcfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.5.2.6 lin master controller command register (lcmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.5.2.7 lin master controller fractional baud rate generator register (lfbrg) . . . . . . . . . . . . . 140 8.5.2.8 lin master controller status register (lstat) 140 8.5.2.9 lin master controller interrupt and capture register (lic) . . . . . . . . . . . . . . . . . . . . . . . . 142 8.5.2.10 lin master controller interrupt enable register (lie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
philips semiconductors SJA2020 arm7 microcontroller with can and lin controllers ? koninklijke philips electronics n.v. 2006. all rights reserved. for more information, please visit: http://www.semiconductors.philips.com. for sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. date of release: 5 april 2006 document identifier: SJA2020_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 8.5.2.11 lin master controller checksum register (lcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.5.2.12 lin master controller time-out register (lto) 145 8.5.2.13 lin master controller message buffer registers (lid, ldata, ldatb, ldatc and ldatd) . . 146 8.5.2.14 receive buffer register (rbr). . . . . . . . . . . . 148 8.5.2.15 transmit holding register (thr) . . . . . . . . . . 148 8.5.2.16 interrupt enable register (ier) . . . . . . . . . . . 149 8.5.2.17 interrupt id register (iir). . . . . . . . . . . . . . . . 149 8.5.2.18 line control register (lcr) . . . . . . . . . . . . . . 150 8.5.2.19 line status register (lsr) . . . . . . . . . . . . . . . 151 8.5.2.20 scratch register (scr) . . . . . . . . . . . . . . . . . 152 8.6 vectored interrupt controller . . . . . . . . . . . . . 152 8.6.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 8.6.2 vic pin description . . . . . . . . . . . . . . . . . . . . 153 8.6.3 register mapping . . . . . . . . . . . . . . . . . . . . . 153 8.6.4 interrupt priority mask register (int_prioritymask) . . . . . . . . . . . . . . . . 155 8.6.5 interrupt vector register (int_vector). . . . 155 8.6.6 interrupt pending register (int_pending_1_31) . . . . . . . . . . . . . . . . . 157 8.6.7 interrupt controller features register (int_features). . . . . . . . . . . . . . . . . . . . . 157 8.6.8 interrupt request register (int_request) . 157 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . 160 10 thermal characteristics. . . . . . . . . . . . . . . . . 162 11 static characteristics. . . . . . . . . . . . . . . . . . . 162 12 dynamic characteristics . . . . . . . . . . . . . . . . 165 13 package outline . . . . . . . . . . . . . . . . . . . . . . . 167 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . 168 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 168 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . 169 14.5 package related soldering information . . . . . 169 15 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 171 17 legal information. . . . . . . . . . . . . . . . . . . . . . 172 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 172 17.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 172 18 contact information. . . . . . . . . . . . . . . . . . . . 172 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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