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generalplus technology inc. reserves the right to c hange this documentation without prior notice. inf ormation provided by generalplus technology inc. is believed to be accurate and reli able. however, generalplus technology inc. makes n o warranty for any errors which may appear in this document. contact generalplus techn ology inc. to obtain the latest version of device s pecifications before placing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other right s of third parties which may result from its use. in addition, generalplus products are not authorize d for use as critical components in life support de vices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonabl y be expected to result in significant injury to th e user, without the express written approval of gen eralplus. p p r r e e l l i i m m i i n n a a r r y y oct. 29, 2010 version 0.1 g g p p m m 6 6 p p 1 1 0 0 0 0 9 9 a a 1 1 6 6 - - p p i i n n r r e e m m o o t t e e c c o o n n t t r r o o l l l l e e r r w w i i t t h h 8 8 k k b b o o t t p p r r o o m m
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 2 oct. 28, 2010 preliminary version: 0.1 table of contents page t able of c ontents ................................................... ................................................... ................................................... .............................2 16-pin remote controller with 16/8/4kb otp rom................................................ ................................................... ....................4 1. general description........................................ ................................................... ................................................... ........................ 4 2. features ........................................... ................................................... ................................................... ............................................4 3. block diagram............................................ ................................................... ................................................... ................................5 4. signal descriptions ....................................... ................................................... ................................................... .......................... 6 4.1. p in d escription ................................................... ................................................... ................................................... .....................6 4.2. pin a ssignment (t op v iew ) .................................................. ................................................... ................................................... ....6 4.2.1. sop16 package for GPM6P1009A....................... ................................................... ................................................... .......... 7 5. functional descriptions....................................... ................................................... ................................................... .................8 5.1. c entral p rocessing u nit ................................................... ................................................... ................................................... .....8 5.1.1. cpu introduction................................... ................................................... ................................................... .......................... 8 5.1.2. cpu register....................................... ................................................... ................................................... ...........................8 5.2. m emory o rganization ................................................... ................................................... ................................................... ......... 10 5.2.1. introduction ....................................... ................................................... ................................................... ............................ 10 5.2.2. memory space ....................................... ................................................... ................................................... ....................... 10 5.2.3. configuration register ............................. ................................................... ................................................... ..................... 10 5.2.4. special function registers (sfr) ................... ................................................... ................................................... .............. 12 5.3. c lock s ource ................................................... ................................................... ................................................... ..................... 14 5.4. p ower s aving m ode ................................................... ................................................... ................................................... ............ 14 5.4.1. introduction ....................................... ................................................... ................................................... ............................ 14 5.4.2. sleep mode ......................................... ................................................... ................................................... ....................... 15 5.4.3. freeze mode........................................ ................................................... ................................................... ...................... 15 5.5. i nterrupt ................................................... ................................................... ................................................... ............................ 17 5.5.1. introduction ....................................... ................................................... ................................................... ............................ 17 5.5.2. interrupt register ................................. ................................................... ................................................... ......................... 18 5.6. r eset s ources ................................................... ................................................... ................................................... .................... 19 5.6.1. introduction ....................................... ................................................... ................................................... ............................ 19 5.6.2. power-on reset (por) ............................... ................................................... ................................................... ................. 19 5.6.3. low voltage reset (lvr) ............................ ................................................... ................................................... .................. 19 5.6.4. watchdog timer reset (wdr) ......................... ................................................... ................................................... ............. 19 5.7. i/o ports .............................................. ................................................... ................................................... ................................ 21 5.7.1. introduction ....................................... ................................................... ................................................... ............................ 21 5.7.2. port b............................................. ................................................... ................................................... ............................... 22 5.7.3. port d ............................................. ................................................... ................................................... .............................. 24 5.8. t imer m odule ................................................... ................................................... ................................................... ...................... 25 5.8.1. introduction ....................................... ................................................... ................................................... ............................ 25 5.9. m ode 0 t imer a (12- bit up c ount t imer ).................................................. ................................................... .................................. 26 5.9.1. mode 0 timer a pwm with carrier signal mode ........ ................................................... ................................................... .... 26 5.9.2. mode 0 timer a pwm without carrier signal mode ..... ................................................... ................................................... .. 30 5.9.3. mode 0 timer a capture & envelope detect mode...... ................................................... ................................................... .. 31 5.9.4. pwm carrier signal algorithm....................... ................................................... ................................................... ................ 36
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 3 oct. 28, 2010 preliminary version: 0.1 5.10. m ode 0 t imer b (12- bit up c ount t imer ) .................................................. ................................................... ................................. 37 5.11. m ode 1 t imer a (8- bit down c ount t imer ) .................................................. ................................................... .............................. 39 5.11.1. mode 1 timer a pwm with carrier signal mode ........ ................................................... ................................................... .... 40 5.11.2. pwm without carrier signal mode .................... ................................................... ................................................... ............ 44 5.11.3. capture & envelope detect mode ..................... ................................................... ................................................... ............ 45 5.11.4. pwm carrier signal algorithm....................... ................................................... ................................................... ................ 50 5.12. m ode 1 t imer b .................................................. ................................................... ................................................... ..................... 50 5.13. ir t ransfer /r eceiver m odule ................................................... ................................................... .............................................. 53 5.14. a lphabetical l ist of i nstruction s et ................................................... ................................................... ................................... 54 6. electrical characteristics .................................... ................................................... ................................................... ........... 59 6.1. a bsolute m aximum r atings ................................................... ................................................... ................................................... 59 6.2. ac c haracteristics (t a = 25 ) .................................................. ................................................... .............................................. 59 6.3. dc c haracteristics (vdd = 3.0v, t a = 25 ) .................................................. ................................................... .......................... 59 7. application circuits ........................................... ................................................... ................................................... .................... 62 7.1. GPM6P1009A a pplication c ircuits ................................................... ................................................... ....................................... 62 7.2. pcb l ayout g uideline ................................................... ................................................... ................................................... ......... 63 8. disclaimer......................................... ................................................... ................................................... ......................................... 64 9. revision history............................................ ................................................... ................................................... ........................... 65
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 4 oct. 28, 2010 preliminary version: 0.1 16-pin remote controller with 16/8/4kb otp rom 1. general description this document contains device-specific information for GPM6P1009A. it is a special chips for remote contro l with 512 bytes built-in sram and 8k bytes built-in otp rom. it includes three timers and up to 12 software selectable gener al i/os. additionally, it provides one frequency programmabl e and duty selectable pulse width modulation (pwm) output for remote control. and it provides a built-in capture mode t imer for input signal frequency detecting by infrared learning fun ction. it operates over a wide voltage range of 2.0v - 3.6v@4 mhz. it has a sleep mode for power saving which retains the contents of ram, but stops the oscillator and causes all oth er chip functions to be inoperative. sleep mode can be rel eased by using external wakeup sources. in addition, it pro vides a freeze mode for power savings and key board locking when power-supply voltage is detected lower than v lvr . in freeze mode, cpu and peripheral are stopped, and all i/os maintain floating with input function disabled. the freeze mode releases when power-supply voltage recover from v lvr . especially, it has a very accuracy internal osc, wh ich can match the spec 1.5%(typ) @ 2.0v~3.6v and can be used for most applications. meanwhile, the built-in ir transfer module can make ir control and usage easily. 2. features cpu ? 151 instructions ? 13 addressing modes ? up to 8mhz clock operation memories ? 8k bytes program otp rom ? 512 bytes ram including stack area reset management ? enhanced reset system ? power on reset (por) ? low voltage reset (lvr) ? watchdog reset (wdr) interrupt management ? 8 internal interrupts i/o ports ? max 11 multifunction bi-directional i/os. and it has a vpp pin with input (with pull low or high resistor) and output low multifunction. ? each incorporates with pull-up resistor, pull-down resistor or floating input, depending on programmer?s settin gs on the corresponding registers. ? i/o ports with led driving capability ? i/o ports with 16ma current sink clock management ? internal oscillator: 4mhz or 8mhz (selectable by c ode option) 1.5%(typ), @ 2.0v~3.6v ? crystal input: 4~ 8mhz @ 2.0v~3.6v power management ? two power saving modes: sleep, freeze modes 1 analog peripheral ? lvr: low voltage reset (1.8v or 2.2v selectable by code option) 12-bit up count or 8bit down count selectable (by s fr) timer (timer a) ? timer mode with clock source selectable ? pwm output in carrier signal mode with duty and dr iver current programmable ? pwm output in no carrier signal mode with driver c urrent programmable ? capture the input signal frequency ? detect the signal envelop 12-bit up count or down count selectable (by sfr) t imer (timer b) ? timer mode with clock source selectable ? timer a?s carry signal can be its clock source watchdog timer ? frequency: 0.95hz @ 4mhz(system clock) key wake up ? key change wake-up from sleep mode ir ? built-in ir tx can drive ir led with up to 200ma driving capability @ vdd=3.0v & v rmt =3.0v. ? built-in ir rx can supply capture function with se nsitivity adjustable. (2ua, 5ua, 8ua, 11ua)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 5 oct. 28, 2010 preliminary version: 0.1 table 2-1 GPM6P1009A configuration ccp cpu osc. voltage (v) speed (mhz) cap cnt pwm int xtal part no. rom type 2.0~3.6 4 rom (byte) ram (byte) ir tx/rx io no. pkg 2.4~3.6 8 GPM6P1009A otp 2.0~3.6 4 8k 512 tx/rx 1 1 1 ? ? 12 sop16 3. block diagram figure 3-1 the block diagram of GPM6P1009A
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 6 oct. 28, 2010 preliminary version: 0.1 4. signal descriptions 4.1. pin description type: i = input, o = output, s = supply pin name GPM6P1009A sop16 type main function alternate function pb5 8 i/o pb4 7 i/o pb3 6 i/o pb2 5 i/o pb1 4 i/o pb0 3 i/o portb[5:0] : bi-directional programmable input/output port. i t can be configured as pull-up resistor, pull-down resistor or floating input, open-drain pm os output, or cmos output. the sink current (i ol ) of this i/o can reach 16ma (vdd = 3.0v, v ol = 0.2*vdd) enough to drive led. normal wakeup source, if key is changed, chip wakeu p from sleep mode. key scan wakeup source, if key change is detected, chip wakeup from sleep mode. vpp /pd5 14 i/o vpp power supply : otp program power supply. portd[5] : bi-directional programmable input/output port. i t can be configured as pull-up resistor, pull-down resistor or floating input, open-drain nm os output. the sink current (i ol ) of this i/o can reach 16 ma (vdd = 3.0v, v ol = 0.2*vdd) enough to drive led. key scan wakeup source, if key change is detected, chip wakes up from sleep mode. pd4 13 i/o pd3 12 i/o pd2 11 i/o portd[4:2] : bi-directional programmable input/output port. i t can be configured as pull-up resistor, pull-down resistor or floating input, open-drain pm os output, or cmos output. the sink current (i ol ) of this i/o can reach 16 ma (vdd = 3.0v, v ol = 0.2*vdd) enough to drive led. key scan wakeup source, if key change is detected, chip wakes up from sleep mode. xti / pd1 10 i/o crystal input : it will be connected with external crystal for a cr ystal oscillation circuitry in crystal mode. portd[1] : bi-directional programmable input/output port. i t can be configured as pull-up resistor, pull-down resistor or floating input, open-drain pm os output, or cmos output. the sink current (i ol ) of this i/o can reach 16ma (vdd = 3.0v, v ol = 0.2*vdd) enough for driving led. xto /pd0 9 i/o crystal output : it is connected with external crystal for a crysta l oscillation circuitry in crystal mode. portd[0] : bi-directional programmable input/output port. it can be configured as pull-up resistor, pull-down resistor or floating input, open-drain pm os output, or cmos output. the sink current (i ol ) of this i/o can reach 16 ma (vdd = 3.0v, v ol = 0.2*vdd) enough to drive led. key scan wakeup source, if key change is detected, chip wakeup from sleep mode. rmt 15 o remote ir signal transmit or receive pin. vref 2 s the power supply for sram block. vdd 16 s power supply vss 1 s ground 4.2. pin assignment (top view)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 7 oct. 28, 2010 preliminary version: 0.1 4.2.1. sop16 package for GPM6P1009A 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vss vref pb0 pb1 pb2 pb3 pb4 pb5 vdd rmt pd5/vpp pd4 pd3 pd2 pd1/xti pd0/xto
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 8 oct. 28, 2010 preliminary version: 0.1 5. functional descriptions 5.1. central processing unit 5.1.1. cpu introduction the microprocessors of GPM6P1009A is a high perform ance processor equipped with six internal registers: acc umulator, program counter, x register, y register, stack poin ter, and processor status register. this cpu is a fully sta tic cmos design. the oscillation frequency could be varied up to 8.0 mhz depending on the application. 5.1.2. cpu register the cpu has six registers that are the program coun ter (pc), an accumulator (a), two index registers (x, y), the st ack pointer (sp), and the status register (p). the program counter c onsists of 16-bit register. figure 5-1 system registers x, y register in address mode, x and y registers can be used as index registers or buffer registers. these register contents are a dded to the specified address, which becomes the actual address . some operations such as increment, decrement, comparison and data transfer function can be used in x and y registers. accumulator the accumulation is an 8-bit general-purpose regist er, which can be operated with transfer, temporary saving, condit ion judgment, etc. stack pointer the cpu has an 8-bit-wide register indicating the l ocation in the stack to be accessed (push or pop) when a subroutin e call or interrupt occurs. when subroutine call is executed or an interrupt oc currence is accepted, the value of stack point is updated autom atically. fixed value by hardware 01 7 0 15 8 stack area range($0180~$01ff) sp figure 5-2 stack point register [example] 5-1initialized stack point value ldx #c_stack_bottom ; initial stack pointer at $1ff txs ;transfer to stack point program counter (pc) the program counter is a 16-bit wide register. it consists of two 8-bit registers which registers are pch and pcl. t his register indicates the address of next instruction to be exe cuted. in reset state, the content of program counter is stored wit h $fffc. status register (p) the 8-bit status register contains the interrupt ma sk and 6 flags representative of the result of the instruction jus t executed. this register can also be handled by the php and plp ins tructions. these bits can be individually controlled by specif ic instructions. the detailed description is shown in following desc ription. note: not all instructions affect status register. a de tailed instruction description will be discussed in 6502 i nstruction manual. negative flag bit this flag indicates the bit7 status of the result o f a data or arithmetic operation. programmer can use this bit to do some operations, e.g. branch condition or bit operation. overflow flag bit this flag indicates whether the overflow has occurr ed in arithmetic operation. when the result of an addition or subtr action is over +127 or less than ?128, this overflow bit is set to ?1?.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 9 oct. 28, 2010 preliminary version: 0.1 decimal mode flag this flag indicates which mode is operated by arith metic operation. the cpu has two operation modes; binary mode and decima l mode for arithmetic operation. programmer can use the instruction to change modes. interrupt disable flag this bit can enable or disable all interrupt except nmi interrupt source. if this bit is set to ?1?, cpu will ignore interrupt signal. on the contrary, if this bit is set to ?0?, cpu wil l accept interrupt signal. zero flag this flag indicates the result of a data or arithme tic operation. if the result is equal to zero, the zero flag is set t o ?1?. contrary, this bit is set to ?0? by other values. carry flag this bit is set to ?1 if the result of addition ope ration generates a carry, or if the result of subtraction doesn?t gene rate a borrowing. in addition, some shift instructions or rotate inst ructions also change this bit. figure 5-3 status register
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 10 oct. 28, 2010 preliminary version: 0.1 5.2. memory organization 5.2.1. introduction GPM6P1009A separates address spaces to program memo ry and data memory. program memory can be read only. it c ontains up to 8k bytes of program memory. data memory that co ntains 512 bytes of ram including stack area can be read and w ritten. 5.2.2. memory space memory address allocations on the GPM6P1009A are di vided into several parts. the first 128 addresses are allocat ed for special function registers, including function control regi sters and i/o control registers, which allow programmer to use th e first page instruction to set up this register and help to red uce program size. cpu view io & reg ram rom memory mapping: ram view ram $0000~$007f $0080~$027f $e000~$ffff $000~$1ff reserved $0280~$5fff rom view rom $0000~$1fff rom reserved $6000~$7fff $8000~$dfff figure 5-4 shows GPM6P1009A memory map. its ram consists of 512 bytes (including stack). in cpu view, the ram locations are from $080 through $27f. it is ma pped to $000~$1ff respectively in ram view. it supports 8k bytes of rom. in cpu view, the rom address is located on $6 000 ~ $7fff. and the rom area, $e000~$ffff, is double ma pped to the area $00000 ~ $01fff. the address of nmi, reset _ _ _ _ _ _ _ _ _ _ and irq exception vectors are located from $fffa to $ffff. the exception vectors should be specified in the program to have proper operation. figure 5-5 interrupt vector area [example] 5-2 interrupt vector table in software vector: .section dw v_nmi dw v_reset dw v_irq 5.2.3. configuration register the configuration register is used to setup the ope ration condition. and its cpu view address is $fff8 & $fff9. it is ma pped to the special reserved rom address $1ff8 & $1ff9 (for 8k rom) GPM6P1009A has the following configuration options. crystal resonator or internal oscillator clock sou rce option. lvr enable or disable option. watchdog enable or disable option. iosc frequency 4mhz or 8mhz selection option. lvr trigger voltage 1.8v or 2.2v selection option. users can refer to the device configuration registe r and set it in [project/ setting/ configuration register] of forti s ide as figure 5-6. device configuration register (opcode0, $fff8) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name optchk2 optchk1 optchk0 security reserved wdtenb lvrenb sysclks access r r r r r r r r default 1 1 1 1 1 1 1 1 bit [7:4] optchk [2:0]: configuration check bits must be filled in 101. security: disable/enable security protection. read or not re ad data from otprom 1: security disable
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 11 oct. 28, 2010 preliminary version: 0.1 0: security enable bit [3] reserved bit [2] wdtenb: disable/enable watchdog 0= wdt is enabled 1= wdt is disabled bit [1] lvrenb: disable/enable lvr 0= lvr is enabled 1= lvr is disabled bit [0] sysclks: iosc (internal) / crystal selection 0= iosc 1= crystal device configuration register (opcode1, $fff9) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name reserved reserved reserved reserved reserved r eserved lvrvsel ioscfsel access r r r r r r r r default 1 1 1 1 1 1 1 1 bit [7:2] reserved bit [1] lvrvsel: lvr trigger voltage selection 0= lvr trigger voltage is 1.8v 1= lvr trigger voltage is 2.2v bit [0] ioscfsel: iosc frequency selection 0= iosc frequency is 4mhz 1= iosc frequency is 8mhz
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 12 oct. 28, 2010 preliminary version: 0.1 figure 5-6 device configuration register set in for tis ide 5.2.4. special function registers (sfr) GPM6P1009A has many control registers. all of the control registers are used by mcu and peripheral function b lock for controlling the desired operations. some of the con trol registers contain control and status bits for peripheral modu le such as timer unit, interrupt control unit, etc. note that the r eserved addresses are not implemented on the chip. some of bits in c ontrol register are read only. when writing to them, there are no any effects on the corresponding bits. the following table shows the summary of the control registers. the detailed information of each control registers are explained in each peripheral section. GPM6P1009A special function registers description $0000~$000a: i/o port address register reset value r/w bit7 bit6$ bit5 bit4 bit3 bit2 bit1 bit0 $00 p_iob_dir 00h r/w r/0 r/0 port b direction control $02 p_iod_dir 00h r/w r/0 r/0 port d direction control $04 p_iob_att 00h r/w r/0 r/0 port b attribute register $06 p_iod_ att 00h r/w r/0 r/0 port d attribute register $08 p_iob_dat 00h r/w r/0 r/0 write data into the port b data register and read d ata from the i/o pad. $0a p_iod_dat 00h r/w r/0 r/0 write data into the port d data register and read d ata from the i/o pad.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 13 oct. 28, 2010 preliminary version: 0.1 $0011~$001d: int flag & other special register address register reset value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p_pwm_drv 00h w - r/0 r/0 r/0 pwmdrv0 - - - $11 p_rx_sen 00h w - r/0 r/0 r/0 - tmacaps sense1 sense0 $12 p_sys_sleep 00h w c_sys_sleep= aah (write other data system to reset. ) $13 p_int_ctrl 00h r/w tmadte tmaoie capie tmboie f1kie f4kie f32kie f2mie $14 p_int_flag 00h r/w tmadtf tmaoif capif tmboif f1kif f4kif f32kif f2mif $16 p_int_flagc 00h r/w envdet r/0 r/0 r/0 r/0 r/0 r/0 r/0 $17 p_tim_sel 00h r/w timons irenb ncdten r/0 r/0 r/0 r/0 r/0 $1b p_sc_iob 00h r/w r/0 r/0 pb5se pb4se pb3se pb2se pb1se pb0se $1d p_sc_iod 00h r/w r/0 r/0 pd5se pd4se pd3se pd2se pd1se pd0se $0020~0026: timer control address register reset value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $20 p_wdt_ctrl 00h w c_wdt_clr= aah (write other data system to reset.) $21 p_tma_ctrl 00h r/w tmaes capeg tmaclk1 tmaclk0 tmadut1 tmadut0 tmamod1 tmamod0 $22 p_tmb_ctrl 00h r/w tmbes r/0 tmbclk1 tmbclk0 r/0 r/0 r/0 r/0 p_tma_cntl r mode 0 timer a counter low byte 8-bit pre-value for counter mode. p_tma_pwml w mode 0 timer a pwm carrier signal low byte 8-bit pe riod value for pwm mode. p_tma_capl r mode 0 timer a received carrier signal low byte 8-b it period width value for capture mode. p_tma_envl w mode 0 timer a received carrier signal low byte 8-b it period width pre-value for envelope mode. p_tma_cntf r mode 1 timer a counter pre-value for counter mode. p_tma_pwmf w mode 1 timer a pwm carrier signal period value for pwm mode. $23 p_tma_envf xxh w mode 1 timer a received carrier signal period width pre-value for envelope mode. p_tma_cnth r r/0 r/0 r/0 r/0 mode 0 timer a counter high byte 4-bit pre-value fo r counter mode. p_tma_pwmh w - - - - mode 0 timer a pwm carrier signal high byte 4-bit p eriod value for pwm mode. p_tma_caph r r/0 r/0 r/0 r/0 mode 0 timer a received carrier signal high byte 4- bit period width value for capture mode. p_tma_envh w - - - - mode 0 timer a received carrier signal high byte 4- bit period width pre-value for envelope mode. p_tma_pwmd w mode 1 timer a pwm carrier signal high pulse width value for pwm mode. p_tma_capd r mode 1 timer a received carrier signal period width value for capture mode. $24 p_tma_envd xxh r mode 1 timer a received carrier signal period width value for evnvelope mode. p_tmb_cntl r mode 0 timer b counter low byte 8-bit pre-value. p_tmb_regl w mode 0 timer b low byte 8-bit register. p_tmb_cntl r mode 1 timer b counter low byte 8-bit pre-value. $25 p_tmb_regl xxh w mode 1 timer b low byte 8-bit register. p_tmb_cnth r r/0 r/0 r/0 r/0 mode 0 timer b counter high byte 4-bit pre-value. p_tmb_regh w - - - - mode 0 timer b high byte 4-bit register p_tmb_cnth r r/0 r/0 r/0 r/0 mode 1 timer b counter high byte 4-bit pre-value. $26 p_tmb_regh xxh w - - - - mode 1 timer b high byte 4-bit register
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 14 oct. 28, 2010 preliminary version: 0.1 5.3. clock source GPM6P1009A supports crystal / ceramic or internal o scillator, as shown in the following diagram, figure 5-7. they c an be selected by device configuration register at address ($fff8. 0) and can be set in fortis ide, as figure 5-6. the detailed configuration register setting of devi ce has been given in section 5.2.3 configuration registe. figure 5-7 two types of clock sources 5.4. power saving mode 5.4.1. introduction to reduce the current consumption when the system d oes not need to be active, sleep mode and freeze mode can b e utilized. these two modes are able to reduce power consumption and save power. they also feature different wakeup time. user must write corresponding value to sleep control reg ister to enter sleep mode. and the system will enter freeze mode automatically when power supply is lower than a spe cial value or power down. for more information about sleep and f reeze modes, please see figure 5-8 and they will be depic ted in the next two sections.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 15 oct. 28, 2010 preliminary version: 0.1 normal mode sleep mode freeze mode write aah to p_sys_sleep power on reset ioa change & battery uninstall wait tw new battery install vdd < vlvr ioa change & battery exist figure 5-8 power saving mode operation 5.4.2. sleep mode sleep mode function will disable all system clocks, including the clock generation circuit. once the system enters s leep mode, lvr function is disabled, ram and i/os will remain in their previous states until being awakened. the system w ill be waked up by any change on port b (m-type key) or any key touching (t-type key). after GPM6P1009A are awakened, the i nternal cpu will remain on previous dtate until tw 65536 x t1 (tw = R waiting time & t1 = system clock cycle); and then c ontinue processing the program. (see figure 5-9). t1 = 1 / (f cpu ), tw R 65536 x t1 to enter sleep mode, programmer must write #c_sys_s leep ($aa) to sleep control register (p_sys_sleep). figure 5-9 sleep mode 5.4.3. freeze mode
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 16 oct. 28, 2010 preliminary version: 0.1 if the power-supply voltage drops below v lvr (see figure 5-10), the system will go into freeze mode. low voltage r eset (lvr) will reset all functions into the initial operation al (stable) state. in freeze mode, system clock and cpu is stopped; ram r emains on its previous states; all i/os are floating with input function disabled. freeze mode would be released if the bat tery is removed and reinstalled battery which voltage is hi gher than v lvr (2.2v or 1.8v). the system watch dog action don?t occur in freeze mode. t2=8* t1 t w t1 cpu clk fosc vdd(vref) 2.2v or 1.8v reset freeze system reset vss vref vdd battery off battery on lvr figure 5-10 freeze mode sleep control register (p_sys_sleep, $0012) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name sleepctrl7 sleepctrl6 sleepctrl5 sleepctrl4 sleepctrl3 sleepctrl2 sleepctrl1 sleepctrl0 access w w w w w w w w bit [7:0] sleepctrl [7:0]: operation mode control. $aa = write to enter sleep mode (c_sys_sleep) other data = reset system [example] 5-3 let mcu enter sleep mode lda p_iob_dat ; latch portb lda #c_sys_sleep ; sleep command $aa sta p_sys_ sleep ; go to sleep mode
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 17 oct. 28, 2010 preliminary version: 0.1 5.5. interrupt 5.5.1. introduction GPM6P1009A provides eight types of interrupt source s with the same normal interrupt level. the eight types of in terrupt sources are timer a envelope detect interrupt, timer a capt ure interrupt, timer a overflow interrupt, timer b overflow interr upt, time fosc/1024 interrupt, time fosc/4096 interrupt, time fosc/32768 interrupt, time fosc/2097152 interrupt. these interrupts have individual status (occurred o r not) and control (enable or not) registers. in general, onc e an interrupt event occurs, the corresponding flag bit will be se t. if the related interrupt control bit is set to enable interrupt, a n interrupt request signal will be generated and then cpu executes the interrupt service routine. if the related interrupt control bit is disabled, programmer still can observe the corresponding flag bit, but no interrupt request signal will be generated. the in terrupt flag bits must be cleared in the interrupt service routine to prevent program from deadlock. with any instruction, interrupts pe nding during the previous instruction is served. before entering interrupt service routine, the syst em saves the current pc address into bottom of the stack such as address $1ff and $1fe in figure 5-11. and abstract the interrup t service routine first address from $fffe and $ffff. in a c orresponding way, the system abstract the return pc address from the bottom of the stack when finished the interrupt service (see figure 5-12). these interrupt sources are listed as [table] 5-1 and will be described in corresponding section. [table] 5-1 interrupt source list source interrupt flag register interrupt control register source interrupt flag register interrupt control register envelope detect interrupt tmadtf($0014.7) tmadte($0013.7) time fosc/1024 f1kif($0014.3) f1kie($0013.3) timer a overflow tmaoif($0014.6) tmaoie($0013.6) time fosc/4096 f4kif($0014.2) f4kie($0013.2) capture interrupt capif($0014.5) capie($0013.5) tim e fosc/32768 f32kif($0014.1) f32kie($0013.1) timer b overflow tmboif($0014.4) tmboie($0013.4) time fosc/2097152 f2mif($0014.0) f2mie($0013.0) figure 5-11 interrupt triggered by irb figure 5-12 leave interrupt routine
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 18 oct. 28, 2010 preliminary version: 0.1 5.5.2. interrupt register interrupt flag register (p_int_flag, $0014) bit 7 6 5 4 3 2 1 0 name tmadtf tmaoif capif tmboif fd1kif fd4kif fd32k if fd2mif access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this flag is cleared by writing the corresponding b it by ?1?. bit 7 tmadtf : timer a envelope detect interrupt flag 0 = no event 1 = event has occurred bit 6 tmaoif : timer a overflow interrupt flag 0 = no event 1 = event has occurred bit 5 capif : timer a capture interrupt flag 0 = no event 1 = event has occurred bit 4 tmboif : timer b overflow interrupt flag 0 = no event 1 = event has occurred bit 3 fd1kif : time fosc/1024 interrupt flag 0 = no event 1 = event has occurred bit 2 fd4kif : time fosc/4096 interrupt flag 0 = no event 1 = event has occurred bit 1 fd32kif : time fosc/32768 interrupt flag 0 = no event 1 = event has occurred bit 0 fd2mif : time fosc/2097152 interrupt flag 0 = no event 1 = event has occurred interrupt control register (p_int_ctrl, $0013) bit 7 6 5 4 3 2 1 0 name tmadte tmaoie capie tmboie fd1kie fd4kie fd32k ie fd2mie access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 tmadte : timer a envelope detect interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 6 tmaoie : timer a overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 5 capie : timer a capture interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 4 tmboie : timer b overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 3 fd1kie : time fosc/1024 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 2 fd4kie : time fosc/4096 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 1 fd32kie : time fosc/32768 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 0 fd2mie : time fosc/2097152 interrupt enable bit 0 = interrupt disable 1 = interrupt enable envelop detect register (p_int_flagc, $0016) bit 7 6 5 4 3 2 1 0 name envdet - - - - - - - access r - - - - - - - default 0 - - - - - - - bit 7 envdet : envelope flag showing whether envelope exist or n ot. 0 = no envelope exist 1 = envelope exist bit [6:0] reversed
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 19 oct. 28, 2010 preliminary version: 0.1 [example] 5-4 enable timer a overflow interrupt ;=========================; ; main loop routine ;=========================; lda #c_int_tmaoie sta p_int_ctrl ; enable timer a overflow int cli ; enable int ;=========================; ;irq interrupt service routine ;=========================; lda #c_int_tmaoif sta p_int_flag ; clear int request flag sta p_int_ctrl ; enable timer a overflow int 5.6. reset sources 5.6.1. introduction there are three types of reset sources for the syst em, power-on reset (por), low voltage reset (lvr), watchdog time r reset (wdr). these reset sources can be concluded as ext ernal events and internal events. the internal events co me from the program run away. figure 5-13 shows the affected r egion for each reset source. figure 5-13 reset sources 5.6.2. power-on reset (por) a por is generated when vdd is rising from 0v. when vdd rises to an acceptable level (~1.45v), the power on reset circuit will start a power-on sequence. after that, the system will operate in target speed and start to activate. 5.6.3. low voltage reset (lvr) the on-chip low voltage reset (lvr) circuitry force s the system entering freeze mode when the mcu voltage falls bel ow the specific lvr trigger voltage. this function preven ts mcu from working at an invalid operating voltage range. a device configuration register bit $fff8.1(can be set in fortis ide as figure 5-6) is used to enable or disable this fu nction. if this function is enabled, the lvr circuit will monitor p ower level while chip is operating. if the power is lower than the specific level for a specific period, the system will enter freeze mode and all i/os will be locked. 5.6.4. watchdog timer reset (wdr) on-chip watchdog circuitry makes the device enterin g reset when mcu goes into an unknown state without watchdog cle aring information. this function prevents the mcu from b eing stuck in an abnormal condition. watchdog timer (wdt) can be disabled or enabled through configuring register bit $fff8.2 (can be set in fortis ide as figure 5-6). watchdog timer reset wi ll be
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 20 oct. 28, 2010 preliminary version: 0.1 generated by a time-out event of the wdt automatica lly when watchdog is enabled. watchdog timer reset will reset the cpu and restart the program. to avoid a wdt time-out reset, user should write # c_wdt_clr (=$aa) to p_wdt_ctrl periodically. if a reset signal is generated, it will also clear the wdt counter and r estart the wdt. different reset sequences as the following figures: figure 5-14 reset sequence figure 5-15 power-on reset sequence figure 5-16 watch-dog reset sequence
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 21 oct. 28, 2010 preliminary version: 0.1 watchdog control register (p_wdt_ctrl, $0020) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name wdtctrl7 wdtctrl6 wdtctrl5 wdtctrl4 wdtctrl3 wdtctrl2 wdtctrl1 wdtctrl0 access w w w w w w w w bit [7:0] wdtctrl [7:0]: operation mode control register $aa = write to clear watchdog cnt (c_wdt_clr) other data = reset system [example] 5-5 clear watch dog counter lda # c_wdt_clr ; clear watch dog command $aa sta p_wdt_ ctrl 5.7. i/o ports 5.7.1. introduction GPM6P1009A has three ports, port b and port d. the se port pins may be multiplexed with an alternate function for the peripheral features on the device. in general, whe n an initial reset state occurs, all ports are used as a general purpose input port. there are three parts, data, direction and a ttribution registers, in these io structures. each correspond ing bit in these ports should be given a value. in m-type keyboard application, port b should be co nfigured as input ports, and in sleep mode any change occurred in these ports will cause system wakeup. in t-type keyboard appli cation, each port of port b and port d can be selected as scan k ey independently by configuring register p_sc_iox. if the port is configured as scan key, it worked as input with pul l high resistor and output fixed frequency low pulse in sleep mode. any of the keys touch would cause system wakeup. the setting rules are as follows: the direction setting determines whether this pin is an input or an output. the data register is used to read the value on the port, which can be different when programmer sets the port to d ifferent configuration (input pull-high/pull- low). please refer to the [table] 5-1 for pd[5] and [table] 5-2 for pb[5:0], pd[4:0]?s setting. [table] 5-1 i/o configurations (for pd[5]) attribution (p_iox_att) direction (p_iox_dir) data (p_iox_dat) function description 0 0 0 floating input with float 0 0 1 pull low input with pull-low 0 1 0 driving low output data 0 1 1 floating float 1 0 0 floating input with float 1 0 1 pull high input with pull-high 1 1 0 floating float 1 1 1 driving low output data [table] 5-2 i/o configurations (for pb[5:0] and pd[ 4:0]) attribution (p_iox_att) direction (p_iox_dir) data (p_iox_dat) function description 0 0 0 floating input with float 0 0 1 pull low input with pull-low 0 1 0 driving low output data 0 1 1 driving high output data 1 0 0 floating input with float
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 22 oct. 28, 2010 preliminary version: 0.1 attribution (p_iox_att) direction (p_iox_dir) data (p_iox_dat) function description 1 0 1 pull high input with pull-high 1 1 0 driving high output data 1 1 1 driving low output data register control logic pull high pull low pin pad p_iox_dat(w) p_iox_att(r/w) p_iox_dat(r) p_iox_dir(r/w) driver low figure 5-17 block diagram of i/o port (pd[5]) register control logic pull high pull low pin pad p_iox_dat(w) p_iox_att(r/w) p_iox_dat(r) p_iox_dir(r/w) figure 5-18 block diagram of i/o port (pb[5:0] and pd[4:0]) 5.7.2. port b port b is a 6-bit programmable bi-directional port. the port is controlled by direction control register p_iob_dir, and attribution register _p_iob_att. reading p_iob_dat will get th e real io value.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 23 oct. 28, 2010 preliminary version: 0.1 port b direction register (p_iob_dir, $0000) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iob_dir access - - r/w default 00h bit [7:6] reserved bit [5:0] p_iob_dir: port b direction register. 0 = input 1 = output port b attribution register (p_iob_att, $0004) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iob_att access - - default 00h bit [7:6] reserved bit [5:0] p_iob_att: port b attribution register port b data register (p_iob_ dat, $0008) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iob_ dat access - - r/w default 00h bit [7:6] reserved bit [5:0] p_iob_ dat: port b data value. read to get port b value write to configure output high/low or configure inp ut with pull high/low resistor. [example] 5-6 set port b [3:0] as output with low d ata and port b [5:4] as input with pulling high. lda #$0f ; stor e accumulator with $0f sta p_iob_dir ; set direction lda #$00 ; store accumulator with $00 sta p_iob_att ; set attribute lda #$30 ; store accumulator with $30 sta p_iob_dat ; set port data [example] 5-7 set port b [5:0] as input with float. lda #$00 ; store accumulator with $00 sta p_iob_att ; set direction sta p_iob_dir ; se t attribute sta p_iob_dat ; set port data
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 24 oct. 28, 2010 preliminary version: 0.1 port b can be configured as scan key or not by key scan select register. port b key scan select register (p_sc_iob, $001b) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - pb5se pb4se pb3se pb2se pb1se pb0se access - - r/w r/w r/w r/w r/w r/w default 00h bit [7:6] reserved bit [5:0] p_sc_iob: port b key scan select register. 0: no key scan function 1: with key scan function. [example] 5-8 set pb[3:0] as key scan port. lda #$0f sta p_sc_iob ; set pb[3:0] as key scan port 5.7.3. port d port d is a 6-bit programmable bi-directional port. the port is controlled by direction control register p_iod_dir, and attribution register p_iod_att. reading p_iod_dat will get the real io value. in addition, port d is multiplexed with var ious special functions. after reset, the default setting for po rt d is used as general i/o ports. and pd5 can set as input pull l ow/high or driver low but without driver high function. [table] 5-3 port d function list port d pin bit shared function pd0 bit0 crystal output (xto) pd1 bit1 crystal input (xti) pd5 bit5 otp program power supply (vpp) port d direction register (p_iod_dir, $0002) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iod_dir access - - r/w default 00h bit [7:6] reserved bit [5:0] p_iod_dir : port d direction register. 0 = input 1 = output port d attribution register (p_iod_att, $0006) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iod_att access - - r/w default 00h bit [7:6] reserved bit [5:0] p_iod_att : port d attribution register port d data register (p_iod_ dat, $000a)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 25 oct. 28, 2010 preliminary version: 0.1 bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - p_iod_ dat access - - r/w default 00h bit [7:6] reserved bit [5:0] p_iod_ dat : port d data value. read to get port d value write to configure output high/low or configure inp ut with pull high/low resistor. [example] 5-9 set port d[1:0] as output with low data. lda #$03 ; store accumulator with $03 sta p_iod_dir ; set direction lda #$00 ; store accumulator with $00 sta p_iod_att ; set attribute sta p_iod_dat ; set port data port d can be configured as scan key or not by key scan select register. port d key scan select register (p_sc_iod, $001d) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - pd5se pd4se pd3se pd2se pd1se pd0se access - - r/w r/w r/w r/w r/w r/w default 00h bit [7:6] reserved bit [5:0] p_sc_iod: port d key scan select register. 0: no key scan function 1: with key scan function. [example] 5-10 set pd[3:0] as key scan port. lda #$0f sta p_sc_iod ; set pd[3:0] as key scan port 5.8. timer module 5.8.1. introduction GPM6P1009A has two timers, timer a and timer b resp ectively. timer a and timer b can be set as mode 0 (12-bit up count and 12-bit up count) or mode 1 (8-bit down count and 12 -bit down count) timer by configuring the timer select regist er (p_tim_sel.7). timer a contains one powerful pwm f unction and is controlled by corresponding control register s. this function can be easily configured. timer a also ha s a capture function which can capture the frequency of input s ignal. and timer a has another function is envelope detection; it can detect envelope waveform of input signal with or without c arrier signal. each timer?s function summary is shown as [table] 5 -4. [table] 5-4 summary of timer function for gpm6p1009 a timer counter pwm capture envelope detect timer a yes yes yes yes timer b yes none none none
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 26 oct. 28, 2010 preliminary version: 0.1 5.9. mode 0 timer a (12-bit up count timer) when timer a is selected as 12-bit up count timer v ia configuring the corresponding bits of the control register ( p_tim_sel [7]), the timer a is special for generating carrier signal in ir control application. timer a?s input clock is selectable ( fosc/1, fosc/2, fosc/4, fosc/16), which can be configured by contro l register p_tma_ctrl [5:4]. timer a provides with two pwm modes, and the pwm signal is sent to ir tx (rmt) pin. the dri ver current of these two kinds of pwm are programmable by configur ing tx pwm driving current control source register (p_pwm_ drv [3]). 12-bit up count timer a module has the following fe atures: readable and writable clock source selectable interrupt-on-overflow from #$fff to #$000 supports pwm with carrier signal mode supports pwm without carrier signal mode supports capture mode for learning function supports envelope detect mode for learning functio n 12-bit up count timer a pwm block pb3 capture block int block data bus ir rxtx block mu x rmt figure 5-19 12-bit up count timer a block diagram 5.9.1. mode 0 timer a pwm with carrier signal mode timer a can be configured as pwm mode for generatin g carrier signal. in pwm with carrier signal mode, the 12-bi t timer is an up counter with input clock selectable (fosc/1, fosc/2 , fosc/4, fosc/16). when timer a is started, the value of 4- bit high-byte (low-nibble) register and 8-bit low-byte register w ould firstly be loaded into the 12-bit counter and then the counter starts count up from the loaded value. if an overflow occurs, the value of high-byte (low-nibble) register (p_tma_cnth) and lo w-byte register (p_tma_cntl) would be reloaded into the co unter automatically and the counter starts count up again . so the carrier signal with frequency programmable can be g enerated by this pwm mode via configuring these two registers. also users can select pwm duty cycle (1/3, 1/4, 1/5, 1/2) via configuring the corresponding bits of the control register ( p_tma_ctrl [3:2]). the carrier signal?s enabled or disabled bit can be controlled by two methods depended on which clock source is selec ted by timer b. if timer b is selected one of the first t hree clock source (fosc, fosc/4 or fosc/64) by p_tmb_ctrl [5:4] (tmbc lk [1:0]), timer a?s carrier signal on/ off is controlled by t imer a?s enabled/ disabled control bit (tmaes) directly. in addition , pwm output function also can be disabled by writing 1 to regis ter irenb($17.6).
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 27 oct. 28, 2010 preliminary version: 0.1 figure 5-20 mode 0 timer a pwm mode diagram figure 5-21 mode 0 timer a normal pwm generation wi thout envelop
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 28 oct. 28, 2010 preliminary version: 0.1 figure 5-22 the waveform of mode 0 timer a pwm with carrier signal mode (1/3 duty, on/off control by t maes) another method to generate envelope pwm signal is t hat timer a and timer b must be used together. timer a must ge nerate carry clock at first, which is same as normal pwm g eneration. then enable timer b and select timer a carrier sign al as its input clock. and timer b register must be written in the right data, which represents the carry number. when tmbovf hap pen, another value must be written into timer b register , which represents the no carry clock number. envelop with carrier is on or off only when timer b overflow events occur one by one. then, the envelop pwm signal will be generated at r mt port at last.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 29 oct. 28, 2010 preliminary version: 0.1 12 bit up-counter fosc regh (4 bits) regl (8 bits) data bus mu x fosc/4 fosc/16 enb enb duty and pwm control block tmadut[1:0] carry p_tma_ctrl($21) tmadut1 tmaclk0 tmaclk1 tmamod0 tmamod1 tmadut0 capeg tmaes 1 0 0 p_int_ctrl($13) f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte p_int_flag($14) f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf tmaoif p_tma_pwmh($24) tmaprdh p_tma_pwml($23) tmaprdl tmapwm tx ir (rmt ) p_pwm_drv($11) pwmdrv0 tmaes tmacrr mux carry_en tmbclk[1:0] tmamod[1:0] (from tmb) fosc/2 timons($17.7)=0, 12-bit up count timer a pwm with carrier mode irenb ($17.6) mode control block timons($17.7)=0, 12-bit up count timer b 12-bit up-counter fosc regh (4 bits) regl (8 bits) data bus overflow mux fosc/4 fosc/64 tmacrr tfr ck ckn q qn rn tmbes carry_en p_tmb_ctrl($22) tmbclk0 tmbclk1 tmbes p_int_ctrl($13) f1kie tmboie f2mie f32kie f4kie tmaoie tmboif p_int_flag($14) f1kif tmboif f2mif f32kif f4kif tmaoif 11 p_tmb_cnth($26) tmbcnth p_tmb_cntl($25) tmbcntl w_tmb_regh figure 5-23 envelope pwm generated by mode 0 timer a & mode 0 timer b diagram
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 30 oct. 28, 2010 preliminary version: 0.1 figure 5-24 the waveform of mode 0 timer a pwm with carrier signal mode (1/3 duty, on/off control by m ode 0 timer b overflow events) 5.9.2. mode 0 timer a pwm without carrier signal mode pwm without carrier signal mode is used to generate envelop pwm signal without carrier signal. in this mode, i r tx (rmt) pin just output high or low, and is controlled by timer a?s enabled or disabled control bit or timerb?s overflow events in turn. the same as pwm with carrier signal mode, the 12-bit ti mer is an up counter with input clock selectable (fosc/1, fosc/2 , fosc/4, fosc/16). when timera is started, the value of hig h-byte (low-nibble) register and low-byte register would f irstly be loaded into the 12-bit counter and then the counter starts to count up from the loaded value. if an overflow occurs, the value of high-byte (low-nibble) register and low-byte register would b e reloaded into the counter automatically and the counter starts to count up again. the internal carrier signal is generated but does n ot be sent to ir tx pin. figure 5-25 the waveform of mode 0 timer a pwm with out carrier signal mode (on/off control by tmaes)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 31 oct. 28, 2010 preliminary version: 0.1 figure 5-26 the waveform of mode 0 timer a pwm with out carrier signal mode (on/off control by mode 0 t imer b overflow events) 5.9.3. mode 0 timer a capture & envelope detect mode in ir learning function application, timer a should be configured as capture mode for measuring the frequency of inpu t signal from rmt pin. in capture mode, the 12-bit timer is an u p counter which counts from 00h with input clock selectable ( fosc/1, fosc/2, fosc/4, fosc/16). when rising or falling (selectab le via p_tma_ctrl) edge of rx is captured, the high-byte ( low-nibble) value of the counter would be loaded into register high and the low byte value of counter would be loaded into regi ster low, at the same time, it generates an interrupt (capif) and th en the counter is cleared to 00h. when the timer overflows, the o verflow interrupt (tmaoif) occurs. the input carrier signa l cycle time is recorded in register low (p_tma_capl) and register high (p_tma_caph). of course, if the time data that wou ld to be record is bigger than the biggest data that these t wo registers can be loaded, the overflows of timer a should be count inclusively.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 32 oct. 28, 2010 preliminary version: 0.1 tmons($17.7)=0, 12-bit up count timer a capture mode 12bit up counter fosc capture block regh (4 bits) regl (8 bits) data bus tmaoif capif m u x fosc/4 fosc/16 tmaclk[1:0] carry mu x rmt pb3 p_rx_sen($11) tmacaps senses0 senses1 p_tma_ctrl($21) tmadut1 tmaclk0 tmaclk1 tmamod0 tmamod1 tmadut0 capeg tmaes 1 1 0 capeg capie p_int_ctrl($13) f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte p_int_flag($14) f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf p_tma_caph($24) tmawidh p_tma_capl($23) tmawidl capif fosc/2 figure 5-27 mode 0 timer a block diagram (capture m ode) after capture the carrier frequency, timer a should be configured as envelope detect mode for measuring the envelope of input signal from rmt pin. if the data received is a signal with carrier signa l (judged by use software method), the register ncdten ($17.5) shoul d be clear as 0. in order to detect the envelope, enter captu re mode at first, and get the carrier frequency (named f crr ). then load the value (0xfff-1.5* f crr ) to timer a counter registers (p_tma_envh & p_tma_envl, $24 & $23) and enter envelope detect mo de. if the first rising or falling-edge of carry wave arri ve, envelope interrupt occur (tmadtif=1) and envdet ($16.7) is s et to ?1?, and the value (0xfff-1.5* f crr ) is loaded to counter automatically, and counter starts to count. if next rising or fal ling-edge arrive, the value (0xfff-1.5* f crr ) will be reloaded into the counter, and envdet($16.7) does not change its status (still equal ?1?). however, if the next carry wave does not arrive on time (that?s over 1.5* f crr ), timer a overflow happens resulting in envelope interrupt occurring, and make envdet($16.7) changed to ?0?. so check envdet bit can know whether envelope exist or not. and if the data received is a signal without carrie r signal (judge by use software method), the register ncdten ($17.5) s hould be set as 1. the signal (without carrier signal) received delivered to envdet($16.7) directly. also user can check envdet bit to get the input signal with carrier signal.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 33 oct. 28, 2010 preliminary version: 0.1 timons($17.7)=0, 12-bit up count timer a envelope detect mode 12 bit up-counter fosc capture block regh (4 bits) regl (8 bits) data bus enb enb tmaoif m u x fosc/4 fosc/16 envelop detect envdet mode tmaoif & envdet mode mu x rmt pb3 p_rx_sen($11) tmacaps senses0 senses1 p_int_ctrl($13) f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte p_int_flag($14) f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf p_tma_ctrl($21) tmadut1 tmaclk0 tmaclk1 tmamod0 tmamod1 tmadut0 capeg tmaes 1 1 1 env_int tmaclk[1:0] p_tma_envh($24) tmaprvh p_tma_envl($23) tmaprvl ncdten ($17.5) fosc/2 figure 5-28 mode 0 timer a block diagram (envelope detect mode) figure 5-29 mode 0 timer a envelope detect flow
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 34 oct. 28, 2010 preliminary version: 0.1 figure 5-30 the waveform of mode 0 timer a envelope detect timer special configure register (p_tim_sel, $0017) bit 7 6 5 4 3 2 1 0 name timons irenb ncdten - - - - - access r/w r/w r/w - - - - - default 0 0 0 0 0 0 0 0 bit 7 timons: timer a/b up or down count select. 0, timer a 12-bit up count; timer b 12-bit up coun t. (c_timab_up) 1, timer a 8-bit down count; timer b 12-bit down count. (c_timab_dn) bit 6 irenb: pwm output function enable/disable. 0, pwm output function enable; (c_pwm_en) 1, pwm output function disable. (c_pwm_dis) bit 5 ncdten: with carrier or without carrier signal envelope detect select 0, with carrier signal; (c_envdt_ca) 1, without carrier signal. (c_ envdt_nca) bit [4:0] reserved mode 0 timer a control register (p_tma_ctrl, $0021) bit 7 6 5 4 3 2 1 0 name tmaes capeg tmaclk1 tmaclk0 tmadut1 tmadut0 tmamod1 tmamod0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 tmaes: timer a enable/disable control. 0, disable; (c_tmaes_dis) 1, enable. (c_tmaes_en) bit 6 capeg: timer a capture edge selection. 0, rising; (c_tmacap_rise) 1, falling. (c_tmacap_fall) bit [5:4] tmaclk[1:0]: timer a clock source select bits 00 = fosc (c_tmaclk_1) 01 = fosc/2 (c_tmaclk_2) 10 = fosc/4 (c_tmaclk_4) 11 = fosc/16 (c_tmaclk_16) bit [3:2] tmadut[1:0]: timer a pwm duty selection 00: 1/3 (c_tmadut_3) 01: 1/4 (c_tmadut_4) 10: 1/5 (c_tmadut_5) 11: 1/2 (c_tmadut_2) bit [1:0] tmamod[1:0]: timer a mode setting 00: pwm (c_tmamod_wtc) 01: pwm1 (enter the mode, pwm out always high) (c_tmamod_woc) 10: capture (c_tmamod_cap) 11: envelop detect (c_tmamod_ende) mode 0 timer a count low byte register (p_tma_cntl, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmacntl7 tmacntl6 tmacntl5 tmacntl4 tmacntl3 tmacntl2 tmacntl1 tmacntl0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmacntl [7 0]: timer a low byte 8-bit pre-value for the counte r. read: timer a count low byte value(r) write: timer a pre-load count low byte value (w)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 35 oct. 28, 2010 preliminary version: 0.1 mode 0 timer a pwm low byte period register (p_tma_ pwml, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmaprdl7 tmaprdl6 tmaprdl5 tmaprdl4 tmaprdl3 tmaprdl2 tmaprdl1 tmaprdl0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmaprdl [7 0]: timer a low byte 8-bit period value for the pwm . read: timer a count low byte value(r) write: pwm signal carrier signal pre-load period lo w byte value (w) mode 0 timer a capture low byte width register (p_t ma_capl, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmawidl7 tmawidl6 tmawidl5 tmawidl4 tmawidl3 tmawidl2 tmawidl1 tmawidl0 access r r r r r r r r default 0 0 0 0 0 0 0 0 bit [7:0] tmawidl [7 0]: timer a low byte 8-bit width value for the capt ure. read: capture mode received carrier signal period ( frequency) low byte value(r) mode 0 timer a envelope low byte pre-value register (p_tma_envl, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmaprvl7 tmaprvl6 tmaprvl5 tmaprvl4 tmaprvl3 tmaprvl2 tmaprvl1 tmaprvl0 access w w w w w w w w default 0 0 0 0 0 0 0 0 bit [7:0] tmaprvl [7 0]: timer a low byte 8-bit pre-value for the envelo pe detect. write: envelope detect mode received carrier signal pre-load period (frequency) low byte value (w) mode 0 timer a count high byte register (p_tma_cnth , $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmacnth3 tmacnth2 tmacnth1 tmacnth0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3:0] tmacnth [3 0]: timer a high byte 4-bit pre-value for the count er. read: timer a count high byte value (r) write: timer a pre-load count high byte value (w) mode 0 timer a pwm high byte period register (p_tma _pwmh, $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmaprdh3 tmaprdh2 tmaprdh1 tmaprdh0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3:0] tmaprdh [3 0]: timer a high byte 4-bit period value for the pw m. read: timer a count high byte value(r) write: pwm signal carrier signal pre-load period hi gh byte value (w)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 36 oct. 28, 2010 preliminary version: 0.1 mode 0 timer a capture high byte width register (p_ tma_caph, $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmawidh3 tmawidh2 tmawidh1 tmawidh0 access r r r r r r r r default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3:0] tmawidh [3 0]: timer a high byte 4-bit period value for the ca pture. read: timer a width high byte value (r) mode 0 timer a envelope high byte width register (p _tma_envh, $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmaprvh3 tmaprvh2 tmaprvh1 tmaprvh0 access w w w w w w w w default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3:0] tmaprvh [3 0]: timer a high byte 4-bit period value for the en velope detect. write: envelope detect mode received carrier signal pre-load period (frequency) high byte value (w) [example] 5-11 set timer a as pwm with carrier sign al mode. lda #c_timab_up + #c_pwm_en sta p_tim_sel ; set timer as up count and enable pwm output functio n lda #$fc ; before starting timer, set timer a counter initia l value first sta p_tma_pwml ; set low 8-bit pre-value lda #$0f sta p_tma_pwmh ;set high 4-bit pre-value lda #c_tmaes_en + #c_tmaclk _4 +#c_tmadut_3 + #c_t mamod_wtc sta p_tma_ctrl ;set clock source fosc/4, 1/3duty, pwm with carrier signal mode 5.9.4. pwm carrier signal algorithm the frequency of pwm carrier signal (f pwm ) generated by timer a depends on three factors. the initial value (v reg =12-bit preload preiod) is filled into high-byte (low-nibble) register (p_tma_pwmh [3:0]) and low-byte register (p_tma_pwml [7:0]) the duty of the carrier signal (dut = pwm duty). the frequency of timer a clock source (f timer ) v reg = p_tma_pwmh[4:0]+p_tma_pwml[7:0] dut = one of (1/3, 1/4, 1/5, 1/2), defined by p_tma _ctrl[3:2] if f timer = f osc /1 or f osc /2, defined by p_tma_ctrl[5:4] then v reg = 4097- f timer / f pwm * dut for example, if user needs to generate 38 khz 1/3 d uty pwm carrier frequency and timer clock source is 4mhz/1 (system clock is 4mhz). condition: f pwm = 38 khz, f timer =4mhz, dut=1/3 v reg = 4097 ? (4m/38k)*1/3 = 4062 =fdeh then the result fdeh can be written into the pwm hi gh/low register, and the 38 khz pwm signal is generated. v reg = p_tma_pwmh[4:0]+p_tma_pwml[7:0] dut = one of (1/3, 1/4, 1/5, 1/2), defined by p_tma _ctrl[3:2] if f timer = f osc /4, f osc /16 , defined by p_tma_ctrl[5:4] then v reg = 4096- f timer / f pwm * dut for example, if user need to generate 38 khz 1/3 du ty pwm carrier frequency, and system frequency is 4mhz. an d f osc /4 is selected as timer clock. condition: f pwm = 38 khz, f timer = 4mhz/4, dut=1/3 v reg = 4096 ? (1m/38k)*1/3 = 4087 =ff7h then the result ff7h can be written into the pwm hi gh/low register, and the 38 khz pwm signal is generated.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 37 oct. 28, 2010 preliminary version: 0.1 [example] 5-12 set timer a as pwm with carrier sign al mode and the carrier frequency is 38 khz with 1/ 3 duty (clock source=fosc/1). lda #c_timab_up + #c_pwm_en sta p_tim_sel ; set timer as up count and enable pwm output functio n lda #$de ; before starting timer, set timer a counter initia l value first sta p_tma_ pwml ; set low 8-bit pre-value lda #$0f sta p_tma_ pwmh ;set high 4-bit pre-value lda #c_tmaes_en + #c_tmaclk _1 +#c_tmadut_3 + #c_t mamod_wtc sta p_tma_ctrl ;set clock source fosc/1, 1/3duty, pwm with carrier signal mode [example] 5-13 set timer a as pwm with carrier sign al mode and the carrier frequency is 38 khz with 1/ 3 duty (clock source=fosc/4). lda #c_timab_up + #c_pwm_en sta p_tim_sel ;set timer as up count and enable pwm output funct ion lda #$f7 ; before starting timer, set timer a counter initia l value first sta p_tma_ pwml ; se t low 8-bit pre-value lda #$0f sta p_tma_ pwmh ;set high 4-bit pre-value lda #c_tmaes_en + #c_tmaclk _4 +#c_tmadut_3 + #c_t mamod_wtc sta p_tma_ctrl ;set clock source fosc/4, 1/3 duty, pwm with carrier signal mode 5.10. mode 0 timer b (12-bit up count timer) when timer a is selected as 12-bit up count timer v ia configuring the corresponding bit of register (p_tim_sel[7]), t imer b is selected as 12-bit up count timer too. timer b is special for envelope signal generation in ir controller applica tion. the 12-bit timer is an up counter with input clock sele ctable (fosc/1, fosc/4, fosc/64, tmacar) via configuring the contro l register p_tmb_ctrl [5:4] (tmbclk [1:0]). and the value of low-byte register (p_tmb_cntl) and high-byte (low-nibble) re gister (p_tmb_cnth) would be reloaded into the 12-bit up c ounter and an interrupt (tmboif) would be generated whenever a n overflow occurs. the interrupt frequency can be freely sele cted by selecting different clock source and configuring th e low-byte register and high-byte (low-nibble) register with d ifferent values. timer b module has the following features: readable and writable clock source selectable interrupt-on-overflow from #$fff to #$000
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 38 oct. 28, 2010 preliminary version: 0.1 figure 5-31 mode 0 timer b block diagram tmbclk[1:0] carry_en tmboif tmb_cnt * ffc * * * w_tmb_regh w_tmb_regl tmbes tmb_reg 000 0fc ffc * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * tmbclk[1:0] 00 xx ffd figure 5-32 the waveform of mode 0 timer b mode 0 timer b control register (p_tmb_ctrl, $0022) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmbes - tmbclk1 tmbclk0 - - - - access r/w - r/w r/w - - - - default 0 - 0 0 - - - - bit [7] tmbes : timer b enable/disable control selected bit. 0 = disable (c_tmbes_dis) 1 = enable (c_tmbes_en) bit [6] reserved
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 39 oct. 28, 2010 preliminary version: 0.1 bit [5:4] tmbclk[1 0] : timer b clock source selected bits 00 = fosc (c_tmbclk_1) 01 = fosc/4 (c_tmbclk_4) 10 = fosc/64 (c_tmbclk_64) 11 = tmacrr (c_tmbclk_tmacrr) bit [3:0] reserved mode 0 timer b low 8-bit data register (p_tmb_cntl, $0025) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmbcntl7 tmbcntl6 tmbcntl5 tmbcntl4 tmbcntl3 tmbcntl2 tmbcntl1 tmbcntl0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmbcntl [7 0]: timer b low byte 8-bit pre-value for the counte r. read: timer b count low byte value (r) write: timer b pre-load count low byte value (w) mode 0 timer b high 4-bit data register (p_tmb_cnth , $0026) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmbcnth3 tmbcnth2 tmbcnth1 tmbcnth0 access - - - - r/w r/w r/w r/w default - - - - 0 0 0 0 bit [7:4] reserved bit [3:0] tmbcnth [3 0]: timer b high byte 4-bit pre-value for the count er. read: timer b count high byte value (r) write: timer b pre-load count high byte value (w) [example] 5-14 set timer b selects timer a carrier signal as counter clock. lda #c_timab_up sta p_tim_sel ; set timer a/b as 12-bit up count timers lda #$fc ; before starting timer, set timer b counter initial value first sta p_tmb_cntl ; set low 8-bit pre-value lda #$0f sta p_tmb_cnth ; set high 4-bit pre-value lda #c_tmbes_en + #c_tmbclk_tmacrr sta p_tmb_ctrl ;set clock source for tma_carrier 5.11. mode 1 timer a (8-bit down count timer) when timer a is selected as 8-bit down count timer via configuring the corresponding bits of the control register ( p_tim_sel [7]), timer a is special for generating carrier signal in ir control application. timer a?s input clock is selectable ( fosc/1, fosc/2, fosc/4, fosc/16), which can be configured by contro l register p_tma_ctrl [5:4]. timer a provides with two pwm modes, and the pwm signal is sent to ir tx (rmt) pin. the dri ver current of these two kinds of pwm are programmable by configur ing tx pwm driving current control source register (p_pwm_ drv [3]). 8-bit down count timer a module has the following f eatures: readable and writable clock source selectable interrupt-on-overflow from #$00 to #$ff supports pwm with carrier signal mode supports pwm without carrier signal mode supports capture mode for learning function supports envelope detect mode for learning functio n
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 40 oct. 28, 2010 preliminary version: 0.1 figure 5-33 mode 1 timer a block diagram 5.11.1. mode 1 timer a pwm with carrier signal mode timer a can be configured as pwm mode for generatin g carrier signal. in pwm with carrier signal mode, the 8-bit timer is a down counter with input clock selectable (fosc/1, fosc/2 , fosc/4, fosc/16). when timer a is started, the value of 8- bit cycle width (frequency) set register would firstly be loaded in to the 8-bit counter and the value of 8-bit high pulse width (du ty) set register would be loaded into the compare unit. and then th e counter starts count down from the loaded value. pwm initi al output low, and if the counter value is same as the value in co mpare unit, the pwm would switch to high. if an overflow occurs, t he pwm switch to low once again, and the value of frequenc y register (p_tma_pwmf, $23) and duty register (p_tma_pwmd, $2 4) would be reloaded into the counter and the compare unit automatically and the counter starts count down aga in. so the carrier signal with frequency and duty programmable can be generated by this pwm mode via configuring these tw o registers. the carrier signal?s enabled or disabled bit can be controlled by two methods depended on which clock source is selec ted by timer b. if timer b is selected one of the first t hree clock source (fosc, fosc/4 or fosc/64) by p_tmb_ctrl [5:4] (tmbc lk [1:0]), timer a?s carrier signal on/ off is controlled by t imer a?s enabled/ disabled control bit (tmaes) directly. in addition , pwm output function also can be disabled by writing 1 to regis ter irenb($17.6).
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 41 oct. 28, 2010 preliminary version: 0.1 8 bit down-counter fosc regd (8 bits) regf (8 bits) data bus mu x fosc/4 fosc/16 tmaclk[1:0] pwm control block ir tx overflow p_tma_ctrl($21) tmaclk0 tmaclk1 tmamod0 tmamod1 capeg tmaes 1 0 0 p_int_ctrl($13) f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte p_int_flag($14) f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf tmaovf p_tma_pwmd($24) tmahwid p_tma_pwmf($23) tmapwid pwmdrv[0] ($11.0) compare timons($17.7)=1, 8-bit down count timer a pwm with carrier mode fosc/2 irenb ($17.6) figure 5-34 mode 1 timer a pwm mode diagram figure 5-35 mode 1 timer a normal pwm generation wi thout envelop
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 42 oct. 28, 2010 preliminary version: 0.1 w_tma_regd w_tma_regf tma_regf tmbclk[1:0] 00 00 or 01 or 10 00 04 tma_regd 00 01 tmaes tmaclk[1:0] tmacrr tmaoif tma_cnt tmamod[1:0] 01 * 04 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 04 01 01 01 01 01 01 01 01 01 * ir tx (rmt) tmapwm figure 5-36 the waveform of mode 1 timer a pwm with carrier signal mode (1/5 duty, on/off control by t maes) another method to generate envelope pwm signal is t hat timer a and timer b must be used together. timer a must ge nerate carry clock at first, which is same as normal pwm g eneration. then enable timer b and select timer a carrier sign al as its input clock. and timer b register must be written in the right data, which represents the carry number. when tmbovf hap pen, another value must be written into timer b register , which represents the no carry clock number. envelop with carrier is on or off only when timer b overflow events occur one by one. then, the envelop pwm signal will be generated at r mt port at last.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 43 oct. 28, 2010 preliminary version: 0.1 8 bit down-counter fosc regd (8 bits) regf (8 bits) data bus mu x fosc/4 fosc/16 tmaclk[1:0] pwm control block ir tx overflow p_tma_ctrl($21) 1 0 0 p_int_ctrl($13) p_int_flag($14) tmaovf p_tma_pwmd($24) p_tma_pwmf($23) pwmdrv[0] ($11.0) compare timons($17.7)=1, 8-bit down count timer a pwm with carrier mode fosc/2 irenb ($17.6) timons($17.7)=1, 12-bit down count timer b 12-bit down-counter fosc regh (4 bits) regl (8 bits) data bus overflow mux fosc/4 fosc/64 tmacrr tfr ck ckn q qn rn tmbes carry_en p_tmb_ctrl($22) p_int_ctrl($13) tmboif p_int_flag($14) 11 p_tmb_cnth($26) p_tmb_cntl($25) w_tmb_regh figure 5-37 envelope pwm generated by mode 1 timer a & mode 1 timer b diagram
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 44 oct. 28, 2010 preliminary version: 0.1 figure 5-38 the waveform of mode 1 timer a pwm with carrier signal mode (1/5 duty, on/off control by m ode 1timer b overflow events) 5.11.2. pwm without carrier signal mode pwm without carrier signal mode is used to generate envelop pwm signal without carrier signal. in this mode, i r tx (rmt) pin just output high or low, and is controlled by timer a?s enabled or disabled control bit or timer b?s overflow events i n turn. the same as pwm with carrier signal mode, the 8-bit tim er is a down counter with input clock selectable (fosc/1, fosc/2 , fosc/4, fosc/16). when timer a is started, the value of 8- bit pre-value register (p_tma_pwmf, $23) would firstly be loaded into the 8-bit counter and then the counter starts to count down from the loaded value. if an overflow occurs, the value of pre-value register would be reloaded into the counter automat ically and the counter starts to count down again. the internal c arrier signal is generated but does not be sent to ir tx pin. w_tma_regd w_tma_regf tma_regf tmbclk[1:0] ir tx (rmt) tmapwm 00 00 or 01 or 10 00 04 tma_regd 00 01 tmaes tmaclk[1:0] tmacrr tmaoif tma_cnt tmamod[1:0] 01 * 04 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 04 01 01 01 01 01 01 01 01 01 * figure 5-39 the waveform of mode 1 timer a pwm with out carrier signal mode (on/off control by tmaes)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 45 oct. 28, 2010 preliminary version: 0.1 figure 5-40 the waveform of mode 1 timer a pwm with out carrier signal mode (on/off control by mode 1 t imer b overflow events) 5.11.3. capture & envelope detect mode in ir learning function application, timer a should be configured as capture mode for measuring the frequency of inpu t signal from rx pin. in capture mode, the 8 bit timer is a down counter which counts from ffh with input clock selectable (fosc/1 , fosc/2, fosc/4, fosc/16). when rising or falling (selectab le via p_tma_ctrl) edge of rx is captured, the value of th e counter would be loaded into capture register (p_tma_capd, $24), at the same time, it generates an interrupt (capif) and th en the counter is set to ffh. when the timer overflows, the overf low interrupt (tmaoif) occurs. the input carrier signal cycle ti me is recorded in capture register (p_tma_capd). of course, if the time data that would to be record is bigger than the biggest data that this register can be loaded, the overflows of the timer a should be count inclusively.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 46 oct. 28, 2010 preliminary version: 0.1 8 bit down-counter p_int_ctrl($13) p_int_flag($14) timons($17.7)=1, 8-bit down count timer capture mode fosc capture block m u x fosc/4 fosc/16 & mu x rmt pb3 p_rx_sense($11) tmacaps * * senses0 senses1 f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf tmaclk0 tmaclk1 tmamod0 tmamod1 capeg tmaes 1 cap_int tmaclk[1:0] p_tma_ctrl($21) p_tma_capd($24) tmacwid ff tmaovf fosc/2 regd (8 bits) 1 0 figure 5-41 mode 1 timer a block diagram (capture m ode) when timer a is an 8-bit down count timer, the enve lope of input signal from rx(rmt) pin can be measured just only i n envelope detect mode. and users do not need get carrier fre quency value in capture mode firstly. the carrier frequency val ue also is captured into capture register (p_tma_envd, $24) in envelope detect mode. if the data received is a signal with carrier signa l (judged by use software method), the register ncdten ($17.5) shoul d be clear 0. in order to detect the envelope, firstly get the ca rrier frequency (named f crr ) from capture register (p_tma_envd, $24). then load the value (1.5* f crr ) to timer a counter register (p_tma_envf, $23). if the first rising or falling- edge of carry wave arrive, envelope interrupt occur (tmadtf=1) an d envdet ($16.7) is set to ?1?, and the value (1.5* f crr ) is loaded to counter automatically, and counter starts to count. if next rising or falling-edge arrive, the value (1.5* f crr ) will be reloaded into the counter, and envdet ($16.7) not changed its status (still equal ?1?). however, if the next carry wave does not arr ive on time (that?s over 1.5* f crr ), timer a overflow happens resulting in envelope interrupt occurring, and make envdet ($16. 7) changed to ?0?. so check envdet bit can know whether envelo pe exist or not. and if the data received is a signal without carrie r signal (judged by use software method), the register ncdten ($17.5 ) should be set 1. the signal (without carrier signal) receive d delivered to envdet ($16.7) directly. also user can check envdet bit to get the input signal with carrier signal.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 47 oct. 28, 2010 preliminary version: 0.1 tmacaps * * senses0 senses1 f1kie tmboie capie f2mie f32kie f4kie tmaoie tmadte f1kif tmboif capif f2mif f32kif f4kif tmaoif tmadtf tmadut1 tmaclk0 tmaclk1 tmamod0 tmamod1 tmadut0 capeg tmaes tmacwid tmapprv figure 5-42 mode 1 timer a block diagram (envelope detect mode) figure 5-43 mode 1timer a envelope detect flow
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 48 oct. 28, 2010 preliminary version: 0.1 figure 5-44 the waveform of mode 1 timer a envelope detect mode 1 timer a control register (p_tma_ctrl, $0021) bit 7 6 5 4 3 2 1 0 name tmaes capeg tmaclk1 tmaclk0 - - tmamod1 tmamod0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 tmaes: timer a enable/disable control. 0, disable; (c_tmaes_dis) 1, enable. (c_tmaes_en) bit 6 capeg: timer a capture edge selection. 0, rising; (c_tmacap_rise) 1, falling. (c_tmacap_fall) bit [5:4] tmaclk[1:0]: timer a clock source select bits 00 = fosc (c_tmaclk_1) 01 = fosc/2 (c_tmaclk_2) 10 = fosc/4 (c_tmaclk_4) 11 = fosc/16 (c_tmaclk_16) bit [3:2] reserved bit [1:0] tmamod[1:0]: timer a mode setting 00: pwm (c_tmamod_wtc) 01: pwm1 (enter the mode, pwm out always high) (c_tmamod_woc) 10: capture (c_tmamod_cap) 11: envelop detect (c_tmamod_ende) mode 1 timer a count register (p_tma_cntf, $23) (r/ w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmacnt7 tmacnt6 tmacnt5 tmacnt4 tmacnt3 tmacnt2 tmacnt1 tmacnt0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmacnt [7 0]: timer a 8-bit pre-value for the counter. read: timer a count value(r) write: timer a pre-load count value (w) mode 1 timer a pwm carrier signal period (frequency ) register for pwm mode(p_tma_pwmf, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmapwid7 tmapwid6 tmapwid5 tmapwid4 tmapwid3 tmapwid2 tmapwid1 tmapwid0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmapwid [7 0]: timer a carrier signal period(frequency) value for the pwm. read: timer a count value(r) write: timer a pre-load carrier signal period(frequ ency) value (w)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 49 oct. 28, 2010 preliminary version: 0.1 mode 1 timer a carrier signal period (frequency) wi dth pre-value register for envelope detect mode(p_t ma_envf, $23) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmapprv7 tmapprv6 tmapprv5 tmapprv4 tmapprvd3 tmapprv2 tmapprv1 tmapprv0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmapprv [7 0]: timer a 8-bit width pre-value period(frequency) for the carrier signal of envelope. write: pre-load period(frequency) width value for c arrier signal of envelope (w) mode 1 timer a pwm carrier signal high pulse (duty) width register for pwm mode (p_tma_pwmd, $24) (r/w ) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmahwid7 tmahwid6 tmahwid5 tmahwid4 tmahwid3 tmahwid2 tmahwid1 tmahwid0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmahwid [7 0]: timer a 8-bit high pulse (duty) value for the c arrier signal of pwm. read: timer a high pulse (duty) value (r) write: timer a pre-load carrier signal high pulse ( duty) value (w) mode 1 timer a received carrier signal period (freq uency) width register for capture mode(p_tma_capd, $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmacwid7 tmacwid6 tmacwid5 tmacwid4 tmacwid3 tmacwid2 tmacwid1 tmacwid0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmacwid [7 0]: timer a 8-bit width value period(frequency) for the carrier signal of capture. read: period(frequency) width value for carrier sig nal of capture (r) mode 1 timer a received carrier signal period (freq uency) width register for envelope detect mode (p_t ma_envd, $24) (r/w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmacwid7 tmacwid6 tmacwid5 tmacwid4 tmacwid3 tmacwid2 tmacwidh1 tmacwid0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmacwid [7 0]: timer a 8-bit width value period(frequency) for the carrier signal of envelope. read: period(frequency) width value for carrier sig nal of envelope (r) [example] 5-15 set timer a as pwm with carrier sign al mode. lda #c_timab_dn + #c_pwm_en sta p_tim_sel ; set timer as down count and enable pwm output funct ion lda #$0f ; before starting timer, set timer a counter initia l value first sta p_tma_pwmf ; set period pre-value lda #$08 sta p_tma_pwmd ;set high pulse pre-value (duty=($ 08+1)/($0f+1)=9/16) lda #c_tmaes_en + #c_tmaclk _4 + #c_tmamod_wtc sta p_tma_ctrl ;set clock source fosc/4, pwm with carrier signal m ode
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 50 oct. 28, 2010 preliminary version: 0.1 5.11.4. pwm carrier signal algorithm the frequency of pwm carrier signal (f pwm ) generated by timer a depends on three factors. the initial value (v regf =8-bit preload preiod) is filled into register (p_tma_pwmf [7:0]). the initial value (v regd =8-bit preload high pulse value) is filled into register (p_tma_pwmd [7:0]). the frequency of timer a clock source (f timer ) v regf = p_tma_pwmf[7:0] v regd = p_tma_pwmd[7:0] if f timer = f osc /1 or f osc /2 or f osc /4 or f osc /16, defined by p_tma_ctrl[5:4] then v regf = f timer / f pwm -1 v regd = (f timer / f pwm ) * dut for example, if user needs to generate 38 khz 2/5 d uty pwm carrier frequency and timer clock source is 4mhz/1 (system clock is 4mhz). condition: f pwm = 38 khz, f timer =4mhz, dut=2/5 v regf = f timer / f pwm -1= 104 =68h v regd = (f timer / f pwm ) * dut = 42 =2ah then the result 68h and 2ah can be written into the pwm period register and high pulse register separately, and th e 38 khz pwm signal is generated. [example] 5-16 set timer a as pwm with carrier sign al mode and the carrier frequency is 38 khz with 2/ 5 duty (clock source=fosc/1). lda #c_timab_dn + #c_pwm_en sta p_tim_sel ; set timer as down count and enable pwm output funct ion lda #$68 ; before starting timer, set timer a counter initia l value first sta p_tma_ pwmf ; set low period pre-value lda #$2a sta p_tma_ pwmd ;set high pulse pre-value(2/5 dut y) lda #c_tmaes_en + #c_tmaclk _1 + #c_tmamod_wtc sta p_tma_ctrl ;set clock source fosc/1, pwm with carrier signal m ode 5.12. mode 1 timer b timer b is special for envelope signal generation i n ir controller application. the 12-bit timer is a down counter wi th input clock selectable (fosc/1, fosc/4, fosc/64, tmacar) via co nfiguring the control register p_tmb_ctrl [5:4] (tmbclk [1:0]). and the value of low-byte register (p_tmb_cntl) and high-by te (low-nibble) register (p_tmb_cnth) would be reloade d into the 12-bit up counter and an interrupt (tmboif) would b e generated whenever an overflow occurs. the interrupt frequen cy can be freely selected by selecting different clock source and configuring the low-byte register and high-byte (low-nibble) re gister with different values. timer b module has the following features: readable and writable clock source selectable interrupt-on-overflow from #$000 to #$fff
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 51 oct. 28, 2010 preliminary version: 0.1 12 bit down-counter fosc regh (4 bits) regl (8 bits) data bus overflow mux fosc/4 fosc/64 carry_clk w26 tfr ck ckn q qn rn tmbes carry_en p_tmb_ctrl($22) tmbclk0 tmbclk1 tmbes p_int_ctrl($13) f1kie tmboie f2mie f32kie f4kie tmaoie tmbovf_int p_int_flag($14) f1kif tmboif f2mif f32kif f4kif tmaoif tmb_cntl($25) tmbcntl tmb_cnth($26) tmbcnth 11 timons($17.7)=1, 12-bit down count timer b figure 5-45 mode 1 timer b block diagram figure 5-46 the waveform of mode 1 timer b mode 1 timer b control register (p_tmb_ctrl, $0022) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmbes - tmbclk1 tmbclk0 - - - - access r/w - r/w r/w - - - - default 0 - 0 0 - - - - bit [7] tmbes : timer b enable/disable control selected bit. 0 = disable (c_tmbes_dis) 1 = enable (c_tmbes_en)
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 52 oct. 28, 2010 preliminary version: 0.1 bit [6] reserved bit [5:4] tmbclk[1 0] : timer b clock source selected bits 00 = fosc (c_tmbclk_1) 01 = fosc/4 (c_tmbclk_4) 10 = fosc/64 (c_tmbclk_64) 11 = tmacrr (c_tmbclk_tmacrr) bit [3:0] reserved mode 1 timer b low 8-bit data register (p_tmb_cntl, $0025) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name tmbcntl7 tmbcntl6 tmbcntl5 tmbcntl4 tmbcntl3 tmbcntl2 tmbcntl1 tmbcntl0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] tmbcntl [7 0]: timer b low byte 8-bit pre-value for the counte r. read: timer b count low byte value (r) write: timer b pre-load count low byte value (w) mode 1 timer b high 4-bit data register (p_tmb_cnth , $0026) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - tmbcnth3 tmbcnth2 tmbcnth1 tmbcnth0 access - - - - r/w r/w r/w r/w default - - - - 0 0 0 0 bit [7:4] reserved bit [3:0] tmbcnth [3 0]: timer b high byte 4-bit pre-value for the count er. read: timer b count high byte value (r) write: timer b pre-load count high byte value (w) [example] 5-17 set timer b selects timer a carrier signal as counter clock. lda #c_timab_dn + #c_pwm_en sta p_tim_sel ; set timer as down count and enable pwm output funct ion lda #$fc ; before starting timer, set timer b counter initial value first sta p_tmb_cntl ; set low 8-bit pre-value lda #$0f sta p_tmb_cnth ; set high 4-bit pre-value lda #c_tmbes_en + #c_tmbclk_tmacrr sta p_tmb_ctrl ;set clock source for tma_carrier
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 53 oct. 28, 2010 preliminary version: 0.1 5.13. ir transfer/receiver module rxtx is an analog block of GPM6P1009A which can dri ve ir led by tx, and can translate the ir led sense current t o digital signal. rx_sen register can control this block. user can a djust pwm output driving capability by setting value of pwmdr v [0], and adjust the sensitivity of rx block by sense [1:0]. meanwhile, by setting the value of tacaps to ?1?, capture signal can be input from pb3 pin. tmapwm signal (as showed in figure 5-47) controls l ed driver mos. when in pwm mode, timer a can generate pwm si gnal, and the pwm duty, frequency, on/off switch can be a ccuracy controlled by timer a. the envelope pwm signal can be generated by timer a and timer b. and it has been illustrated in timer instruction. rx block translates sense curre nt to digital signal rxout, and rxout is sent to timer a block, w hich can get the carrier frequency in capture mode. rxout rxen rxvos[1:0] pwmdrv[0] tx to battery ir led rmt rx tmapwm figure 5-47 rxtx module diagram timer a pwm drive register (p_pwm_drv, $11) (w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - pwmdrvs0 - - - access w w w w w w w w default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3] pwmdrvs[0] : pwm driving current selected bits. 0 = pwm 1/2 driving current (c_pwmdrv_1) 1 = pwm 2/2 driving current (c_pwmdrv_2) bit [2:0] please refer to p_rx_sen register. timer a sense control register (p_rx_sen, $11) (w) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - tmacaps senses1 senses0 access w w w w w w w w default 0 0 0 0 0 0 0 0 bit [7:4] reserved bit [3] please refer to p_pwm_drv register.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 54 oct. 28, 2010 preliminary version: 0.1 bit [2] tmacaps: timer a capture input selected bit. 0 = rmt pad (c_rx_cap) 1 = pb3 (c_rx_pb3) bit [1:0] senses[1:0]: rx sense selected bits. 00 01 10 11 sensitivity max min 00 = rx sense level 1 (c_rx_sense_1) sense current >=2ua 01 = rx sense level 2 (c_rx_sense_2) sense current >=5ua 10 = rx sense level 3 (c_rx_sense_3) sense current >=8ua 11 = rx sense level 4 (c_rx_sense_4) sense current >=11ua 5.14. alphabetical list of instruction set no. mnemonic op code byte no cycle no operation flag nv-bdizc 1. adc #dd 69 2 2 2. adc aa 65 2 3 3. adc aa, x 75 2 4 4. adc aaaa 6d 3 4 5. adc aaaa,x 7d 3 4(a) 6. adc aaaa,y 79 3 4(a) 7. adc (aa,x) 61 2 6 8. adc (aa), y 71 2 5(a) add to accumulator with carry. a ? (a) + (m) + c if d-flag set to 1, the adc performs decimal operat ion. nv--d-zc 9. and #dd 29 2 2 10. and aa 25 2 3 11. and aa, x 35 2 4 12. and aaaa 2d 3 4 13. and aaaa,x 3d 3 4(a) 14. and aaaa,y 39 3 4(a) 15. and (aa,x) 21 2 6 16. and (aa), y 31 2 5(a) and memory data with accumulator. a ? (a) ^ (m) n-----z- 17. asl a 0a 1 2 18. asl aa 06 2 5 19. asl aa,x 16 2 6 20. asl aaaa 0e 3 6 21. asl aaaa,x 1e 3 6(a) arithmetic shift left n-----zc 22. bcc aa 90 2 2(c) branch if carry bit clear if (c) = 0, then pc ? (pc) + ?? -------- 23. bcs aa b0 2 2(c) branch if carry bit set if (c) = 1, then pc ? (pc) + ?? -------- 24. beq aa f0 2 2(c) branch if equal if (z) = 1, then pc ? (pc) + ?? -------- 25. bit aa 24 2 3 26. bit aaaa 2c 3 4 test bit in memory with accumulator z ? (a) ^ (m), n ? (m 7 ), v ? (m 6 ) nv----z- 0 3 2 1 4 5 6 7 c 0
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 55 oct. 28, 2010 preliminary version: 0.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 27. bmi aa 30 2 2(c) branch if minus if (n) = 1, then pc ? (pc) + ?? -------- 28. bne aa d0 2 2(c) branch if not equal if (z) = 0, then pc ? (pc) + ?? -------- 29. bpl aa 10 2 2(c) branch if plus if (n) = 0, then pc ? (pc) + ?? -------- 30. brk 00 1 7 software interrupt if (b) = 1, then pc ? (pc) + 1 ---b-i-- 31. bvc aa 50 2 2(c) branch if overflow bit clear if (v) = 0, then pc ? (pc) + ?? -------- 32. bvs aa 70 2 2(c) branch if overflow bit set if (v) = 1, then pc ? (pc) + ?? -------- 33. clc 18 1 2 clear c-flag U c ? ?0? -------0 34. cld d8 1 2 clear d-flag U d ? ?0? ----0--- 35. cli 58 1 2 clear i-flag: i ? ?0? -----0-- 36. clv b8 1 2 clear v-flag: v ? ?0? -0------ 37. cmp #dd c9 2 2 38. cmp aa c5 2 3 39. cmp aa, x d5 2 4 40. cmp aaaa cd 3 4 41. cmp aaaa,x dd 3 4(a) 42. cmp aaaa,y d9 3 4(a) 43. cmp (aa,x) c1 2 6 44. cmp (aa), y d1 2 5(a) compare memory data with accumulator, (a) ? (m) n-----zc 45. cpx #dd e0 2 2 46. cpx aa e4 2 3 47. cpx aaaa ec 3 4 compare memory data with x-register, (x) ? (m) n-----zc 48. cpy #dd c0 2 2 49. cpy aa c4 2 3 50. cpy aaaa cc 3 4 compare memory data with y-register, (y) ? (m) n-----zc 51. dec aa c6 2 5 52. dec aa, x d6 2 6 53. dec aaaa ce 3 6 54. dec aaaa,x de 3 7 55. dex ca 1 2 56. dey 88 1 2 decrement m ? (m) - 1 n-----z- 57. eor #dd 49 2 2 58. eor aa 45 2 3 59. eor aa, x 55 2 4 60. eor aaaa 4d 3 4 61. eor aaaa,x 5d 3 4(a) 62. eor aaaa,y 59 3 4(a) 63. eor (aa,x) 41 2 6 64. eor (aa), y 51 2 5(a) exclusive or a ? (a) (m) n-----z-
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 56 oct. 28, 2010 preliminary version: 0.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 65. inc aa e6 2 5 66. inc aa, x f6 2 6 67. inc aaaa ee 3 6 68. inc aaaa,x fe 3 7 increment m ? (m) + 1 n-----z- 69. inx e8 1 2 x ? x + 1 n-----z- 70. iny c8 1 2 y ? y + 1 n-----z- 71. jmp aaaa 4c 3 3 72. jmp (aaaa) 6c 3 6 unconditional jump pc ? jump address -------- 73. jsr aaaa 20 3 6 jump to subroutine (sp) ? (pc h ), sp ? sp ? 1, (sp) ? (pc l ), sp ? sp ? 1, pc ? aaaa -------- 74. lda #dd a9 2 2 75. lda aa a5 2 3 76. lda aa, x b5 2 4 77. lda aaaa ad 3 4 78. lda aaaa,x bd 3 4(a) 79. lda aaaa,y b9 3 4(a) 80. lda (aa,x) a1 2 6 81. lda (aa), y b1 2 5(a) load accumulator a ? (m) n-----z- 82. ldx #dd a2 2 2 83. ldx aa a6 2 3 84. ldx aa, y b6 2 4 85. ldx aaaa ae 3 4 86. ldx aaaa,y be 3 4(a) load x-register x ? (m) n-----z- 87. ldy #dd a0 2 2 88. ldy aa a4 2 3 89. ldy aa, x b4 2 4 90. ldy aaaa ac 3 4 91. ldy aaaa,x bc 3 4(a) load y-register y ? (m) n-----z- 92. lsr a 4a 1 2 93. lsr aa 46 2 5 94. lsr aa, x 56 2 6 95. lsr aaaa 4e 3 6 96. lsr aaaa,x 5e 3 6(a) logical shift right n-----zc 97. nop ea 1 2 no operation -------- 98. ora #dd 09 2 2 99. ora aa 05 2 3 100. ora aa, x 15 2 4 101. ora aaaa 0d 3 4 102. ora aaaa,x 1d 3 4(a) 103. ora aaaa,y 19 3 4(a) 104. ora (aa,x) 01 2 6 105. ora (aa), y 11 2 5(a) logical or a ? (a) v (m) n-----z- 106. pha 48 1 3 (sp) ? a, sp ? sp - 1 -------- 0 3 2 1 4 5 6 7 c 0
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 57 oct. 28, 2010 preliminary version: 0.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 107. php 08 1 3 (sp) ? p status, sp ? sp -1 108. pla 68 1 4 sp ? sp +1, a ? (sp) -------- 109. plp 28 1 4 sp ? sp +1, p status ? (sp) restored 110. rol a 2a 1 2 111. rol aa 26 2 5 112. rol aa, x 36 2 6 113. rol aaaa 2e 3 6 114. rol aaaa,x 3e 3 6(a) rotate left through carry n-----zc 115. ror a 6a 1 2 116. ror aa 66 2 5 117. ror aa, x 76 2 6 118. ror aaaa 6e 3 6 119. ror aaaa,x 7e 3 6(a) rotate right through carry n-----zc 120. rti 40 1 6 return from interrupt sp ? sp + 1, p status ? (sp), sp ? sp + 1, pc l ? (sp), sp ? sp +1, pc h ? (sp) restored 121. rts 60 1 6 return from subroutine sp ? sp + 1, pc l ? (sp), sp ? sp +1, pc h ? (sp) -------- 122. sbc #dd e9 2 2 123. sbc aa e5 2 3 124. sbc aa, x f5 2 4 125. sbc aaaa ed 3 4 126. sbc aaaa,x fd 3 4(a) 127. sbc aaaa,y f9 3 4(a) 128. sbc (aa,x) e1 2 6 129. sbc (aa), y f1 2 5(a) subtract with carry a ? (a) ? (m) - ~(c) nv----zc 130. sec 38 1 2 set c-flag: c ? ?1? -------1 131. sed f8 1 2 set d-flag: d ? ?1? ----1--- 132. sei 78 1 2 set i-flag: i ? ?1? -----1-- 133. sta aa 85 2 3 134. sta aa, x 95 2 4 135. sta aaaa 8d 3 4 136. sta aaaa,x 9d 3 5 137. sta aaaa,y 99 3 5 138. sta (aa,x) 81 2 6 139. sta (aa), y 91 2 6 store accumulator in memory (m) ? a -------- 140. stx aa 86 2 3 141. stx aa, y 96 2 4 142. stx aaaa 8e 3 4 store x-register in memory (m) ? x -------- 143. sty aa 84 2 3 144. sty aa, x 94 2 4 145. sty aaaa 8c 3 4 store y-register in memory (m) ? y -------- 146. tax aa 1 2 transfer accumulator to x-register: x ? a n-----z- 0 3 2 1 4 5 6 7 c
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 58 oct. 28, 2010 preliminary version: 0.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 147. tay a8 1 2 transfer accumulator to y-register: y ? a n-----z- 148. tsx ba 1 2 transfer sp to x-register: x ? sp n-----z- 149. txa 8a 1 2 transfer x-register to accumulator: a ? x n-----z- 150. txs 9a 1 2 transfer x-register to sp: sp ? x n-----z- 151. tya 98 1 2 transfer y-register to accumulator: a ? y n-----z- notes: 1. cycle (a): cycle+1 when cross a boundary. 2. cycle(c): cycle+1 if the branch condition is tru e; cycle+2 if the branch condition is true and cros s a boundary.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 59 oct. 28, 2010 preliminary version: 0.1 6. electrical characteristics 6.1. absolute maximum ratings characteristics symbol ratings dc supply voltage v + < 5.0v input voltage range v in -0.5v to v + + 0.5v operating temperature t a 0 to + 70 storage temperature t sto -50 to +150 average pwm max driving current i rmt 150ma vdd total max current i vddm 100ma vss total max current i vssm 120ma note: stresses beyond those given in the absolute maximum rating table may cause operational errors or damag e to the device. for normal operational conditions see ac/dc electrical characteristics. 6.2. ac characteristics (t a = 25 ) limit characteristics min. typ. max. unit test condition osc accuracy @ freq=4mhz osc variation -3.0 1.5 3.0 % vdd = 2.0v - 3.6v, t a =25c 6.3. dc characteristics (vdd = 3.0v, t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage1 vdd 2.0 - 3.6 v f cpu = 4.0mhz, for 2-battery operating voltage2 vdd 2.4 - 3.6 v f cpu = 8.0mhz, for 2-battery operating current i op - 4.0 8.0 ma f cpu = 8.0mhz @ 3.6v, no load m-type key standby current i mstby - - 1.0 ua vdd = 3.6v t-type key standby current i tstby - - 2.0 ua vdd = 3.6v, key loading 50pf input high level v ih 0.7vdd - - v vdd = 3.0v input low level v il - - 0.3vdd v vdd = 3.0v output high level pb, pc, pd v oh 0.8vdd - - v vdd = 3.0v i oh = -6ma output low level pb, pc, pd v ol - - 0.2vdd v vdd = 3.0v i ol = 16ma pull high input pull high resistor pa, pb, pc, pd r h 30 50 70 kohm vdd = 3.0v pull low input pull low resistor pa, pb, pc, pd r l 30 50 70 kohm vdd = 3.0v max pwm driving current i pwm 200 - - ma vdd = 3.0v,v rmt =3.0v pwmdrv0=1 1.7 1.85 2.0 v lvrvsel=0 lvr active voltage (by option) v lvr 2.1 2.25 2.4 v lvrvsel=1
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 60 oct. 28, 2010 preliminary version: 0.1 internal 4mhz oscillator rc type temperature charac teristic. power voltage (vdd) = 3v. typical temperature = 25 c. typical internal oscillator rc type frequency = 4mh z. testing temperature range = 0 c ~ 70 c osc freqency vs temperature 3.980 3.985 3.990 3.995 4.000 4.005 4.010 0 10 20 30 40 50 60 70 f r e q u e n c y ( k h z ) typ.vdd=3v typ.vdd=3v typ.vdd=3v typ.vdd=3v temperature( 0 c) internal 4mhz oscillator rc type power voltage chara cteristic. temperature = 25 c. typical power voltage (vdd) = 3v. typical internal oscillator rc type frequency = 4mh z. testing power voltage range (vdd) = 1.8v~3.6v.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 61 oct. 28, 2010 preliminary version: 0.1 osc freqency vs voltage 4.000 4.000 4.001 4.001 4.002 4.002 4.003 4.003 4.004 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 voltage(v) f r e q u e n c y ( m h z ) typ.25 typ.25 typ.25 typ.25 0 00 0 c cc c
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 62 oct. 28, 2010 preliminary version: 0.1 7. application circuits 7.1. GPM6P1009A application circuits pb0 pb1 pb2 pb3 pb4 pb5 pd0 pd1 pd2 pd3 pd4 pd5 m-type keyboard vss vref vdd rmt GPM6P1009A
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 63 oct. 28, 2010 preliminary version: 0.1 7.2. pcb layout guideline to avoid the unexpected noises to end up with abnor mal cpu operations, the following cares must be exe rcised while doing the pcb layout: 1. forbidden insert jump 0ohm resistor in the conne ct line between vss pin and power source, this line should be as short as possible, and its width keep wider than 3mm is better. 2. the gnd line of all these voltage stabilize inte ntion capacitors should be pull from power source s eparately divided from chip gnd line. 3. c1 placed between vref and vss must be as closed as possible to ic itself, it is necessary for all GPM6P1009A application circuits for power stabilization and power down data protect ion. 4. c2 must be as closed as possible to ic itself to o, it is necessary for body GPM6P1009A. 5. c3 only is placed in some special application fo r ir led power stabilization, its gnd must be as cl osed as possible to power source gnd. 6. the power and gnd connect lines between these de vice should be short and wide as possible, the widt h keep more than 1mm is better.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 64 oct. 28, 2010 preliminary version: 0.1 8. disclaimer the information appearing in this publication is be lieved to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indemnificat ion provisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutory implied or by description regar ding the information in this publication or regarding the freedom of the describ ed chip(s) from patent infringement. furthermore, generalplus makes no warranty of merchantability or fitness for any purp ose. generalplus reserves the right to halt produc tion or alter the specifications and prices at any time without n otice. accordingly, the reader is cautioned to ver ify that the data sheets and other information in this publication are current before placing orders. products described herein are inte nded for use in normal commercial applications. applications involving unusual envir onmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by generalplus for such appl ications. please note that application circuits illustrated in this document a re for reference purposes only.
p p r r e e l l i i m m i i n n a a r r y y GPM6P1009A ? generalplus technology inc. proprietary & confidential 65 oct. 28, 2010 preliminary version: 0.1 9. revision history date revision # description page oct. 29, 2010 0.1 original 65

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