cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 1/7 BCR1002N3 c y s t ek product s pecification pnpn epitaxial planar scr BCR1002N3 descriptions the BCR1002N3 is designed for high volume consumer a pplications such as temperature, light, and speed control; process and remote control, and warning systems where reliability of operation is important. features ? practical level triggering and holding characteristics ? on state current rating of 0.2a rms ? sensitive gate allows triggering by microcontrollers and other logic circuits ? pb-free package symbol outline ordering information device package shipping BCR1002N3-0-t1-g sot-23 (pb-free lead plating an d halogen-free package) 3000 pcs / tape & reel BCR1002N3 sot-23 a g gate a anode k cathode g k environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pc s / tape & reel, 7? reel product rank, zero for no rank products product name http://
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 2/7 BCR1002N3 c y s t ek product s pecification absolute maximum ratings (t j =25 c) parameter symbol limits unit peak repetitive off-state voltage @t j =-40 to 125 , r gk =1k v drm 140 v on-state current @t c =80 i t(rms) 350 ma average on-state current @ t c =80 i t(av) 220 ma reverse peak gate voltage @t a =25 , pulse width 1 s v grm 8 v forward peak gate current @t a =25 , pulse width 1 s i gm 500 ma forward average gate power @ t a =25 , t=8.3ms p g(av) 100 mw thermal resistance, junction to ambient r ja 556 c/w thermal resistance, junction to case r jc 208 c/w junction temperature tj -40~+125 c storage temperature tstg -40~+150 c note : stress exceeding maximum ratings may damage the de vice. maximum ratings are st ress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. v drm can b e ap p lied o n a co n tinuo us b a sis. ratings app l y fo r zero o r n e g a tiv e gate v o ltag e ; howev er , p o s itive g a te vol t a ge s h al l n o t be appl i e d c onc u rre nt wi t h negat i v e p o t e nt i a l on t h e a n o d e . b l oc ki n g v o l t a ge shal l not be t e st ed wi t h a constant current source such that the voltage ratings of the device are exceeded. characteristics (ta=25 c) symbol min. typ. max. unit test conditions i drm - - 100 a v d =140v, r gk =1k , t c =125 i drm - - 10 a v d =140v, r gk =1k , t c =25 *v tm - - 1.5 v i tm =200ma i gt - - 100 a v d =7v, r l =100 i h - - 5 ma v d =7v, r gk =1k i l - - 6 ma v d =7v, i g =200 a v gt - - 0.8 v v d =7v, r l =100 dv/dt 25 - - v/ s v d =35v, r gk =1k di/dt 30 - - a/ s i g =10ma, di g /dt=100ma/ s, p w =10 s *pulse test: pulse width 300 s, duty cycle 2%
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 3/7 BCR1002N3 c y s t ek product s pecification recommended soldering footprint
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 4/7 BCR1002N3 c y s t ek product s pecification typical characteristics g a t e t ri gge r curre nt vs j unc t i on t e m pe ra t ure 0 10 20 30 40 50 60 70 -5 0 - 25 0 2 5 5 0 7 5 1 0 0 12 5 j u n c t i o n t e m p e r a t u re ---t j ( ) g a t e t ri gg e r c u rre n t ---i gt ( a) g a t e t ri gge r v o l t a g e vs j u n c t i on t e m p e r a t ure 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1 - 5 0 - 2 50 2 55 07 5 1 0 0 1 2 5 j u n c t i o n t e mp e ra t ure ---t j ( c ) g a t e t ri g g e r v o l t a g e --- v gt (v ) h o ld in g c u r r en t v s j u n c ti o n t em p e r a tu r e 0.1 1 10 - 50 - 25 0 2 5 50 75 1 00 1 25 j u n c t i o n t e mpe ra t u re ---t j ( c ) h o l d i n g c u rre n t ---i h (ma ) l a t c hi ng curre n t vs j unc t i o n t e m pe ra t ure 10 10 0 10 00 - 50 - 25 0 25 50 75 10 0 125 j u n c t i o n t e mpe r a t u r e ---t j ( c ) l a t c hi ng c ur r e n t - - - i l ( a) o n - s t at e c h ar act er is tic s 10 10 0 10 00 00 . 4 0 . 8 1 . 2 1 . 6 2 i ns t a nt a ne ou s o n- s t a t e v ol t a ge - - - v t (v ) i n s t an t an e o u s o n - s t at e c u r r en t - - - i t (m a) t j =-40c t j =25c t j =125c
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 5/7 BCR1002N3 c y s t ek product s pecification reel dimension carrier tape dimension
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 6/7 BCR1002N3 c y s t ek product s pecification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) 183 c 60-150 seconds 217 c 60-150 seconds ? time (t l ) peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cys t ech electronics corp. s pec. no. : c700 n3 issued date : 20 08.02.25 revised date :20 14.01.24 page no. : 7/7 BCR1002N3 c y s t ek product s pecification sot-23 dimension h j k d a l g v c b 3 2 1 s style: pin 1.cathode 2.gate 3.anode marking: date code device code 3-lead sot-23 plastic surface mounted package cystek package code: n3 te cr xx *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0034 0.0070 0.085 0.177 b 0.0472 0.0630 1.20 1.60 k 0.0128 0.0266 0.32 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1083 2.10 2.75 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0005 0.0040 0.013 0.10 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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