CXD8947Q ( 1/3 )
ill08 c-mos address bus sw -top view- ********** 1 10 15 20 25 75 70 65 60 55 100 95 90 85 80 30 35 40 45 50 5 gnd v dd (+5v) gnd v dd (+5v) gnd v dd (+5v) gnd v dd (+5v) pin
no. 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
i
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i
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i
i
i
i
? ? ? i
i
i
i
i
i
i
i
i i/o signal ck1
ck1d
hin6
hin5
hin4
hin3
hin2
hin1
hin0
mod3
mod2
mod1
mod0
nc
gnd
v dd
v9
v8
v7
v6
v5
v4
v3
v2
v1
pin
no. 26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 i/o i
i
i
i
i
o
o
o
o
o
o
o
o
? ? o
o
o
o
o
o
o
o
o
o signal v0
vm1
vm2
vdly
test
bce
bwe
b0
b1
b2
b3
b4
b5
gnd
v dd
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
pin
no. 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75 76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 pin
no. i/o o
i
i
i
i
i
i
i
i
i
i
o
i
i
i
? ? i
i
i
i
i
i
i
i signal b16
vd
pshd
floe
fldch
fldmask
rbank0
rbank1
rbank2
rbank3
cstop
cen
cctl
mul0
mul1
gnd
v dd
mul2
mul3
mul4
mul5
mul6
mul7
mul8
mul9
i/o i
i
i
i
o
o
o
o
o
o
o
o
o
o
? ? o
o
o
o
o
o
o
o
o (v dd =+5v) signal wbank0
wbank1
wbank2
wbank3
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
gnd
v dd
a6
a5
a4
a3
a2
a1
a0
awe
ace
CXD8947Q(2/3)
64
65
68
69
70
71
72
73
74
75
57
58
59
60
17
18
19
20
21
22
23
24
25
26
27
28 76
77
78
79
63
1
2
61
30
55
56
54
53
52
29 3
4
5
6
7
8
9
10
11
12
13
80
81
82
83
84
85
86
87
88
89
92
93
94
95
96
97
98 33
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
51 100
99
31
32
62 hin6
hin5
hin4
hin3
hin2
hin1
hin0 mod3
mod2
mod1
mod0 mul0
mul1
mul2
mul3
mul4
mul5
mul6
mul7
mul8
mul9 v9
v8
v7
v6
v5
v4
v3
v2
v1
v0 vm1
vm2 wbank0
wbank1
wbank2
wbank3 cctl
ck1
ck1d
cstop
test
fldch
fldmask
floe
pshd
vd
vdly a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
ace
awe
bce
bwe
cen rbank0
rbank1
rbank2
rbank3
CXD8947Q (3/3) hin6~0 mod3~0 wbank3~0 7 4 4 4 10 11 1 11 1 4 co 7 1 ci 1 4 1 1 1 mul9~0 v9~0
vm1 vm2 vdly rbank3~0 vd pshd cstop ck1d ck1 1 1 clock buffer rst rst pswe fldch floe 1 1 1 1 1 (we) (ce) 1 rst 1 en 17bit
counter cen 1 17 16 17 17 1 add17 17 1 2 2 bus b16~0 bus bwe, bce 9 counter 1 1 d3
d2
d1
d0 ld l en(sync) (sync) rst 1 0 fldmask 7 17 10 10 1 ci 17 1 0 we oe 2 1 0 add17 17 2 bus a16~0 bus awe, ace 0 3-9 10-13 64,65,68
68-75 76-79 17-26 27,28 29 57-60 52 53 61 2 1 80-89,
92-98 33-38,
41-51 99,100 31,32
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