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1. general description the lpc11e6x are an arm cortex -m0+ based, low-cost 32-bit mcu family operating at cpu frequencies of up to 50 mhz. the lpc11e6x support up to 256 kb of flash memory, a 4 kb eeprom, and 36 kb of sram. the arm cortex-m0+ is an easy-to-use, ener gy-efficient core using a two-stage pipeline and fast single-cycle i/o access. the peripheral complement of the lpc11e6x includes a dma controller, a crc engine, two i 2 c-bus interfaces, up to five usarts, tw o ssp interfaces, pwm/timer subsystem with six configurable multi- purpose timers, a real-time clock, one 12-bit adc, temperature sensor, function-configurable i/o ports, and up to 80 general-purpose i/o pins. for additional documentation related to the lpc11e6x parts, see section 18 ? references ? . 2. features and benefits ? system: ? arm cortex-m0+ processor (version r0p1), running at frequencies of up to 50 mhz with single-cycle multiplier and fast single-cycle i/o port. ? arm cortex-m0+ built-in nested vectored interrupt controller (nvic). ? ahb multilayer matrix. ? system tick timer. ? serial wire debug (swd) and jtag boundary scan modes supported. ? micro trace buffer (mtb) supported. ? memory: ? up to 256 kb on-chip flash programming memory with page erase. ? up to 32 kb main sram. ? up to two additional sram blocks of 2 kb each. ? up to 4 kb eeprom. ? rom api support: ? boot loader. ? usart drivers. ? i2c drivers. ? dma drivers. ? power profiles. ? flash in-application programming (iap) and in-system programming (isp). lpc11e6x 32-bit arm cortex-m0+ microcontr oller; up to 256 kb flash and 36 kb sram; 4 kb eeprom; 12-bit adc rev. 1.1 ? 17 april 2014 product data sheet
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 2 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? 32-bit integer division routines. ? digital peripherals: ? simple dma engine with 16 channels and programmable input triggers. ? high-speed gpio interface connected to th e arm cortex-m0+ io bus with up to 80 general-purpose i/o (gpio) pins with conf igurable pull-up/pu ll-down resistors, programmable open-drain mode, input inverter, and programmable glitch filter and digital filter. ? pin interrupt and pattern match engine using eight selectable gpio pins. ? two gpio group interrupt generators. ? crc engine. ? configurable pwm/timer subsystem (two 16-bit and two 32-bit standard counter/timers, two state-configurable timers (sctimer/pwm)) that provides: ? up to four 32-bit and two 16-bit counter/timers or two 32-bit and six 16-bit counter/timers. ? up to 21 match outputs and 16 capture inputs. ? up to 19 pwm outputs with 6 independent time bases. ? windowed watchdog timer (wwdt). ? real-time clock (rtc) in the always-on power domain with separate battery supply pin and 32 khz oscillator. ? analog peripherals: ? one 12-bit adc with up to 12 input channel s with multiple inte rnal and external trigger inputs and with sample rates of up to 2 msamples/s. the adc supports two independent conversion sequences. ? temperature sensor. ? serial interfaces: ? up to five usart interfaces, all with dma, synchronous mode, and rs-485 mode support. four usarts use a shared fractional baud generator. ? two ssp controllers with dma support. ? two i 2 c-bus interfaces. one i 2 c-bus interface with specialized open-drain pins supports i2c fast-mode plus. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy for ? 25 ? c ? t amb ? +85 ? c that can optionally be used as a system clock. ? on-chip 32 khz oscillator for rtc. ? crystal oscillator with an op erating range of 1 mhz to 25 mhz. oscillator pins are shared with the gpio pins. ? programmable watchdog osc illator with a frequency range of 9.4 khz to 2.3 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. ? clock output function with divi der that can reflec t the crystal oscillator, the main clock, the irc, or the watchdog oscillator. ? power control: ? integrated pmu (power management unit) to minimize power consumption. ? reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. ? wake-up from deep-sleep and power-down modes on external pin inputs and usart activity.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 3 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? power-on reset (por). ? brownout detect. ? unique device serial number for identification. ? single power supply (2.4 v to 3.6 v). ? separate vbat supply for rtc. ? operating temperature range -40 c to 105 c. ? available as lqfp48, lqfp64, and lqfp100 packages. 3. applications 4. ordering information 4.1 ordering options ? three-phase e-meter ? car radio ? gps tracker ? medical monitor ? gaming accessories ? pc peripherals table 1. ordering information type number package name description version LPC11E67JBD48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11e68jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc11e68jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 table 2. ordering options type number flash/ kb eeprom/ kb sram/ kb usart0 usart1 usart2 usart3 usart4 i 2 c ssp pwm/ timers 12-bit adc channels gpio LPC11E67JBD48 128 4 20 yyyyn2 2 6 8 36 lpc11e68jbd64 256 4 36 yyyyn2 2 6 10 50 lpc11e68jbd100 256 4 36 yyyyy2 2 6 12 80
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 4 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 5. marking 5.1 product id entification the lpc11e6x devices typically have th e following top-side marking for lqfp100 packages: lpc11e6xjbd100 xxxxxx xx xxxyywwxr[x] the lpc11e6x devices typically have th e following top-side marking for lqfp64 packages: lpc11e6xj xxxxxx xx xxxyywwxr[x] the lpc11e6x devices typically have th e following top-side marking for lqfp48 packages: lpc11e6xj xx xx xxxyy wwxr[x] field ?yy? states the year the device was m anufactured. field ?ww? states the week the device was manufactured during that year. field ?r? identifies the device revision. fig 1. lqfp64/100 package marking fig 2. lqfp48 package marking 1 n terminal 1 index area aaa-011231 aaa-011232 terminal 1 index area 1 n
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 5 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 6. block diagram grey-shaded blocks show peripherals that can provide hardware triggers for dm a transfers or have dma request lines. (1) available on lpc11e68jbd100 only. fig 3. lpc11e6x block diagram arm cortex-m0+ swd test/debug interface systick nvic processor core precision irc system pll watchdog oscillator system oscillator rtc oscillator general purpose backup registers clock generation 256/128 kb flash rom 36/20 kb sram 4 kb eeprom temperature sensor memory port0/1/2 gint0/1 pintsel pint/ pattern match sctimer0/ pwm hs gpio+ sctimer1/ pwm dma trigger pwm/timer subsystem usart0 usart1 usart3 usart4 (1) fm+ i2c0 usart2 ssp1 ssp0 i2c1 syscon iocon pmu crc flash ctrl eeprom ctrl system/memory control ct16b0 ct32b0 ct16b1 ct32b1 wwdt rtc always-on power domain system timer serial peripherals 12-bit adc0 trigger mux analog peripherals ahb multilayer matrix ahb/apb bridges dma lpc11e6x pads n iocon aaa-011045
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 6 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 7. pinning information 7.1 pinning fig 4. lqfp48 pinning lpc11e6xjbd48 37 swdio/pio0_15 24 pio0_7 38 pio0_16/wakeup 23 pio0_6 39 pio0_23 22 pio1_24 40 v dda 21 pio2_4 41 v ssa 20 pio2_7 42 pio0_17 19 pio2_3 43 v ss 18 pio1_23 44 v dd 17 pio0_21 45 pio0_18 16 pio0_5 46 pio0_19 15 pio0_4 47 vbat 14 pio0_3 48 rtcxin 13 pio1_20 1 rtcxout 36 pio1_13 2v ss 35 vrefn 3 reset/pio0_0 34 vrefp 4pio0_1 33 trst/pio0_14 5v ss 32 tdo/pio0_13 6 pio2_0/xtalin 31 tms/pio0_12 7 pio2_1/xtalout 30 tdi/pio0_11 8v dd 29 pio0_22 9pio2_5 28 swclk/pio0_10 10 pio0_20 27 pio0_9 11 pio0_2 26 pio0_8 12 pio2_2 25 pio1_21 aaa-011046
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 7 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 5. lqfp64 pinning lpc11e6xjbd64 49 pio1_13 32 pio2_15 50 swdio/piio0_15 31 pio1_28 51 pio0_16/wakeup 30 pio0_7 52 pio0_23 29 pio0_6 53 v dda 28 pio1_24 54 v ssa 27 pio2_4 55 pio1_9 26 pio2_7 56 pio0_17 25 pio2_6 57 v ss 24 pio2_3 58 v dd 23 pio1_23 59 v dd 22 pio0_21 60 pio0_18 21 pio0_5 61 pio0_19 20 pio0_4 62 pio1_0 19 pio0_3 63 vbat 18 pio1_20 64 pio1_19 17 pio1_27 1 rtcxin 48 vrefn 2 rtcxout 47 vrefp 3v ss 46 trst/pio0_14 4 reset/pio0_0 45 tdo/pio0_13 5pio0_1 44 pio1_30 6pio1_7 43 tms/pio0_12 7v ss 42 tdi/pio0_11 8pio2_0 41 pio1_29 9pio2_1 40 pio0_22 10 v dd 39 swclk/pio0_10 11 pio2_5 38 pio0_9 12 pio0_20 37 pio0_8 13 pio1_10 36 pio2_19 14 pio0_2 35 pio1_21 15 pio1_26 34 v dd 16 pio2_2 33 pio2_18 aaa-011047 fig 6. lqfp100 pinning lpc11e6xjbd100 76 100 50 26 1 25 75 51 aaa-011048
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 8 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 7.2 pin description table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions reset /pio0_0 348 [8] i; pu i reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor ex ecution to begin at address 0. this pin also serves as the debug select input. low level selects the jtag boundary scan. high level selects the arm swd debug mode. in deep power-down mode, this pin must be pulled high externally. the reset pin can be left unconnected or be used as a gpio pin if an external reset function is not needed and deep power-down is not used. io pio0_0 ? general purpose digital input/output pin. pio0_1 459 [6] i; pu io pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o clkout ? clockout pin. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2 11 14 19 [6] i; pu io pio0_2 ? general purpose port 0 input/output 2. io ssp0_ssel ? slave select for ssp0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. - r_0 ? reserved. pio0_3 14 19 30 [6] i; pu io pio0_3 ? general purpose digital input/output pin. - r ? reserved. r_1 ? reserved. pio0_4 15 20 31 [7] ia io pio0_4 ? general purpose port 0 input/output 4 (open-drain). io i2c0_scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. - r_2 ? reserved. pio0_5 16 21 32 [7] ia io pio0_5 ? general purpose port 0 input/output 5 (open-drain). io i2c0_sda ? i 2 c-bus data input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. - r_3 ? reserved. pio0_6 23 29 44 [6] i; pu io pio0_6 ? general purpose port 0 input/output 6. - r ? reserved. io ssp0_sck ? serial clock for ssp0. - r_4 ? reserved.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 9 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio0_7 24 30 45 [5] i; pu io pio0_7 ? general purpose port 0 input/output 7 (high-current output driver). i u0_cts ? clear to send input for usart. - r_5 ? reserved. io i2c1_scl ? i 2 c-bus clock input/output. this pin is not open-drain. pio0_8 26 37 58 [6] i; pu io pio0_8 ? general purpose port 0 input/output 8. io ssp0_miso ? master in slave out for ssp0. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. - r_6 ? reserved. pio0_9 27 38 59 [6] i; pu io pio0_9 ? general purpose port 0 input/output 9. io ssp0_mosi ? master out slave in for ssp0. o ct16b0_mat1 ? match output 1 for 16-bit timer 0. - r_7 ? reserved. swclk/pio0_10 28 39 60 [6] i; pu io swclk ? serial wire clock. swclk is enabled by default on this pin. in boundary scan mode: tck (test clock). io pio0_10 ? general purpose digital input/output pin. io ssp0_sck ? serial clock for ssp0. o ct16b0_mat2 ? 16-bit timer0 mat2 tdi/pio0_11 30 42 64 [3] i; pu io tdi ? test data in for jtag interface. in boundary scan mode only. io pio0_11 ? general purpose digital input/output pin. ai adc_9 ? a/d converter, input channel 9. o ct32b0_mat3 ? match output 3 for 32-bit timer 0. o u1_rts ? request to send output for usart1. io u1_sclk ? serial clock input/output for usart1 in synchronous mode. tms/pio0_12 31 43 66 [3] i; pu io tms ? test mode select for jtag interface. in boundary scan mode only. io pio0_12 ? general purpose digital input/output pin. ai adc_8 ? a/d converter, input channel 8. i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. i u1_cts ? clear to send input for usart1. tdo/pio0_13 32 45 68 [3] i; pu io tdo ? test data out for jtag interface. in boundary scan mode only. io pio0_13 ? general purpose digital input/output pin. ai adc_7 ? a/d converter, input channel 7. o ct32b1_mat0 ? match output 0 for 32-bit timer 1. i u1_rxd ? receiver input for usart1. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 10 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller trst /pio0_14 33 46 69 [3] i; pu io trst ? test reset for jtag interface. in boundary scan mode only. io pio0_14 ? general purpose digita l input/output pin. ai adc_6 ? a/d converter, input channel 6. o ct32b1_mat1 ? match output 1 for 32-bit timer 1. o u1_txd ? transmitter output for usart1. swdio/pio0_15 37 50 81 [3] i; pu io swdio ? serial wire debug i/o. swdio is enabled by default on this pin. in boundary scan mode: tms (test mode select). io pio0_15 ? general purpose digital input/output pin. ai adc_3 ? a/d converter, input channel 3. o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio0_16/wakeup 38 51 82 [4] i; pu io pio0_16 ? general purpose digital input/output pin. this pin also serves as the deep power-down mode wake-up pin with 20 ns glitch filter. pull this pin high externally before entering deep power-dow n mode. pull this pin low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. i adc_2 ? a/d converter, input channel 2. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. - r_8 ? reserved. pio0_17 42 56 90 [6] i; pu io pio0_17 ? general purpose digital input/output pin. o u0_rts ? request to send output for usart0. i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. io u0_sclk ? serial clock input/output for usart0 in synchronous mode. pio0_18 45 60 94 [6] i; pu io pio0_18 ? general purpose digital input/output pin. i u0_rxd ? receiver input for usart0. used in uart isp mode. o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio0_19 46 61 95 [6] i; pu io pio0_19 ? general purpose digital input/output pin. o u0_txd ? transmitter output for usart0. used in uart isp mode. o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio0_20 10 12 17 [6] i; pu io pio0_20 ? general purpose digital input/output pin. i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. i u2_rxd ? receiver input for usart2. pio0_21 17 22 33 [6] i; pu io pio0_21 ? general purpose digital input/output pin. o ct16b1_mat0 ? match output 0 for 16-bit timer 1. io ssp1_mosi ? master out slave in for ssp1. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 11 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio0_22 29 40 62 [3] i; pu io pio0_22 ? general purpose digital input/output pin. ai adc_11 ? a/d converter, input channel 11. i ct16b1_cap1 ? capture input 1 for 16-bit timer 1. io ssp1_miso ? master in slave out for ssp1. pio0_23 39 52 83 [3] i; pu io pio0_23 ? general purpose digital input/output pin. ai adc_1 ? a/d converter, input channel 1. - r_9 ? reserved. i u0_ri ? ring indicator input for usart0. io ssp1_ssel ? slave select for ssp1. pio1_0 -6297 [6] i; pu io pio1_0 ? general purpose digital input/output pin. o ct32b1_mat0 ? match output 0 for 32-bit timer 1. - r_10 ? reserved. o u2_txd ? transmitter output for usart2. pio1_1 --28 [6] i; pu io pio1_1 ? general purpose digital input/output pin. o ct32b1_mat1 ? match output 1 for 32-bit timer 1. - r_11 ? reserved. o u0_dtr ? data terminal ready output for usart0. pio1_2 --55 [6] i; pu io pio1_2 ? general purpose digital input/output pin. o ct32b1_mat2 ? match output 2 for 32-bit timer 1. - r_12 ? reserved. i u1_rxd ? receiver input for usart1. pio1_3 --72 [3] i; pu io pio1_3 ? general purpose digital input/output pin. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. - r_13 ? reserved. io i2c1_sda ? i 2 c-bus data input/output (not open-drain). ai adc_5 ? a/d converter, input channel 5. pio1_4 --23 [6] i; pu io pio1_4 ? general purpose digital input/output pin. i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. - r_14 ? reserved. i u0_dsr ? data set ready input for usart0. pio1_5 --47 [6] i; pu io pio1_5 ? general purpose digital input/output pin. i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. - r_15 ? reserved. i u0_dcd ? data carrier detect input for usart0. pio1_6 --98 [6] i; pu io pio1_6 ? general purpose digital input/output pin. - r_16 ? reserved. i u2_rxd ? receiver input for usart2. i ct32b0_cap1 ? capture input 1 for 32-bit timer 0. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 12 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio1_7 -610 [6] i; pu io pio1_7 ? general purpose digital input/output pin. - r_17 ? reserved. i u2_cts ? clear to send input for usart2. i ct16b1_cap0 ? capture input 0 for 32-bit timer 1. pio1_8 --61 [6] i; pu io pio1_8 ? general purpose digital input/output pin. - r_18 ? reserved. o u1_txd ? transmitter output for usart1. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio1_9 -5586 [3] i; pu io pio1_9 ? general purpose digital input/output pin. i u0_cts ? clear to send input for usart0. o ct16b1_mat1 ? match output 1 for 16-bit timer 1. ai adc_0 ? a/d converter, input channel 0. pio1_10 -1318 [6] i; pu io pio1_10 ? general purpose digital input/output pin. o u2_rts ? request to send output for usart2. io u2_sclk ? serial clock input/output for usart2 in synchronous mode. o ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_11 --65 [6] i; pu io pio1_11 ? general purpose digital input/output pin. io i2c1_scl ? i 2 c1-bus clock input/out put (not open-drain). o ct16b0_mat2 ? match output 2 for 16-bit timer 0. i u0_ri ? ring indicator input for usart0. pio1_12 --89 [6] i; pu io pio1_12 ? general purpose digital input/output pin. io ssp0_mosi ? master out slave in for ssp0. o ct16b0_mat1 ? match output 1 for 16-bit timer 0. - r_21 ? reserved. pio1_13 36 49 78 [6] i; pu io pio1_13 ? general purpose digital input/output pin. i u1_cts ? clear to send input for usart1. o sct0_out3 ? sctimer0/pwm output 3. - r_22 ? reserved. pio1_14 --79 [6] i; pu io pio1_14 ? general purpose digital input/output pin. io i2c1_sda ? i 2 c1-bus data input/output (not open-drain). o ct32b1_mat2 ? match output 2 for 32-bit timer 1. - r_23 ? reserved. pio1_15 --87 [6] i; pu io pio1_15 ? general purpose digital input/output pin. io ssp0_ssel ? slave select for ssp0. o ct32b1_mat3 ? match output 3 for 32-bit timer 1. - r_24 ? reserved. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 13 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio1_16 --96 [6] i; pu io pio1_16 ? general purpose digital input/output pin. io ssp0_miso ? master in slave out for ssp0. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. - r_25 ? reserved. pio1_17 --34 [6] i; pu io pio1_17 ? general purpose digital input/output pin. i ct16b0_cap2 ? capture input 2 for 16-bit timer 0. i u0_rxd ? receiver input for usart0. - r_26 ? reserved. pio1_18 --43 [6] i; pu io pio1_18 ? general purpose digital input/output pin. i ct16b1_cap1 ? capture input 1 for 16-bit timer 1. o u0_txd ? transmitter output for usart0. - r_27 ? reserved. pio1_19 -644 [6] i; pu io pio1_19 ? general purpose digital input/output pin. i u2_cts ? clear to send input for usart2. o sct0_out0 ? sctimer0/pwm output 0. - r_28 ? reserved. pio1_20 13 18 29 [6] i; pu io pio1_20 ? general purpose digital input/output pin. i u0_dsr ? data set ready input for usart0. io ssp1_sck ? serial clock for ssp1. o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio1_21 25 35 56 [6] i; pu io pio1_21 ? general purpose digital input/output pin. i u0_dcd ? data carrier detect input for usart0. io ssp1_miso ? master in slave out for ssp1. i ct16b0_cap1 ? capture input 1 for 16-bit timer 0. pio1_22 --80 [3] i; pu io pio1_22 ? general purpose digital input/output pin. io ssp1_mosi ? master out slave in for ssp1. i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. ai adc_4 ? a/d converter, input channel 4. - r_29 ? reserved. pio1_23 18 23 35 [6] i; pu io pio1_23 ? general purpose digital input/output pin. o ct16b1_mat1 ? match output 1 for 16-bit timer 1. io ssp1_ssel ? slave select for ssp1. o u2_txd ? transmitter output for usart2. pio1_24 22 28 42 [6] i; pu io pio1_24 ? general purpose digital input/output pin. o ct32b0_mat0 ? match output 0 for 32-bit timer 0. io i2c1_sda ? i 2 c-bus data input/output (not open-drain). table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 14 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio1_25 - - 100 [6] i; pu io pio1_25 ? general purpose digital input/output pin. o u2_rts ? request to send output for usart2. io u2_sclk ? serial clock input/output for usart2 in synchronous mode. i sct0_in0 ? sctimer0/pwm input 0. - r_30 ? reserved. pio1_26 -1520 [6] i; pu io pio1_26 ? general purpose digital input/output pin. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. i u0_rxd ? receiver input for usart0. - r_19 ? reserved. pio1_27 -1722 [6] i; pu io pio1_27 ? general purpose digital input/output pin. o ct32b0_mat3 ? match output 3 for 32-bit timer 0. o u0_txd ? transmitter output for usart0. - r_20 ? reserved. io ssp1_sck ? serial clock for ssp1. pio1_28 -3146 [6] i; pu io pio1_28 ? general purpose digital input/output pin. i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. io u0_sclk ? serial clock input/output for usart in synchronous mode. o u0_rts ? request to send output for usart0. pio1_29 -4163 [3] i; pu io pio1_29 ? general purpose digital input/output pin. io ssp0_sck ? serial clock for ssp0. i ct32b0_cap1 ? capture input 1 for 32-bit timer 0. o u0_dtr ? data terminal ready output for usart0. ai adc_10 ? a/d converter, input channel 10. pio1_30 -4467 [6] i; pu io pio1_30 ? general purpose digital input/output pin. io i2c1_scl ? i 2 c1-bus clock input/out put (not open-drain). i sct0_in3 ? sctimer0/pwm input 3. - r_31 ? reserved. pio1_31 - - 48 [5] i; pu io pio1_31 ? general purpose digital input/output pin (high-current output driver). pio2_0 6812 [9] i; pu io pio2_0 ? general purpose digital input/output pin. ai xtalin ? input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. pio2_1 7913 [9] i; pu io pio2_1 ? general purpose digital input/output pin. ao xtalout ? output from the oscillator amplifier. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 15 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio2_2 12 16 21 [6] i; pu io pio2_2 ? general purpose digital input/output pin. o u3_rts ? request to send output for usart3. io u3_sclk ? serial clock input/output for usart3 in synchronous mode. o sct0_out1 ? sctimer0/pwm output 1. pio2_3 19 24 36 [6] i; pu io pio2_3 ? general purpose digital input/output pin. i u3_rxd ? receiver input for usart3. o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio2_4 21 27 41 [6] i; pu io pio2_4 ? general purpose digital input/output pin. o u3_txd ? transmitter output for usart3. o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio2_5 91115 [6] i; pu io pio2_5 ? general purpose digital input/output pin. i u3_cts ? clear to send input for usart3. i sct0_in1 ? sctimer0/pwm input 1. pio2_6 -2537 [6] i; pu io pio2_6 ? general purpose digital input/output pin. o u1_rts ? request to send output for usart1. io u1_sclk ? serial clock input/output for usart1 in synchronous mode. i sct0_in2 ? sctimer0/pwm input 2. pio2_7 20 26 40 [6] i; pu io pio2_7 ? general purpose digital input/output pin. io ssp0_sck ? serial clock for ssp0. o sct0_out2 ? sctimer0/pwm output 2. pio2_8 --2 [6] i; pu io pio2_8 ? general purpose digital input/output pin. i sct1_in0 ? sctimer1/pwm input 0. pio2_9 --3 [6] i; pu io pio2_9 ? general purpose digital input/output pin. i sct1_in1 ? sctimer1/pwm_in1 pio2_10 --16 [6] i; pu io pio2_10 ? general purpose digital input/output pin. o u4_rts ? request to send output for usart4. io u4_sclk ? serial clock input/output for usart4 in synchronous mode. pio2_11 --24 [6] i; pu io pio2_11 ? general purpose digital input/output pin. i u4_rxd ? receiver input for usart4. pio2_12 --25 [6] i; pu io pio2_12 ? general purpose digital input/output pin. o u4_txd ? transmitter output for usart4. pio2_13 --26 [6] i; pu io pio2_13 ? general purpose digital input/output pin. i u4_cts ? clear to send input for usart4. pio2_14 --27 [6] i; pu io pio2_14 ? general purpose digital input/output pin. i sct1_in2 ? sctimer1/pwm input 2. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 16 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller pio2_15 -3249 [6] i; pu io pio2_15 ? general purpose digital input/output pin. i sct1_in3 ? sctimer1/pwm input 3. pio2_16 --50 [6] i; pu io pio2_16 ? general purpose digital input/output pin. o sct1_out0 ? sctimer1/pwm output 0. pio2_17 --51 [6] i; pu io pio2_17 ? general purpose digital input/output pin. o sct1_out1 ? sctimer1/pwm output 1. pio2_18 -3352 [6] i; pu io pio2_18 ? general purpose port 2 input/output 18. o sct1_out2 ? sctimer1/pwm output 2. pio2_19 -3657 [6] i; pu io pio2_19 ? general purpose port 2 input/output 19. o sct1_out3 ? sctimer1/pwm output 3. pio2_20 - - 75 [6] i; pu io pio2_20 ? general purpose port 2 input/output 20. pio2_21 - - 76 [6] i; pu io pio2_21 ? general purpose port 2 input/output 21. pio2_22 - - 77 [6] i; pu io pio2_22 ? general purpose port 2 input/output 22. pio2_23 - - 1 [6] i; pu io pio2_23 ? general purpose port 2 input/output 23. rstout - - 88 [6] ia io internal reset status output. rtcxin 48 1 5 [2] - - rtc oscillator input. this input should be grounded if the rtc is not used. rtcxout 1 2 6 [2] - - rtc oscillator output. vrefp 34 47 73 - - adc positive reference voltage. if the adc is not used, tie vrefp to v dd . vrefn 35 48 74 - - adc negative voltage reference. if the adc is not used, tie vrefn to v ss . v dda 40 53 84 - - analog voltage supply. v dda should typically be the same voltages as v dd but should be isolated to minimize noise and error. v dda should be tied to v dd if the adc is not used. v dd 44, 8 58, 10, 34, 59 92, 14, 71, 54, 93 - - supply voltage to the internal regulator and the external rail. vbat 47 63 99 - - battery supply. s upplies power to the rtc. if no battery is used, tie vbat to vdd or to ground. v ssa 41 54 85 - - analog ground. v ssa should typically be the same voltage as v ss but should be isolated to minimize noise and error. v ssa should be tied to v ss if the adc is not used. v ss 43, 2, 5 57, 3, 7 91, 7, 11, 53, 70 - - ground. n.c. - - 39 not connected. n.c. - - 38 not connected. table 3. pin description pin functions are selected through the iocon registers. see table 2 for availability of usart4 pin functions. symbol lqfp48 lqfp64 lqfp100 reset state [1] type description of pin functions
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 17 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] pin state at reset for default function: i = input; o = outpu t; ai = analog input; pu = internal pull-up enabled; ia = inact ive, no pull-up/down enabled; f = floating; if the pins are not used, tie floating pi ns to ground or power to mi nimize power consumption. [2] special analog pad. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as analog input, digital sect ion of the pad is disabled and the pin is not 5 v tolerant; includes digital, prog rammable filter. [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as analog input, digital sect ion of the pad is disabled and the pin is not 5 v tolerant; includes digital input glitch filter. wakeup pin. the wake-up pin function can be disabled and the pin can be used for other purposes if the rtc is enabled for wakin g up the part from deep power-down mode [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis; includes high-current output driver. [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [7] i 2 c-bus pin compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. the pin requires an external pull-up to provide output func tionality. when power is switched off, this pin is floating and does not disturb the i2c lines. open-drain configuration applies to all functions on this pin. [8] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [9] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog crystal oscillator connections. when confi gured for the crystal oscillator input/output, digi tal section of the pad is disabled and the pin is not 5 v tolerant; includes digital, programmable filter.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 18 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8. functional description 8.1 arm cortex-m0+ core the arm cortex-m0+ core runs at an operating frequency of up to 50 mhz using a two-stage pipeline. integrated in the core ar e the nvic and serial wire debug with four breakpoints and two watchpoints. the arm co rtex-m0+ core supports a single-cycle i/o enabled port for fast gpio access. the core includes a single-cycle multiplier and a system tick timer. 8.2 ahb multilayer matrix the ahb multilayer matrix supports two masters, the m0+ core and the dma. all masters can access all slaves (peripherals and memories).
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 19 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 7. ahb multilayer matrix arm cortex-m0+ test/debug interface dma ahb-to-apb bridge eeprom hs gpio slaves sram1 system bus masters flash rom ahb multilayer matrix = master-slave connection wwdt usart0 ct32b0 i2c0 flashctrl ssp0 ct32b1 dma trigmux pmu i2c1 adc iocon rtc group0 group1 usart1 ssp1 usart4 syscon main sram0 sram2 sctimer0/pwm sctimer1/pwm pint/pattern match crc dma registers ct16b0 ct16b1 usart2 usart3 usart2 aaa-011051
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 20 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.3 on-chip flash programming memory the lpc11e6x contain up to 256 kb on-chi p flash program memory. the flash can be programmed using in-system programming (isp) or in-application programming (iap) via the on-chip boot loader software. the flash memory is divided into 24 x 4 kb and 5 x 32 kb sectors. individual pages of 256 byte each can be erased using the iap erase page command. 8.4 eeprom the lpc11e6x contain 4 kb of on-chip by te-erasable and byte -programmable eeprom data memory. the eeprom can be programmed using in-application programming (iap) via the on-chip boot loader software. 8.5 sram the lpc11e6x contain a total of up to 36 kb on-chip static ram memory. the main sram block contains either 16 kb or 32 kb of main sram0. two a dditional sram blocks of 2 kb (sram1 and sram2) are located in separate areas of the memory map. see figure 8 . 8.6 on-chip rom the on-chip rom contains the boot loader and the following application programming interfaces (apis): ? in-system programming (isp) and in-application programming (iap) support for flash including iap erase page command. ? iap support for eeprom ? power profiles for configuring po wer consumption and pll settings ? 32-bit integer division routines ? apis to use the following peripherals: ? i2c ? usart0 and usart1/2/3/4 ? dma 8.7 memory mapping the lpc11e6x incorporates several distinct memory regions, shown in the following figures. figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb (advanced high-performance bus) perip heral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb (a dvanced peripheral bus) peripheral area is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this addr essing scheme allows si mplifying the address decoding for each peripheral.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 21 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.8 nested vectored inte rrupt controller (nvic) the nested vectored interrupt controller (nvi c) is part of the cortex-m0+. the tight coupling to the cpu allows for lo w interrupt latency and efficient processing of late arriving interrupts. fig 8. lpc11e6x memory map apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 8000 0x4005 c000 0x4006 0000 0x4006 4000 0x4006 c000 0x4007 0000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 12-bit adc usart0 pmu i2c0 20 - 21 reserved 11 - 13 reserved rtc i2c1 30 - 31 reserved 0 1 2 3 4 5 6 7 8 9 0x4002 c000 dma trigmux 10 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 8000 0x1fff 0000 0x1fff 8000 0x2000 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved reserved 2 kb sram2 reserved 0x4000 0000 0x4008 0000 0x4008 4000 apb peripherals reserved crc 0x5000 8000 dma 0x5000 c000 0x5000 e000 sctimer0/pwm 0xa000 0000 gpio 0xa000 4000 0xa000 8000 gpio pint 0x5001 0000 sctimer1/pwm 0x2000 4000 0x2000 4800 2 kb sram1 0x2000 0800 32 kb main sram0 0x1000 4000 16 kb main sram0 0x1000 0000 lpc11e6x 0x0004 0000 256 kb on-chip flash (lpc11e68) 0x0002 0000 128 kb on-chip flash (lpc11e67) 32 kb boot rom 0x1400 0000 0x1400 1000 4 kb mtb registers 0x0000 0000 0x0000 00c0 active interrupt vectors reserved reserved reserved reserved ssp0 ssp1 16-bit counter/timer 1 16-bit counter/timer 0 iocon system control (syscon) 19 usart4 22 23 gpio group0 interrupt 24 gpio group1 interrupt 0x4007 4000 0x4007 8000 usart1 27 28 usart2 29 usart3 25 - 26 reserved flash/eeprom controller 0xe000 0000 0xe010 0000 private peripheral bus aaa-011052
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 22 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.8.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc11e6x, the nvic supports vectored interrupts for each of the peripherals and the eight pin interrupts. the following peripheral interrupts are ored to contribute to one interrupt in the nvic: ? usart1, usart4 ? usart2, usart3 ? sctimer0/pwm, sctimer1/pwm ? bod, wwdt ? adc end-of-sequence a interrupt, threshold crossing interrupt ? adc end-of-sequence b interrupt, overrun interrupt ? flash, eeprom ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interr upt generation. 8.8.2 interrupt sources each peripheral device has at least one interr upt line connected to the nvic but can have several interrupt flags. individual interrupt flags can also represent more than one interrupt source. 8.9 iocon block the iocon block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. connect peripherals to the appropriate pins be fore activating the peripheral and before enabling any related interrupt. enabling an analog function disables the digita l pad. however, the internal pull-up and pull-down resistors as well as the pin hysteres is must be disabled to obtain an accurate reading of the analog input. 8.9.1 features ? programmable pin function. ? programmable pull-up, pull-down, or repeater mode. ? all pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled. ? programmable pseudo open-drain mode. ? programmable (on/off) 10 ns glitch filt er on pins pio0_22, pio0_23, pio0_11 to pio0_16, pio1_3, pio1_9, pio1_22, and pio 1_29. the glitch filter is turned on by default. ? programmable hysteresis. ? programmable input inverter.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 23 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? digital filter with programmabl e filter constant on all pins. the minimum filter constant is 1/50 mhz = 20 ns. 8.9.2 standard i/o pad configuration figure 9 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with co nfigurable open-drain output ? digital input: weak pull-up resistor (pmos device) enabled/disabled ? digital input: weak pull-down resistor (nmos device) enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input digital filter selectable on all pins. in addition, a 10 ns digital glitch filter is selectable on pins with analog function. ? analog input 8.10 fast general-purpo se parallel i/o (gpio) device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. fig 9. standard i/o pin configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input pin configured as digital output driver pin configured as digital input pin configured as analog input programmable digital filter 10 ns glitch filter aaa-010776
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 24 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller lpc11e6x use accelerated gpio functions: ? gpio registers are located on the arm co rtex m0+ io bus for fastest possible single-cycle i/o timing, allowing gpio toggling with rates of up to 25 mhz. ? an entire port value can be written in one instruction. ? mask, set, and clear operations are supported for the entire port. 8.10.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. 8.11 pin interrupt/pattern match engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. any digital pin except pins pio2_8 and pi o2_23 can be co nfigured through the syscon block as input to the pin interrupt or pattern match engine. the registers that control the pin interrupt or pattern match engine are lo cated on the io+ bus for fast single-cycle access. 8.11.1 features ? pin interrupts ? up to eight pins can be selected from all digital pins except pins pio2_8 and pio2_23 as edge- or level-sensitive inte rrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrupt on rising or falling edges or both. ? level-sensitive interrupt pins can be high- or low-active. ? pin interrupts can wake up the part from sleep mode, deep-sleep mode, and power-down mode. ? pin interrupt pattern match engine ? up to 8 pins can be selected from all digi tal pins except pins pio2_8 and pio2_23 to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can be programmed to also generate an rxev notification to the arm cpu. ? the pattern match engine d oes not facilitate wake-up.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 25 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.12 gpio group interrupts the gpio pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sens itive interrupts. for each port/pin connected to one of the two the gpio grouped interr upt blocks (gint0 and gint1), the gpio grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are. the gpio grouped in terrupt registers also se lect whether the interrup t output will be level or edge triggered and whether it will be based on the or or th e and of all of the enabled inputs. when the designated pattern is detected on the selected input pins, the gpio grouped interrupt block generates an interrupt. if the part is in a power-savings mode, it first asynchronously wakes the part up prior to asserting the interrupt request. the interrupt request line can be cleared by writing a one to the interrupt status bit in the control register. 8.12.1 features ? two group interrupts are supported to reflect two distinct interrupt patterns. ? the inputs from any number of digital pins can be enabled to contribute to a combined group interrupt. ? the polarity of each input enabled for th e group interrupt can be configured high or low. ? enabled interrupts can be logically combined through an or or and operation. ? the grouped interrupts can wake up the pa rt from sleep, deep-sleep or power-down modes. 8.13 dma controller the dma controller can access all memories and the usar t and ssp peripherals using dma requests. dma transfers can also be triggered by internal events like the adc interrupts, timer match outputs, the pin in terrupts (pint0 and pint1) and the sctimer dma requests. 8.13.1 features ? 16 channels with 14 channels connected to peripheral request inputs. ? dma operations can be triggered by on-chip events or two pin interrupts. each dma channel can select one trigger input from 12 sources. ? priority is user selectable for each channel. ? continuous priority arbitration. ? address cache with two entries. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 26 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.14 usart0 remark: the lpc11e6x contains two distinctive types of uart interfaces: usart0 is software-compatible with the usart interface on the lpc11e1x/3x parts. usart1 to usart4 use a different register interface. the usart0 includes full modem control, support for synchronous mode, and a smart card interface. the rs-485/9-bit mode a llows both software address detection and automatic address detection using 9-bit mode. the usart0 uses a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 8.14.1 features ? maximum usart0 data bit rate of 3.125 mbit/s in asynchronous mode and 10 mbit/s in synchronous slave and master mode. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. ? support for synchronous mode. ? includes smart card interface. ? dma support. 8.15 usart1/2/3/4 remark: the lpc11e6x contains two distinctive types of uart interfaces: usart0 is software-compatible with the usart interface on the lpc11e1x/lpc11e3x parts. usart1 to usart4 use a different regist er interface to achieve the same uart functionality except for modem and smart card control. remark: usart4 is available only on part lpc11e68jbd100. interrupts generated by the usart1/2/3/4 peripherals can wake up the part from deep-sleep and power-down modes if the usart is in synchronous mode, the 32 khz mode is enabled, or the cts interrupt is enabled. this wake-up mechanism is not available with the usart0 peripheral. 8.15.1 features ? maximum bit rates of 3.125 mbit/s in asynchronous mode and 10 mbit/s in synchronous mode. ? 7, 8, or 9 data bits and 1 or 2 stop bits
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 27 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. (rs-485 possible with software address detection and transceiver direction control.) ? rs-485 transceiver output enable. ? autobaud mode for automatic baud rate detection ? parity generation and checking: odd, even, or none. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator with auto-baud function. ? a fractional rate divider is shared among all usarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? loopback mode for testing of data and flow control. ? in synchronous slave mode, wakes up the part from deep-sleep and power-down modes. ? special operating mode allows operation at up to 9600 baud using the 32 khz rtc oscillator as the uart clock. this mode can be used while the device is in deep-sleep or power-down mode and can wake-up the device when a character is received. ? usart transmit and receive functions c an operated with the system dma controller. 8.16 ssp serial i/o controller (ssp0/1) the ssp controllers operate on a ssp, 4-wire ssi, or microwire bus. the controller can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data trans fer. the ssp supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 8.16.1 features ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi (serial peripheral interface), 4-wire texas instruments ssi (serial synchronous interface), and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 28 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? 4-bit to 16-bit frame ? dma support 8.17 i 2 c-bus serial i/o controller the lpc11e6x contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 8.17.1 features ? one i 2 c-interface (i2c0) is an i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface supports fast-mode plus with bit rates up to 1 mbit/s. ? one i 2 c-interface (i2c1) uses standard digital pins. the i 2 c-bus interface supports bit rates up to 400 kbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 8.18 timer/pwm subsystem four standard timers and two state configurable timers can be combined to create multiple pwm outputs using the match outputs and the match registers for each timers. each timer can create multiple pwm outputs with its own time base.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 29 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller the standard timers and the sctimers combine to up to eight independent timers. each sctimer can be configured either as one 32-bi t timer or two independently counting 16-bit timers which use the same input clock. the following combinations are possible: table 4. pwm resources pwm outputs peripheral pin functions available for pwm match registers used lqfp100 lqfp64 lqfp48 lqfp100 lqfp64 lqfp48 3 3 3 ct16b0 ct16b0_mat0, ct16b0_mat1, ct16b0_mat2 ct16b0_mat0, ct16b0_mat1, ct16b0_mat2 ct16b0_mat0, ct16b0_mat1, ct16b0_mat2 4 2 2 2 ct16b1 ct16b1_mat0, ct16b1_mat1 ct16b1_mat0, ct16b1_mat1 ct16b1_mat0, ct16b1_mat1 3 3 3 3 ct32b0 three of ct32b0_mat0, ct32b0_mat1, ct32b0_mat2, ct32b0_mat3 three of ct32b0_mat0, ct32b0_mat1, ct32b0_mat2, ct32b0_mat3 three of ct32b0_mat0, ct32b0_mat1, ct32b0_mat2, ct32b0_mat3 4 3 3 3 ct32b1 three of ct32b1_mat0, ct32b1_mat1, ct32b1_mat2, ct32b1_mat3 three of ct32b1_mat0, ct32b1_mat1, ct32b1_mat2, ct32b1_mat3 three of ct32b1_mat0, ct32b1_mat1, ct32b1_mat2, ct32b1_mat3 4 443sctimer0/ pwm sct0_out0, sct0_out1, sct0_out2, sct0_out3 sct0_out0, sct0_out1, sct0_out2, sct0_out3 sct0_out1, sct0_out2, sct0_out3 up to 5 42- sctimer1/ pwm sct1_out0, sct1_out1, sct1_out2, sct1_out3 sct1_out2, sct1_out3 - up to 5 table 5. timer configurations 32-bit timers resources 16-bit timers resources 4 ct32b0, ct32b1, sctimer0/pwm as 32-bit timer, sctimer1/pwm as 32-bit timer 2 ct16b0, ct16b1 2 ct32b0, ct32b1 6 ct16b0, ct16b1, sctimer0/pwm as two 16-bit timers, sctimer1/pwm as two 16-bit timers 3 ct32b0, ct32b1, sctimer0/pwm as 32-bit timer (or sctimer1/pwm as 32-bit timer) 4 ct16b0, ct16b1, sctimer1/pwm as two 16-bit timers (or sctimer0/pwm as two 16-bit timers)
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 30 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.18.1 state configurable timers (sctimer0/pwm and sctimer1/pwm) the state configurable timer can create timed output signals such as pwm outputs triggered by programmable events. combinations of events can be used to define timer states. the sctimer/pwm can control the ti mer operations, capture inputs, change states, and toggle outputs triggered only by events entirely without cpu intervention. if multiple states are not implemented, the sctimer/pwm simply operates as one 32-bit or two 16-bit timers with matc h, capture, and pwm functions. 8.18.1.1 features ? each sctimer/pwm supports: ? 5 match/capture registers. ? 6 events. ? 8 states. ? 4 inputs and 4 outputs. ? counter/timer features: ? each sctimer is configurable as two 16-bit counters or one 32-bit counter. ? counters can be clocked by the system clock or selected input. ? configurable as up counters or up-down counters. ? configurable number of match and capture registers. up to five match and capture registers total. ? upon match create the following events: inte rrupt; stop, limit, halt the timer or change counting direction; toggle outputs. ? counter value can be loaded into capture register triggered by a match or input/output toggle. ? pwm features: ? counters can be used in conjunction with match registers to toggle outputs and create time-proportioned pwm signals. ? up to four single-edge or dual-edge pwm outputs with independent duty cycle and common pwm cycle length. ? event creation features: ? the following conditions define an event: a counter match condition, an input (or output) condition such as an rising or fa lling edge or level, a combination of match and/or input/output condition. ? selected events can limit, halt, start, or stop a counter or change its direction. ? events trigger state changes, output togg les, interrupts, and dma transactions. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by events that can happen in the state while the counter is running. ? a state changes into another state as a result of an event.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 31 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. ? sctimer match outputs (ored with the gene ral purpose timer match outputs) serve as adc hardware trigger inputs. 8.18.2 general purpose external event counter/timers (ct32b0/1 and ct16b0/1) the lpc11e6x includes two 32-bit counter/ti mers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also incl udes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.18.2.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can ta ke a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? pwm output function. ? match outputs and capture inputs serve as hardware triggers for adc conversions. 8.19 system tick timer (systick) the arm cortex-m0+ incl udes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 8.20 windowed watc hdog timer (wwdt) the purpose of the wwdt is to prevent an unre sponsive system state. if software fails to update the watchdog within a programmable time window, the watchdog resets the microcontroller
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 32 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.20.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time before watchdog time-out. ? software enables the wwdt, but a hardware reset or a watchdog reset/interrupt is required to disable the wwdt. ? incorrect feed sequence causes reset or interrupt, if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the irc or the dedicated watchdog oscillator (wdosc). the clock sour ce selection provides a wide range of potential timing choices of watchdog oper ation under different power conditions. 8.21 real-time clock (rtc) the rtc resides in a separate always-on voltage domain with battery back-up. the rtc uses an independent oscilla tor, also located in th e always-on voltage domain. 8.21.1 features ? 32-bit, 1 hz rtc counter and associated match register for alarm generation. ? separate 16-bit high-resolution/wake-up timer clocked at 1 khz for 1 ms resolution with a more that one minute maximum time-out period. ? rtc alarm and high-resolution/wake-up ti mer time-out each generate independent interrupt requests. either time-out can wake up the part from any of the low power modes, including deep power-down. 8.22 analog-to-digital converter (adc) the adc supports a resolution of 12 bit and fast conversion rates of up to 2 msamples/s. sequences of analog-to-digital conversions can be triggered by multiple sources. possible trigger sources are the counter/timer match outputs and capture inputs and the arm txev. the adc includes a hardware threshold compar e function with zero-crossing detection. 8.22.1 features ? 12-bit successive approximation analog to digital converter. ? 12-bit conversion rate of up to 2 msamples/s. ? temperature sensor voltage output selectable as internal voltage source for channel 0. ? two configurable conversion sequ ences with independent triggers.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 33 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? optional automatic high/low threshold comparison and zero-crossing detection. ? power-down mode and low-power operating mode. ? measurement range vrefn to vrefp (typically 3 v; not to exceed v dda voltage level). ? burst conversion mode for single or multiple inputs. 8.23 temperature sensor the temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a ctat voltage (complement to absolute temperature). the output voltage varies inversely with device temperature with an absolute accuracy of better than 5 ? c over the full temperature range ( ? 40 ? c to +105 ? c) for typical sample s. the temperature sensor is only approximately linear with a slight curvature. the output voltage is measured over different ranges of temperatures and fit with linear-least-square lines. after power-up and after switching the input channels of the adc, the temperature sensor output must be allowed to settle to its stab le value before it can be used as an accurate adc input. for an accurate measurement of the temper ature sensor by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 34 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.24 clocking and power control 8.24.1 clock generation 8.24.2 power domains the lpc11e6x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the backup registers. the vbat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. the device core power (v dd ) is used to operate the rtc whenever v dd is present. therefor e, there is no power drain from the rtc battery when v dd is available and v dd ? vbat + 0.3 v. fig 10. clock generation watchdog oscillator irc oscillator system clock divider sysahbclkctrl (ahb clock enable) cpu, system control, pmu memories, peripheral clocks ssp0 peripheral clock divider ssp0 ssp1 peripheral clock divider ssp1 usart0 peripheral clock divider usart0 wdt wdclksel (wdt clock select) clkoutsel (clkout clock select) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin rtc oscillator, 32 khz output rtcoscctrl (rtc osc enable) system clock system pll irc system oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) main clock irc n clock divider frgclkdiv usart1 usart2 usart3 usart4 ioconclkdiv clock divider iocon glitch filter 7 fractional rate generator aaa-011053
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 35 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.24.3 integrated oscillators the lpc11e6x include the fo llowing independent oscillators: the system oscillator, the internal rc oscillator (irc), the watchdog oscillator, and the 32 khz rtc oscillator. each oscillator can be used for more than one purpo se as required in a pa rticular application. following reset, the lpc11e6x o perates from the internal rc oscillator until software switches to a different clock source. the ir c allows the system to operate without any external crystal and the bootloader co de to operate at a known frequency. see figure 10 for an overview of the lpc11e6x clock generation. 8.24.3.1 internal rc oscillator the irc can be used as the clock source fo r the wdt or as the clock that drives the system pll and then the cpu. the nominal irc frequency is 12 mhz. upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc11e6x use the irc as the clock source. software can later switch to one of the other available clock sources. 8.24.3.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. fig 11. power distribution real-time clock backup registers wake-up control regulator 32 khz oscillator always-on/rtc power domain main power domain rtcxin vbat vdd rtcxout vdd vss to memories, peripherals, oscillators, pll to core to i/o pads adc temp sense adc power domain vdda vssa lpc11e6x ultra low-power regulator wakeup aaa-011054
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 36 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. the system oscillator has a wake -up time of approximately 500 s. 8.24.3.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 9.4 khz and 2.3 mhz. th e frequency spread over processing and temperature is ? 40 % (see also ta b l e 1 4 ). 8.24.3.4 rtc oscillator the low-power rtc osc illator provides a 1 hz clock and a 1 khz clock to the rtc and a 32 khz clock output that can be used to obtain the main clock (see figure 10 ). 8.24.4 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz. to support this frequency range, an additional divider keeps the cco within its frequency range while the pll is providing the desired output frequency. the output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset. software can enable the pll later. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 8.24.5 clock output the lpc11e6x feature a clock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 8.24.6 wake-up process the lpc11e6x begin operation by using the 12 mhz irc oscillator as the clock source at power-up and when awakened from deep power-down mode. this mechanism allows chip operation to resume quickl y. if the application uses the main oscillator or the pll, software must enable these comp onents and wait for them to stabilize. only then can the system use the pll and main os cillator as a clock source. 8.24.7 power control the lpc11e6x support various power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock rate can also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this power cont rol mechanism allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals. this register allows fine-tuning of power
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 37 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control. 8.24.7.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc11e6x for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 8.24.7.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and can generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses. 8.24.7.3 deep-sleep mode in deep-sleep mode, the lpc11e6x is in sleep-mode and all peripheral clocks and all clock sources are off except for the irc. the irc output is disabled unless the irc is selected as input to the watchdog timer. in addition all analog blocks are shut down and the flash is in stand-by mode. in deep-sleep mode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc11e6x can wake up from deep-sleep mode via reset, selected gpio pins, a watchdog timer interrupt, an rtc interrupt, or any interrupts that the usart1 to usart4 interfaces can create in deep-sleep mode. the usart wake-up requires the 32 khz mode, the synchronous mode, or the cts interrupt to be set up. deep-sleep mode saves power and allows for short wake-up times. 8.24.7.4 power-down mode in power-down mode, the lpc11e6x is in sleep-mode and all peripheral clocks and all clock sources are off except for watchdog os cillator if selected. in addition all analog blocks and the flash are shut down. in powe r-down mode, the application can keep the bod circuit running for bod protection.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 38 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller the lpc11e6x can wake up from power-down mode via reset, selected gpio pins, a watchdog timer interrupt, an rtc interrupt, or any interrupts that the usart1 to usart4 interfaces can create in power-down mo de. the usart wake-up requires the 32 khz mode, the synchronous mode, or the cts interrupt to be set up. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 8.24.7.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin and the always-on rtc power domain. the lpc11e6x can wake up from deep power-down mode via the wakeup pin or a wake-up signal generated by the rtc interrupt. the lpc11e6x can be blocked from entering d eep power-down mode by setting a lock bit in the pmu block. blocking the deep power-down mode enables the application to keep the watchdog timer or the bod running at all times. if the wakeup pin is used in th e application, an ex ternal pull-up resist or is required on the wakeup pin to hold it h igh while the part is in deep power-down mode. to wake up from deep power-down mode, pull the wakeup pin low. in addition, pull the reset pin high to prevent it from floating while in deep power-down mode. 8.25 system control 8.25.1 reset reset has four sources on the lpc11e6x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been initialized to predetermined values. the internal reset status is reflected on the rstout pin. in deep power-down mode, an external pull-up resistor is required on the reset pin. the reset pin is operational in active, sleep, deep-sleep, and power-down modes if the reset function is selected in the iocon regist er for pin pio0_0 (this is the default). a low-going pulse as short as 50 ns executes the reset and also wakes up the part if in sleep, deep-sleep or power-down mode. the reset pin is not functional in deep power-down mode.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 39 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 8.25.2 brownout detection the lpc11e6x includes two levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic to cause a cpu interrupt. alternatively, so ftware can monitor the signal by reading a dedicated status register. two threshold levels can be selected to cause a forced reset of the chip. 8.25.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details, see the lpc11u6x/e6x user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart. fig 12. reset pin configuration 9 66 uhvhw ddd 9 '' 9 '' 9 '' 5 sx (6' (6' qv5& */,7&+),/7(5 3,1
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 40 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details, see the lpc11u6x/ex user manual . 8.26 emulation and debugging debug functions are integrated into the arm cortex-m0+. serial wire debug functions are supported in addition to a standard jtag boundary scan. the arm cortex-m0+ is configured to support up to four breakpoints and two watch points. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc11e6x is in reset. to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 41 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 9. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 8 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins ex cept true open-drain pins pio0_4 and pio0_5. [4] including the voltage on outputs in 3-state mode. [5] v dd(io) present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd(io) is powered down. table 6. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage [2] ? 0.5 4.6 v v dda analog supply voltage ? 0.5 4.6 v v ref reference voltage on pin vrefp ? 0.5 4.6 v v bat battery supply voltage ? 0.5 4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(io) supply voltage is present [3] [4] ? 0.5 +5.5 v on open-drain i2c-bus pins pio0_4 and pio0_5 [5] ? 0.5 +5.5 v v ia analog input voltage [6] [7] ? 0.5 4.6 v v i(xtal) crystal input voltage pins configured for xtalin and xtalout [2] ? 0.5 +2.5 v v i(rtcx) 32 khz oscillator input voltage [2] ? 0.5 4.6 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ? c - 100 ma t stg storage temperature [8] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [9] -3k v
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 42 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [6] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [7] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [8] dependent on package type. [9] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 10. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. table 7. thermal resistance value (c/w): 15 % symbol parameter conditions typ unit lqfp48 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 67 ?c/w 1 m/s 58 ?c/w 2.5 m/s 53 ?c/w 8-layer (4.5 in ? 3 in) 0 m/s 100 ?c/w 1 m/s 79 ?c/w 2.5 m/s 71 ?c/w ? jc thermal resistance junction-to-case 15 ?c/w ? jb thermal resistance junction-to-board 19 ?c/w lqfp64 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 58 ?c/w 1 m/s 51 ?c/w 2.5 m/s 47 ?c/w 8-layer (4.5 in ? 3 in) 0 m/s 81 ?c/w 1 m/s 66 ?c/w 2.5 m/s 60 ?c/w t j t amb p d r th j a ? ?? ? ?? +=
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 43 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 11. static characteristics ? jc thermal resistance junction-to-case 18 ?c/w ? jb thermal resistance junction-to-board 23 ?c/w lqfp100 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 49 ?c/w 1 m/s 44 ?c/w 2.5 m/s 41 ?c/w 8-layer (4.5 in ? 3 in) 0 m/s 66 ?c/w 1 m/s 55 ?c/w 2.5 m/s 51 ?c/w ? jc thermal resistance junction-to-case 18 ?c/w ? jb thermal resistance junction-to-board 24 ?c/w table 7. thermal resistance value (c/w): 15 % symbol parameter conditions typ unit table 8. static characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 2.4 3.3 3.6 v v dda analog supply voltage 2.4 3.3 3.6 v v ref reference voltage on pin vrefp 2.4 - v dda v v bat battery supply voltage 2.4 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz; default mode; v dd = 3.3 v [2] [3] [4] [6] [7] -2.3- ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.5- ma system clock = 50 mhz; default mode; v dd = 3.3 v [2] [3] [6] [7] [9] -7.8- ma system clock = 50 mhz; low-current mode; v dd = 3.3 v [2] [3] [6] [7] [9] -6.4- ma
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 44 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller i dd supply current sleep mode; system clock = 12 mhz; default mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.2- ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [2] [3] [4] [6] [7] -0.8- ma system clock = 50 mhz; default mode; v dd = 3.3 v [2] [3] [9] [6] [7] -3.3- ma system clock = 50 mhz; low-current mode; v dd = 3.3 v [2] [3] [9] [6] [7] -2.8- ma i dd supply current deep-sleep mode; v dd = 3.3 v; t amb =25 ?c [2] [3] [10] -275350 ? a t amb =105 ?c- - 6 4 0 ? a i dd supply current power-down mode; v dd = 3.3 v t amb =25 ?c [2] [3] [10] -522 ? a t amb =105 ?c- - 1 3 0 ? a i dd supply current deep power-down mode; v dd = 3.3 v; vbat = 0 or vbat = 3.0 v rtc oscillator running t amb =25 ?c [2] [11] -1.25 ? a t amb =105 ?c- - 1 4 rtc oscillator input grounded [2] [11] -550- na i bat battery supply current deep power-down mode; v dd = v dda = 3.3 v; vbat = 3.0 v; rtc oscillator running -0- - rtc off - 0 - - i bat battery supply current v dd = v dda = 0 v; vbat = 3.0 v rtc oscillator running - 1.2 - ? a standard port pins configured as digital pins, reset ; see figure 13 i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510 na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510 na v i input voltage v dd ? 2.4 v; 5 v tolerant pins [13] [14] 0-5 v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd -- v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage 0.05v dd -- v table 8. static characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 45 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller v oh high-level output voltage i oh =4 ma v dd ? 0.4 - - v v ol low-level output voltage i ol =4 ma - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 4 - - ma i ol low-level output current v ol =0.4v 4 - - ma i ohs high-level short-circuit output current v oh =0v [15] --45 ma i ols low-level short-circuit output current v ol =v dd [15] --50 ma i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v; 2.4 v ? v dd ? 3.6 v ? 10 ? 50 ? 85 ? a v dd lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 46 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] system oscillator enabled; i rc disabled; system pll disabled. [6] bod disabled. [7] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to usart, clkout, and iocon disabled in system configuration block. [8] irc enabled; system oscillator disabled; system pll enabled. [9] irc disabled; system oscill ator enabled; system pll enabled. [10] all oscillators and analog blocks turned off. [11] wakeup pin pulled high externally. [12] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [13] including voltage on outputs in tri-state mode. [14] tri-state outputs go into tri-state mode in deep power-down mode. i pd pull-down current v i =5v [16] 10 50 150 ? a i pu pull-up current v i =0v [16] ? 10 ? 50 ? 85 ? a v dd lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 47 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [15] allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] pull-up and pull-down currents are measured across t he weak internal pull-up/pull-down resistors. see figure 13 . [17] to v ss . [18] the parameter values specified are simulated and absolute values. [19] the input voltage of the rtc oscillator is limited as follows: v i(rtcx) , v o(rtcx) < max(vbat, v dd ). [20] including bonding pad capacitance. fig 13. pin input/output current measurement aaa-010819 + - pin pio0_n i oh i pu - + pin pio0_n i ol i pd v dd a a
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 48 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 11.1 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f), all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 50 mhz: irc disabled; pll enabled; sysosc enabled. fig 14. active mode: typical supply current i dd versus supply voltage v dd ddd 9 '' 9 , '' '' , '' p$ p$ p$ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+]
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 49 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regi ster (sysahbclkctrl = 0x1f; all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 50 mhz: irc disabled; pll enabled; sysosc enabled. fig 15. active mode: typical supply current i dd versus temperature conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f) all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 48 mhz: irc disabled; pll enabled; sysosc enabled. fig 16. sleep mode: typical supply current i dd versus temperature for different system clock frequencies ddd whpshudwxuh?& , '' '' , '' p$ p$ p$ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] ddd ?& 0+] 0+] 0+] p$ p$ p$ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+]
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 50 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller conditions: bod disabled; all osc illators and analog blocks disabled fig 17. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd conditions: bod disabled; all oscill ators and analog blocks disabled; v dd = 2.4 v to 3.6 v. fig 18. power-down mode: typical supply current i dd versus temperature for different supply voltages v dd ddd 7?& , '' '' , '' $ $ $ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ddd 7?& , '' '' , '' $ $ $
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 51 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller conditions: rtc running; vbat = 0 v fig 19. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd conditions: rtc not running; v bat = 3.0 v; v dd floating. fig 20. deep power-down mode: typical battery supply current i bat versus temperature ddd 7?& , '' '' , '' $ $ $ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ddd 7?& , %$7 %$7 , %$7 $ $ $
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 52 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 11.2 coremark data the coremark scores serve as a guideline to select the best power mode for a given application. to find the most suitable power mode, run the application in mode and compare power consumption and performance. measured with keil uvision v.4.72 . measured with keil uvision v.4.60. conditions: conditions: v dd = 3.3 v; active mode; all peripherals exc ept one uart and the sctimer disabled in the sysahbclkctrl register; internal pull-up resistors enabled; bod disabled. fig 21. coremark score for different power mode settings of the power profiles aaa-011173 0 10 20 30 40 50 1 1.25 1.5 1.75 2 2.25 2.5 system clock frequency (mhz) cm cm cm (((iterations/s)/mhz)) (((iterations/s)/mhz)) (((iterations/s)/mhz)) cpu performance cpu performance cpu performance efficiency efficiency efficiency default/low-current default/low-current default/low-current aaa-011174 0 10 20 30 40 50 1 1.25 1.5 1.75 2 2.25 2.5 system clock frequency (mhz) cm cm cm (((iterations/s)/mhz)) (((iterations/s)/mhz)) (((iterations/s)/mhz)) cpu performance cpu performance cpu performance efficiency efficiency efficiency default/low-current default/low-current default/low-current measured with keil uvision v.4.72 . measured with keil uvision v.4.60. conditions: conditions: v dd = 3.3 v; active mode; all peripherals exc ept one uart and the sctimer disabled in the sysahbclkctrl register; internal pull-up resistors enabled; bod disabled. fig 22. active mode: coremark power consumption i dd for different power mode settings of the power profiles aaa-011175 0 10 20 30 40 50 0 2.5 5 7.5 10 12.5 15 system clock frequency (mhz) i dd dd i dd (ma) (ma) (ma) cpu performance cpu performance cpu performance default default default efficiency efficiency efficiency low-current low-current low-current aaa-011176 0 10 20 30 40 50 0 2.5 5 7.5 10 12.5 15 system clock frequency (mhz) i dd dd i dd (ma) (ma) (ma) default default default cpu performance cpu performance cpu performance efficiency efficiency efficiency low-current low-current low-current
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 53 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller the power profiles optimize the chip performance for power consumption or core efficiency by controlling the flash a ccess and core power. as shown in figure 21 and figure 22 , different power modes result in different coremark scores reflecting the trade-off of efficiency and power consumption. in cpu and efficiency modes, the power profiles aim to keep the core efficiency at a maximum for the given system frequency. depending on optimal flash access parameters that change with frequency, the coremark score and also the power consumption change. since the compiled code for coremark testing runs out of flash memory, the core mark score depends on the compiler version. 11.3 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code accessing the periphera l is executed except for the adc. measured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator and pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. table 9. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.24 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.28 - - irc runnin g; pll off; independent of main clock frequency. watchdog oscillator at 600 khz/2 0 - - system oscillator running; pll off; independent of main clock frequency. bod 0.05 - - independent of main clock frequency. system pll 0.25 - - - clkout - 0.25 0.89 system pll is source of clkout. rom - 0.09 0.37 - flashreg - 0.17 0.66 - flasharray - 0.13 0.52 - sram1 - 0.15 0.59 - sram2 - 0.14 0.56 - gpio + pin interrupt/pattern match - 0.18 0.69 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. iocon - 0.08 0.30 - sctimer0/pwm + sctimer1/pwm - 0.29 1.1 - ct16b0 - 0.05 0.17 - ct16b1 - 0.04 0.16 - ct32b0 - 0.04 0.13 - ct32b1 - 0.03 0.13 - rtc - 0.02 0.10 -
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 54 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller wwdt - 0.05 0.17 main clock select ed as clock source for the wdt. i2c0 - 0.05 0.22 - i2c1 - 0.05 0.18 - ssp0 - 0.15 0.59 - ssp1 - 0.15 0.58 - usart0 - 0.31 1.19 - usart1 - 0.12 0.50 - usart2 - 0.13 0.49 - usart3 + usart4 - 0.21 0.81 - adc0 - 2.15 2.68 register interface disabled in sysahbclkctrl and ana log block disabled in pdruncfg registers. power consumption measured while the adc is sampling a single channel with an adc clock of 12 mhz or 48 mhz. temperature sensor 0.18 - - - dma - 0.28 1.1 - crc - 0.04 0.14 - table 9. power consumption for individual analog and digital blocks ?continued peripheral typical supply current in ma notes n/a 12 mhz 48 mhz
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 55 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 11.4 electrical pin characteristics conditions: v dd = 2.4 v; on pin pio0_7 and pio1_31. conditions: v dd = 3.3 v; on pin pio0_7 and pio1_31. fig 23. high-drive output: typical high-level output voltage v oh versus high-level output current i oh ddd , 2+ p$ 9 2+ 2+ 9 2+ 9 9 9 9 ?& 9 ?& 9?& 9?& 9?& 9 ?& 9?& 9?& ddd , 2+ p$ 9 2+ 2+ 9 2+ 9 9 9 9 & 9 & 9 ?& 9 & 9 & 9 ?& 9 & 9 & 9 ?& 9 & 9 & 9 ?& conditions: v dd = 2.4 v; on pins pio0_4 and pio0_5. conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 24. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2/ , 2/ p$ p$ p$ 9& 9& 9 ?& 9& 9& 9?& 9& 9& 9?& 9& 9& 9?& ddd 9 2/ 9 , 2/ 2/ , 2/ p$ p$ p$ 9 & 9 & 9? & 9 & 9 & 9? & 9 & 9 & 9? & 9 & 9 & 9? &
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 56 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 2.4 v; standard port pins and high-drive pins pio0_7 and pio1_31. conditions: v dd = 3.3 v; standard port pins and high-drive pins pio0_7 and pio1_31. fig 25. typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2/ , 2/ p$ p$ p$ 9 & 9 & 9 ?& 9 & 9 & 9 ?& 9 & 9 & 9 ?& 9 & 9 & 9 ?& ddd 9 2/ 9 , 2/ 2/ , 2/ p$ p$ p$ 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& conditions: v dd = 2.4 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 26. typical high-level output voltage v oh versus high-level output source current i oh ddd , 2+ p$ 9 2+ 2+ 9 2+ 9 9 9 9 9 & 9?& 9 9 & 9?& 9 9 & 9?& 9 9 & 9?& ddd , 2+ p$ 9 2+ 2+ 9 2+ 9 9 9 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?&
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 57 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 2.4 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 27. typical pull-up current i pu versus input voltage v i ddd 9 , 9 , 38 38 , 38 $ $ $ 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& ddd 9 , 9 , 38 38 , 38 $ $ $ 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& conditions: v dd = 2.4 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 28. typical pull-down current i pd versus input voltage v i ddd 9 , 9 , 3' 3' , 3' $ $ $ 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& ddd 9 , 9 , 3' 3' , 3' $ $ $ 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?& 9 & 9 & 9?&
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 58 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 12. dynamic characteristics 12.1 flash/eeprom memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes to the flash. t amb <= +85 ? c. flash programming with iap calls (see lpc11e6x user manual ). 12.2 external clock for th e oscillator in slave mode remark: the input voltage on the xtal1/2 pins must be ? 1.95 v (see table 8 ). for connecting the oscillator to the xtal pins, also see section 14.3 . [1] parameters are valid over operating temp erature range unless otherwise specified. table 10. flash characteristics t amb = ? 40 ? c to +105 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 20 - years unpowered 20 40 - years t er erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 11. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd = 2.7 v to 3.6 v. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance 100000 1000000 - cycles t ret retention time powered 100 200 - years unpowered 150 300 - years t prog programming time 64 bytes - 2.9 - ms table 12. dynamic characteristic : external clock (xtalin input) t amb = ? 40 ? c to +105 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 59 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. 12.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. fig 29. external clock timing (with an amplitude of at least v i(rms) = 200 mv) w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ ddd table 13. dynamic char acteristics: irc t amb = ? 40 ? c to +105 ? c; 2.7 v ? v dd ? 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency ? 25 ?c ? t amb ? +85 ? c 12 - 1 % 12 12 + 1 % mhz ? 40 ?c ? t amb < ? 25 ? c 12 - 2 % 12 12 + 1 % mhz 85 ?c < t amb ? 105 ? c 12 - 1.5 % 12 12 + 1.5 % mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?25 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 30. typical internal rc oscillator frequency versus temperature ddd whpshudwxuh?& i i 0+] 0+] 0+] 9 9 9 9 9 9 9 9 9 9 9 9
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 60 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +105 ? c) is ? 40 %. [3] see the lpc11e6x user manual. 12.4 i/o pins [1] applies to standard port pins and reset pin. 12.5 i 2 c-bus table 14. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4-khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz table 15. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +105 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 16. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus; on pins pio0_4 and pio0_5 01mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus; on pins pio0_4 and pio0_5 - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus; on pins pio0_4 and pio0_5 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus; on pins pio0_4 and pio0_5 0.26 - ? s
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 61 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with res pect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus; on pins pio0_4 and pio0_5 0- ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus; on pins pio0_4 and pio0_5 50 - ns table 16. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c. [2] symbol parameter conditions min max unit
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 62 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 31. i 2 c-bus pins clock timing ddd w i 6'$ w i 6 w +''$7 6&/ i 6&/ w 9''$7 w +,*+ w /2: w 68'$7
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 63 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 12.6 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 105 ? c; 2.4 v ? v dd ? 3.6 v. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd = 3.3 v. table 17. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (i n spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns t ds data set-up time in spi mode [2] 15 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns fig 32. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 64 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 33. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 65 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 12.7 usart interface the maximum usart bit rate for all usarts is 3.125 mbit/s in asynchronous mode and 10 mbit/s in synchronous slave and master mode. [1] t cy(clk) = (main clock cycle time)/(uartclkdiv x 2 x (256 x dlm + dll)). see the lpc11e6x user manual um10732 . [1] t cy(clk) = u_pclk/brgval. see the lpc11e6x user manual um10732 . table 18. usart dynamic characteristics usart0 t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v; c l = 10 pf. simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter min max unit t cy(clk) clock cycle time [1] 100 - ns usart master (in synchronous mode) t su(d) data input set-up time 44 - ns t h(d) data input hold time 0 - ns t v(q) data output valid time - 10 ns t h(q) data output hold time 0 - ns usart slave (in synchronous mode) t su(d) data input set-up time 5 - ns t h(d) data input hold time 20 - ns t v(q) data output valid time - 40 ns t h(q) data output hold time 25 - ns table 19. usart dynamic char acteristics usart1/2/3/4 t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v; c l = 10 pf. simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter min max unit t cy(clk) clock cycle time [1] 100 - ns usart master (in synchronous mode) t su(d) data input set-up time 44 - ns t h(d) data input hold time 0 - ns t v(q) data output valid time - 10 ns t h(q) data output hold time 0 - ns usart slave (in synchronous mode) t su(d) data input set-up time 5 - ns t h(d) data input hold time 0 - ns t v(q) data output valid time - 40 ns t h(q) data output hold time 20 - ns
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 66 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 12.8 sctimer/pwm output timing to estimate the skew between different outputs, compare the worst case to worst case (or best case to best case) values of individual pins. fig 34. usart timing 8qb6&/.&/.32/ 7;' 5;' 7 f\fon w vx' w k' w y4 67$57 %,7 w k4 8qb6&/.&/.32/ 67$57 %,7 %,7 %,7 ddd table 20. sctimer/pwm output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v. simulated skew (over process, voltage, and temperature) between any two sct outputs; sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter min max unit sctimer0/pwm t sk(o) output skew time < 1 2 ns sctimer1/pwm t sk(o) output skew time < 1 2 ns
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 67 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 13. characteristics of analog peripherals [1] interrupt and reset levels are selected by writing t he level value to the bod control register bodctrl, see the lpc11e6x user manual . interrupt levels 0 and 1 are reserved. table 21. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 2 assertion - 2.54 - v de-assertion - 2.68 - v interrupt level 3 assertion - 2.82 - v de-assertion - 2.93 - v reset level 2 assertion - 2.34 - v de-assertion - 2.49 - v reset level 3 assertion - 2.62 - v de-assertion - 2.77 - v
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 68 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the input resistance of adc channel 0 is higher than for all other channels. [3] c ia represents the external capacitance on the analog input channel for sampling speeds of 2 msamples/s. [4] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 35 . [5] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 35 . [6] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 35 . [7] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 35 . [8] t amb = 25 ? c; maximum sampling frequency f s = 2 msamples/s and analog input capacitance c ia =0.1pf. [9] input resistance z i is inversely proportional to the sampling freq uency and the total input capacity including c ia : z i ? 1 / (f s ? c i ). see figure 36 ? adc input impedance ? . table 22. 12-bit adc stat ic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 2.4 v to 3.6 v; vrefp = v dda ; v ssa = 0; vrefn = v ssa . adc calibrated at t = 25 ?? c. symbol parameter conditions min typ [1] max unit v ia analog input voltage [2] 0- v dda v c ia analog input capacitance [3] --0.1pf f clk(adc) adc clock frequency v dda ??? 2.7 v 50 mhz v dda ??? 2.4 v 25 mhz f s sampling frequency v dda ??? 2.7 v - - 2 msamples/s v dda ??? 2.4 v - - 1 msamples/s e d differential linearity error [4] -- ? 2.5 lsb e l(adj) integral non-linearity [5] -- ? 2.5 lsb e o offset error [6] -- ? 4.5 lsb v err(fs) full-scale error voltage [7] -- ? 0.5 % z i input impedance f s = 2 msamples/s [8][9] 0.1 - - m ?
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 69 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 35. 12-bit adc characteristics 002aaf436 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - v ss 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 70 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [1] absolute temperature accuracy. [2] typical values are deriv ed from nominal simulation (v dda = 3.3 v; t amb = 27 ? c; nominal process models). fig 36. adc input impedance table 23. temperature sensor stati c and dynamic characteristics v dda = 2.4 v to 3.6 v symbol parameter conditions min typ max unit dt sen sensor temperature accuracy t amb = ? 40 ? c to +105 ?c [1] - ? 5- ?c e l linearity error t amb = ? 40 ? c to +105 ?c- ? 4- ?c t s(pu) power-up settling time to 99% of temperature sensor output value [2] -14 - ? s table 24. temperature sensor linear-least-square (lls) fit parameters v dda = 2.4 v to 3.6 v fit parameter range min typ max unit lls slope t amb = ? 40 ? c to +105 ?c- ? 2.36 - mv/ ?c lls intercept t amb = ? 40 ? c to +105 ? c - 606 - mv dac adc r sw = 5 ...25 r 1 = 0.25 k...2.5 k c ia c dac adcn_0 adcn_[1:11] aaa-011748 c io c io
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 71 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 14. application information 14.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 2 2 : ? the adc input trace must be short and as close as possible to the lpc11e6x chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? if the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 14.2 typical wake-up times [1] the wake-up time measured is the time between when a gpio input pin is trigger ed to wake the device up from the low power modes and from when a gpio output pin is set in the interrupt service routine (isr) wake-up handler. [2] irc enabled, all peripherals off. v dda = 3.3 v; measured on a typical silicon sample. fig 37. typical lls fit of the temperature sensor output voltage ddd whpshudwxuh?& 9 2 9 2 p9 p9 p9 table 25. typical wake-up times v dd = 3.3 v; t amb = 25 c. power modes wake-up time sleep mode (12 mhz) [1] [2] 2.6 ? s deep-sleep mode [1] [3] 4.4 ? s power-down mode [1] [3] 86.8 ? s deep power-down mode [4] 276 ? s
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 72 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller [3] watchdog oscillator disabled, brown-out detect (bod) disabled. [4] wake-up from deep power-down causes the part to go through entire reset process. the wake-up time measured is the time between when a wake-up pin is tr iggered to wake the device up from the low power modes and when a gpio output pin is set in the reset handler. 14.3 xtal input and crystal osci llator component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 38 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 39 and in ta b l e 2 6 and ta b l e 2 7 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 39 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 2 6 ). fig 38. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 73 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 14.4 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plane. loops must be made as small as possible in fig 39. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 26. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz to 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz to 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz to 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz to 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 27. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz to 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz to 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 74 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as po ssible. smaller values of c x1 and c x2 should be chosen according to the increase in parasitics of the pcb layout. 14.5 rtc oscillator component selection the 32 khz crystal must be connected to the part via the rtcxin and rtcxout pins as shown in figure 40 . if the rtc is not used, the rtcxin pin can be grounded. select c x1 and c x2 based on the external 32 khz crystal used in the application circuitry.the pad capacitance c p of the rtcxin and rtcxout pad is 3 pf. if the external crystal?s load capacitance is c l , the optimal c x1 and c x2 can be selected as: c x1 = c x2 = 2 x c l ? c p fig 40. rtc oscillator components lpc1xxx rtcxin rtcxout c x2 c x1 xtal = c l c p r s l aaa-010822
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 75 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 15. package outline fig 41. package outline lqfp48 (sot313-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 76 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 42. package outline lqfp64 (sot314-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 77 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 43. package outline lqfp100 (sot407-1) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1)(1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 78 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 16. soldering fig 44. reflow soldering for the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 79 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 45. reflow soldering for the lqfp64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 80 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller fig 46. reflow soldering for the lqfp100 package sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 81 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 17. abbreviations 18. references [1] lpc11u6x/e6x user manual um10732: http://www.nxp.com/documen ts/user_manual/um10732.pdf [2] lpc11e6x errata sheet: http://www.nxp.com/documents /errata_sheet/es_lpc11e6x.pdf table 28. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection gpio general purpose input/output pll phase-locked loop rc resistor-capacitor spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port uart universal asynchronous receiver/transmitter
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 82 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 19. revision history table 29. revision history document id release date data sheet status change notice supersedes lpc11e6x v.1.1 20140417 product data sheet - lpc11e6x v.1 modifications: ? data sheet status changed to product data sheet. ? section 5 ? marking ? updated with revision information. lpc11e6x v.1 20140326 objective data sheet - -
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 83 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 84 of 86 nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc11e6x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 1.1 ? 17 april 2014 85 of 86 continued >> nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.1 product identification . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 functional description . . . . . . . . . . . . . . . . . . 18 8.1 arm cortex-m0+ core . . . . . . . . . . . . . . . . . . 18 8.2 ahb multilayer matrix . . . . . . . . . . . . . . . . . . . 18 8.3 on-chip flash programming memory . . . . . . . 20 8.4 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.5 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.6 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.7 memory mapping . . . . . . . . . . . . . . . . . . . . . . 20 8.8 nested vectored interrupt controller (nvic) . 21 8.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.8.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 22 8.9 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9.2 standard i/o pad configuration . . . . . . . . . . . . 23 8.10 fast general-purpose parallel i/o (gpio) . . . 23 8.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.11 pin interrupt/pattern match engine . . . . . . . . . 24 8.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.12 gpio group interrupts. . . . . . . . . . . . . . . . . . . 25 8.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.13 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 25 8.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.14 usart0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.15 usart1/2/3/4. . . . . . . . . . . . . . . . . . . . . . . . . 26 8.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.16 ssp serial i/o controller (ssp0/1) . . . . . . . . . 27 8.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.17 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 28 8.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.18 timer/pwm subsystem. . . . . . . . . . . . . . . . . . 28 8.18.1 state configurable timers (sctimer0/pwm and sctimer1/pwm) . . . . . . . . . . . . . . . . . . . 30 8.18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18.2 general purpose external event counter/timers (ct32b0/1 and ct16b0/1) . . . . . . . . . . . . . . 31 8.18.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 system tick timer (systick) . . . . . . . . . . . . . . 31 8.20 windowed watchdog ti mer (wwdt) . . . . . . 31 8.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 real-time clock (rtc) . . . . . . . . . . . . . . . . . 32 8.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.22 analog-to-digital converter (adc). . . . . . . . . 32 8.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.23 temperature sensor . . . . . . . . . . . . . . . . . . . . 33 8.24 clocking and power control . . . . . . . . . . . . . . 34 8.24.1 clock generation . . . . . . . . . . . . . . . . . . . . . . 34 8.24.2 power domains . . . . . . . . . . . . . . . . . . . . . . . 34 8.24.3 integrated oscillators . . . . . . . . . . . . . . . . . . . 35 8.24.3.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 35 8.24.3.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 35 8.24.3.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 36 8.24.3.4 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 36 8.24.4 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.24.5 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.24.6 wake-up process . . . . . . . . . . . . . . . . . . . . . . 36 8.24.7 power control . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.24.7.1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 37 8.24.7.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.24.7.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 37 8.24.7.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 37 8.24.7.5 deep power-down mode . . . . . . . . . . . . . . . . 38 8.25 system control . . . . . . . . . . . . . . . . . . . . . . . . 38 8.25.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.25.2 brownout detection . . . . . . . . . . . . . . . . . . . . 39 8.25.3 code security (code read protection - crp) 39 8.26 emulation and debugging . . . . . . . . . . . . . . . 40 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41 10 thermal characteristics . . . . . . . . . . . . . . . . . 42 11 static characteristics . . . . . . . . . . . . . . . . . . . 43 11.1 power consumption . . . . . . . . . . . . . . . . . . . . 48 11.2 coremark data . . . . . . . . . . . . . . . . . . . . . . . . 52 11.3 peripheral power consumption . . . . . . . . . . . 53 11.4 electrical pin characteristics. . . . . . . . . . . . . . 55 12 dynamic characteristics. . . . . . . . . . . . . . . . . 58 12.1 flash/eeprom memory . . . . . . . . . . . . . . . . 58 12.2 external clock for the oscillator in slave mode 58 12.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 59 12.4 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.6 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 63
nxp semiconductors lpc11e6x 32-bit arm cortex-m0+ microcontroller ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 april 2014 document identifier: lpc11e6x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 12.7 usart interface. . . . . . . . . . . . . . . . . . . . . . . 65 12.8 sctimer/pwm output timing . . . . . . . . . . . . . 66 13 characteristics of analog peripherals . . . . . . 67 14 application information. . . . . . . . . . . . . . . . . . 71 14.1 adc usage notes . . . . . . . . . . . . . . . . . . . . . . 71 14.2 typical wake-up times . . . . . . . . . . . . . . . . . . 71 14.3 xtal input and crystal oscillator component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.4 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.5 rtc oscillator component selection . . . . . . . . 74 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 75 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 82 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 83 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 83 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21 contact information. . . . . . . . . . . . . . . . . . . . . 84 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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