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? semiconductor components industries, llc, 2014 may, 2014 ? rev. 2 1 publication order number: NCP1032/d NCP1032 low power pwm controller with on-chip power switch and startup circuits for telecom systems the NCP1032 is a miniature high?voltage monolithic switching converter with on?chip power switch and startup circuits. it incorporates in a single ic all the active power control logic and protection circuitry required to implement, with minimal external components several switching regulator applications, such as a secondary side bias supply or a low power dc?dc converter. this converter is ideally suited for 24 v and 48 v telecom and medical isolated power supply applications. the NCP1032 can be configured in any single?ended topology such as forward or flyback converter. the NCP1032 is targeted for applications requiring up to 3 w. the internal error amplifier allows the NCP1032 to be easily configured for secondary or primary side regulation operation in isolated and non?isolated configurations. the fixed frequency oscillator is optimized for operation up to 1 mhz and is capable of external frequency synchronizati on, providing additional design flexibility. in addition, the NCP1032 incorporates undervoltage and overvoltage line detectors, programmable cycle?by?cycle current limit, internal soft?start, and thermal shutdown to protect the controller under fault conditions. features ? on chip high 200 v power switch circuit and startup circuit ? internal startup regulator with auxiliary winding override ? programmable oscillator frequency operation up to 1 mhz ? external frequency synchronization capability ? frequency fold?down under fault conditions ? trimmed 2% internal reference ? programmable cycle?by?cycle current limit ? internal soft?start ? active leading edge blanking circuit ? line under and over voltage protection ? over temperature protection ? these are pb?free devices typical applications ? poe (power over ethernet)/pd. refer to application note and8247 ? secondary side bias supply for isolated dc?dc converters ? stand alone low power dc?dc converter ? low power bias supply ? low power boost converter ? medical isolated power supplies ? bias supply for telecom systems. refer to app note and8119/d http://onsemi.com marking diagrams 1032 = specific device marking x = a or b a = assembly location l = wafer lot y = year w = work week = pb?free package pin connections (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. ordering information wdfn8 mn suffix case 511bh 1032x alyw ?? ?? ?? ?? ? ? ? ? wdfn8 (top view) gnd gnd c t v fb comp v cc v drain cl uv/ov 1
NCP1032 http://onsemi.com 2 figure 1. typical application ? dual output auxiliary regulated isolated flyback d1 d2 cout cvcc cin r3 r4 rcl cct cc rc cp r1 r2 ncp 1032 vdrain vcc cl comp vfb gnd ct uv/ov vin vout 2.2 f 22 f 2.2 f figure 2. NCP1032 simplified block diagram i1 3.0 v/ 3.5 v s r pwm comp ncl nss 30 ns one shot ? + 2.5 v error amplifier ? + ? + 5.7 v ? + ? + uv comp ov comp 2.24 v i2 duty leb iset fb comp ov/uv 7.6 v 10.2 v fault logic nuvlo nlowvcc hivcc nuvlo nlowvcc hivcc in1 in2 in3 in4 uvbar uvbar nuv out2 nuv nov nov in5 in6 nstart fault fault fault lebout lebout current limit ss in7 thermal trip 12.5 ma pgnd vdrain out3 driver rt uvbar internal bias nstart vcc internal bias internal bias (all pins except vdrain pin are protected by 10 v esd diodes) cycle = 75% delay 2 k 2 k 1.0 v 2 k 2 k 2 k 3.5 v 150 k 2 k 6.6 v q set clr q
NCP1032 http://onsemi.com 3 table 1. functional pin description pin name function description 1 gnd ic ground ground reference pin for the circuit. 2 c t oscillator frequency selection an external capacitor connected to this pin sets the oscillator frequency up to 1 mhz. the oscillator can be synchronized to a higher frequency by charging or discharging ct to trip the internal 3.0 v/3.5 v comparators. if a fault condition exists, the power switch is disabled and the frequency is reduced. 3 v fb feedback signal input the regulated voltage is scaled down to 2.5 v by means of a resistor divider. regulation is achieved by comparing the scaled voltage to an internal 2.5 v reference. 4 comp error amplifier compensation the output of the internal error amplifier. external compensation network between comp and vfb pin is required for stable operation. 5 cl current limit threshold selection a resistor r cl connected between this pin and ground sets the peak current value of the current limit. if the cl pin is left open, the current limit value is set to its initial maximum value of approximately 12 ma (c lim_max ). programmable current limit threshold, together with internal soft?start feature effectively limits the primary transformer high current peaks during startup phase. 6 uv/ov input line undervoltage and overvoltage shutdown input line voltage is scaled down using an external resistor divider. the minimum operating vin voltage is achieved when the voltage on uv/ov pin reaches uv threshold 1.0 v. the maximum operating voltage is then limited by 2.4 v on uv/ov pin. a device version without ov protection feature is available, see ordering information section. 7 v cc powers the internal circuitry supplies power to the internal control circuitry. connect an external capacitor for energy storage during startup. the vcc voltage should not exceed 16 v during operation. 8 v drain drain connection connects the power switch and startup circuit to the primary transformer windings. ep ep thermal flag this is the thermal flag for the ic and should be soldered to the ground plane. table 2. maximum ratings rating symbol value unit power switch and startup circuits voltage bvdss ?0.3 to +200 v vcc power supply voltage v cc ?0.3 to +16 v power supply voltage on all pins, except vdrain and vcc v io ?0.3 to +10 v drain current peak during transformer saturation i ds(pk) 1.0 a thermal resistance junction?to?air ?w dfn8 3x3, case 511bh (100 sq mm, 2oz) (note 4) (500 sq mm, 2oz) (note 4) (100 sq mm,2oz,) (note 5) r ja 109 64 44 c/w maximum junction temperature t jmax 150 c storage temperature range t stg ?60 to +150 c esd capability, human body model pins 1?7 (note 1) 4.0 kv esd capability, machine model pins 1?7 (note 1) 400 v pin 8 is connected to the high voltage startup and power switch which is protected to the maximum drain voltage 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device series contains esd protection and passes the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 2. this device contains latch?up protection and it exceeds 100 ma per jedec standard: jesd78 class ii 3. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a 4. eia jedec 51.3, single layer pcb with added heat spreader 5. eia jedec 51.7, four layer pcb with added heat spreader
NCP1032 http://onsemi.com 4 table 3. electrical characteristics (for typical values tj = 25 c, for min/max values tj = ?40 c to +125 c, v drain = 48 v, v cc = 12 v, unless otherwise noted) symbol parameter conditions min typ max unit supply section and vcc management v cc_on vcc voltage at which the switcher starts operation v cc increasing 9.9 10.2 10.5 v v cc_min minimum operating vcc after turn on at which hv current source restarts v cc decreasing 7.40 7.55 7.7 v v cc_rst vcc undervoltage lockout voltage v cc decreasing, v fb = v comp 6.75 6.95 7.15 v i cc1 internal ic consumption power switch enabled mosfet is switching at 300 khz 2.0 2.9 4.0 ma i cc2 internal ic consumption power switch disabled no fault condition, v fb = 2.7 v ? 2.0 2.5 ma i cc3 internal ic consumption power switch disabled fault condition, v fb = 2.7 v, v uv/ov < 1.0 v ? 0.75 1.5 ma power switch circuit r dson power switch circuit on?state resistance i d = 100 ma t j = 25 c t j = 125 c ? ? 4.2 4.9 5.1 8.0 bvdss power switch circuit and startup breakdown voltage i ds_off = 100 a, v uv_ov < 1.0 v tj = 25 c 200 ? ? v i ds_off power switch circuit and startup circuit off?state leakage current v drain = 200 v, v uv_ov < 1.0 v t j = 25 c t j = ?40 c to 125 c ? ? 20 20 25 30 a t r switching characteristics ? rise time v ds = 48 v, r l = 480 , time (10%?90%) ? 7 ? ns t f switching characteristics ? fall time v ds = 48 v, r l = 480 , time (90%?10%) ? 10 ? ns internal startup current source i start1 hv current source vcc = 0 v, tj = 25 c tj = ?40 c to 125 c 10.0 9.0 12.0 ? 14.0 15.0 ma i start2 hv current source vcc = v cc_on ? 0.2 v tj = 25 c tj = ?40 c to 125 c 9.0 8.0 11.0 ? 13.0 16.0 ma v start_min minimum startup voltage i start2 = 0.5 ma, vcc = v cc_on ? 0.2 v, tj = 25 c ? 16.3 ? v error amplifier v ref reference voltage v comp = v fb , follower mode t j = 25 c t j = ?40 c to 125 c 2.45 2.40 2.5 2.5 2.55 2.60 v reg line line regulation v cc = 8 v to 16 v, t j = 25 c ? 1.0 3.0 mv i vfb input bias current v fb = 2.3 v ? 70 150 na i src comp source current v fb = 2.3 v 80 95 125 a i snk comp sink current v fb = 2.7 v 500 700 900 a v c_max comp maximum voltage i src = 0 a, v fb = 2.3 v 3.95 4.17 4.5 v v c_min comp minimum voltage i snk = 0 a, v fb = 2.7 v ? 91 200 mv a vol open loop voltage gain (note 6) ? 80 ? db gbw gain bandwidth product (note 6) ? 1.0 ? mhz
NCP1032 http://onsemi.com 5 table 3. electrical characteristics (for typical values tj = 25 c, for min/max values tj = ?40 c to +125 c, v drain = 48 v, v cc = 12 v, unless otherwise noted) symbol unit max typ min conditions parameter current limit and pwm comparator c lim_max max current limit threshold cl pin floating, t j = 25 c, (di/dt = 0.5 a/ s) 420 512 600 ma c lim_min min current limit threshold r cl = 20 k , t j = 25 c, (di/dt = 0.1 a/ s) ? 57 ? ma t plh propagation delay from current limit detection to the drain off state (note 6) ? 100 ? ns t on_min min on time pulse width fsw = 300 khz (note 6) ? 240 ? ns t ss soft?start duration (note 6) ? 2.0 ? ms line under/overvoltage protections v uv undervoltage lockout threshold v fb = v comp, vin decreasing 0.95 1.067 1.18 v v uv_hys undervoltage lockout hysteresis ? 70 ? mv iuv input bias current v fb = 2.3 v ? 0 1 a v ov overvoltage lockout threshold v fb = v comp, vin increasing (note 7) 2.3 2.41 2.5 v v ov_hys overvoltage lockout hysteresis ? 158 ? mv temperature management tsd thermal shutdown (note 6) 175 c hysteresis in shutdown (note 6) 20 c internal oscillator f osc1 oscillation frequency, 300 khz c t = 560 pf (note 9) t j = 25 c t j = ?40 c to 125 c 275 270 300 ? 325 335 khz f osc2 oscillation frequency, 960 khz c t = 100 pf, t j = 25 c ? 960 ? khz i ct_c timing charge current v ct = 3.25 v ? 172 ? a i ct_d timing discharge current v ct = 3.25 v 517 a v r_pk oscillator ramp peak voltage ? 3.492 ? v v r_vly oscillator ramp valley ? 2.992 ? v dc max maximum duty cycle 70 76.5 80 % product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. guaranteed by design and characterized 7. the ov/uv option is disabled on the NCP1032b version 8. oscillator frequency can be externally synchronized to the maximum frequency of the device
NCP1032 http://onsemi.com 6 typical operating characteristics ? dual output isolated flyback converter figure 3. efficiency vs. i out at v in = 24, 36, 48 and 72 v, t1 = coilcraft b0226?el figure 4. v cc pin load regulation at v in = 24, 36, 48 and 72 v i out (ma) i out (ma) 200 175 150 100 75 50 25 0 0 10 20 30 50 60 70 80 200 175 150 100 75 50 25 0 12.060 12.065 12.070 12.075 12.080 12.090 12.095 12.100 figure 5. startup sequence, r cl open, output load = 80 (i out = 150 ma), 1 v cc 3.0 v/ div dc, 2 v out 3.0 v/div dc, 3 v in 10.0 v/ div dc, 4 i pri 100 ma/div dc, t = 20 ms/div figure 6. soft?start, r cl open, output no load 1 v cc 3.0 v/div dc, 2 v out 3.0 v/div dc, 3 vin 10.0 v/div dc, 4 i pri 100 ma/div dc, t = 500 s/div figure 7. soft?start, r cl = 32 k (c lim = 250 ma), output load = 240 (i out = 50 ma), 1 v cc 3.0 v/div dc, 2 v out 3.0 v/div dc, 3 v in 10.0 v/div dc, 4 i pri 100 ma/div dc, t = 1.0 ms/div figure 8. discontinuous conduction mode (dcm), i out = 150 ma, 2 v drain 20 v/div dc, 3 i sec 30 ma/div dc, 4 i pri 100 ma/div, dc, t = 500 ns/div efficiency (%) v out (v) 125 225 40 36 v 48 v 72 v 24 v 18 v 125 225 12.085 36 v 48 v 72 v 24 v 18 v
NCP1032 http://onsemi.com 7 typical operating characteristics figure 9. frequency vs. timing capacitor c t at 25 c figure 10. oscillator frequency vs. junction temperature capacitance (pf) ambient temperature ( c) 2480 2000 1520 1040 560 80 50 100 200 400 800 1600 100 80 60 40 20 0 ?20 ?40 300 400 500 600 800 900 1000 1100 figure 11. maximum duty ratio vs. temperature figure 12. maximum duty ratio vs. vcc voltage ambient temperature ( c) v cc (v) 100 80 60 40 20 0 ?20 ?40 74.0 74.2 74.6 74.8 75.0 75.4 75.8 76.0 15 14 13 12 11 10 9 8 74.0 74.3 74.6 74.9 75.2 75.5 figure 13. minimum on time vs. vcc figure 14. power switch circuit and startup circuit leakage current vs. drain voltage v cc (v) drain voltage (v) 15 14 13 12 11 10 9 8 100 120 160 180 220 240 280 300 240 200 160 120 80 40 0 0 4 8 12 16 20 28 30 frequency (khz) switching frequency (khz) duty cycle (%) duty cycle (%) min on time (ns) i ds(off) , power switch and startup circuits leakage current ( a) 120 700 c t = 82 pf c t = 220 pf c t = 560 pf 120 74.4 75.2 75.6 1.04 mhz 597 khz 320 khz 128 khz 16 v drain = 100 v v drain = 48 v v drain = 15 v 16 140 200 260 v drain = 100 v v drain = 48 v v drain = 15 v 24 6 10 14 18 22 26 2 125 c 25 c ?40 c
NCP1032 http://onsemi.com 8 typical operating characteristics figure 15. power switch r dson vs. junction temperature figure 16. vdrain startup threshold over temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 2.9 3.1 3.5 3.9 4.3 4.7 5.1 5.5 100 80 60 40 20 0 ?20 ?40 16.10 16.14 16.18 16.22 figure 17. startup current vs. junction temperature figure 18. undervoltage lockout threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 10.2 10.4 10.8 11.2 11.6 11.8 12.4 12.8 100 80 60 40 20 0 ?20 ?40 6.930 6.935 6.940 6.945 6.950 6.955 6.960 6.965 figure 19. supply voltage thresholds vs. junction temperature figure 20. vcc input current at 12 v with an 18 v applied drain voltage 25 c vs oscillator frequency t j , junction temperature ( c) frequency (khz) 100 80 60 40 20 0 ?20 ?40 7.25 7.50 8.00 8.50 9.00 9.50 10.00 10.50 800 700 600 500 400 300 200 100 2.00 2.25 3.00 3.25 3.75 4.25 4.75 5.25 r ds(on) , power switch on resistance ( ) v cc(reset) , undervoltage lockout threshold (v) i start , startup current (ma) v cc(reset) , undervoltage lockout threshold (v) uv threshold (v) input current (ma) 120 3.3 3.7 4.1 4.5 4.9 5.3 v cc = 16 v v cc = 12 v v cc = 8 v 16.12 16.16 16.20 16.24 16.30 16.34 16.38 16.28 16.32 16.36 16.40 16.26 120 120 10.6 11.0 11.4 12.0 12.2 12.6 v cc = v cc(on) ? 0.2 v v cc = 0 v 120 120 7.75 8.25 8.75 9.25 9.75 10.25 startup threshold minimum operating threshold 900 1000 2.50 2.75 3.50 4.00 4.50 5.00
NCP1032 http://onsemi.com 9 typical operating characteristics figure 21. operating supply current vs. supply voltage at 320 khz figure 22. vcc input current vs. temperature over frequency span vdrain = 48 v v cc , supply voltage (v) ambient temperature ( c) 15 14 13 12 11 10 9 8 2.1 2.3 2.7 2.9 3.1 3.5 3.7 4.1 100 80 60 40 20 0 ?20 ?40 2.0 2.5 3.5 4.0 4.5 5.5 6.0 6.5 figure 23. comp clamp voltage vs. junction temperature figure 24. reference voltage vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 4.11 4.12 4.14 4.16 4.18 4.20 4.21 4.23 100 80 60 40 20 0 ?20 ?40 2.488 2.490 2.491 2.493 2.495 2.496 2.498 2.500 figure 25. comp source current vs. junction temperature figure 26. comp sink current vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 94.00 94.25 94.75 95.00 95.25 95.75 96.00 96.50 100 80 60 40 20 0 ?20 ?40 620 640 680 700 720 740 780 800 i cc1 , operating supply current (ma) input current (ma) vc clamp (v) reference voltage (v) source current ( a) sink current ( a) 16 2.5 3.3 3.9 v drain = 48 v t j = 25 c c t = 560 pf 120 3.0 5.0 1.04 mhz 597 khz 320 khz 128 khz 2.489 2.492 2.494 2.497 2.499 120 v cc = 16 v v cc = 12 v v cc = 8 v 120 94.50 95.50 96.25 v cc = 16 v v cc = 12 v v cc = 8 v 120 660 760 120 4.13 4.15 4.17 4.19 4.22
NCP1032 http://onsemi.com 10 typical operating characteristics figure 27. undervoltage threshold vs. junction temperature figure 28. overvoltage threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 1.060 1.061 1.063 1.065 1.067 1.069 1.070 1.072 100 80 60 40 20 0 ?20 ?40 2.394 figure 29. under/overvoltage hysteresis vs. junction temperature figure 30. current limit threshold vs. r cl , current slew rate = 0.5 a/ s t j , junction temperature ( c) riset (k ) 100 80 60 40 20 0 ?20 ?40 60 80 90 110 130 150 160 180 180 140 120 100 80 60 40 20 50 100 150 200 250 350 400 450 figure 31. current limit threshold vs. current slew rate figure 32. current limit threshold vs. t j , current slew riset = open = 0.5 a/ s, riset = 55 k = 0.3 a/ s, riset = 22 k = 0.1 a/ s current slew rate (ma/ s) t j , junction temperature ( c) 1000 800 700 400 300 200 100 0 270 280 290 300 310 320 330 340 100 80 60 40 20 0 ?20 ?40 50 100 200 250 300 400 500 550 uv threshold (v) ov threshold (v) vuv/ov(hys), hysteresis (mv) i lim , current limit threshold (ma) i lim , current limit threshold (ma) v cc = 16 v v cc = 12 v v cc = 8 v 120 1.062 1.064 1.066 1.068 1.071 v cc = 16 v v cc = 12 v v cc = 8 v 120 2.396 2.398 2.400 2.402 2.404 2.406 2.408 2.410 2.412 2.414 2.416 2.418 2.420 2.422 70 100 120 140 170 120 ov hysteresis uv hysteresis 160 200 300 600 500 900 25 v 72 v 120 h i lim , current limit threshold (ma) 120 150 350 450 riset = open riset = 50 k riset = 22 k
NCP1032 http://onsemi.com 11 ct ramp ct charge signal pwm comparator output power switch circuit gate drive pwm latch output leading edge blanking output current limit propagation current limit threshold output overload normal pwm operating range figure 33. pulse width modulation timing diagram delay output overload normal operation startup mode dynamic self supply vcc(on) vcc(off) vcc(reset) 0 v istart 0 ma 0 v 3.0 v 2.5 v 0 v 0 v figure 34. auxiliary winding operation with output overload timing diagram v drain v fb v uv
NCP1032 http://onsemi.com 12 introduction the NCP1032 is a monolithic voltage?mode switching regulator designed for isolated and non?isolated bias supply applications. the internal startup circuit and the mosfet are rated at 200 v, making them ideal for 24 v through 48 v telecom and 42 v automotive applications. in addition, the NCP1032 can operate from an existing 12 v supply. the regulator is optimized for operation up to 1 mhz. the NCP1032 device incorporates all of the active power, control logic, protection circuitry, and power switch in a single ic. the compact design allows the designer to use minimal external components on several switching regulator applications, such as a secondary side bias supply or a low power dc?dc converter. the NCP1032 is available in the space saving wdfn8 3 x 3 mm package and is targeted for applications requiring up to 3 w. the NCP1032 has an extensive set of features including programmable cycle?by?cycle current limit, internal soft?start, input line under and over voltage detection comparators with hysteresis, regulator output undervoltage lockout with hysteresis and over temperature protection providing protection during fault conditions. a description of each of the functional blocks is given below and the functional block diagram is shown in figure 2. startup supply circuit and undervoltage lockout the NCP1032 contains an internal 200 v startup regulator that eliminates the need for external startup components. the startup regulator consists of a 12 ma (typical) current source that supplies power from the input line (vdrain) pin to charge the capacitor on the v cc pin (c vcc ). the act of charging the c vcc capacitor until it reaches 10.2 v while holding the power switch off is called startup mode (sm). once the current source charges the v cc voltage to 10.2 v (typical) the startup circuit is disabled and if no faults are present, the power switch circuit is enabled. the internal control circuitry will draw its current from the energy held by the c vcc capacitor. the startup regulator turns on again once v cc reaches 7.55 v. the charging of the c vcc capacitor to 10.2 v by the current source and the dischar ging by the control circuitry to 7.55 v will be henceforth referred to as dynamic self supply (dss). if v cc falls below 7.55 v while switching, the device enters a restart mode (rm). while in the rm the c vcc capacitor is allowed to discharge to 6.95 v while the power switch is enabled. once the 6.95 v threshold is reached, the power switch circuit is disabled, and the startup regulator is enabled to charge the c vcc capacitor. the power switch is enabled again once the v cc voltage reaches 10.2 v. therefore, the external c vcc capacitor must be sized such that a voltage greater than 6.95 v is maintained on the v cc pin while the converter output reaches regulation. the output is delayed 0.4 ms (t ss_delay ) from the released undervoltage lockout to the first switching pulse. the soft?start time t ss is fixed at 2 ms to ramp the current from its minimum value to its maximum value. the soft?start time is load and rcl dependent and can be computed in the soft?start section. the designer must evaluate the current draw of the regulator at the desired switching frequency over the v cc and temperature operating range shown in figures 20 ? 22. c vcc is calculated using the following equation: c vcc i cc t ss_delay t ss v cc_on v cc_min 2.95 f 4.0 ma 0.4 ms 2.0 ms 10.2 v 6.95 v (eq. 1) i cc includes the NCP1032 bias current (i cc1_max ) and any additional current used to bias the feedback (if used). assuming an i cc1_max of 3.5 ma plus a 0.5 ma bias current for the feedback sensing resistors (if used), and tss of 2 ms, c vcc is calculated at 2.95 f and should be rounded up to ensure design margin to 3.3 f. please note that if the feedback sensing resistors are connected to the v cc pin (isolated main output topology) and c vcc is increased to match c out , the transient response of the converter will suffer. the poor transient response is due to the imbalanced capacitance to current ratio. the auxiliary winding has a significantly greater capacitance to current ratio than the output winding, taking it longer for c vcc to follow c out during a transient condition. after initial startup, the v cc pin should be biased above v cc_min using an auxiliary winding. this will prevent the startup regulator from turning on during normal operation, reducing device power dissipation. a load should not be directly connected to the v cc pin. a load greater than 12 ma will override the startup circuit possibly damaging the part. the maximum voltage rating of the startup circuit is 200 v. power dissipation should be observed to avoid exceeding the maximum power dissipation of the package. figure 35 shows the recommended configuration for a non?isolated flyback converter. figure 35. non?isolated bias supply configuration d1 d2 cout cvcc cin r3 r4 rcl cct cc rc cp r1 r2 vdrain vcc cl comp vfb gnd ct uv/ov vin vout t1 lsec lbias lpri NCP1032
NCP1032 http://onsemi.com 13 soft?start the NCP1032 features an internal soft?start which reduces power?on stress and also contributes to the lower output overshoot. once the v cc_on threshold is reached and there are no fault conditions, the power switch is enabled and the cycle?by?cycle current limit is ramped up slowly to the current limit threshold set by the cl pin. if the cl pin is open, the current limit will be set to its maximum value and the soft?start time will be 2 ms as shown in figure 36. the equation below can be used to calculate the soft?start time for all other current limit set values. tssr set current min current max current min current t ss 1.07 ms 300 ma 57 ma 512 ma 57 ma 2ms (eq. 2) comp voltage 4.2 v 3.5 3.0 v pwm signal ramp inductor current current limit 57 ma set limit soft?start time correction time figure 36. soft?start time the compensation of the converter must be manipulated to minimize the overshoot of the output voltage during startup, details are in the compensation section. line under and over voltage detectors the NCP1032 incorporates vin input line under voltage (uv) and over voltage (ov) shutdown circuits. if the uv/ov pin is set below 1.0 v or above 2.4 v thresholds the power switch will stop switching and the part will use dss until the problem is corrected. the comparators incorporate typical voltage hysteresis of 70 mv (uv) and 158 mv (ov) to prevent noise from inadvertently triggering the shutdown circuit. the uv/ov sense pin can be biased using an external resistor divider from the input line as shown in figure 37. the uv/ov pin should be bypassed using a 1 nf capacitor to prevent triggering the uv/ov circuit during normal switching operation. r3 vin 1 nf r4 1 v 2.4 v ov comparator uv comparator fault ov enable figure 37. uv/ov resistor divider from the input line c uv logic the resistive network impedance must not be too high to keep good voltage accuracy and not too low to minimize power losses. a 200 k to 1.2 m range is recommended for the high side resistor r3. if the designer wanted to set the undervoltage threshold to 32 v, the resistor divider should be designed according to the following equation: r4 v uv r3 v in_uv v uv 34.49 k 1.067 1m 32 v 1.067 34.0 k (r96 value) (eq. 3)
NCP1032 http://onsemi.com 14 the ov threshold monitored at the uv/ov pin is 2.41 times higher than the uv threshold, leading to an ov threshold of 73.3 v for the calculated r96 value. designers can quickly set the ov/uv thresholds by referencing figure 38. figure 38. uv/ov resistor divider thresholds with r4 set to 10 k r3 (k ) 450 400 500 350 300 250 200 150 10 20 40 50 70 90 100 120 input voltage (v) 30 60 80 110 overvoltage threshold undervoltage threshold the uv/ov pin can also be used to implement a remote enable/disable function. if an external transistor pulls the uv/ov pin below 1.0 v (or above 2.4 v) the converter will be disabled and no switching is allowed. a device version is available without the ov protection feature, see the ordering information section. error amplifier the internal error amplifier (ea) regulates the output voltage of the bias supply. the scaled signal is fed into the feedback pin (vfb) which is the inverting input of the error amplifier. it compares a scaled voltage signal to an internal trimmed 2.5 v reference connected to its non?inverting input. the output of the error amplifier is internally connected to a pwm comparator and also available externally through the comp pin for frequency compensation. to insure normal operation, the ea compensation should be selected such that the ea frequency response crosses 0 db below 80 khz. the error amplifier feedback bias current is less than 200 na over the operating range. the output source and sink currents are typically 95 a and 700 a, respectively. under load transient conditions, comp may need to move from the bottom to the top of the c t ramp. a large current is required to complete the comp swing if small resistors or large capacitors are used to implement the compensation network. in which case, the comp swing will be limited by the ea source current. optimum transient responses are obtained if the compensation components allow the comp pin to swing across its operating range in 1 cycle. oscillator, voltage feed forward, and sync capability the oscillator is optimized for operation up to 1 mhz and its frequency is set by the external timing capacitor (c t ) connected to the c t pin. the oscillator has two modes of operation: free running and synchronized (sync). while in free running mode, an internal current source sequentially charges and discharges c t generating a voltage ramp between 3.0 v and 3.5 v. under normal operating conditions, the charge (i ct_c ) and discharge (i ct_d ) currents are typically 172 a and 515 a, respectively. the charge/discharge current ratio of 1:3 discharges c t in 25% of the total period. the power switch is disabled while c t is dischar ging, guaranteeing a maximum duty cycle of 75% as shown in figure 39. 25% 75% signal power switch enabled comp max duty cycle figure 39. auxiliary winding operation with output overload timing diagram c t ramp c t charge the oscillator frequency should be set no more than 25% below the target sync frequency to maintain an adequate voltage ramp and provide good noise immunity. a possible circuit to synchronize the oscillator is shown in figure 40. c1 r1 r2 2 figure 40. external frequency synchronization circuit c t c t
NCP1032 http://onsemi.com 15 voltage feed forward can be implemented by connecting a resistor from the input voltage to the c t pin. rff supplies a current that allows the input voltage to modify the maximum duty cycle rather than the standard 75% maximum. if the designer wanted to implement a fixed lower duty cycle, a resistor can be tied to a fixed voltage source such as v aux or a voltage reference. if voltage feed forward is used, the freque ncy can shift dramatically depending on the value of the resistor. cin rff cct ncp 1032 vdrain gnd ct vin z1 4 v iff 2.2 f off on time off time on time 66% off on time 75% 58% 53% off time on time 42% off time on time 38% off time on time 29% off time on 21% off time on feed forward voltage ct pin voltage figure 41. voltage feed forward r vff vin min ramp i ct_d d max i ct_c i ct_d 320 k 32 v 3.25 v 517 a 62% 172 a 517 a (eq. 4) pwm comparator and latch the pulse width modulator (pwm) comparator compares the error amplifier output (comp) to the c t ramp and generates a proportional duty cycle. the power switch is disabled while comp voltage is below the c t ramp signal. once comp reaches the ramp signal, the power switch is enabled. if comp is at the bottom of the c t ramp, the converter operates at minimum duty cycle. while comp increases, the duty cycle increases until comp reaches the peak of the c t ramp, at which point the controller operates at maximum duty cycle. the c t charge signal is filtered through a one shot pulse generator to set the pwm latch and enable switching at the beginning of each period. switching is allowed while the c t ramp is below comp and a current limit fault is not present. the pulse width modulation technique is seen in figure 39. the pwm comparator and latch propagation delay are less than 200 ns. if the system is designed to operate with a minimum on time less than 200 ns (no or light load), the converter will skip pulses. skipping pulses is usually not a problem, unless operating at a frequency close to the audible range. skipping pulses is more likely when operating at high frequencies during high input voltage and minimum load conditions. a 2 k series resistor is included for esd protection between the internal ea output and the comp pin. under normal operation, a 220 mv offset is observed between the c t ramp and the comp crossing points. the series resistor does not interact with the error amplifier transfer function. programmable current limit the power switch circuit incorporates sensefet ? technology to monitor the drain current. a sense voltage is generated by driving a sense element, r sense , with a current proportional to the drain current. the sense voltage is compared to an externally programmable reference voltage on the non?inverting input of the current limit comparator. if the sense voltage exceeds the setup reference level, the comparator resets the pwm latch and the switching cycle is terminated. the reference level threshold is programmable by a resistor (r cl ) connected to the cl pin shown in figure 42. by limiting the peak current to the needs of the application, the transformer sizing can be scaled appropriately to the specific requirements which allows the pcb footprint to be minimized. the NCP1032 maximum drain current limit thresholds are 512 ma. r cl 114 ln(rset) 142 (eq. 5 ) r cl 309 ln(rset) 893 rset
42.2 k 200 k rset 42.2 k current limit comparator fault logic sense mosfet driver leading edge blanking gnd vdrain 100 ns rcl soft?start ramp + + ? cl figure 42. current limit threshold and propagation delay 3.2 a
NCP1032 http://onsemi.com 16 the propagation delay is measured from the time an overcurrent fault appears at power switch circuit drain, to the start of the turn?off transition as shown in figure 43. the current limit propagation delay time is typ. 100 ns. the propagation must be accounted for when designing the power supply, as it will result in a constant power output through the transformer when the output is shorted. the constant power can cause the transformer to rise in temperature permanently damaging the magnetics. this can be mitigated by placing a 10 resistor in series with the output rectification diode. t figure 43. current limit threshold and propagation delay i sw i lim t phl vin l p t phl adaptive leading edge blanking each time the power switch circuit is turned on, a narrow voltage spike appears across r sense . the spike is due to the power switch circ uit gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. the spike can cause a premature reset of the pwm latch. a proprietary active leading edge blanking (leb) circuit masks the current signal to prevent the voltage spike from resetting the pwm latch. the active leb masks the current signal until the power switch turn on transition is complete. the adaptive leb period provides better current limit control compared to a fixed blanking period. power switch circuit protection the NCP1032 monolithically integrates a 200 v power switch with control logic circuitry. the power switch is designed to directly drive the converter transformer. the gate drive is tailored to control switching transitions and help limit electromagnetic interference (emi). for a flyback topology a large transient voltage spike appears at the transformers primary side after the power switch turns off. these spikes are a function of the transformer leakage inductance (l lp ) on either the primary or secondary side. a circuit is needed to clamp the leakage spike, limiting the voltage drain excursion to a safe value. the operating v drain_max is 200 v as depicted in figure 44. two such circuits are the passive rcd network or a zener clamp as depicted in figure 45 and figure 46. t figure 44. power switch waveforms with clamping v in v clamp v r v drain v ls (leakage spike) v drain_max (180 v) vin d_clamp cclamp ? + cin d1 + rcl t1 ? cvcc cout rclamp u? NCP1032_33 vcc 7 vdrain 8 cl 5 vfb 3 comp 4 gnd 1 uv/ov 6 ct 2 figure 45. passive rcd clamp network v f the passive rcd network is the most standard circuitry and the formula below is used to calculate r clamp and c clamp . r clamp 2 v clamp v clamp (v out v f ) n l lp i peak 2 f sw c clamp v clamp v ls f sw r clamp (eq. 6)
NCP1032 http://onsemi.com 17 the voltage leakage spike (v ls ) is usually selected 50 to 70% above the reflected value v r = n x (v out + v f ) and (v in + v clamp ) must be below the operating v drain?max which is 200 v. the diode used for the clamping circuit needs to be at minimum fast or ultrafast recovery and an mura110 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. the worse case occurs when i peak and v in are at the maximum. dz_clamp vin d_clamp ? + cin d1 + rcl t1 ? cvcc cout u? NCP1032_33 vcc 7 vdrain 8 cl 5 vfb 3 comp 4 gnd 1 uv/ov 6 ct 2 figure 46. zener clamp network v f the zener diode is probably the most expensive but of fers the best protection and a very precise clamping level. select the zener voltage to set v ls level between 10 to 15 v above the reflected voltage v r so vzener = v ls + v r . the zener diode must be able to handle the voltage rating and power dissipation during the switch turn?off time. for the NCP1032, a 0.5 w zener diode, like the mmsz47t1 is suitable. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at 165 c, the power switch circuit is disabled. once the junction temperature falls below 145 c, the NCP1032 is allowed to resume normal operation. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a substitute for proper heat sinking. application considerations typical applications a 12 v / 3 w bias supply for 36 v to 75 v telecom systems, 1500 v isolation dc?dc converters. the NCP1032 is configured in flyback topology and operates in discontinuous conduction mode (dcm) to offer a low?cost, high ef ficiency solution. the circuit schematic is shown in figure 47. transformer t1 is available as a coilcraft b0226?el. capacitor c ct sets the switching frequency at approximately 300 khz. output voltage regulation and overall efficiency are shown in figure 3 and figure 4 on page 6. the resistor divider formed by r3 and r4 sets the undervoltage lockout threshold at about 32 v. application note and8119/d describes the design of this bias supply system. ? + 2.2 f cin d2 nrvb0540 r2 5.1 k r1 19.6 k 2.2 f cvcc d1 mbr140 22 f cout + cc 100 nf rc 18 k cp 68 pf r3 1 m r4 32.4 560 pf cct t1 lsec lpri lbias u1 NCP1032 vcc 7 vdrain 8 cl 5 vfb 3 comp 4 gnd 1 uv/ov 6 ct 2 l1 2.2 h cclp 1 nf mbr1h100 dclp rclp 18 k 1000 pf c1 1 nf cuv ? figure 47. 48 v to isolated 12 v / 3 w bias supply schematic
NCP1032 http://onsemi.com 18 layout recommendations to prevent emi problems high current copper traces which have high frequency switching should be optimized. therefore, use short and wide traces for power current paths and for power ground traces especially transformer trace connections (primary and secondary). when power is transferred from input to output, there is a period of time when the power switch is on, referred to as ?on time,? and a period of time when the switch is off, referred to as ?off time.? when the power switch is on, the input voltage is applied across the primary side of the transformer and current increases in the primary inductance. further, when the power switch is on the output current is supplied from the output capacitance. when the power switch is off, current on the primary side conducts through the clamp or snubber circuit. on the secondary side current is conducting through the rectification diode, providing power to the output and replenishing energy in the output capacitances as shown in figure 48. electromagnetic radiation is minimized by keeping vdrain leads, output diode, and output bypass capacitor leads as short as possible. it is important to minimize the area of the vdrain nodes and used the ground plane under the switcher circuitry to prevent interplane coupling and minimize cross?talk to sensitive signals and ics. the exposed pad of the package must be connected to the ground plane of the board which is important for emi and thermal management. finally, it is always good practice to keep sensitive traces such as feedback connection (vfb and comp) as far away from switched signal connections (vdrain) as possible. figure 48 shows an example of an optimized pcb layout. thermal considerations careful attention must be paid to the internal power dissipation of the NCP1032. power dissipation is a function of efficiency and output power. as output power requirements increase, proper component selection includes adjusting rdson, forward voltage of diodes, and enlar ging packages. for example, if a transformer?s size were increased to lower the dcr or/and increase the inductance efficiency will improve at heavier loads. the exposed thermal pad is designed to be soldered to the ground plane used as a heat sink. the ground plane size should be maximized and connected to the internal and bottom copper ground planes with thermal vias placed directly under the package to spread heat generated by the NCP1032 as depicted figure 48. figure 48. recommended pcb layout
NCP1032 http://onsemi.com 19 ? + 2.2 f cin r2 20 k r1 20 k d1 mbr140sft1g 22 f cout + cc 100 nf rc 18 k cp 68 pf r3 1 m r4 32.4 560 pf cct vin 32 to 75 v lsec lpri u1 NCP1032 vcc 7 vdrain 8 cl 5 vfb 3 comp 4 gnd 1 uv/ov 6 ct 2 cclp 1 nf mbr1h100sft3g dclp rclp 18 k 1 nf cuv ? vout 5.0 v 600 ma d4 mmsz5243bt1g q1 nss1c201lt1g r7 18 k t1 4:1 1.0 f cvcc figure 49. 48 v to 5.0 v dc?dc converter without auxiliary winding ? + 2.2 f cin r2 20 k r1 20 k d1 mbr140sft1g 22 f cout + cc 100 nf rc 18 k cp 68 pf r3 1 m r4 32.4 560 pf cct lpri vin 32 to 75 v lsec u1 NCP1032 vcc 7 vdrain 8 cl 5 vfb 3 comp 4 gnd 1 uv/ov 6 ct 2 cclp 1 nf mbr1h100sft3g dclp rclp 18 k 1 nf cuv ? vout 12.0 v 300 ma t1 3:1 100 nf cvcc figure 50. 48 v to 12.0 v dc?dc converter without auxiliary winding
NCP1032 http://onsemi.com 20 d1 mura115 cout 22 f cin 1 f r3 294 k rcl 40.2 k cct cc 1.5 nf cp 100 pf r1 78.7 k NCP1032 vdrain vcc cl comp vfb gnd ct uv/ov vin vout 560 f 100 v 50 ma r4 10 k r2 2 k rc 100 k figure 51. typical application circuit boost circuit configuration ordering information device ov protection marking package shipping ? NCP1032amntxg enable 1032a wdfn8 3x3 (pb?free) 3,000 / tape & reel NCP1032bmntxg disable 1032b wdfn8 3x3 (pb?free) 3,000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP1032 http://onsemi.com 21 package dimensions wdfn8 3x3, 0.65p case 511bh issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.25 0.35 d 3.00 bsc d2 2.20 2.40 e 3.00 bsc e2 1.40 1.60 e 0.65 bsc l 0.20 0.40 1 4 8 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 pitch 1.66 3.30 1 dimensions: millimeters 0.53 8x note 4 0.40 8x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ??? ??? ??? 0.15 outline package e recommended k 0.45 ref 5 2.46 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP1032/d sensefet is a registered trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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