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| ? semiconductor components industries, llc, 2014 february, 2014 ? rev. p0 1 publication order number: noim1sm9600a/d noim1sm9600a, noim2sm9600a advance information mano 9600 9.6 megapixel rolling shutter cmos image sensor features ? 9.6 megapixel resolution in 3840 2500 format ? 2.4 m 2.4 m square pixels (shared 4t pixel architecture) ? 2/3 inch optical format ? monochrome (sm) version ? 20 frames per second (fps) at full resolution ? 200 mw / 500 mw power consumption at 5 fps / 20 fps ? four low ? voltage differential signaling (lvds) high speed serial outputs or one 10 ? bit cmos output ? on-chip 10-bit analog-to-digital converter (adc) ? windowing to attain higher frame rate ? rolling shutter ? on-chip fixed pattern noise (fpn) correction ? serial peripheral interface (spi) ? automatic exposure control (aec) ? phase locked loop (pll) ? high dynamic range (hdr) ? dual power supply (1.8 v and 3.3 v) ? 0 c to 70 c operational temperature range ? 52-pin lcc ? 500 mw power dissipation (lvds) ? 200 mw power dissipation (cmos) ? these devices are pb ? free and are rohs compliant applications ? biometrics (fingerprinting) ? machine vision ? inspection ? microscopy description the mano9600 is a rolling shutter cmos image sensor with a resolution of 3840 x 2500 pixels. the high sensitivity 2.4 m x 2.4 m pixels supports correlated double sampling readout reducing noise and increasing dynamic range. a high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions of interest. higher frame rates are achieved with region of interest or sub ? sampled readout modes. the sensor has built ? in features for bias control and power supply regulation. the sensor has on ? chip programmable gain amplifiers and 10 ? bit a/d converters. the integration time and gain parameters can be reconfigured without any visible image artifact. optionally the on ? chip automatic exposure control loop (aec) controls these parameters dynamically. the image?s black level is either calibrated automatically or can be adjusted by adding a user programmable offset. the image data interface of the m1 ? sm part consists of four lvds lanes running at 620 mbps, facilitating frame rates up to 20 frames per second. a separate synchronization and clock channel containing payload information is provided to facilitate the image reconstruction at the receive end. the m2 ? sm part provides a parallel cmos output interface at reduced frame rate of 5 frames per second. the mano 9600 is packaged in a 52 ? pin lcc package and is available in a monochrome without micro lens. contact your local on semiconductor office for more information. this document contains information on a new product. specifications and information herein are subject to change without notice . http://onsemi.com figure 1. mano 9600 package photograph
noim1sm9600a, noim2sm9600a http://onsemi.com 2 ordering information part number description package noim1sm9600a-qdc lvds interface mono 52 ? pin lcc package NOIM2SM9600A-QDC cmos interface mono the m1-sm base part is used to reference the mono version of the lvds interface; the m2-sm base part is used to reference the mono version of the cmos interface. note: the mano 9600 does not utilize a micro lens. ordering code definition opto m1: mano lvds m2: mano cmos m = mono (no microlens) commercial temperature range n o m1 a 9600 m sd q ? c s: standard process 9.6 megapixel resolution additional functionality d = d263 glass i image sensors package q = lcc on semiconductor package mark following is the mark on the bottom side of the package with pin 1 to the left center line 1: noi xx sm9600a where xx denotes lvds (m1) / cmos (m2) line 2: -qdc line 3: awlyyww ; where line 3 is the lot traceability as shown below figure 2. generic package mark xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week nnnn = serial number noim1sm9600a, noim2sm9600a http://onsemi.com 3 contents features 1 ..................................... applications 1 ................................. description 1 .................................. ordering information 2 ......................... ordering code definition 2 ...................... package mark 2 ............................... contents 3 .................................... specifications 4 ................................ overview 6 .................................... operating modes 10 ............................. sensor operation 10 ............................. additional features 25 ........................... data output format 31 .......................... register map 44 ................................ package information 56 .......................... glass lid 62 .................................... handling precautions 63 ......................... limited warranty 63 ............................ specifications and user references 63 .............. acronyms 64 ................................... glossary 65 .................................... noim1sm9600a, noim2sm9600a http://onsemi.com 4 specifications key specifications table 1. general specifications parameter specification active pixels 3840 x 2500 pixel size 2.4 m x 2.4 m (shared 4t pixel architecture) shutter type rolling shutter master clock m1-sm: 62 mhz when pll is used, 310 mhz (10-bit) / 248 mhz (8-bit) when pll is not used m2-sm: 62 mhz adc resolution 10-bit, 8-bit lvds outputs m1-sm: 4 data + sync + clock cmos outputs m2-sm: 10-bit parallel output, frame_valid, line_valid, clock data rate m1-sm: 4 x 620 mbps (10-bit) / 4 x 496 mbps (8-bit) m2-sm: 62 mhz power dissipation m1 ? sm in 10 ? bit mode: 700 mw at 20 fps frame rate m2 ? sm: 540 mw at 5 fps frame rate package type 52-pin lcc table 2. electro ? optical specifications parameter specification frame rate at full resolution m1 ? sm: 20 fps m2 ? sm: 5 fps optical format 2/3 inch conversion gain 0.072 lsb10/e - 56 v/e - dark noise 1.5 lsb10, 21 e - responsivity at 550 nm 4 lsb10 /nj/cm 2 full well charge 13500 e - qe x ff 40% at 550 nm pixel fpn 1.3 lsb10 row fpn 0.07 lsb10 column fpn 1.3 lsb10 prnu < 4% of signal dark signal 13.8 e - /s @ 25 c, 2.4 lsb10/s at +24 c dynamic range 54 db signal to noise ratio (snr) 40 db table 3. recommended operating ratings (note 1) symbol description min max units t j (note 2) operating temperature range 0 70 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. absolute maximum ratings (notes 2 and 3) symbol parameter min max units abs (1.8 v supply group) abs rating for 1.8 v supply group ?0.5 2.25 v abs (3.3 v supply group) abs rating for 3.3 v supply group ?0.5 4.3 v t s abs storage temperature range 0 150 c abs storage humidity range at 85 c 85 %rh electrostatic discharge (esd) human body model (hbm): js ? 001 ? 2010 2000 v charged device model (cdm): jesd22 ? c101 500 lu latch-up: jesd ? 78 200 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. operating ratings are conditions in which operation of the device is intended to be functional. 2. stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyo nd those specified is not implied. 3. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625 ? a. refer to application note an52561. noim1sm9600a, noim2sm9600a http://onsemi.com 5 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 4, 5, 6 and 7) parameter description min typ max units power supply parameters vdd_33 supply voltage, 3.3 v 3.1 3.3 3.6 v vdd_18 supply voltage, 1.8 v 1.6 1.8 2 v vdd_pix supply voltage, pixel 3.1 3.3 3.6 v idd_pix current consumption pixel supply 0.8 1 1.2 ma ptot_20fps/5fps total power consumption at 20 fps / 5 fps 700 / 540 mw pstby power consumption in standby mode 50 mw pstby_lp power consumption in low power standby mode 10 mw popt power consumption at lower pixel rates configurable i/o - lvcmos (jedec- jesd8c-01) - conforming to standard - additional specifications and deviations listed fpardata data rate on parallel channels 62 mbps cout output load 10 pf tr rise time 3 4.5 6 ns tf fall time 2.5 3.5 5 ns i/o - lvds (eia/tia-644) - conforming to standard - additional specifications and deviations listed fserdata data rate on data channels for 20 fps / 5 fps 620 / 150 mbps fserclock clock rate of output clock for 20 fps / 5 fps 310 / 75 mhz vicm lvds input common mode level 0.3 1.25 2.2 v tccsk channel to channel skew 50 ps electrical/interface fin input clock rate for 20 fps / 5 fps 62 / 15 mhz tidc input clock duty cycle 45 50 55 % tj input clock jitter 20 ps fspi spi clock rate for 20 / 5 fps 10 / 2.5 mhz ratspi ratio: fin/fspi 6 sensor requirements fps frame rate at full resolution (cmos / lvds) 5 / 20 fps fps_roi1 xres x yres = 3334 x 2500 5.8 / 24 fps fps_roi2 xres x yres = 3840 x 2160 6 / 25 fps fps_roi3 xres x yres = 1024 x 1024 32 / 135 fps fps_roi4 xres x yres = 640 x 480 88 / 366 fps fps_roi5 xres x yres = 512 x 512 91 / 377 fps fps_roi6 xres x yres = 256 x 256 227 / 942 fps rot row overhead time at 20 / 5 fps 1.55 / 6.4 s fpix pixel rate minimum at 5 fps, maximum at 20 fps 60 248 mpix/s i/o - lvcmos (jedec - jesd8c-01) - conforming to standard - additional specifications and deviations listed fpardata data rate on parallel channels 62 fps 4. all parameters are characterized for dc conditions after thermal equilibrium is established. 5. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 6. minimum and maximum limits are guaranteed through test and design. 7. for recommendations on power supply management guidelines, refer to application note an65464: vita 2000 hsmc cyclone referenc e board design recommendations. noim1sm9600a, noim2sm9600a http://onsemi.com 6 overview figure 3 and figure 4 give an overview of the major functional blocks of the m1 ? sm and m2 ? sm sensor respectively. the system clock is received by the cmos clock input. a pll generates the internal, high speed, clocks, which are distributed to the other blocks. optionally, the m1 ? sm can also accept a high speed lvds clock, in which case the pll will be disabled. the sequencer defines the sensor timing and controls the image core. the sequencer is started either autonomously (master mode) or on assertion of an external trigger (slave mode). the image core contains all pixels and readout circuits. the column structure selects pixels for readout and performs correlated double sampling (cds). the data comes out sequentially and is fed into the analog front end (afe) block. the programmable gain amplifier (pga) of the afe adds the offset and gain. the output is a fully differential analog signal that goes to the adc, where the analog signal is converted to a 10 ? bit data stream. depending on the operating mode, eight or ten bits are fed into the data formatting block. this block adds synchronization information to the data stream based on the frame timing. for the m1 ? sm version, the data then goes to the low voltage serial (lvds) interface block which sends the data out through the i/o ring. the m2 ? sm sensor does not have an lvds interface but sends out the data through a 10 ? bit parallel interface. on-chip programmability is achieved through the serial peripheral interface (spi). see the register map on page 44 for register details. a bias block generates bias currents and voltages for all analog blocks on the chip. by controlling the bias current, the speed-versus-power of each block can be tuned. all biasing programmability is contained in the bias block. the sensor can automatically control exposure and gain by enabling the automatic exposure control block (aec). this block regulates the integration time along with the analog and digital gains to reach the desired intensity. image core the image core consists of: ? pixel array ? address decoders and row drivers ? pixel biasing the pixel array contains 3840 (h) x 2500 (v) readable pixels with a pixel pitch of 2.4 m. four dummy pixel rows and columns are placed at every side of the pixel array to eliminate possible edge effects. the sensor uses a 4t pixel architecture, which makes it possible to read out the pixel array in rolling shutter mode with correlated double sampling (cds). the function of the row drivers is to access the image array line by line to reset or read the pixel data. the row drivers are controlled by the on-chip sequencer and can access the pixel array in rolling shutter modes. the pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. phase locked loop the pll accepts a (low speed) clock and generates the required high speed clock. optionally this pll can be bypassed. typical input clock frequency is 62 mhz. lvds clock receiver the lvds clock receiver receives an lvds clock signal and distributes the required clocks to the sensor. typical input clock frequency is 310 mhz in 10-bit mode and 248 mhz in 8-bit mode. the clock input needs to be terminated with a 100 resistor. column multiplexer all pixels of one image row are stored in the column sample-and-hold (s/h) stages. these stages store both the reset and integrated signal levels. the data stored in the column s/h stages is read out through 8 parallel differential outputs operating at a frequency of 31 mhz. at this stage, the reset signal and integrated signal values are transferred into an fpn-corrected differential signal. the column multiplexer also supports read-1-skip-1 and checkerboard subsampling. bias generator the bias generator generates all required reference voltages and bias currents that the on-chip blocks use. an external resistor of 47 k , connected between pin ibias_master and gnd_33, is required for the bias generator to operate properly. analog front end the afe contains 8 channels, each containing a pga and a 10-bit adc. for each of the 8 channels, a pipelined 10-bit adc is used to convert the analog image data into a digital signal, which is delivered to the data formatting block. a black calibration loop is implemented to ensure that the black level is mapped to match the correct adc input level. data formatting the data block receives data from two adcs and multiplexes this data to one data stream. a cyclic redundancy check (crc) code is calculated on the passing data. a frame synchronization data block is configured to transmit synchronization codes such as frame start, line start, frame end, and line end indications. noim1sm9600a, noim2sm9600a http://onsemi.com 7 the data block calculates a crc once per line for every channel. this crc code can be used for error detection at the receiving end. serializer and lvds interface (m1 ? sm only) the serializer and lvds interface block receives the formatted (10-bit or 8-bit) data from the data formatting block. this data is serialized and transmitted by the lvds output driver. in 10-bit mode, the maximum output data rate is 620 mbps per channel. in 8-bit mode, the maximum output data rate is 496 mbps per channel. in addition to the lvds data outputs, two extra lvds outputs are available. one of these outputs carries the output clock, which is skew aligned to the output data channels. the second l vds output contains frame format synchronization codes to serve system-level image reconstruction. output mux (m2 ? sm only) the output mux multiplexes the four data channels to one channel and transmits the data words using a 10-bit parallel cmos interface. frame synchronization information is communicated by means of frame and line valid strobes. sequencer the sequencer: ? controls the image core. starts and stops integration in rolling shutter mode and controls pixel readout. ? applies the window settings. organizes readouts so that only the configured window is read. ? controls the column multiplexer and analog core. applies gain settings and subsampling modes at the correct time, without corrupting image data. ? starts up the sensor correctly when leaving standby mode. automatic exposure control the aec block implements a control system to modulate the exposure of an image. both integration time and gains are controlled by this block to target a predefined illumination level. noim1sm9600a, noim2sm9600a http://onsemi.com 8 block diagram figure 3. block diagram ? m1 ? sm analog front end (afe) data formatting serializers & lvds interface spi interface lvds clock input lvds interface 8 analog channels 8 x 10 bit digital channels 4 lvds channels 1 sync channel 1 clock channel 4 x 10 bit digital channels row decoder column structure image core bias image c ore automatic exposure control (aec) reset pll pixel array (3840 x 2500) cmos clock input lvds receiver clock distribution control & registers noim1sm9600a, noim2sm9600a http://onsemi.com 9 block diagram figure 4. block diagram ? m2 ? sm analog front end (afe) data formatting output mux spi interface cmos interface 8 analog channels 8 x 10 bit digital channels 10 bit parallel data frame valid indication line valid indication 4 x 10 bit digital channels row decoder column structure image core bias image c ore automatic exposure control (aec) reset pll pixel array (3840 x 2500) clock distribution control & registers cmos clock input noim1sm9600a, noim2sm9600a http://onsemi.com 10 operating modes the mano 9600 sensor operates in rolling shutter mode rolling shutter mode the shutter mechanism is an electronic rolling shutter and the sensor operates in a streaming mode similar to a video. this mechanism is controlled by the on-chip sequencer logic. there are two y pointers. one points to the row that is to be reset for rolling shutter operation, the other points to the row to be read out. functionally, a row is reset first and selected for read out sometime later. the time elapsed between these two operations is the exposure time. figure 5 schematically indicates the relative shift of the integration times of different lines during the rolling shutter operation. each row is read and reset in a sequential way. each row in a particular frame is integrated for the same time, but all lines in a frame ?see? a different stare time. as a consequence, fast horizontal moving objects in the field of view give rise to motion artifacts in the image; this is an unavoidable property of a rolling shutter. in rolling shutter mode, the pixel fixed pattern noise (fpn) is corrected on-chip by using the cds technique. after light integration on all pixels in a row is complete, the storage node in the pixel is reset. afterwards the integrated signal is transferred to that pixel storage node. the difference between the reset level and integrated signal is the fpn corrected signal. the advantage of this technique, compared to the ds technique used in the global shutter modes, is that the reset noise of the pixel storage node is cancelled. this results in a lower temporal noise level. figure 5. rolling shutter operation sensor operation flowchart figure 6 shows the sensor operation flowchart. the sensor can be in six different ?states?. every state is indicated with the oval circle. these states are: ? power off ? low power standby ? standby (1) ? standby (2) ? idle ? running these states are ordered by power dissipation. in ?power-off? state, the power dissipation is minimal; in ?running? state the power dissipation is maximal. on the other hand, the lower the power consumption, the more actions (and time) are required to put the sensor in ?running? state and grab images. this flowchart allows the trade-off between power saving and enabling time of the sensor. next to the six ?states? a set of ?user actions?, indicated by arrows, are included in the flowchart. these user actions make it possible to move from one state to another. sensor states power off in this state, the sensor is inactive. all power supplies are down and the power dissipation is zero. low power standby in low power standby state, all power supplies are on, but internally every block is disabled. no internal clock is running (pll / lvds clock receiver is disabled). all register settings are unchanged. only a subset of the spi registers is active for read/write in order to be able to configure clock settings and leave the low power standby state. the only spi registers that should be touched are the ones required for the ?enable clock management? action described in enable clock management ? part 1 on page 12 standby (1) in standby state, the pll/lvds clock receiver is running, but the derived logic clock signal is not enabled. standby (2) in standby state, the derived logic clock signal is running. all spi registers are active, meaning that all spi registers can be accessed for read or write operations. all other blocks are disabled. idle in the idle state, all internal blocks are enabled, except the sequencer block. the sensor is ready to start grabbing images as soon as the sequencer block is enabled. running in running state, the sensor is enabled and grabbing images. noim1sm9600a, noim2sm9600a http://onsemi.com 11 figure 6. sensor operation flowchart power up sequence enable clock management - part 2 (first pass after hard reset) low-power standby required register upload standby (2) soft power-up idle enable sequencer running sensor (re-)configuration (optional) disable sequencer soft power-down disable clock management part 2 power off power down sequence intermediate standby enable clock management - part 2 (not first pass after hard reset) sensor (re-)configuration (optional) sensor (re-)configuration (optional) assertion of reset_n pin enable clock management - part 1 poll lock indication (only when pll is enabled) disable clock management part 1 standby (1) noim1sm9600a, noim2sm9600a http://onsemi.com 12 user actions: power up functional mode sequences power up sequence figure 7 shows the power up sequence of the sensor. the figure indicates that the first supply to ram p-up is the vdd_18 supply, followed by vdd_33 and vdd_pix respectively. it is important to comply with the described sequence. any other supply ramping sequence may lead to high current peaks and, as consequence, a failure of the sensor power up. the clock input should start running when all supplies are stabilized. when the clock frequency is stable, the reset_n signal can be de-asserted. after a wait period of 10 s, the power up sequence is finished and the first spi upload can be initiated. note: the ?clock input? can be the cmos pll clock input (clk_pll), or the lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 7. power up sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us > 10us spi upload enable clock management ? part 1 the ?enable clock management? action configures the clock management blocks and activates the clock generation and distribution circuits in a pre-defined way. first, a set of clock settings must be uploaded through the spi register. these settings are dependent on the desired operation mode of the sensor. table 6 shows the spi uploads to be executed to configure the sensor for m1-sm 8-bit serial, m1-sm 10-bit serial, or m2-sm 10-bit parallel mode, with and without the pll. in the serial modes, if the pll is not used, the l vds clock input must be running. in the m2-sm 10-bit parallel mode, the pll is bypassed. the clk_pll clock is used as sensor clock. it is important to follow the upload sequence listed in table 6. use of phase locked loop if pll is used, the pll is started after the upload of the spi registers. the pll requires (dependent on the settings) some time to generate a stable output clock. a lock detect circuit detects if the clock is stable. when complete, this is flagged in a status register. note: the lock detect status must not be checked for the m2-sm sensor. check this flag by reading the spi register. when the flag is set, the ?enable clock managem ent- part 2? action can be continued. when pll is not used, this step can be bypassed as shown in figure 6 on page 11. table 6. enable clock management register upload ? part 1 upload # address data description m1-sm 8-bit mode with pll 1 2 0x0000 monochrome sensor 2 32 0x200c configure clock generator 3 8 0x0000 release pll soft reset 4 16 0x0003 enable pll m1-sm 8-bit mode without pll 1 2 0x0000 monochrome sensor 2 32 0x2008 configure clock management 3 20 0x0001 enable lvds clock input m1-sm 10-bit mode with pll 1 2 0x0000 monochrome sensor 2 32 0x2004 configure clock generator 7 8 0x0000 release pll soft reset 8 16 0x0003 enable pll m1-sm 10-bit mode without pll 1 2 0x0000 monochrome sensor noim1sm9600a, noim2sm9600a http://onsemi.com 13 table 6. enable clock management register upload ? part 1 upload # description data address 2 32 0x2000 configure clock management 3 20 0x0001 enable lvds clock input m2-sm 10-bit mode 1 2 0x0002 monochrome sensor parallel mode selection 2 32 0x200c configure clock management 3 2 0x0002 parallel mode selection 4 16 0x0007 configure pll bypass mode enable clock management - part 2 the next step to configure the clock management consists of spi uploads which enables all internal clock distribution. the required uploads are listed in table 7. note that it is important to follow the upload sequence listed in table 7. table 7. enable clock management register upload ? part 2 upload # address data description m1-sm 8-bit mode with pll 1 9 0x0000 release clock generator soft reset 2 32 0x200e enable logic clock 3 34 0x0001 enable logic blocks m1-sm 8-bit mode without pll 1 9 0x0000 release clock generator soft reset 2 32 0x200a enable logic clock 3 34 0x0001 enable logic blocks m1-sm 10-bit mode with pll 1 9 0x0000 release clock generator soft reset 2 32 0x2006 enable logic clock 3 34 0x0001 enable logic blocks m1-sm 10-bit mode without pll 1 9 0x0000 release clock generator soft reset 2 32 0x2002 enable logic clock 3 34 0x0001 enable logic blocks m2-sm 10-bit mode 1 9 0x0000 release clock generator soft reset 2 32 0x200e enable logic clock 3 34 0x0001 enable logic blocks noim1sm9600a, noim2sm9600a http://onsemi.com 14 required register upload in this phase, the ?reserved? register settings are uploaded through the spi register. different settings are not allowed and may cause the sensor to malfunction. the required uploads are listed in table 8. note: this table is subject to change. table 8. required registered upload upload # address data 1 192 0x0800 2 42 0x0002 3 128 0x4320 4 205 0x00a0 5 129 0x0001 6 230 0x0044 7 231 0x09cb 8 197 0x2364 9 256 0x0000 10 257 0x01df 11 258 0x0000 12 259 0x09c3 13 260 0x0000 14 261 0x01df 15 262 0x0000 16 263 0x09c3 17 201 0x07d0 18 65 0x885b 19 72 0x0000 20 43 0x4701 21 384 0x0900 22 385 0x0be1 23 386 0x0bc5 24 387 0x0381 25 388 0x0181 26 389 0x218f 27 390 0x2185 28 391 0x2101 29 392 0x0501 30 393 0x07c6 31 394 0x0781 32 395 0x0581 33 396 0x258f 34 397 0x2585 35 398 0x2501 36 399 0x0102 37 400 0x1346 38 401 0x0341 39 402 0x0141 40 403 0x214f 41 404 0x2145 42 405 0x2101 43 406 0x0501 44 407 0x0746 45 408 0x0741 46 409 0x0541 47 410 0x254f 48 411 0x2545 49 412 0x2501 50 413 0x0101 51 414 0x8101 52 415 0x8901 53 416 0x990e 54 417 0x8901 55 418 0x8901 56 419 0xc901 57 420 0xd90e 58 421 0xc901 59 422 0xc900 60 423 0x0900 61 424 0x1be1 62 425 0x1bc5 63 426 0x1b89 64 427 0x0b82 65 428 0x0381 66 429 0x0181 67 430 0x218f 68 431 0x2185 69 432 0x2101 70 433 0x0501 71 434 0x07c6 72 435 0x0781 73 436 0x0581 74 437 0x258f 75 438 0x2585 76 439 0x2501 77 440 0x0102 78 441 0x1346 79 442 0x0341 noim1sm9600a, noim2sm9600a http://onsemi.com 15 required registered upload (table 8. continued) upload # address data 80 443 0x0141 81 444 0x214f 82 445 0x2145 83 446 0x2101 84 447 0x0501 85 448 0x0746 86 449 0x0741 87 450 0x0541 88 451 0x254f 89 452 0x2545 90 453 0x2501 91 454 0x0101 92 455 0x8101 93 456 0x990e 94 457 0x8901 95 458 0x8901 96 459 0xc901 97 460 0xd90e 98 461 0xc900 99 220 0x2700 100 462 0x0900 101 463 0x1be1 102 464 0x1bc5 103 465 0x1b89 104 466 0x0b82 105 467 0x0381 106 468 0x0181 107 469 0x218f 108 470 0x2185 109 471 0x2101 110 472 0x0501 111 473 0x07c6 112 474 0x0781 113 475 0x0581 114 476 0x258f 115 477 0x2585 116 478 0x2501 117 479 0x0102 118 480 0x1346 119 481 0x0341 120 482 0x0141 121 483 0x2142 122 484 0x2101 123 485 0x0501 124 486 0x0746 125 487 0x0741 126 488 0x0541 127 489 0x2542 128 490 0x2501 129 491 0x0101 130 492 0x8101 131 493 0x990e 132 494 0x8901 133 495 0x8901 134 496 0xc901 135 497 0xd90e 136 498 0xc900 137 219 0x004e 138 499 0x0010 139 216 0x737f note: upload #5: cmos mode only. do not show line valid for black lines. [9:1]=0. uncalibrated black offset upload #8: mux bl coeffs. [13:13] = 1 upload #20: select dac. [7:4]=0 noim1sm9600a, noim2sm9600a http://onsemi.com 16 soft power up during the soft power up action, the internal blocks are enabled and prepared to start processing the image data stream. this action exists of a set of spi uploads. the soft power up uploads are listed in table 9. table 9. soft power up register uploads for mode dependent registers upload # address data description m1-sm 8-bit mode with pll 1 32 0x200f enable analog clock distribution 2 112 0x0007 enable lvds transmitters m1-sm 8-bit mode without pll 1 32 0x200b enable analog clock distribution 2 112 0x0007 enable lvds transmitters m1-sm 10-bit mode with pll 1 32 0x2007 enable analog clock distribution 2 112 0x0007 enable lvds transmitters m1-sm 10-bit mode without pll 1 32 0x2003 enable analog clock distribution 2 112 0x0007 enable lvds transmitters m2-sm 10-bit mode 1 32 0x200f enable analog clock distribution table 10. soft power up for lvds and cmos outputs upload # address lvds cmos 1 32 0x400f 0x200f 2 10 0x0000 0x0000 3 64 0x0001 0x0001 4 72 0x0000 0x0000 5 81 0x8880 0x8880 6 42 0x006e 0x006e 7 40 0x0003 0x0003 8 48 0x0001 0x0001 9 112 0x0007 0x0000 10 128 0x4320 enable sequencer during the ?enable sequencer? action, the frame grabbing sequencer is enabled. the sensor starts grabbing images in the configured operation mode. refer to sensor states on page 10 for an overview of the possible operation modes. the ?enable sequencer ? action consists of a set of register uploads. the required uploads are listed in table 11. table 11. enable sequencer register upload upload # address data description 1 192 0x0003 enable of sequencer in rolling shutter mode note : this address contains other configuration bits to select the operation mode noim1sm9600a, noim2sm9600a http://onsemi.com 17 user actions: functional modes to power down sequences disable sequencer during the ?disable sequencer? action, the frame grabbing sequencer is stopped. the sensor stops grabbing images and returns to the idle mode. the ?disable sequencer ? action consists of a set of register uploads. as listed in table 12. table 12. disable sequencer register upload upload # address data description 1 192 0x0002 disable sequencer. note that this address contains other configuration bits to select the operation mode. soft power down during the soft power down action, the internal blocks are disabled and the sensor is put in standby state to reduce the current dissipation. this action exists of a set of spi uploads. the soft power down uploads are listed in table 13. table 13. soft power down register upload upload # address data description 1 112 0x0000 disable lvds transmitters 2 48 0x0000 disable afe 3 40 0x0000 disable column multiplexer 4 64 0x0000 disable biasing block 5 10 0x0999 soft reset disable clock management - part 2 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 14. table 14. disable clock management register upload ? part 2 upload # address data description m1-sm 8-bit mode with pll 1 34 0x0000 disable logic blocks 2 32 0x200c disable logic clock 3 9 0x0009 soft reset clock generator m1-sm 8-bit mode without pll 1 34 0x0000 disable logic blocks 2 32 0x2008 disable logic clock 3 9 0x0009 soft reset clock generator m1-sm 10-bit mode with pll 1 34 0x0000 disable logic blocks 2 32 0x2004 disable logic clock 3 9 0x0009 soft reset clock generator m2-sm 10-bit mode without pll 1 34 0x0000 disable logic blocks 2 32 0x2000 disable logic clock 3 9 0x0009 soft reset clock generator m2-sm 10-bit mode noim1sm9600a, noim2sm9600a http://onsemi.com 18 table 14. disable clock management register upload ? part 2 upload # description data address 1 34 0x0000 disable logic blocks 2 32 0x200c disable logic clock 3 9 0x0009 soft reset clock generator disable clock management - part 1 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 15. table 15. disable clock management register upload ? part 1 upload # address data description 1 16 0x0000 disable pll 2 8 0x0099 soft reset pll 3 20 0x0000 configure clock management power down sequence figure 8 illustrates the timing diagram of the preferred power down sequence. it is important that the sensor is in reset before the clock input stops running. otherwise, the internal pll becomes unstable and the sensor gets into an unknown state. this can cause high peak currents. the same applies for the ramp down of the power supplies. the preferred order to ramp down the supplies is first vdd_pix, second vdd_33, and finally vdd_18. any other sequence can cause high peak currents. note: the ?clock input? can be the cmos pll clock input (clk_pll), or the lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 8. power down sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us noim1sm9600a, noim2sm9600a http://onsemi.com 19 sensor reconfiguration during the standby, idle, or running state several sensor parameters can be reconfigured. ? frame rate and exposure time: frame rate and exposure time changes can occur during standby, idle, and running states. ? signal path gain: signal path gain changes can occur during standby, idle, and running states. ? windowing: changes with respect to windowing can occur during standby, idle, and running states. refer to window readout on page 25. ? subsampling: changes of the subsampling mode can occur during standby, idle, and running states. refer to subsampling and binning on page 26 for more information. sensor configuration this device contains multiple configuration registers. some of these registers can only be configured while the sensor is not acquiring images (while register 192[0] = 0), while others can be configured while the sensor is acquiring images. for the latter category of registers, it is possible to distinguish the register set that can cause corrupted images (limited number of images containing visible artifacts) from the set of registers that are not causing corrupted images. these three categories are described here. static readout parameters some registers are only modified when the sensor is not acquiring images. reconfiguration of these registers while images are acquired can cause corrupted frames or even interrupt the image acquisition. therefore, it is recommended to modify these static configurations while the sequencer is disabled (register 192[0] = 0). the registers shown in t able 16 should not be reconfigured during image acquisition. a specific configuration sequence applies for these registers. refer to the operation flow and startup description. table 16. static readout parameters group addresses description clock generator 32 configure according to recommendation image core 40 configure according to recommendation afe 48 configure according to recommendation bias 64?71 configure according to recommendation lvds 112 configure according to recommendation all reserved registers keep reserved registers to their default state, unless otherwise described in the recommendation dynamic configuration potentially causing image artifacts the category of registers as shown in table 16 consists of configurations that do not interrupt the image acquisition process, but may lead to one or more corrupted images during and after the re-configuration. a corrupted image is an image containing visible artifacts. a typical example of a corrupted image is an image which is not uniformly exposed. the effect is transient in nature and the new configuration is applied after the transient effect. table 17. dynamic configuration potentially causing image artifacts group addresses description black level configuration 128?129 197[8] reconfiguration of these registers may have an impact on the black-level calibration algorithm. the effect is a transient number of images with incorrect black level compensation. sync codes 129[13] 130?135 incorrect sync codes may be generated during the frame in which these registers are modified. datablock test configurations 144?150 modification of these registers may generate incorrect test patterns during a transient frame. noim1sm9600a, noim2sm9600a http://onsemi.com 20 dynamic readout parameters it is possible to reconfigure the sensor while it is acquiring images. frame-related parameters are internally resynchronized to frame boundaries, such that the modified parameter does not affect a frame that has already started. however, there can be restrictions to some registers as shown in table 18. some reconfiguration may lead to one frame being blanked. this happens when the modification requires more than one frame to settle. the image is blanked out and training patterns are transmitted on the data and sync channels. table 18. dynamic readout parameters group addresses description subsampling/binning 232[4:0] subsampling or binning is synchronized to a new frame start. subsampling / binning also required to reconfigure black line address (230[9:5]), last line address 231[12:0] and y ? start offset (230[4:0]) as mentioned in detail in register map given in table 45 on page 44. reconfiguration of these parameters cause one frame to be blanked out black lines 197 reconfiguration of these parameters causes one frame to be blanked out as the reset pointers need to be recalculated for the new frame timing. dummy lines 198 reconfiguration of these parameters causes one frame to be blanked out as the reset pointers need to be recalculated for the new frame timing. roi configuration 195 256?263 optionally, it is possible to blank out one frame after reconfiguration of the active roi in rolling shutter mode. therefore, register 192[9] must be asserted (blank_roi_switch configuration). a roi switch is only detected when a new window is selected as the active window (reconfiguration of register 195). reconfiguration of the roi dimension of the active window does not lead to a frame blank and can cause a corrupted image. exposure reconfiguration 203 exposure reconfiguration does not cause artifact. gain reconfiguration 204 gains are synchronized at the start of a new frame. optionally, one frame latency can be incorporated to align the gain updates to the exposure updates (refer to register 199[13] - gain_lat_comp). freezing active configurations though the readout parameters are synchronized to frame boundaries, an update of multiple registers can still lead to a transient effect in the subsequent images, as some configurations require multiple register uploads. for example, to reconfigure sub ? sampling / binning scheme we also need to update black line address, y ? start offset and last line address registers. internally, the sensor synchronizes these configurations to frame boundaries, but it is still possible that the reconfiguration of multiple registers spans over two or even more frames. to avoid inconsistent combinations, freeze the active settings while altering the spi registers by disabling synchronization for the corresponding functionality before reconfiguration. when all registers are uploaded, re ? enable the synchronization. the sensor?s sequencer then updates its active set of registers and uses them for the coming frames. the freezing of the active set of registers can be programmed in the sync_configuration registers, which can be found at the spi address 206. figure 9 shows a re-configuration that does not use the sync_configuration option. as depicted, new spi configurations are synchronized to frame boundaries. with sync_configuration = ?1?. configurations are synchronized to the frame boundaries. figure 10 shows the usage of the sync_configuration settings. before uploading a set of registers, the corresponding sync_configuration is de-asserted. after the upload is completed, the sync_configuration is asserted again and the sensor resynchronizes its set of registers to the coming frame boundaries. as seen in the figure, this ensures that the uploads performed at the end of frame n+2 and the start of frame n+3 become active in the same frame (frame n+4). figure 9. frame synchronization of configurations (no freezing) time line spi registers active registers frame n frame n+1 frame n+2 frame n+3 frame n+4 noim1sm9600a, noim2sm9600a http://onsemi.com 21 figure 10. reconfiguration using sync_configuration frame nframe n+1?frame n+2?frame n+3?frame n+4 time line sync_configuration spi registers active registers this configuration is not taken into account as sync_register is inactive. note: spi updates are not taken into account while sync_configuration is inactive. the active configuration is frozen for the sensor. table 19 lists the several sync_configuration possibilities along with the respective registers being frozen. table 19. alternate sync configurations group affected registers description sync_rs_x_length rs_x_length update of x ? length configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_black_lines black_lines update of black line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_dummy_lines dummy_lines update of dummy line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_exposure mult_timer fr_length exposure update of exposure configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_gain mux_gainsw afe_gain update of gain configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_roi roi_active0[7:0] subsampling binning black line address last line address y ? start offset update of active roi configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. note: the window configurations themselves are not frozen. reconfiguration of active windows is not gated by this setting. table 20. configurable parameters for black level algorithm group addresses description black line generation 197[7:0] black_lines this register configures the number of black lines that are generated at the start of a frame. at least one black line must be generated. the maximum number is 127. note: when the automatic black-level calibration algorithm is enabled, make sure that this register is configured properly to produce sufficient black pixels for the black-level filtering. the number of black pixels generated per line is dependent on the operation mode and window configurations: as the line length is fundamental for rolling shutter operation, the length of a black line is defined by the active window. 197[8:9] gate_first_line when asserting this configuration, the first black lines of the frame are blanked out and is not used for black calibration. it is recommended to enable this functionality, because the first black lines can have a different behavior caused by boundary effects. when enabling, the number of black lines must be set to at least two in order to have valid black samples for the calibration algorithm. noim1sm9600a, noim2sm9600a http://onsemi.com 22 table 20. configurable parameters for black level algorithm group description addresses black value filtering 129[0] auto_blackcal_enable internal black-level calibration functionality is enabled when set to ?1?. required black level offset compensation is calculated on the black samples and applied to all image pixels. when set to ?0?, the automatic black-level calibration functionality is disabled. it is possible to apply an offset compensation to the image pixels, which is defined by the registers 129[10:1]. note: black sample pixels are not compensated; the raw data is sent out to provide ex- ternal statistics and, optionally, calibrations. 129[9:1] blackcal_offset black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ?0?. the sign of the offset is determined by register 129[10] (blackcal_offset_dec). note: all channels use the same offset compensation when automatic black calibration is disabled. the calculated black calibration factors are frozen when this register is set to 0x1ff (all ? ?1?) in auto calibration mode. any value different from 0x1ff re-enables the black calibration algorithm. this freezing option can be used to prevent eventual frame to frame jitter on the black level as the correction factors are recalculated every frame. it is recom- mended to enable the black calibration regularly to compensate for temperature changes. 129[10] blackcal_offset_dec sign of blackcal_offset. if set to ?0?, the black calibration offset is added to each pixel. if set to ?1?, the black calibration offset is subtracted from each pixel. this register is not used when auto_blackcal_enable is set to ?1?. 128[10:8] black_samples the black samples are low-pass filtered before being used for black level calculation. the more samples are taken into account, the more accurate the calibration, but more samples require more black lines, which in turn affects the frame rate. the effective number of samples taken into account for filtering is 2^ black_samples. note: an error is reported by the device if more samples than available are requested (refer to register 136). noim1sm9600a, noim2sm9600a http://onsemi.com 23 serial peripheral interface the sensor configuration registers are accessed through an spi. the spi consists of four wires: ? sck: serial clock ? ss_n: active low slave select ? mosi: master out, slave in, or serial data in ? miso: master in, slave out, or serial data out the spi is synchronous to the clock provided by the master (sck) and asynchronous to the sensor?s system clock. when the master wants to write or read a sensor?s register, it selects the chip by pulling down the slave select line (ss_n). when selected, data is sent serially and synchronous to the spi clock (sck). figure 11 shows the communication protocol for read and write accesses of the spi registers. the mano 9600 sensor uses 9-bit addresses and 16-bit data words. data driven by the system is colored blue in figure 11, while data driven by the sensor is colored yellow. the data in grey indicates high-z periods on the miso interface. red markers indicate sampling points for the sensor (mosi sampling); green markers indicate sampling points for the system (miso sampling during read operations). the access sequence is: 1. select the sensor for read or write by pulling down the ss_n line. 2. one spi clock cycle after selecting the sensor, the 9-bit data is transferred, most significant bit first. the sck clock is passed through to the sensor as indicated in figure 11. the sensor samples this data on a rising edge of the sck clock (mosi needs to be driven by the system on the falling edge of the sck clock). 3. the tenth bit sent by the master indicates the type of transfer: high for a write command, low for a read command. 4. data transmission: - for write commands, the master continues sending the 16-bit data, most significant bit first. - for read commands, the sensor returns the requested address on the miso pin, most significant bit first. the miso pin must be sampled by the system on the falling edge of sck (assuming nominal system clock frequency and maximum 10 mhz spi frequency). 5. when data transmission is complete, the system deselects the sensor one clock period after the last bit transmission by pulling ss_n high. maximum frequency for the spi depends on the input clock and type of sensor. the frequency is 1/6 th of the pll input clock or 1/30 th (in 10-bit mode) and 1/24 th (in 8-bit mode) of the lvds input clock frequency. at nominal input frequency (62 mhz / 310 mhz / 248 mhz), the maximum frequency for the spi is 10 mhz. bursts of spi commands can be issued by leaving at least two spi clock periods between two register uploads. deselect the chip between the spi uploads by pulling the ss_n pin high. figure 11. spi read and write timing diagram .. a1 a0 `1' a8 d15 d14 .. .. .. .. d1 d0 sck mo si ss_n sp i ? write miso a7 .. .. .. a1 a0 `0' a8 sck mo si ss_n spi ? rea d miso a7 .. .. d15 d14 .. .. .. .. d1 d0 ts_mosi th_mosi t_sssck t_sc ks s ts _mi so th_mi so t_sc ks s t_sssck ts _mos i th_mosi ts ck ts ck noim1sm9600a, noim2sm9600a http://onsemi.com 24 rolling shutter mode the exposure time during rolling shutter mode is always an integer multiple of line-times. the exposure time is defined by the register exposure and expressed in number of lines. the register fr_length and mult_timer are not used in this mode. the maximum exposure time is limited by the frame time. it is possible to increase the exposure time at the cost of the frame rate by adding so called dummy lines. a dummy line lasts for the same time as a re gular line, but no pixel data is transferred to the system. the number of dummy lines is controlled by the register dummy_lines. the rolling shutter exposure mechanism is graphically shown in figure 12. figure 12. integration control in rolling shutter mode note: the duration of one line is the sum of the rot and the time required to read out one line (depends on the number of active kernels in the window). optionally, this readout time can be extended by the configuration rs_x_length. this register, expressed in number of periods of the logic clock (16.129 ns for the m1-sm version and 64.516 ns for the m2-sm version), determines the length of the x-readout. however, the minimum for rs_x_length is governed by the window size (x-size). it is clear that when the number of rows and/or the length of a row are reduced (by windowing or subsampling), the frame time decreases and consequently the frame rate increases. to be able to artificially increase the frame time, it is possible to: ? add dummy clock cycles to a row time ? add dummy rows to the frame noim1sm9600a, noim2sm9600a http://onsemi.com 25 additional features multiple window readout the mano9600 sequencer supports windowed readout. the user can limit the data output per frame, which allows increasing the frame rate. window configuration only a single window is supported. do not activate more than one window (register 195). however, it is possible to configure more than one window and dynamically switch between the different window configurations. note that switching between two different windows might result in a corrupted frame. this is inherent in the rolling shutter mechanism, where each line must be reset sequentially before being read out. this corrupted window can be blanked out by setting register 206[8]. in this case, a dead time is noted on the lvds interface when the window ? switch occurs in the sensor. during this blank out, training patterns are sent out on the data and sync channels for the duration of one frame. silicon restriction when switching between rois ? trigger condition(s) ? y_start line is lower than previous y_start line ? scope of impact ? frame_valid fails and sensor stops operating ? recommendation ? ensure that register 206[8] = 1. (blank_roi_switch) ? to set a new roi: reg 206[5] = 0 // disable sync_roi ? // update roi ? settings of the _active_roi here. reg 206[5] = 1 // re ? enable sync_roi figure 13 shows the four parameters defining a region of interest (roi). figure 13. region of interest configuration 2500 pixels 3480 pixels y-start y-end x-start?x-end ? x ? start[8:0] x-start defines the x-starting point of the desired window. the sensor reads out 8 pixels in one single clock cycle. as a consequence, the granularity for configuring the x-start position is also 8 pixels for no sub sampling. the value configured in the x-start register is multiplied by 8 to find the corresponding column in the pixel array when there is no subsampling / binning. ? x-end[8:0] this register defines the window end point on the x-axis. similar to x-start, the granularity for this configuration is one kernel. x-end needs to be larger than x-start. ? y-start[12:0] the starting line of the readout window. the granularity of this setting is one line. ? y-end[12:0] the end line of the readout window. y-end must be configured larger than y-start. this setting has the same granularity as the y-start configuration. pixel array addressing scheme for no ? subsampling/ binning. address mapping of pixel array rows to on ? chip sequencer is shown in table 21 as per following formula: y-address of sequencer = row number table 21. sequencer y-address mapping for no-subsampling / binning row number sequencer y-address 0 0 1 1 2 2 3 3 4 4 5 5 ? ? ? ? 2497 2497 2498 2498 2499 2499 even columns of pixel array are addressed by the sequencer through following mapping: x-address of sequencer 8 + 1 = pixel array column number odd columns of pixel array are addressed by sequencer through following mapping: (x-address of sequencer ? 1) 8 + 1 = pixel array column number table 22 shows the column to its read out address mapping in sequencer for even and odd kernels of a row. noim1sm9600a, noim2sm9600a http://onsemi.com 26 table 22. sequencer x-address mapping for no-subsampling / binning pixel array column no. kernel number sequencer x-address 0 ? 14 (every second pixel) 0 0 1 ? 15 (every second pixel) 1 1 16 ? 30 (every second pixel) 2 2 17 ? 31 (every second pixel) 3 3 ? ? ? 3808 ? 3822 (every second pixel) 476 476 3809 ? 3823 (every second pixel) 477 477 3824 ? 3838 (every second pixel) 478 478 3825 ? 3839 (every second pixel) 479 479 subsampling and binning subsampling is used to reduce the image resolution. this allows increasing the frame rate. two subsampling modes are supported: read ? 1 ? skip ? 1 and checkerboard subsampling. pixel binning is also supported to increase the dynamic range of the sensor. two binning schemes are supported: 1x2 and 2x2. during these sub ? sampling/ binning schemes, address mapping of pixel array rows and columns to on ? chip sequencer y ? address and x ? address respectively, is different from no ? subsampling. so user should configure windows according to the appropriate address mapping explained in detail for each subsampling/ binning scheme in following sections. following table shows an example of freezing and releasing of the register updates, to reconfigure subsampling/binning scheme. table 23. upload sequence for subsampling / binning addresses data description 206[5] 0x0 de ? assert sync_roi. the sensor continues with its previous configurations. 232 enable/disable the required sub ? sampling / binning as mentioned in detail in register map, given in table 45 on page 44 230 reconfigure y ? start offset and black line address as mentioned in detail in register map, given in table 45 on page 44 for required subsampling / binning 231 reconfigure last line address as mentioned in detail in register map, given in table 45 on page 44 for required subsampling / binning 206[5] 0x1 assert sync_roi, to enable above uploads for next frame. this reconfiguration will cause one frame to be blanked out. read-1-skip-1 the read ? 1 ? skip ? 1 subsampling scheme can be enabled. subsampling occurs both in x ? and y ? direction. figure 14 shows which pixels are read and which ones are skipped. figure 14. read-1-skip-1 subsampling read skip pixel (0;0) y x 2 2 binning the 2 2 binning scheme can also be enabled. during this binning scheme, pixels being readout are charge binned (summed) with pixel adjacent to them in the next row (in y ? direction) and then charge binned pixels of two rows are voltage binned (averaged) with adjacent charge binned pixels in x ? direction. (see table 15). figure 15. 2 x 2 binning charge (summing) binning in y ? direction pixel (0;0) y x voltage (averaging) binning after above summing in x ? direction noim1sm9600a, noim2sm9600a http://onsemi.com 27 row/column address mapping during read ? 1 ? skip ? 1 subsampling and 2 2 binning. during read ? 1 ? skip ? 1 sub ? sampling, only even pixels of every alternative row are read out. these rows are addressed by on ? chip sequencer according to the following formula: y ? sequencer address of a row = row number / 2 for 2 2 binning, mapping of binned rows is done to sequencer addresses according to the following formula. y ? sequencer address of a row = binning of (row number / 2, row number / 2+1), where y ? address = row number / 2. table 24 shows address mapping of rows to be read out in read ? 1 ? skip ? 1 subsampling and 2 2 binning mode to the sequencer y ? address. table 24. sequencer y-address mapping for read-1-skip-1 subsampling and 2 x 2 binning row no. (for r1s1 subsampling) row no. (for 2 x 2 binning) sequencer y-address 0 (0,1) 0 2 (2,3) 1 4 (4,5) 2 6 (6,7) 3 ? ? ? 2494 (2494, 2495) 1247 2496 (2496, 2497) 1248 2498 (2498, 2499) 1249 table 25 shows the address mapping of pixel array columns to x ? address in sequencer for read ? 1 ? skip ? 1 subsampling and 2 2 binning schemes. table 25. sequencer x-address mapping for read-1-skip-1 subsampling and 2 x 2 binning pixel array even column no. (for r1s1 subsampling) pixel array even column no. (for 2 x 2 binning) kernel no. sequencer x-address 0 ? 14 (every second pixel) (0,1) ? (14,15) 0 0 16 ? 30 (every second pixel) (16,17) ? (30,31) 1 1 ? ? ? ? 3808 ? 3822 (every second pixel) (3808,3809) ? (3822,3823) 238 238 3824 ? 3838 (every second pixel) (3824,3825) ? (3838,3839) 239 239 checkerboard subsampling in this subsampling scheme, read out of even pixels of one row is followed by odd pixels of the next row. figure 16 shows the pixels that are read and the pixels that are skipped. figure 16. checkerboard subsampling read skip pixel (0;0) y x 1 2 binning the 1 2 binning can be enabled to increase the dynamic range. during this binning scheme, pixels being read out are charge binned (summed) with adjacent pixels in the same column, as shown in figure 17. figure 17. 1 x 2 binning scheme pixel (0;0) y x 1 x 2 charge (summing) binning noim1sm9600a, noim2sm9600a http://onsemi.com 28 row/column addressing scheme during checkerboard subsampling and 1 2 binning during check ? board pattern subsampling, readout of even pixel segment (only even pixels of row) of a row is followed by odd pixel segment (only odd pixels of row) of next row. these segments are addressed according to following relation: y ? address of even pixel segment of even row = row number y ? address of odd pixel segment of odd row = row number address mapping of rows to y ? address during checkerboard subsampling is shown in table 26. table 26. sequencer y-address mapping for checkerboard subsampling row no. (checkerboard subsampling) row segment (checkerboard subsampling) sequencer y-address 0 even 0 1 odd 1 2 even 2 3 odd 3 4 even 4 5 odd 5 ? ? ? 2494 even 2494 2495 odd 2495 2496 even 2496 2497 odd 2497 2498 even 2498 2499 odd 2499 for 1 2 binning, every pixel in one row is binned with adjacent pixel of its next row, so there is one output data row, for every two consecutive rows. y ? address of sequencer 2 = binning of (row number, row number + 1), where y ? address = row number/2 for 1 2 binning, row address mapping to sequencer is shown in table 27. table 27. sequencer y-address mapping for 1 x 2 binning row no. (1 x 2 binning) sequencer y-address (0, 1) 0 (2, 3) 1 (4, 5) 2 (6, 7) 3 ? ? ? ? (2496, 2497) 1248 (2498, 2499) 1249 for checkerboard subsampling, columns for even pixels of an even row are addressed with mapping shown in table 28, which is according to the following formula. x ? address of sequencer 8 2 = pixel array column number columns for odd pixels of an odd row are addressed with mapping shown in table 29, which is according to the following formula. table 28. sequencer x-address mapping for even pixels of even rows during checkerboard subsampling pixel array even column no. kernel number sequencer x-address 0 ? 14 (every second pixel) 0 0 16 ? 30 (every second pixel) 1 1 ? ? ? 3808 ? 3822 (every second pixel) 238 238 3824 ? 3838 (every second pixel) 239 239 table 29. sequencer x-address mapping for odd pixels of odd rows during checkerboard subsampling pixel array even column no. kernel number sequencer x-address 0 ? 15 (every second pixel) 0 0 17 ? 31 (every second pixel) 1 1 ? ? ? 3809 ? 3823 (every second pixel) 238 238 3825 ? 3839 (every second pixel) 239 239 for 1 2 binning, even columns of pixel array are addressed by sequencer with the following mapping: x ? address of sequencer 8 = pixel array column number odd columns of pixel array are addressed by sequencer with the following mapping: (x ? address of sequencer ? 1) 8 + 1 = pixel array column number table shows the column to its x ? address mapping in sequencer for 1 2 binning. table 30. sequencer x-address mapping for 1 x 2 binning pixel array column no. kernel number sequencer x-address 0 ? 14 (every second pixel) 0 0 1 ? 15 (every second pixel) 1 1 16 ? 30 (every second pixel) 2 2 17 ? 31 (every second pixel) 3 3 ? ? ? 3808 ? 3822 (every second pixel) 476 476 noim1sm9600a, noim2sm9600a http://onsemi.com 29 3809 ? 3823 (every second pixel) 477 477 3824 ? 3838 (every second pixel) 478 478 3825 ? 3839 (every second pixel) 479 479 black calibration the sensor automatically calibrates the black level for each frame. therefore, the device generates a configurable number of electrical black lines at the start of each frame. the desired black level in the resulting output interface can be configured and is not necessarily targeted to ?0?. configuring the target to a higher level yields some information on the left side of the black level distribution, while the other end of the distribution tail is clipped to ?0? when setting the black level target to ?0?. the black level is calibrated for the 8 columns contained in one kernel. configurable parameters for the black ? level algorithm are listed in table 20. black reference the sensor reads out one or more black lines at the start of every new frame. the number of black lines to be generated is programmable and is minimal equal to 1. the length of the black lines depends on the operation mode. for rolling shutter mode, the length of the black line is equal to the line length configured in the active window. the black references are used to perform black calibration and offset compensation in the data channels. the raw black pixel data is transmitted over the usual output interface, while the regular image data is compensated (can be bypassed). on the output interface, black lines can be seen as a separate window, however without frame start and ends (only line start/end). the sync code following the line start and line end indications (?window id?) contains the active window number for rolling shutter operation. black reference data is classified by a bl code. black line address should be configured through spi register 230[9:5] according to the following table. table 31. black line address for different subsampling and binning schemes scheme / pixel architecture black line address normal 2 r1s1 1 r2s2 1 checkerboard 2 1 x 2 binning 1 2 x 2 binning 1 noim1sm9600a, noim2sm9600a http://onsemi.com 30 signal path gain analog gain stages the default settings are optimized for the best performance. digital gain stage the digital gain stage allows fine gain adjustments on the digitized samples. the gain configuration is an absolute 5.7 unsigned number (5 digits before and 7 digits after the decimal point). automatic exposure control the default settings are optimized for the best performance. temperature sensor the mano 9600 has an on-chip temperature sensor which can output a digital code (tsensor) of the silicon junction temperature. the tsensor output is a 8-bit digital count between 0 and 255, proportional to the temperature of the silicon substrate. this reading can be translated directly to a temperature reading in c by calibrating the 8-bit readout at 0 c and 70 c to achieve an output accuracy of 2 c. the tsensor output can also be calibrated using a single temperature point (example: room temperature or the ambient temperature of the application), to achieve an output accuracy of 5 c. the resolution of the temperature sensor in oc / bit is made almost constant over process variations by design. therefore any process variation will result in an offset in the bit count and this offset will remain within 5 c over the temperature range of 0 c and 70 c. tsensor output digital code can be read out through the spi interface. refer to the register map on page 44. the output of the temperature sensor to the spi: tempd_reg_temp<7:0>: this is the 8-bit n count readout proportional to temperature. the input from the spi: the reg_tempd_enable is a global enable and this enables or disables the temperature sensor when logic high or logic low respectively. the temperature sensor is reset or disabled when the input reg_tempd_enable is set to a digital low state. calibration using one temperature point the temperature sensor resolution is fixed for a given type of package for the operating range of 0 c to +70 c and hence devices can be calibrated at any ambient temperature of the application, with the device configured in the mode of operation. interpreting the actual temperature for the digital code readout: the formula used is t j = r (nread - ncalib) + tcalib t j = junction die temperature r = resolution in degrees/lsb (typical 0.75 deg/lsb) nread = tsensor output (lsb count between 0 and 255) tcalib = tsensor calibration temperature ncalib = tsensor output reading at tcalib monitor pins the internal sequencer has two monitor outputs (pin 44 and pin 45) that can be used to communicate the internal states from the sequencer. a three-bit register configures the assignment of the pins. table 32. register setting for the monitor select pin monitor_select [2:0] 192 [13:11] monitor pin description 0x0 monitor0 monitor1 ?0? ?0? 0x1 monitor0 monitor1 integration time rot indication (?1? during rot, ?0? outside) 0x2 monitor0 monitor1 integration time dual/triple slope integration (asserted during ds/ts fot sequence) 0x3 monitor0 monitor1 start of x-readout indication black line indication (?1? during black lines, ?0? outside) 0x4 monitor0 monitor1 frame start indication start of rot indication 0x5 monitor0 monitor1 first line indication (?1? during first line, ?0? for all others) start of rot indication 0x6 monitor0 monitor1 rot indication (?1? during rot, ?0? outside) start of x-readout indication 0x7 monitor0 monitor1 start of x-readout indication for black lines start of x-readout indication for image lines noim1sm9600a, noim2sm9600a http://onsemi.com 31 data output format the mano 9600 is available in two different versions: ? m1-sm: four lvds output channels, together with an lvds clock output and an lvds synchronization output channel. ? m2-sm: a 10-bit parallel cmos output, together with a cmos clock output and ?frame valid? and ?line valid? cmos output signals. m1-sm: lvds interface version lvds output channels the image data output occurs through four lvds data channels where a synchronization lvds channel and an lvds output clock signal synchronizes the data. the four data channels are used to output the image data only. the sync channel transmits information about the data sent over these data channels (includes codes indicating black pixels, normal pixels, and crc codes). 8-bit / 10-bit mode the sensor can be used in 8-bit or 10-bit mode. in 10-bit mode, the words on data and sync channel have a 10-bit length. the output data rate is 620 mbps. in 8-bit mode, the words on data and sync channel have an 8-bit length, the output data rate is 496 mbps. note that the 8-bit mode can only be used to limit the data rate at the consequence of image data word depth. it is not supported to operate the sensor in 8-bit mode at a higher clock frequency to achieve higher frame rates. frame format the frame format is explained by example of the readout of two (overlapping) windows as shown in figure 18 (a). the readout of a frame occurs on a line-by-line basis. the read pointer goes from left to right, bottom to top. figure 18 indicates that, after the fot is completed, the sensor reads out a number of black lines for black calibration purposes. after these black lines, the windows are processed. first a number of lines which only includes information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. from there on, only data of ?roi 1? appears on the data output channels until line position y1_end is reached. during read out of the image data over the data channels, the sync channel sends out frame synchronization codes which give information related to the image data that is sent over the four data output channels. each line of a window starts with a line start (ls) indication and ends with a line end (le) indication. the line start of the first line is replaced by a frame start (fs); the line end of the last line is replaced with a frame end indication (fe). each such frame synchronization code is followed by a window id (range 0 to 7). for overlapping windows, the line synchronization codes of the overlapping windows with lower ids are not sent out (as shown in the illustration: no le/fe is transmitted for the overlapping part of window 0). note: in figure 18, only frame start and frame end sync words are indicated in (b). crc codes are also omitted from the figure. noim1sm9600a, noim2sm9600a http://onsemi.com 32 figure 18. m1 ? sm: frame sync codes (a) (b) y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 reset n exposure time n reset n+1 exposure time n+1 roi 0 fot fot integration time handling readout handling fot roi 1 readout frame n-1 readout frame n roi 0 roi 1 fs0 fs1 fe1 fs0 fs1 fe1 figure 19 shows the detail of a black line readout during global or full-frame readout. figure 19. m1 ? sm: time line for black line readout data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot 0 training tr ls training tr fot rot rot rot rot crc bl timeslot 1 timeslot 157 timeslot 158 timeslot 159 crc timeslot bl 0 blblblblle 0 noim1sm9600a, noim2sm9600a http://onsemi.com 33 figure 20 shows the details of the readout of a number of lines for single window readout, at the beginning of the frame. figure 20. m1 ? sm: time line for single window readout (at the start of a frame) data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot xstart training tr fs id training tr id rot crc img img img img img timeslot xstart + 1 timeslot xend - 2 timeslot xend - 1 timeslot xend crc timeslot img le rot rot rot fot figure 21 shows the detail of the readout of a number of lines for readout of two overlapping windows. figure 21. m1 ? sm: time line showing the readout of two overlapping windows data channels sync channel data channels sync channel sequencer internal state line ys+1 line ye black timeslot xstartm training tr ls idm img le training tr idn rot crc img ls idn img img timeslot xstartn timeslot xendn line ys img rot rot rot fot frame synchr onization for 10 ? bit mode table 33 shows the structure of the frame synchronization code. note that the table shows the default data word (configurable) for 10-bit mode. if more than one window is active at the same time, the sync channel transmits the frame synchronization codes of the window with highest index only. table 33. frame synchronization code details for 10-bit mode sync word bit position register address default value description 9:7 n/a 0x5 frame start indication 9:7 n/a 0x6 frame end indication 9:7 n/a 0x1 line start indication 9:7 n/a 0x2 line end indication 6:0 131[6:0] 0x2a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting noim1sm9600a, noim2sm9600a http://onsemi.com 34 ? window identification frame synchronization codes are always followed by a 3-bit window identification (bits 2:0). this is an integer number, ranging from 0 to 7, indicating the active window. if more than one window is active for the current cycle, the highest window id is transmitted. ? data classification codes for the remaining cycles, the sync channel indicates the type of data sent through the data links: black pixel data (bl), image data (img), or training pattern (tr). these codes are programmable by a register setting. the default values are listed in table 31. table 34. synchronization channel default identification code values for 10-bit mode sync word bit position register address default value description 9:0 132 [9:0] 0x015 black pixel data (bl). this data is not part of the image. the black pixel data is used in- ternally to correct channel offsets. 9:0 133 [9:0] 0x035 valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 9:0 134 [9:0] 0x059 crc value. the data on the data output channels is the crc code of the finished image data line. 9:0 135 [9:0] 0x3a6 training pattern (tr). the sync channel sends out the training pattern which can be pro- grammed by a register setting. frame synchronization in 8-bit mode the frame synchronization words are configured using the same registers as in 10-bit mode. the two least significant bits of these configuration registers are ignored and not sent out. table 32 shows the structure of the frame synchronization code, together with the default value, as specified in spi registers. the same restriction for overlapping windows applies in 8-bit mode. table 35. frame synchronization code details for 8-bit mode sync word bit position register address default value description 7:5 n/a 0x5 frame start (fs) indication 7:5 n/a 0x6 frame end (fe) indication 7:5 n/a 0x1 line start (ls) indication 7:5 n/a 0x2 line end (le) indication 4:0 [6:2] 0x0a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting. ? window identification similar to 10-bit operation mode, the frame synchronization codes are followed by a window identification. the window id is located in bits 4:2 (all other bit positions are ?0?). the same restriction for overlapping windows applies in 8-bit mode. ? data classification codes bl, img, crc, and tr codes are defined by the same registers as in 10-bit mode. bits 9:2 of the respective configuration registers are used as classification code with default values shown in table 33. table 36. synchronization channel default identification code values for 8-bit mode sync word bit position register address default value description 7:0 132 [9:2] 0x05 black pixel data (bl). this data is not part of the image. the black pixel data is used internally to correct channel offsets. 7:0 133 [9:2] 0x0d valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 7:0 134 [9:2] 0x16 crc value. the data on the data output channels is the crc code of the finished image data line. 7:0 135 [9:2] 0xe9 training pattern (tr). the sync channel sends out the training pattern which can be programmed by a register setting. noim1sm9600a, noim2sm9600a http://onsemi.com 35 training patterns on data channels in 10-bit mode, during idle periods, the data channels transmit training patterns, indicated on the sync channel by a tr code. these training patterns are configurable independent of the training code on the sync channel as shown in table 34. in 8-bit mode, the training pattern for the data channels is defined by the same register as in 10-bit mode, where the lower two bits are omitted; see table 35. table 37. training code on sync channel in 10-bit mode sync word bit position register address default value description [9:0] 130 [9:0] 0x3a6 data channel training pattern. the data output channels send out the training pattern, which can be programmed by a register setting. the default value of the training pattern is 0x3a6, which is identical to the training pattern indication code on the sync channel. table 38. training pattern on data channel in 8-bit mode data word bit position register address default value description [7:0] 130 [9:2] 0xe9 data channel training pattern (training pattern). cyclic redundancy code at the end of each line, a crc code is calculated to allow error detection at the receiving end. each data channel transmits a crc code to protect the data words sent during the previous cycles. idle and training patterns are not included in the calculation. the sync channel is not protected. a special character (crc ind ication) is transmitted whenever the data channels send their respective crc code. the polynomial in 10-bit operation mode is x 10 +x 9 +x 6 +x 3 +x 2 + x + 1. the crc encoder is seeded at the start of a new line and updated for every (valid) data word received. the crc seed is configurable using the crc_seed register. when ?0?, the crc is seeded by all-?0?; when ?1? it is seeded with all-?1?. in 8-bit mode, the polynomial is x 8 +x 6 +x 3 +x 2 +1. the crc seed is configured by means of the crc_seed register. note the crc is calculated for every line. this implies that the crc code can protect lines from multiple windows. noim1sm9600a, noim2sm9600a http://onsemi.com 36 data or der for m1 ? sm to read out the image data through the output channels, the pixel array is organized in kernels. each row consists of 480 kernels. even positioned kernel consists of 8 consecutive even pixels and odd positioned kernel consists of 8 consecutive odd kernels. so the kernel size is 8 pixels in x ? direction by 1 pixel in y ? direction. f igure 22 indicates how the kernels are organized. the first kernel (kernel [0, 0]) is located in the bottom left corner. the data order of this image data on the data output channels depends on the subsampling mode. figure 22. kernel organization in pixel array roi kernel (0,0) kernel (479,2499) kernel (x_start,y_start) 0 7 3 2 1 5 6 pixel array pixel (0,2499) pixel (3839,0) ? m1 ? sm: no subsampling the image data is read out in kernels of eight pixels in x ? direction by one pixel in y ? direction. one data channel output delivers two pixel values of one kernel sequentially. figure 23 shows how a kernels are read out over the four output channels. each row consists of 480 kernels. first pair of kernels is read out ascending, while the next pair of kernels is read out descending. similarly, all even pairs of kernels are read out in ascending order and odd pairs of kernel are read out in descending order. table 39 indicates the pixel data order of each channel for 1st 16 data ? outputs. shaded grey cells shows data order for even pair of kernels and the non ? shaded cells shows data order for odd pair of kernels. table 39. m1 ? sm: data output order when subsampling is disabled data number pixels on channel 0 pixels on channel 1 pixels on channel 2 pixels on channel 3 0 0 4 8 12 1 2 6 10 14 2 1 5 9 13 3 3 7 11 15 4 30 26 22 18 5 28 24 20 16 6 31 27 23 19 7 29 25 21 17 8 32 36 40 44 9 34 38 42 46 10 33 37 41 45 11 35 39 43 47 12 62 58 54 50 13 60 56 52 48 14 63 59 55 51 15 61 57 53 49 figure 23. m1 ? sm: data output order when subsampling is disabled kernel 0 kernel 3 kernel 2 kernel 1 0 8 6 4 2 10 14 12 1 st kernel of 1 st pair channel #0 channel #1 channel#3 channel#2 1 9 7 5 3 13 15 2 nd kernel of 1 st pair 11 channel #0 channel #1 channel#3 channel#2 1 st pair of kernel 2nd pair of kernel 30 22 24 26 28 20 16 18 1 st kernel of 2 nd pair channel #1 channel#3 channel#2 31 23 25 27 29 19 17 2 nd kernel of 2 nd pair 21 channel #0 channel #1 channel#3 channel#2 channel #0 noim1sm9600a, noim2sm9600a http://onsemi.com 37 ? m1 ? sm: read ? 1 ? skip ? 1 subsampling for read ? 1 ? skip ? 1 sub ? sampling, only even pixels of a row are readout with next full row of pixels (even/odd pixels of next row) skipped. hence one line is read out in 240 kernels. data for even kernels are read out in ascending order and for odd kernels it is read out in descending order as shown in figure 24. table 40 shows the data order for first eight data outputs of a row. figure 24. m1 ? sm: data output order for read ? 1 ? skip ? 1 subsampling kernel 0 kernel 3 kernel 2 kernel 1 0 8 6 4 2 10 14 12 pixel # (even kernel) channel #0 channel #1 channel#3 channel#2 30 22 24 26 28 18 16 pixel # (odd kernel) 10 ? bit 10 ? bit msb lsb msb lsb note: the bit order is always msb first, regardless the kernel number 20 channel #0 channel #1 channel#3 channel#2 table 40 shows data order for readout of even and odd kernels for read ? 1 ? skip ? 1 subsampling for first eight data outputs on output channels. table 40. m1 ? sm: data output order read ? 1skip ? 1 subsampling data number pixels on channel 0 pixels on channel 1 pixels on channel 2 pixels on channel 3 0 0 4 8 12 1 2 6 10 14 2 30 26 22 18 3 28 24 20 16 4 32 36 40 44 5 34 38 42 46 6 62 58 54 50 7 60 56 52 48 note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no ? subsampling? readout. m1 ? sm: checkerboard subsampling for checkerboard subsampling, readout of even pixels of one row is followed by readout of odd pixels of the next row. figure 25 and figure 40 show how a even and odd kernels are read out over the four output channels, for even and odd pixels segment of a row respectively. each segment consists of 240 kernels. for even pixel segment of a row, even positioned kernels are read out ascending, while for odd positioned kernels the data order is reversed (descending). for odd pixel segment of a line also, even positioned kernels are read out ascending, while for odd positioned kernel the data order is reversed (descending). note that a window should always start at an even x ? address, such that the first kernel of a segment is always at an even position. noim1sm9600a, noim2sm9600a http://onsemi.com 38 figure 25. m1 ? sm: data output order for even pixels of line during checkerboard subsampling kernel 0 kernel 3 kernel 2 kernel 1 0 8 6 4 2 10 14 12 pixel # (even kernel) channel #0 channel #1 channel#3 channel#2 30 22 24 26 28 18 16 pixel # (odd kernel) 10 ? bit 10 ? bit msb lsb msb lsb note: the bit order is always msb first, regardless the kernel number 20 channel #0 channel #1 channel#3 channel#2 table 41 shows data order for readout of even and odd kernels of even pixels of a line for first eight data outputs on output channels. table 41. m1 ? sm: data output order for even pixels of line during checkerboard subsampling data number pixels on channel 0 pixels on channel 1 pixels on channel 2 pixels on channel 3 0 0 4 8 12 1 2 6 10 14 2 30 26 22 18 3 28 24 20 16 4 32 36 40 44 5 34 38 42 46 6 62 58 54 50 7 60 56 52 48 table 42 shows data order for readout of even and odd kernels of odd pixels of a line for first eight data outputs on output channels. table 42. m1 ? sm: data output order for odd pixels of line during checkerboard subsampling data number pixels on channel 0 pixels on channel 1 pixels on channel 2 pixels on channel 3 0 1 5 9 13 1 3 7 11 15 2 31 27 23 19 3 29 25 21 17 4 33 37 41 45 5 35 39 43 47 6 63 59 55 51 7 61 57 53 49 noim1sm9600a, noim2sm9600a http://onsemi.com 39 figure 26. m1 ? sm: data output order for odd pixels of line during checkerboard subsampling kernel 0 kernel 3 kernel 2 kernel 1 1 9 7 5 3 11 15 13 pixel # (even kernel) channel #0 channel #1 channel#3 channel#2 31 23 25 27 29 19 17 pixel # (odd kernel) 21 channel #0 channel #1 channel#3 channel#2 time time 10 ? bit 10 ? bit msb lsb msb lsb note: the bit order is always msb first m1 ? sm: 1 x 2 binning for 1 2 binning, every pixel in an even row is binned with a similar positioned pixel in the odd row. data output format is the same as readout of normal row readout with no subsampling. data order is similar to that shown in figure 23 and table 40 on page 37. the only difference is that every pixel in even row is binned with the corresponding pixel in the next odd row. m1 ? sm: 2 x 2 binning for 2 2 binning, data order for even and odd kernel is shown in figure 27, showing binning between two adjacent pixels in x ? direction for row 0 and row 1. figure 27. m1 ? sm: data output order for 2 x 2 binning kernel 0 kernel 3 kernel 2 kernel 1 0,1 8,9 6,7 4,5 2,3 10,11 14,15 12,13 pixel # (even kernel) channel #0 channel #1 channel#3 channel#2 30,31 22,23 24,25 26,27 28,29 18,19 16,17 pixel # (odd kernel) 10 ? bit 10 ? bit msb lsb msb lsb note: binning of 22,23 pixel of row 0 and 22,23 pixel of row1. the bit order is always msb first 20,21 channel #0 channel #1 channel#3 channel#2 noim1sm9600a, noim2sm9600a http://onsemi.com 40 table 43 shows data order for 2 2 binning of two pixels in even row with same pixel# in odd row for first eight data outputs on output channels. table 43. m1 ? sm: data output order for 2 x 2 binning data number pixels on channel 0 pixels on channel 1 pixels on channel 2 pixels on channel 3 0 bin(0,1) bin(4,5) bin(8,9) bin(12,13) 1 bin(2,3) bin(6,7) bin(10,11) bin(14,15) 2 bin(30,31) bin(26,27) bin(22,23) bin(18,19) 3 bin(28,29) bin(24,25) bin(20,21) bin(16,17) 4 bin(32,33) bin(36,37) bin(40,41) bin(44,45) 5 bin(34,35) bin(38,39) bin(42,43) bin(46,47) 6 bin(62,63) bin(58,59) bin(54,55) bin(50,51) 7 bin(60,61) bin(56,57) bin(52,53) bin(48,49) m2 ? sm: cmos interface version cmos output signals the image data output occurs through a single 10-bit parallel cmos data output, operating at 62 mbps. the function of the cmos clock output, ?frame valid? and ?line valid? signal is to synchronize the output data. no windowing information is sent out by the sensor. 8-bit/10-bit mode the 8-bit mode is not supported when using the parallel cmos output interface. frame format frame timing is indicated by means of two signals: frame_valid and line_valid. the frame_valid indication is asserted at the start of a new frame and remains asserted until the last line of the frame is completely transmitted. the line_valid indication serves the following needs: ? while the line_valid indication is asserted, the data channels contain valid pixel data. ? the line valid communicates frame timing as it is asserted at the start of each line and it is de-asserted at the end of the line. low periods indicate the idle time between lines (rot). ? the data channels transmit the calculated crc code after each line. this can be detected as the data words right after the falling edge of the line valid. the readout of a frame occurs on a line ? by ? line basis. the read pointer goes from left to right, bottom to top as shown in figure 29. reset handling is shown in figure 29 (b). the row ?y_start? is reset and then after a wait period of one line time, with line length defined by window size in x ? direction, reset pointer moves to next row ?y_start + 1? and this row is reset. and sequence will continue until row ?y_end? is reset. after exposure time, readout happens according to readout handling shown in figure 29 (c). after rot, row ?y_start? is read out. then after next rot, the pixels of the row addressed by ?y_start + 1? are read out. and sequence will continue until row ?y_end? is read out. figure 28. m2 ? sm: frame timing indication data channels sequencer internal state line ys line ys+1 line ye black fot rot rot rot rot fot rot black frame_valid line_valid noim1sm9600a, noim2sm9600a http://onsemi.com 41 figure 29. m2 ? sm: frame format to read out image data y_end y_start x_start x_end roi rot reset row y_start rot reset row y_start + 1 rot reset row y_end-1 rot reset row y_end rot reset row y_start + 2 rot read row y_start rot rot read row y_end-1 rot read row y_end rot reset handling readout handling fs?lelslele lsls?lels?le (a) (3840,2500) 3840 columns 2500 rows (b) frame valid line valid (c) read row y_start + 1 read row y_start + 2 black lines: black pixel data is also sent through the data channels. to distinguish these pixels from the regular image data, it is possible to ?mute? the frame and/or line valid indications for the black lines. table 44. black line frame_valid and line_valid settings bl_frame_val- id_enable bl_line_val- id_enable description 0x1 0x1 the black lines are handled similar to normal image lines. the frame valid indication is asserted before the first black line and the line valid indication is asserted for every valid (black) pixel. 0x1 0x0 the frame valid indication is asserted before the first black line, but the line valid indication is not asserted for the black lines. the line valid indication indicates the valid image pixels only. this mode is useful when one does not use the black pixels and when the frame valid indication needs to be asserted some time before the first image lines (for example, to precondition isp pipelines). 0x0 0x1 in this mode, the black pixel data is clearly unambiguously indicated by the line valid indication, while the decoding of the real image data is simplified. 0x0 0x0 black lines are not indicated and frame and line valid strobes remain de-asserted. note however that the data channels contains the black pixel data and crc codes (training patterns are inter- rupted). data order to read out the image data through the parallel cmos output, the pixel array is divided in kernels. the kernel size is eight pixels in x ? direction by one pixel in y ? direction. figure 22 on page 35 indicates how the kernels are organized. the data order of this image data depends on the subsampling mode. m2 ? sm: no subsampling the image data is read out in kernels of 8 pixels in x ? direction by 1 pixel in y ? direction. figure 30 shows how a kernel is read out over parallel output channel. one row consists of 480 kernels. these kernels are divided further into pairs of two kernels, hence forming 240 pairs. even pair of kernels is read out in ascending order, while for odd pair of kernels the data order is reversed (descending). noim1sm9600a, noim2sm9600a http://onsemi.com 42 figure 30. m2 ? sm: data output order without subsampling kernel 0 kernel 3 kernel 2 kernel 1 0 2 12 8 4 6 14 10 1 st kernel of 0 th pair 1 3 13 9 5 11 15 2 nd kernel of 0 th pair 7 even pair of kernel odd pair of kernel 30 22 24 26 28 20 16 18 time 31 23 25 27 29 19 17 21 time 1 st kernel of 1 st pair 2 nd kernel of 1 st pair time time m2 ? sm: read ? 1 ? skip ? 1 subsampling to read out the image data with subsampling enabled on a monochrome sensor, two neighboring kernels are combined to a single kernel of 16 pixels in the x ? direction and one pixel in the y ? direction. only the pixels at the even pixel positions inside that kernel are read out. figure 31 shows the data order. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no ? subsampling? readout. figure 31. m2 ? sm: data output order with read ? 1 ? skip ? 1 subsampling kernel 0 kernel 3 kernel 2 kernel 1 0 2 12 8 4 6 14 10 pixel # of even kernel 30 28 18 22 26 20 16 pixel # of odd kernel 24 time time m2 ? sm: checkerboard subsampling to read out the image data with check ? board pattern sub ? sampling enabled on a monochrome sensor, readout of even pixels of one row will be followed by readout of odd pixels of next row. data order for even pixels will be same as read ? 1 ? skip ? 1 as shown in figure 31. data order for readout of odd pixels is shown in figure 32. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no ? subsampling? readout. figure 32. m2 ? sm: data output order for odd pixel during checkerboard subsampling kernel 0 kernel 3 kernel 2 kernel 1 0 3 13 9 5 7 15 11 pixel # of even kernel 31 29 19 23 27 21 17 pixel # of odd kernel 25 time time m2 ? sm: 1 x 2 binning for 1 2 binning, data output order will be same as no ? subsampling as shown in figure 30. the only dif ference is that pixels is binned with same positioned pixel in the next row. m2 ? sm: 2 x 2 binning to read out the image data with 2 2 binning enabled on a monochrome sensor, data order will be same as read ? 1 ? skip ? 1 sub ? sampling but pixel being readout will be binned with odd pixel next to it and same positioned pixels in the next row as shown in figure 33. noim1sm9600a, noim2sm9600a http://onsemi.com 43 figure 33. m2 ? sm: data output order for 2 x 2 binning kernel 0 kernel 3 kernel 2 kernel 1 0,1 2,3 12,13 8,9 4,5 6,7 14,15 10,11 even kernel 30,31 28,29 18,19 22,23 25,27 20,21 16,17 odd kernel 24,25 time time binned pixel # in row 0 and row 1 binned pixel # in row 0 and row 1 noim1sm9600a, noim2sm9600a http://onsemi.com 44 register map each functional entity has a dedicated address space, starting at a block of fset. the register address is obtained by adding the address offset to the block offset. this address must be used to perform spi uploads and is shown in the address column of the register map table. table 45. register map address offset address bit field register name default (hex) default (dec) description type chip id [block offset: 0] 0 0 chip_id 0x04d60 19808 ro [15:0] id 0x04d60 19808 on semiconductor chip id 1 1 reserved 0x0000 0 ro [3:0] reserved 0x0000 0 reserved 2 2 chip_configuration 0x0000 0 rw [1:0] 0x0 0 configure as per part number: noim1sm9600a-qdc: 0x0 NOIM2SM9600A-QDC: 0x2 reset generator [block offset: 8] 0 8 soft_reset_pll 0x099 153 rw [3:0] pll_soft_reset 0x9 9 pll reset 0x9: soft reset state others: operational [7:4] pll_lock_soft_reset 0x9 9 pll lock detect reset 0x9: soft reset state others: operational 1 9 soft_reset_cgen 0x09 9 rw [3:0] cgen_soft_reset 0x9 9 clock generator reset 0x9: soft reset state others: operational 2 10 soft_reset_analog 0x0999 2457 rw [3:0] mux_soft_reset 0x9 9 column mux reset 0x9: soft reset state others: operational [7:4] afe_soft_reset 0x9 9 afe reset 0x9: soft reset state others: operational [11:8] ser_soft_reset 0x9 9 serializer reset 0x9: soft reset state others: operational pll [block offset: 16] 0 16 power_down 0x0004 4 rw [0] pwd_n 0x0 0 pll power down ?0? = power down, ?1? = operational [1] enable 0x0 0 pll enable ?0? = disabled, ?1? = enabled [2] bypass 0x1 1 pll bypass ?0? = pll active, ?1? = pll bypassed noim1sm9600a, noim2sm9600a http://onsemi.com 45 table 45. register map address offset type description default (dec) default (hex) register name bit field address 1 17 config 0x2113 8467 rw [7:0] mdiv 0x13 19 m-divider 19: 10 bit lvds, 15: 8 bit lvds [12:8] ndiv 0x1 1 n-divider [14:13] pdiv 0x1 1 p-divider io [block offset: 20] 0 20 config 0x0000 0 rw [0] clock_in_pwd_n 0x0 0 power down clock input [10:8] reserved 0x0 0 reserved pll lock detector [block offset: 24] 0 24 pll_lock 0x0000 0 ro [0] lock 0x0 0 pll lock indication clock generator [block offset: 32] 0 32 config 0x0004 4 rw [0] enable_analog 0x0 0 enable analog clocks ?0? = disabled, ?1? = enabled [1] enable_log 0x0 0 enable logic clock ?0? = disabled, ?1? = enabled [2] select_pll 0x1 1 input clock selection ?0? = select lvds clock input, ?1? = select pll clock input [3] adc_mode 0x0 0 set operation mode ?0? = 10-bit mode, ?1? = 8-bit mode [4] enable_div_2 0x0 0 enable the divide by 2 circuit ?0? = pll input direct to cgen ?1? = divide pll input by 2 before applying it to cgen [11:8] reserved 0x0 0 reserved [14:12] reserved 0x0 0 reserved general logic [block offset: 34] 0 34 config 0x0000 0 rw [0] enable 0x0 0 logic general enable configuration ?0? = disable ?1? = enable noim1sm9600a, noim2sm9600a http://onsemi.com 46 table 45. register map address offset type description default (dec) default (hex) register name bit field address image core [block offset: 40] 0 40 image_core_config 0x0000 0 rw [0] imc_pwd_n 0x0 0 image core power down ?0? = powered down, ?1? = powered up [1] mux_pwd_n 0x0 0 column multiplexer power down ?0? = powered down, ?1? = powered up [2] colbias_enable 0x0 0 bias enable ?0? = disabled ?1? = enabled afe [block offset:48] 0 48 power_down 0x0000 0 rw [0] pwd_n 0x0 0 power down for afe?s (64 columns) ?0? = powered down, ?1? = powered up bias [block offset: 64] 0 64 power_down 0x0000 0 rw [0] pwd_n 0x0 0 power down bandgap ?0? = powered down, ?1? = powered up 1 65 configuration 0x888b 34955 rw [0] extres 0x1 1 external resistor selection ?0? = internal resistor, ?1? = external resistor [3:1] bgrtrim 0x5 5 bandgap trim [7:4] imc_colpc_ibias 0x8 8 column precharge ibias configuration [11:8] imc_colbias_ibias 0x8 8 column bias ibias configuration [15:12] cp_ibias 0x8 8 charge pump bias 2 66 afe_bias 0x53c8 21448 rw [3:0] afe_ibias 0x8 8 afe ibias configuration [7:4] afe_adc_iref 0xc 12 adc iref configuration [14:8] afe_pga_iref 0x53 83 pga iref configuration 3 67 mux_bias 0x08888 34952 rw [3:0] mux_25u_stage1 0x8 8 column multiplexer stage 1 bias configuration [7:4] mux_25u_stage2 0x8 8 column multiplexer stage 2 bias configuration [11:8] mux_25u_delay 0x8 8 column multiplexer delay bias configuration [15:12] mux_25u_vcmbuff 0x8 8 column multiplexer vcm bias configuration 4 68 lvds_bias 0x0088 136 rw [3:0] lvds_ibias 0x8 8 lvds ibias noim1sm9600a, noim2sm9600a http://onsemi.com 47 table 45. register map address offset type description default (dec) default (hex) register name bit field address [7:4] lvds_iref 0x8 8 lvds iref 5 69 fine_trim 0x0000 0 rw [1:0] mux_stage1_fine_trim 0x0 0 fine trim setting for col ? mux stage1 bias [3:2] mux_stage2_fine_trim 0x0 0 fine trim setting for col ? mux stage2 bias [5:4] mux_auxamp_stage1 _fine_trim 0x0 0 fine trim setting for auxiliary amplifier stage1 bias [7:6] mux_auxamp_stage2 _fine_trim 0x0 0 fine trim setting for auxiliary amplifier stage2 bias [9:8] afe_5u_fine_trim 0x0 0 fine trim setting for afe bias [11:10] adcref_5u_fine_trim 0x0 0 fine trim setting for adc reference bias col ? mux 1 81 config 0x8881 34945 rw [15:0] reserved 0x8881 34945 temperature sensor [block offset: 96] 0 96 sensor enable 0x0000 0 rw [0] reg_tempd_enable 0x0 0 temperature diode enable ?0? = disabled ?1? = enabled 1 97 sensor output 0x0000 0 ro [7:0] tempd_reg_temp 0x00 0 temperature readout serializer/lvds [block offset: 112] 0 112 power_down 0x0000 0 rw [0] clock_out_pwd_n 0x0 0 power down for clock output. ?0? = powered down, ?1? = powered up [1] sync_pwd_n 0x0 0 power down for sync channel ?0? = powered down, ?1? = powered up [2] data_pwd_n 0x0 0 power down for data channels (4 channels) ?0? = powered down, ?1? = powered up data block [block offset: 128] 0 128 blackcal 0x4008 16392 rw [7:0] black_offset 0x08 8 desired black level at output [10:8] black_samples 0x0 0 black pixels taken into account for black calibration. total samples = 2**black_samples [14:11] adc_offset 0x8 8 adc offset = 2**adc_offset. this setting should correspond to the calibration dac setting [15] crc_seed 0x0 0 crc seed ?0? = all-0 ?1? = all-1 noim1sm9600a, noim2sm9600a http://onsemi.com 48 table 45. register map address offset type description default (dec) default (hex) register name bit field address 1 129 general_configuration 0xc001 49153 rw [0] auto_blackcal_enable 0x1 1 automatic blackcalibration is enabled when 1, bypassed when 0 [9:1] blackcal_offset 0x00 0 black calibration offset used when auto_black_cal_en = ?0?. [10] blackcal_offset_dec 0x0 0 blackcal_offset is added when 0, subtracted when 1 [11] compress_bypass 0x0 0 bypass compression of 11 bit adc data to 10 bit output data when 1 [12] bypass 0x0 0 bypass datablock (test only) when ?1?. use default value for normal operation. [13] 8bit_mode 0x0 0 shifts window id indications by 4 cycles. ?0? = 10 bit mode, ?1? = 8 bit mode [14] bl_frame_valid_ enable 0x1 1 assert frame_valid for black lines when ?1?, gate frame_valid for black lines when ?0?. NOIM2SM9600A-QDC [15] bl_line_valid_enable 0x1 1 assert line_valid for black lines when ?1?, gate line_valid for black lines when ?0?. NOIM2SM9600A-QDC 2 130 trainingpattern 0x03a6 934 rw [9:0] trainingpattern 0x3a6 934 training pattern sent on data channels during idle mode. this data is used to perform word alignment on the lvds data channels. [10] reserved 0x0 0 reserved 3 131 sync_code0 0x002a 42 rw [6:0] frame_sync 0x02a 42 frame sync lsbs. note: the 10 th bit indicates frame/ line sync code, 9 th bit indicates start, 8 th bit indicates end. 4 132 sync_code1 0x0015 21 rw [9:0] bl 0x015 21 black pixel identification sync code 5 133 sync_code2 0x0035 53 rw [9:0] img 0x035 53 valid pixel identification sync code 6 134 sync_code3 0x0059 89 rw [9:0] crc 0x059 89 crc value identification sync code 7 135 sync_code4 0x03a6 934 rw [9:0] tr 0x3a6 934 training value identification sync code noim1sm9600a, noim2sm9600a http://onsemi.com 49 table 45. register map address offset type description default (dec) default (hex) register name bit field address datablock - test 16 144 test_configuration 0x0000 0 rw [0] testpattern_en 0x0 0 insert synthesized testpattern when ?1? [1] inc_testpattern 0x0 0 incrementing testpattern when ?1?, constant testpattern when ?0? [2] prbs_en 0x0 0 insert prbs when ?1? [3] frame_testpattern 0x0 0 frame test patterns when ?1?, unframed testpatterns when ?0? [4] test_adc_select 0x0 0 configures which adc of selected channels is selected to output adc data through adc_dout pins 18 146 test_configuration0 0x0100 256 rw [7:0] testpattern0_lsb 0x00 0 testpattern used on datapath #0 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern1_lsb 0x01 1 testpattern used on datapath #1 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 19 147 test_configuration1 0x0302 770 rw [7:0] testpattern2_lsb 0x02 2 testpattern used on datapath #2 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern3_lsb 0x03 3 testpattern used on datapath #3 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 20 148 test_configuration2 0x0504 1284 rw [7:0] testpattern4_lsb 0x04 4 testpattern used on datapath #4 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern5_lsb 0x05 5 testpattern used on datapath #5 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 21 149 test_configuration3 0x0706 1798 rw [7:0] testpattern6_lsb 0x06 6 testpattern used on datapath #6 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern7_lsb 0x07 7 testpattern used on datapath #7 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 22 150 test_configuration16 0x0000 0 rw [1:0] testpattern0_msb 0x0 0 testpattern used when testpattern_en = ?1? [3:2] testpattern1_msb 0x0 0 testpattern used when testpattern_en = ?1? noim1sm9600a, noim2sm9600a http://onsemi.com 50 table 45. register map address offset type description default (dec) default (hex) register name bit field address [5:4] testpattern2_msb 0x0 0 testpattern used when testpattern_en = ?1? [7:6] testpattern3_msb 0x0 0 testpattern used when testpattern_en = ?1? [9:8] testpattern4_msb 0x0 0 testpattern used when testpattern_en = ?1? [11:10] testpattern5_msb 0x0 0 testpattern used when testpattern_en = ?1? [13:12] testpattern6_msb 0x0 0 testpattern used when testpattern_en = ?1? [15:14] testpattern7_msb 0x0 0 testpattern used when testpattern_en = ?1? aec[block offset: 160] 0 160 configuration 0x0010 16 rw [0] enable 0x0 0 aec enable [1] restart_filter 0x0 0 restart aec filter [2] freeze 0x0 0 freeze aec filter and enforcer gains [3] pixel_valid 0x0 0 use every pixel from channel when 0, every 4 th pixel when 1 [4] amp_pri 0x1 1 stage 1 amplifier gets higher priority than stage 2 gain distribution if 1. vice versa if 0 1 161 intensity 0x60b8 24760 rw [9:0] desired_intensity 0xb8 184 target average intensity [13:10] clip- ping_threshold_avg 0x018 24 clipping threshold for average inc factor 3.3 unsigned 6 166 exposure 0x03ff 1023 rw [15:0] fixed_exposure 0x03ff 1023 fixed exposure time 7 167 gain 0x0800 2048 rw [1:0] gain_stage1_select 0x0 0 fixed column amplifier gain [3:2] gain_stage2_select 0x0 0 fixed afe pga gain [15:4] fixed_digital_gain 0x080 128 fixed digital gain 5.7 unsigned 8 168 min_exposure 0x0001 1 rw [15:0] min_exposure 0x0001 1 minimum exposure time 9 169 min_gain 0x0800 2048 rw [1:0] min_gain_stage1 0x0 0 minimum gain stage 1 [3:2] min_gain_stage2 0x0 0 minimum gain stage 2 [15:4] min_digital_gain 0x080 128 minimum digital gain 5.7 unsigned 10 170 max_exposure 0x03ff 1023 rw [15:0] max_exposure 0x03ff 1023 maximum exposure time 11 171 max_gain 0x100d 4109 rw [1:0] max_gain_stage1 0x1 1 maximum gain stage 1 noim1sm9600a, noim2sm9600a http://onsemi.com 51 table 45. register map address offset type description default (dec) default (hex) register name bit field address [3:2] max_gain_stage2 0x3 3 maximum gain stage 2 [15:4] max_digital_gain 0x100 256 maximum digital gain 5.7 unsigned 12 172 hysteresis 0x00083 131 rw [7:0] digital_hysteresis 0x083 131 digital hysteresis 1.7 unsigned [13:8] dim_threshold 0x00 0 dimming threshold [15:14] dim_factor 0x0 0 dimming factor 24 184 total_pixels0 0x0000 0 ro [15:0] total_pixels[15:0] 0x0000 0 total number of pixels sampled for average, lsb 25 185 total_pixels1 0x0000 0 ro [8:0] total_pixels[24:16] 0x0 0 total number of pixels sampled for average, msb 26 186 average_status 0x0000 0 ro [9:0] average 0x000 0 aec average status [12] locked 0x0 0 aec filter lock status 27 187 exposure_status 0x0000 0 ro [15:0] exposure 0x0000 0 aec exposure status 28 188 gain_status 0x00 0 ro [1:0] gain_stage1 0x0 0 gain stage 1 status [3:2] gain_stage2 0x0 0 gain stage 2 status [15:4] digital_gain 0x000 0 aec digital gain status 5.7 unsigned 29 189 reserved 0x0000 0 ro [12:0] reserved 0x000 0 reserved sequencer [block offset: 192] 0 192 general_configuration 0x00 0 rw [0] enable 0x0 0 enable sequencer ?0? = idle, ?1? = enabled [1] rolling_shutter_enable 0x0 0 operation selection ?0? = global shutter, ?1? = rolling shutter [2] zero_rot_enable 0x0 0 zero rot mode selection ?0? = normal rot, ?1? = zero rot [3] x_lag 0x0 0 x ? lag in zero rot mode ?0? = no lag, ?0? = lag [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved noim1sm9600a, noim2sm9600a http://onsemi.com 52 table 45. register map address offset type description default (dec) default (hex) register name bit field address [6] nzrot_xsm_delay_ enable 0x0 0 insert delay between end of rot and start of readout in normal rot readout mode if ?1?. rot delay is defined by register xsm_delay [7] reserved 0x0 0 reserved [8] reserved 0x0 0 reserved [10] roi_aec_enable 0x0 0 enable windowing for aec statistics. ?0? = subsample all windows ?1? = subsample configured window [13:11] monitor_select 0x0 0 control of the monitor pins [14] pls_mode 0x0 0 test mode for pls measurements 1 193 delay_configuration 0x0000 0 rw [7:0] rs_x_length 0x00 0 x-readout duration in rolling shutter mode (extends lines with dummy pixels). [15:8] xsm_delay 0x00 0 delay between rot start and x ? readout (zero rot mode) delay between rot end and x ? readout (normal rot mode with nzrot_xsm_delay_enable=?1?) 3 195 roi_active0 0x0001 1 rw [7:0] roi_active[7:0] 0x01 1 active roi?s selection 5 197 black_lines 0x0102 258 rw [7:0] black_lines 0x02 2 number of black lines. minimum is 1. range 1 ? 255 [8] gate_first_line 0x1 1 blank out first line ?0?: no blank-out ?1?: blank-out [11:9] mask_black_ coefficients 0x0 0 added for mano revb: can be used to reduce the number of black coefficients used during black calibration. when 000, all 8 coefficients are used [12] mux_black_ coefficients 0x1 0 added for mano revb: automatically set number of black coefficients during black calibration according to readout mode 6 198 dummy_lines 0x0000 0 rw [11:0] dummy_lines 0x000 0 number of dummy lines range 0 ? 2047 9 201 exposure 0x0000 0 rw [15:0] exposure 0x0000 0 exposure time rolling shutter: granularity lines 12 204 gain_configuration 0x0a2 162 rw [4:0] gain_stage1 0x02 2 gain stage 1 [12:5] gain_stage2 0x5 5 gain stage 2 noim1sm9600a, noim2sm9600a http://onsemi.com 53 table 45. register map address offset type description default (dec) default (hex) register name bit field address [13] gain_lat_comp 0x0 0 postpone gain update by 1 frame when ?1? to compensate for exposure time updates latency. gain is applied at start of next frame if ?0? 13 205 digital_gain_ configuration 0x0080 128 rw [11:0] db_gain 0x080 128 digital gain 14 206 sync_configuration 0x033f 831 rw [0] sync_rs_x_length 0x1 1 update of rs_x_length will not be sync?ed at start of frame when ?0? [1] sync_black_lines 0x1 1 update of black_lines will not be sync?ed at start of frame when ?0? [2] sync_dummy_lines 0x1 1 update of dummy_lines will not be sync?ed at start of frame when ?0? [3] sync_exposure 0x1 1 update of exposure will not be sync?ed at start of frame when ?0? [4] sync_gain 0x1 1 update of gain settings (gain_sw, afe_gain) will not be sync?ed at start of frame when ?0? [5] sync_roi 0x1 1 update of roi updates (active_roi) will not be sync?ed at start of frame when ?0? [8] blank_roi_switch 0x1 1 blank first frame after roi switching [9] blank_subsampling_ss 0x1 1 blank first frame after sub- sampling/binning mode switching in snapshot shutter mode (always blanked out in rolling shutter mode) [10] exposure_sync_mode 0x0 0 when ?0?, exposure configurations are sync?ed at the start of fot. when ?1?, exposure configurations sync is disabled (continuously syncing). this mode is only relevant for triggered snapshot ? master mode, where the exposure configurations are sync?ed at the start of exposure rather than the start of fot. for all other modes it should be set to ?0?. note: sync is still postponed if sync_exposure=?0?. 21 213 gain_status 0x0000 0 ro [4:0] gain_stage1 0x00 0 current stage 1 gain [12:5] gain_stage2 0x00 0 current stage 2 gain 22 214 digital_gain_status 0x0000 0 ro [11:0] db_gain 0x000 0 current digital gain [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved noim1sm9600a, noim2sm9600a http://onsemi.com 54 table 45. register map address offset type description default (dec) default (hex) register name bit field address 38 230 pixel_array_ address_config 0x88 136 rw [4:0] y_address_offset 0x8 8 offset to y ? address to map the actual pixel array scheme / value normal / 4 r1s1 / 2 r2s2 / 2 chk_board / 4 1x2 binning / 2 2x2 binning / 2 [9:5] black_line_address 0x4 4 black line address for different pixel arch/readout scheme / value normal / 2 r1s1 / 1 r2s2 / 1 chk_board / 2 1x2 binning / 1 2x2 binning / 1 39 231 pixel_array_ address_config 0x1397 5015 rw [12:0] reg_seq_last_line 0x1397 5015 sequencer last line address for different pixel arch/readouts scheme / value normal / 2507 r1s1 / 1253 r2s2 / 1253 chk_board / 2507 1x2 binning / 1253 2x2 binning / 1253 40 232 reg_seq_ subsampling_ binning_modes 0x0 0 rw [0] reg_seq_1x2_binning 0x0 0 enable/disable 1x2 pixel binning ?0? ? disable 1x2 pixel binning ?1? ? enable 1x2 pixel binning [1] reg_seq_2x2_binning 0x0 0 enable/disable 2x2 pixel binning ?0? ? disable 2x2 pixel binning ?1? ? enable 2x2 pixel binning [2] reg_seq_check_board _subsample 0x0 0 enable/disable check board pattern subsampling ?0? ? disable check board pattern subsampling ?1? ? enable check board pattern subsampling [3] reg_seq_r1s1 _subsample 0x0 0 enable/disable read-1-skip-1 subsampling ?0? ? disable read-1-skip-1 subsampling ?1? ? enable read-1-skip-1 subsampling [4] reg_seq_r2s2 _subsample 0x0 0 enable/disable read-2-skip-2 subsampling ?0? ? disable read-2-skip-2 subsampling ?1? ? enable read-2-skip-2 subsampling noim1sm9600a, noim2sm9600a http://onsemi.com 55 table 45. register map address offset type description default (dec) default (hex) register name bit field address 54 246 roi_aec_configuration0 0x0000 0 rw [8:0] x_start 0x00 0 aec roi x start configuration (used for aec statistics when roi_aec_enable=?1?) 55 247 roi_aec_configuration0 0x0000 0 rw [8:0] x_end 0x000 0 aec roi x end configuration (used for aec statistics when roi_aec_enable=?1?) 56 248 roi_aec_configuration1 0x0000 0 rw [12:0] y_start 0x000 0 aec roi y start configuration (used for aec statistics when roi_aec_enable=?1?) 57 249 roi_aec_configuration2 0x0000 0 rw [12:0] y_end 0x0 0 aec roi y end configuration (used for aec statistics when roi_aec_enable=?1?) sequencer roi [block offset: 256] 0 256 roi0_configuration0 0x00 0 rw [8:0] x_start 0x00 0 x start configuration 1 257 roi0_configuration1 0x0ef 239 rw [8:0] x_end 0x0ef 239 x end configuration 2 258 roi0_configuration2 0x0000 0 rw [12:0] y_start 0x0000 0 y start configuration 3 259 roi0_configuration3 0x01387 4999 rw [12:0] y_end 0x01387 4999 y end configuration 4 260 roi1_configuration0 0x00 0 rw [8:0] x_start 0x00 0 x start configuration 5 261 roi1_configuration1 0x0ef 239 rw [8:0] x_end 0x0ef 239 x end configuration 6 262 roi1_configuration2 0x0000 0 rw [12:0] y_start 0x0000 0 y start configuration 7 263 roi1_configuration3 0x01387 4999 rw [12:0] y_end 0x01387 4999 y end configuration noim1sm9600a, noim2sm9600a http://onsemi.com 56 package information pin list mano 9600 has two output versions; m1-sm (lvds) and m2-sm (cmos). the lvds i/os comply to the tia/eia-644-a standard and the cmos i/os have a 3.3 v signal level. table 46 and table 47 show the pin list for both versions. table 46. pin list for m1-sm lvds interface pack pin no. pin name i/o type direction description 1 gnd_33 supply 3.3 v ground 2 vdd_33 supply 3.3 v supply 3 mosi cmos input spi master out - slave in 4 miso cmos output spi master in - slave out 5 sclk cmos input spi clock 6 gnd_18 supply 1.8 v ground 7 vdd_18 supply 1.8 v supply 8 nc not connected 9 clock_outn lvds output lvds clock output (negative) 10 clock_outp lvds output lvds clock output (positive) 11 doutn0 lvds output lvds data output channel #0 (negative) 12 doutp0 lvds output lvds data output channel #0(positive) 13 doutn1 lvds output lvds data output channel #1 (negative) 14 doutp1 lvds output lvds data output channel #1(positive) 15 doutn2 lvds output lvds data output channel #2 (negative) 16 doutp2 lvds output lvds data output channel #2 (positive) 17 doutn3 lvds output lvds data output channel #3 (negative) 18 doutp3 lvds output lvds data output channel #3 (positive) 19 syncn lvds output lvds sync channel output (negative) 20 syncp lvds output lvds sync channel output (positive) 21 vdd_33 supply 3.3 v supply 22 gnd_33 supply 3.3 v ground 23 gnd_18 supply 1.8 v ground 24 vdd_18 supply 1.8 v supply 25 lvds_clock_inn lvds input lvds clock input (negative) 26 lvds_clock_inp lvds input lvds clock input (positive) 27 clk_pll cmos input reference clock input for pll 28 vdd_18 supply 1.8 v supply 29 gnd_18 supply 1.8 v ground 30 ibias_master analog i/o master bias reference. connect 47 k to gnd_33 31 vdd_33 supply 3.3 v supply 32 gnd_33 supply 3.3 v ground 33 vdd_pix_low supply 1.8 v supply 34 vdd_pix supply pixel array supply (3.3 v) 35 gnd_colpc supply pixel array ground (0 v) 36 vdd_pix supply pixel array supply (3.3 v) 37 gnd_colpc supply pixel array ground (0 v) noim1sm9600a, noim2sm9600a http://onsemi.com 57 table 46. pin list for m1-sm lvds interface pack pin no. description direction i/o type pin name 38 gnd_33 supply 3.3 v ground 39 vdd_33 supply 3.3 v supply 40 vdd_pix_low supply 1.8 v supply 41 gnd_colpc supply pixel array ground (0 v) 42 vdd_pix supply pixel array supply (3.3 v) 43 gnd_colpc supply pixel array ground (0 v) 44 vdd_pix supply pixel array supply (3.3 v) 45 nc not connected 46 nc not connected 47 vdd_pix_low supply 1.8 v supply 48 nc not connected 49 monitor0 cmos output monitor output #0 50 monitor1 cmos output monitor output #1 51 reset_n cmos input sensor reset (active low) 52 ss_n cmos input spi slave select (active low) table 47. pin list for m2-sm cmos interface pack pin no. pin name i/o type direction description 1 gnd_33 supply 3.3 v ground 2 vdd_33 supply 3.3 v supply 3 mosi cmos input spi master out - slave in 4 miso cmos output spi master in - slave out 5 sclk cmos input spi clock 6 gnd_18 supply 1.8 v ground 7 vdd_18 supply 1.8 v supply 8 nc not connected 9 dout9 cmos output data output bit #9 10 dout8 cmos output data output bit #8 11 dout7 cmos output data output bit #7 12 dout6 cmos output data output bit #6 13 dout5 cmos output data output bit #5 14 dout4 cmos output data output bit #4 15 dout3 cmos output data output bit #3 16 dout2 cmos output data output bit #2 17 dout1 cmos output data output bit #1 18 dout0 cmos output data output bit #0 19 frame_valid cmos output frame valid output 20 line_valid cmos output line valid output 21 vdd_33 supply 3.3 v supply 22 gnd_33 supply 3.3 v ground 23 clk_out analog analog clock output noim1sm9600a, noim2sm9600a http://onsemi.com 58 table 47. pin list for m2-sm cmos interface pack pin no. description direction i/o type pin name 24 vdd_18 supply 1.8 v supply 25 lvds_clock_inn lvds input lvds clock input (negative) 26 lvds_clock_inp lvds input lvds clock input (positive) 27 clk_pll cmos input reference clock input for pll 28 vdd_18 supply 1.8 v supply 29 gnd_18 supply 1.8 v ground 30 ibias_master analog i/o master bias reference. connect 47 k to gnd_33 31 vdd_33 supply 3.3 v supply 32 gnd_33 supply 3.3 v ground 33 vdd_pix_low supply 1.8 v supply 34 vdd_pix supply pixel array supply (3.3 v) 35 gnd_colpc supply pixel array ground (0 v) 36 vdd_pix supply pixel array supply (3.3 v) 37 gnd_colpc supply pixel array ground (0 v) 38 gnd_33 supply 3.3 v ground 39 vdd_33 supply 3.3 v supply 40 vdd_pix_low supply 1.8 v supply 41 gnd_colpc supply pixel array ground (0 v) 42 vdd_pix supply pixel array supply (3.3 v) 43 gnd_colpc supply pixel array ground (0 v) 44 vdd_pix supply pixel array supply (3.3 v) 45 nc not connected 46 nc not connected 47 vdd_pix_low supply 1.8 v supply 48 nc not connected 49 monitor0 cmos output monitor output #0 50 monitor1 cmos output monitor output #1 51 reset_n cmos input sensor reset (active low) 52 ss_n cmos input spi slave select (active low) noim1sm9600a, noim2sm9600a http://onsemi.com 59 package specification table 48. mechanical specification for mano 9600 ceramic lcc package parameter description min typ max units die (with pin 1 to the left center) die thickness 750 m die placement accuracy in package -50 +50 m die center, x offset to the center of package 2.5 52.5 102.5 m die center, y offset to the center of the package -268.3 -218.3 -168.3 m die position, tilt to the die attach plane -1 0 1 deg die rotation accuracy (referenced to die scribe and lead fingers on package on all four sides) -1 0 1 deg optical center referenced from the die/package center (x-dir) -4.4 m optical center referenced from the die/package center (y-dir) -1359.8 m distance from pcb plane to top of the die surface 1.3 mm distance from top of the die surface to top of the glass lid 0.9 mm glass lid specification xy size (-10%) 19.05 x 19.05 (+10%) mm 2 thickness 0.5 0.55 0.6 mm spectral response range 400 1000 nm transmission of glass lid (refer to figure 44) 92 % mechanical shock jesd22-b104c; condition g 2000 g vibration jesd22-b103b; condition 1 20 2000 hz mounting profile reflow profile according to j-std-020d.1 260 c noim1sm9600a, noim2sm9600a http://onsemi.com 60 package outline drawing figure 34. 52 ? pin lcc package (dimensions in mm) noim1sm9600a, noim2sm9600a http://onsemi.com 61 optical center information the center of the die (cd) is offset from the center of the cavity by (52.5, ? 218.3) m. the center of the cavity is exactly at 50% between the insides of the finger pads. ? die outer dimensions: ? b4 is the reference for the die (0,0) in m ? b1 is at (0,10150) m ? b2 is at (10900,10150) m ? b3 is at (10900,0) m ? active area outer dimensions ? a1 is the at (785.53, 9663.86) m ? a2 is at (10018.33, 9663.86) m ? a3 is at (10018.33, 3642.26) m ? a4 is at (785.53, 3642.26) m ? center of the active area ? aa is at (5401.93, 6653.06) m ? center of the die ? cd is at (5450, 5075) m figure 35. package outline drawing noim1sm9600a, noim2sm9600a http://onsemi.com 62 glass lid the mano 9600 image sensor uses a glass lid without any coatings. figure 36 shows the transmission characteristics of the glass lid. as shown in figure 36 , no infrared attenuating color filter glass is used. (source: http://www.pgo-online.com ). figure 36. transmission characteristics of the glass lid noim1sm9600a, noim2sm9600a http://onsemi.com 63 handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561, image sensor handling and best practices. limited warranty on semiconductor?s image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within 2 (two) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. refer to the on semiconductor rma policy procedure at http://www.onsemi.com/site/pdf/cat_returns_failurean alysis.pdf specifications and user references specifications, application notes and useful resources can be accessible via customer login account at myon - cisp extranet. https://www.onsemi.com/powersolutions/myon/ercispfol der.do acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the mano 9600 is tested prior to being shipped. application note and references ? an65464 vita 2000 hsmc cyclone reference board noim1sm9600a, noim2sm9600a http://onsemi.com 64 acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dnl differential non-llinearity ds double sampling dsnu dark signal non-uniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frame per second fs frame start hbm human body model img image data (regular pixel data) inl integral non-linearity acronym description ip intellectual property le line end ls line start lsb least significant bit lvds low-voltage differential signaling msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu photo response non-uniformity qe quantum efficiency rgb red-green-blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity noim1sm9600a, noim2sm9600a http://onsemi.com 65 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. dnl differential non-linearity (for adcs) dsnu dark signal non-uniformity. this parameter characterizes the degree of non-uniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response non-uniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is oper- ated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodi- ode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sens- itivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels. noim1sm9600a, noim2sm9600a http://onsemi.com 66 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 noim1sm9600a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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