1. general description the 74hc193-q100; 74hct193-q100 is a 4-bit synchronous binary up/down counter. separate up/down clocks, cpu and cpd resp ectively, simplify operation. the outputs change state synchronously with the low-to-high transition of either clock input. if the cpu clock is pulsed while cpd is held high , the device counts up. if the cpd clock is pulsed while cpu is held high, the device co unts down. only one clock input can be held high at any time to guarantee predictable behavior. the device can be cleared at any time by the asynchronous mast er reset input (mr). it may al so be loaded in parallel by activating the asynchronous parallel load input (pl ). the terminal count up (tcu ) and terminal count down (tcd ) outputs are normally high. wh en the circuit has reached the maximum count state of 15, the next high-to-low transition of cpu causes tcu to go low. tcu remains low until cpu goes high agai n, duplicating the count up clock. likewise, the tcd output goes low when the circuit is in the zero state and the cpd goes low. the terminal count outputs duplic ate the clock waveforms and can be used as the clock input signals to the next higher-order circuit in a multistage counter. multistage counters are not fully synchronous, since there is a slight delay time difference added for each stage that is added. the counter may be preset by the asynchronous parallel load capability of the circuit. information on the para llel data inputs (d0 to d3), is loaded into the counter. this information appears on the outputs (q0 to q3) regardless of the conditions of the clock inputs when the parallel load (pl ) input is low. a high level on the master reset (mr) input disables the paralle l load gates. it overrides both clock inputs and sets all outputs (q0 to q3) low. if one of the clock inputs is low during and after a reset or load operation, the next low-to-high tr ansition of that clo ck is interpreted as a legitimate signal and it is counted. inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc193-q100: cmos level ? for 74hct193-q100: ttl level ? synchronous reversible 4-bit binary counting ? asynchronous parallel load ? asynchronous reset ? expandable without external logic ? complies with jedec standard no. 7a 74hc193-q100; 74hct193-q100 presettable synchronous 4-bi t binary up/down counter rev. 1 ? 12 july 2013 product data sheet
74hc_hct139_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 12 july 2013 2 of 29 nxp semiconductors 74hc193-q100; 74hct193-q100 presettable synchronous 4-bit binary up/down counter ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74hc193d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74HC193DB-Q100 ? 40 ? c to +125 ? c ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74hc193pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74hct193d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hct193db-q100 ? 40 ? c to +125 ? c ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74hct193pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 fig 1. functional diagram fig 2. logic symbol 001aag405 flip-flops counter pl 11 cpu 5 tcd 13 tcu 12 q0 3267 151109 q1 q2 q3 d0 d1 d2 d3 cpd 4 mr 14 001aag409 mr q0 q1 q2 q3 pl d0 d1 d2 d3 143267 11151109 4 cpd tcd tcu 5 13 12 cpu
74hc_hct139_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 12 july 2013 3 of 29 nxp semiconductors 74hc193-q100; 74hct193-q100 presettable synchronous 4-bit binary up/down counter fig 3. iec logic symbol 3d ctr4 2ct = 0 1ct = 15 001aag410 10 3 6 15 12 97 13 12 g2 4 g1 5 11 c3 2+ 14 r 1?
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74hc_hct139_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 12 july 2013 5 of 29 nxp semiconductors 74hc193-q100; 74hct193-q100 presettable synchronous 4-bit binary up/down counter 5. pinning information 5.1 pinning 5.2 pin description [1] low-to-high, edge triggered. fig 5. pin configuration so16 fig 6. pin configuration tssop16 and ssop16 ' 9 & |